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fix mali API_VERSION grep
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / arkfb.c
CommitLineData
681e1473
OZ		 1/*
2 * linux/drivers/video/arkfb.c -- Frame buffer device driver for ARK 2000PV
3 * with ICS 5342 dac (it is easy to add support for different dacs).
4 *
5 * Copyright (c) 2007 Ondrej Zajicek <santiago@crfreenet.org>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 *
11 * Code is based on s3fb
12 */
13
681e1473
OZ		 14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/string.h>
18#include <linux/mm.h>
19#include <linux/tty.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/fb.h>
23#include <linux/svga.h>
24#include <linux/init.h>
25#include <linux/pci.h>
ac751efa 26#include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
681e1473
OZ		 27#include <video/vga.h>
28
29#ifdef CONFIG_MTRR
30#include <asm/mtrr.h>
31#endif
32
33struct arkfb_info {
34 int mclk_freq;
35 int mtrr_reg;
36
37 struct dac_info *dac;
38 struct vgastate state;
39 struct mutex open_lock;
40 unsigned int ref_count;
41 u32 pseudo_palette[16];
42};
43
44
45/* ------------------------------------------------------------------------- */
46
47
48static const struct svga_fb_format arkfb_formats[] = {
49 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
50 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 8},
51 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
52 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
53 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
54 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
55 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
56 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8},
57 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
58 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
59 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
60 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
61 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
62 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 8, 8},
63 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
64 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2},
65 SVGA_FORMAT_END
66};
67
68
69/* CRT timing register sets */
70
71static const struct vga_regset ark_h_total_regs[] = {{0x00, 0, 7}, {0x41, 7, 7}, VGA_REGSET_END};
72static const struct vga_regset ark_h_display_regs[] = {{0x01, 0, 7}, {0x41, 6, 6}, VGA_REGSET_END};
73static const struct vga_regset ark_h_blank_start_regs[] = {{0x02, 0, 7}, {0x41, 5, 5}, VGA_REGSET_END};
74static const struct vga_regset ark_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7 }, VGA_REGSET_END};
75static const struct vga_regset ark_h_sync_start_regs[] = {{0x04, 0, 7}, {0x41, 4, 4}, VGA_REGSET_END};
76static const struct vga_regset ark_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
77
78static const struct vga_regset ark_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x40, 7, 7}, VGA_REGSET_END};
79static const struct vga_regset ark_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x40, 6, 6}, VGA_REGSET_END};
80static const struct vga_regset ark_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x40, 5, 5}, VGA_REGSET_END};
81// const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 6}, VGA_REGSET_END};
82static const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
83static const struct vga_regset ark_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x40, 4, 4}, VGA_REGSET_END};
84static const struct vga_regset ark_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
85
86static const struct vga_regset ark_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, VGA_REGSET_END};
87static const struct vga_regset ark_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x40, 0, 2}, VGA_REGSET_END};
88static const struct vga_regset ark_offset_regs[] = {{0x13, 0, 7}, {0x41, 3, 3}, VGA_REGSET_END};
89
90static const struct svga_timing_regs ark_timing_regs = {
91 ark_h_total_regs, ark_h_display_regs, ark_h_blank_start_regs,
92 ark_h_blank_end_regs, ark_h_sync_start_regs, ark_h_sync_end_regs,
93 ark_v_total_regs, ark_v_display_regs, ark_v_blank_start_regs,
94 ark_v_blank_end_regs, ark_v_sync_start_regs, ark_v_sync_end_regs,
95};
96
97
98/* ------------------------------------------------------------------------- */
99
100
101/* Module parameters */
102
48c68c4f 103static char *mode_option = "640x480-8@60";
681e1473
OZ		 104
105#ifdef CONFIG_MTRR
106static int mtrr = 1;
107#endif
108
109MODULE_AUTHOR("(c) 2007 Ondrej Zajicek <santiago@crfreenet.org>");
110MODULE_LICENSE("GPL");
111MODULE_DESCRIPTION("fbdev driver for ARK 2000PV");
112
1abf9172
KH		 113module_param(mode_option, charp, 0444);
114MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
115module_param_named(mode, mode_option, charp, 0444);
116MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
681e1473
OZ		 117
118#ifdef CONFIG_MTRR
119module_param(mtrr, int, 0444);
120MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
121#endif
122
123static int threshold = 4;
124
125module_param(threshold, int, 0644);
126MODULE_PARM_DESC(threshold, "FIFO threshold");
127
128
129/* ------------------------------------------------------------------------- */
130
131
132static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map)
133{
134 const u8 *font = map->data;
135 u8 __iomem *fb = (u8 __iomem *)info->screen_base;
136 int i, c;
137
138 if ((map->width != 8) || (map->height != 16) ||
139 (map->depth != 1) || (map->length != 256)) {
140 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, "
141 "height %d, depth %d, length %d\n", info->node,
142 map->width, map->height, map->depth, map->length);
143 return;
144 }
145
146 fb += 2;
147 for (c = 0; c < map->length; c++) {
148 for (i = 0; i < map->height; i++) {
149 fb_writeb(font[i], &fb[i * 4]);
150 fb_writeb(font[i], &fb[i * 4 + (128 * 8)]);
151 }
152 fb += 128;
153
154 if ((c % 8) == 7)
155 fb += 128*8;
156
157 font += map->height;
158 }
159}
160
55db0923
DM		 161static void arkfb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
162{
163 struct arkfb_info *par = info->par;
164
165 svga_tilecursor(par->state.vgabase, info, cursor);
166}
167
681e1473
OZ		 168static struct fb_tile_ops arkfb_tile_ops = {
169 .fb_settile = arkfb_settile,
170 .fb_tilecopy = svga_tilecopy,
171 .fb_tilefill = svga_tilefill,
172 .fb_tileblit = svga_tileblit,
55db0923 173 .fb_tilecursor = arkfb_tilecursor,
681e1473
OZ		 174 .fb_get_tilemax = svga_get_tilemax,
175};
176
177
178/* ------------------------------------------------------------------------- */
179
180
181/* image data is MSB-first, fb structure is MSB-first too */
182static inline u32 expand_color(u32 c)
183{
184 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
185}
186
187/* arkfb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
188static void arkfb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
189{
190 u32 fg = expand_color(image->fg_color);
191 u32 bg = expand_color(image->bg_color);
192 const u8 *src1, *src;
193 u8 __iomem *dst1;
194 u32 __iomem *dst;
195 u32 val;
196 int x, y;
197
198 src1 = image->data;
199 dst1 = info->screen_base + (image->dy * info->fix.line_length)
200 + ((image->dx / 8) * 4);
201
202 for (y = 0; y < image->height; y++) {
203 src = src1;
204 dst = (u32 __iomem *) dst1;
205 for (x = 0; x < image->width; x += 8) {
206 val = *(src++) * 0x01010101;
207 val = (val & fg) | (~val & bg);
208 fb_writel(val, dst++);
209 }
210 src1 += image->width / 8;
211 dst1 += info->fix.line_length;
212 }
213
214}
215
216/* arkfb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
217static void arkfb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
218{
219 u32 fg = expand_color(rect->color);
220 u8 __iomem *dst1;
221 u32 __iomem *dst;
222 int x, y;
223
224 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
225 + ((rect->dx / 8) * 4);
226
227 for (y = 0; y < rect->height; y++) {
228 dst = (u32 __iomem *) dst1;
229 for (x = 0; x < rect->width; x += 8) {
230 fb_writel(fg, dst++);
231 }
232 dst1 += info->fix.line_length;
233 }
234
235}
236
237
238/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
239static inline u32 expand_pixel(u32 c)
240{
241 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
242 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
243}
244
245/* arkfb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
246static void arkfb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
247{
248 u32 fg = image->fg_color * 0x11111111;
249 u32 bg = image->bg_color * 0x11111111;
250 const u8 *src1, *src;
251 u8 __iomem *dst1;
252 u32 __iomem *dst;
253 u32 val;
254 int x, y;
255
256 src1 = image->data;
257 dst1 = info->screen_base + (image->dy * info->fix.line_length)
258 + ((image->dx / 8) * 4);
259
260 for (y = 0; y < image->height; y++) {
261 src = src1;
262 dst = (u32 __iomem *) dst1;
263 for (x = 0; x < image->width; x += 8) {
264 val = expand_pixel(*(src++));
265 val = (val & fg) | (~val & bg);
266 fb_writel(val, dst++);
267 }
268 src1 += image->width / 8;
269 dst1 += info->fix.line_length;
270 }
271
272}
273
274static void arkfb_imageblit(struct fb_info *info, const struct fb_image *image)
275{
276 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
277 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
278 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
279 arkfb_iplan_imageblit(info, image);
280 else
281 arkfb_cfb4_imageblit(info, image);
282 } else
283 cfb_imageblit(info, image);
284}
285
286static void arkfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
287{
288 if ((info->var.bits_per_pixel == 4)
289 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
290 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
291 arkfb_iplan_fillrect(info, rect);
292 else
293 cfb_fillrect(info, rect);
294}
295
296
297/* ------------------------------------------------------------------------- */
298
299
300enum
301{
302 DAC_PSEUDO8_8,
303 DAC_RGB1555_8,
304 DAC_RGB0565_8,
305 DAC_RGB0888_8,
306 DAC_RGB8888_8,
307 DAC_PSEUDO8_16,
308 DAC_RGB1555_16,
309 DAC_RGB0565_16,
310 DAC_RGB0888_16,
311 DAC_RGB8888_16,
312 DAC_MAX
313};
314
315struct dac_ops {
316 int (*dac_get_mode)(struct dac_info *info);
317 int (*dac_set_mode)(struct dac_info *info, int mode);
318 int (*dac_get_freq)(struct dac_info *info, int channel);
319 int (*dac_set_freq)(struct dac_info *info, int channel, u32 freq);
320 void (*dac_release)(struct dac_info *info);
321};
322
323typedef void (*dac_read_regs_t)(void *data, u8 *code, int count);
324typedef void (*dac_write_regs_t)(void *data, u8 *code, int count);
325
326struct dac_info
327{
328 struct dac_ops *dacops;
329 dac_read_regs_t dac_read_regs;
330 dac_write_regs_t dac_write_regs;
331 void *data;
332};
333
334
335static inline u8 dac_read_reg(struct dac_info *info, u8 reg)
336{
337 u8 code[2] = {reg, 0};
338 info->dac_read_regs(info->data, code, 1);
339 return code[1];
340}
341
342static inline void dac_read_regs(struct dac_info *info, u8 *code, int count)
343{
344 info->dac_read_regs(info->data, code, count);
345}
346
347static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val)
348{
349 u8 code[2] = {reg, val};
350 info->dac_write_regs(info->data, code, 1);
351}
352
353static inline void dac_write_regs(struct dac_info *info, u8 *code, int count)
354{
355 info->dac_write_regs(info->data, code, count);
356}
357
358static inline int dac_set_mode(struct dac_info *info, int mode)
359{
360 return info->dacops->dac_set_mode(info, mode);
361}
362
363static inline int dac_set_freq(struct dac_info *info, int channel, u32 freq)
364{
365 return info->dacops->dac_set_freq(info, channel, freq);
366}
367
368static inline void dac_release(struct dac_info *info)
369{
370 info->dacops->dac_release(info);
371}
372
373
374/* ------------------------------------------------------------------------- */
375
376
377/* ICS5342 DAC */
378
379struct ics5342_info
380{
381 struct dac_info dac;
382 u8 mode;
383};
384
385#define DAC_PAR(info) ((struct ics5342_info *) info)
386
387/* LSB is set to distinguish unused slots */
388static const u8 ics5342_mode_table[DAC_MAX] = {
389 [DAC_PSEUDO8_8] = 0x01, [DAC_RGB1555_8] = 0x21, [DAC_RGB0565_8] = 0x61,
390 [DAC_RGB0888_8] = 0x41, [DAC_PSEUDO8_16] = 0x11, [DAC_RGB1555_16] = 0x31,
391 [DAC_RGB0565_16] = 0x51, [DAC_RGB0888_16] = 0x91, [DAC_RGB8888_16] = 0x71
392};
393
394static int ics5342_set_mode(struct dac_info *info, int mode)
395{
396 u8 code;
397
398 if (mode >= DAC_MAX)
399 return -EINVAL;
400
401 code = ics5342_mode_table[mode];
402
403 if (! code)
404 return -EINVAL;
405
406 dac_write_reg(info, 6, code & 0xF0);
407 DAC_PAR(info)->mode = mode;
408
409 return 0;
410}
411
412static const struct svga_pll ics5342_pll = {3, 129, 3, 33, 0, 3,
413 60000, 250000, 14318};
414
415/* pd4 - allow only posdivider 4 (r=2) */
416static const struct svga_pll ics5342_pll_pd4 = {3, 129, 3, 33, 2, 2,
417 60000, 335000, 14318};
418
419/* 270 MHz should be upper bound for VCO clock according to specs,
420 but that is too restrictive in pd4 case */
421
422static int ics5342_set_freq(struct dac_info *info, int channel, u32 freq)
423{
424 u16 m, n, r;
425
426 /* only postdivider 4 (r=2) is valid in mode DAC_PSEUDO8_16 */
427 int rv = svga_compute_pll((DAC_PAR(info)->mode == DAC_PSEUDO8_16)
428 ? &ics5342_pll_pd4 : &ics5342_pll,
429 freq, &m, &n, &r, 0);
430
431 if (rv < 0) {
432 return -EINVAL;
433 } else {
434 u8 code[6] = {4, 3, 5, m-2, 5, (n-2) | (r << 5)};
435 dac_write_regs(info, code, 3);
436 return 0;
437 }
438}
439
440static void ics5342_release(struct dac_info *info)
441{
442 ics5342_set_mode(info, DAC_PSEUDO8_8);
443 kfree(info);
444}
445
446static struct dac_ops ics5342_ops = {
447 .dac_set_mode = ics5342_set_mode,
448 .dac_set_freq = ics5342_set_freq,
449 .dac_release = ics5342_release
450};
451
452
453static struct dac_info * ics5342_init(dac_read_regs_t drr, dac_write_regs_t dwr, void *data)
454{
455 struct dac_info *info = kzalloc(sizeof(struct ics5342_info), GFP_KERNEL);
456
457 if (! info)
458 return NULL;
459
460 info->dacops = &ics5342_ops;
461 info->dac_read_regs = drr;
462 info->dac_write_regs = dwr;
463 info->data = data;
464 DAC_PAR(info)->mode = DAC_PSEUDO8_8; /* estimation */
465 return info;
466}
467
468
469/* ------------------------------------------------------------------------- */
470
471
472static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7};
473
474static void ark_dac_read_regs(void *data, u8 *code, int count)
475{
c5e04633
DM		 476 struct fb_info *info = data;
477 struct arkfb_info *par;
478 u8 regval;
681e1473 479
c5e04633
DM		 480 par = info->par;
481 regval = vga_rseq(par->state.vgabase, 0x1C);
681e1473
OZ		 482 while (count != 0)
483 {
c5e04633
DM		 484 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
485 code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]);
681e1473
OZ		 486 count--;
487 code += 2;
488 }
489
c5e04633 490 vga_wseq(par->state.vgabase, 0x1C, regval);
681e1473
OZ		 491}
492
493static void ark_dac_write_regs(void *data, u8 *code, int count)
494{
c5e04633
DM		 495 struct fb_info *info = data;
496 struct arkfb_info *par;
497 u8 regval;
681e1473 498
c5e04633
DM		 499 par = info->par;
500 regval = vga_rseq(par->state.vgabase, 0x1C);
681e1473
OZ		 501 while (count != 0)
502 {
c5e04633
DM		 503 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
504 vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]);
681e1473
OZ		 505 count--;
506 code += 2;
507 }
508
c5e04633 509 vga_wseq(par->state.vgabase, 0x1C, regval);
681e1473
OZ		 510}
511
512
513static void ark_set_pixclock(struct fb_info *info, u32 pixclock)
514{
515 struct arkfb_info *par = info->par;
516 u8 regval;
517
518 int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock);
519 if (rv < 0) {
520 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
521 return;
522 }
523
524 /* Set VGA misc register */
c5e04633
DM		 525 regval = vga_r(par->state.vgabase, VGA_MIS_R);
526 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
681e1473
OZ		 527}
528
529
530/* Open framebuffer */
531
532static int arkfb_open(struct fb_info *info, int user)
533{
534 struct arkfb_info *par = info->par;
535
536 mutex_lock(&(par->open_lock));
537 if (par->ref_count == 0) {
ec70a943
DM		 538 void __iomem *vgabase = par->state.vgabase;
539
681e1473 540 memset(&(par->state), 0, sizeof(struct vgastate));
ec70a943 541 par->state.vgabase = vgabase;
681e1473
OZ		 542 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
543 par->state.num_crtc = 0x60;
544 par->state.num_seq = 0x30;
545 save_vga(&(par->state));
546 }
547
548 par->ref_count++;
549 mutex_unlock(&(par->open_lock));
550
551 return 0;
552}
553
554/* Close framebuffer */
555
556static int arkfb_release(struct fb_info *info, int user)
557{
558 struct arkfb_info *par = info->par;
559
560 mutex_lock(&(par->open_lock));
561 if (par->ref_count == 0) {
562 mutex_unlock(&(par->open_lock));
563 return -EINVAL;
564 }
565
566 if (par->ref_count == 1) {
567 restore_vga(&(par->state));
568 dac_set_mode(par->dac, DAC_PSEUDO8_8);
569 }
570
571 par->ref_count--;
572 mutex_unlock(&(par->open_lock));
573
574 return 0;
575}
576
577/* Validate passed in var */
578
579static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
580{
581 int rv, mem, step;
582
583 /* Find appropriate format */
584 rv = svga_match_format (arkfb_formats, var, NULL);
585 if (rv < 0)
586 {
587 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
588 return rv;
589 }
590
591 /* Do not allow to have real resoulution larger than virtual */
592 if (var->xres > var->xres_virtual)
593 var->xres_virtual = var->xres;
594
595 if (var->yres > var->yres_virtual)
596 var->yres_virtual = var->yres;
597
598 /* Round up xres_virtual to have proper alignment of lines */
599 step = arkfb_formats[rv].xresstep - 1;
600 var->xres_virtual = (var->xres_virtual+step) & ~step;
601
602
603 /* Check whether have enough memory */
604 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
605 if (mem > info->screen_size)
606 {
607 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
608 return -EINVAL;
609 }
610
611 rv = svga_check_timings (&ark_timing_regs, var, info->node);
612 if (rv < 0)
613 {
614 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
615 return rv;
616 }
617
618 /* Interlaced mode is broken */
619 if (var->vmode & FB_VMODE_INTERLACED)
620 return -EINVAL;
621
622 return 0;
623}
624
625/* Set video mode from par */
626
627static int arkfb_set_par(struct fb_info *info)
628{
629 struct arkfb_info *par = info->par;
630 u32 value, mode, hmul, hdiv, offset_value, screen_size;
631 u32 bpp = info->var.bits_per_pixel;
632 u8 regval;
633
634 if (bpp != 0) {
635 info->fix.ypanstep = 1;
636 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
637
638 info->flags &= ~FBINFO_MISC_TILEBLITTING;
639 info->tileops = NULL;
640
641 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
642 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
643 info->pixmap.blit_y = ~(u32)0;
644
645 offset_value = (info->var.xres_virtual * bpp) / 64;
646 screen_size = info->var.yres_virtual * info->fix.line_length;
647 } else {
648 info->fix.ypanstep = 16;
649 info->fix.line_length = 0;
650
651 info->flags |= FBINFO_MISC_TILEBLITTING;
652 info->tileops = &arkfb_tile_ops;
653
654 /* supports 8x16 tiles only */
655 info->pixmap.blit_x = 1 << (8 - 1);
656 info->pixmap.blit_y = 1 << (16 - 1);
657
658 offset_value = info->var.xres_virtual / 16;
659 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
660 }
661
662 info->var.xoffset = 0;
663 info->var.yoffset = 0;
664 info->var.activate = FB_ACTIVATE_NOW;
665
666 /* Unlock registers */
ea770789 667 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
681e1473
OZ		 668
669 /* Blank screen and turn off sync */
d907ec04 670 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
ea770789 671 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
681e1473
OZ		 672
673 /* Set default values */
e2fade2c 674 svga_set_default_gfx_regs(par->state.vgabase);
f51a14dd 675 svga_set_default_atc_regs(par->state.vgabase);
a4ade839 676 svga_set_default_seq_regs(par->state.vgabase);
1d28fcad 677 svga_set_default_crt_regs(par->state.vgabase);
21da386d
DM		 678 svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF);
679 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0);
681e1473
OZ		 680
681 /* ARK specific initialization */
d907ec04
DM		 682 svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
683 svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
681e1473 684
c5e04633
DM		 685 vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16);
686 vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24);
687 vga_wseq(par->state.vgabase, 0x15, 0);
688 vga_wseq(par->state.vgabase, 0x16, 0);
681e1473
OZ		 689
690 /* Set the FIFO threshold register */
691 /* It is fascinating way to store 5-bit value in 8-bit register */
692 regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1;
c5e04633 693 vga_wseq(par->state.vgabase, 0x18, regval);
681e1473
OZ		 694
695 /* Set the offset register */
696 pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
21da386d 697 svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value);
681e1473
OZ		 698
699 /* fix for hi-res textmode */
ea770789 700 svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08);
681e1473
OZ		 701
702 if (info->var.vmode & FB_VMODE_DOUBLE)
ea770789 703 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
681e1473 704 else
ea770789 705 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
681e1473
OZ		 706
707 if (info->var.vmode & FB_VMODE_INTERLACED)
ea770789 708 svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04);
681e1473 709 else
ea770789 710 svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04);
681e1473
OZ		 711
712 hmul = 1;
713 hdiv = 1;
714 mode = svga_match_format(arkfb_formats, &(info->var), &(info->fix));
715
716 /* Set mode-specific register values */
717 switch (mode) {
718 case 0:
719 pr_debug("fb%d: text mode\n", info->node);
9c96394b 720 svga_set_textmode_vga_regs(par->state.vgabase);
681e1473 721
c5e04633 722 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
ea770789 723 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
681e1473
OZ		 724 dac_set_mode(par->dac, DAC_PSEUDO8_8);
725
726 break;
727 case 1:
728 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
c5e04633 729 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
681e1473 730
c5e04633 731 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
ea770789 732 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
681e1473
OZ		 733 dac_set_mode(par->dac, DAC_PSEUDO8_8);
734 break;
735 case 2:
736 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
737
c5e04633 738 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
ea770789 739 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
681e1473
OZ		 740 dac_set_mode(par->dac, DAC_PSEUDO8_8);
741 break;
742 case 3:
743 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
744
c5e04633 745 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */
681e1473
OZ		 746
747 if (info->var.pixclock > 20000) {
748 pr_debug("fb%d: not using multiplex\n", info->node);
ea770789 749 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
681e1473
OZ		 750 dac_set_mode(par->dac, DAC_PSEUDO8_8);
751 } else {
752 pr_debug("fb%d: using multiplex\n", info->node);
ea770789 753 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
681e1473
OZ		 754 dac_set_mode(par->dac, DAC_PSEUDO8_16);
755 hdiv = 2;
756 }
757 break;
758 case 4:
759 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
760
c5e04633 761 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
ea770789 762 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
681e1473
OZ		 763 dac_set_mode(par->dac, DAC_RGB1555_16);
764 break;
765 case 5:
766 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
767
c5e04633 768 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
ea770789 769 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
681e1473
OZ		 770 dac_set_mode(par->dac, DAC_RGB0565_16);
771 break;
772 case 6:
773 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
774
c5e04633 775 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */
ea770789 776 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
681e1473
OZ		 777 dac_set_mode(par->dac, DAC_RGB0888_16);
778 hmul = 3;
779 hdiv = 2;
780 break;
781 case 7:
782 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
783
c5e04633 784 vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */
ea770789 785 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
681e1473
OZ		 786 dac_set_mode(par->dac, DAC_RGB8888_16);
787 hmul = 2;
788 break;
789 default:
790 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
791 return -EINVAL;
792 }
793
794 ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul);
38d2620e 795 svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv,
681e1473
OZ		 796 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
797 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
798 hmul, info->node);
799
800 /* Set interlaced mode start/end register */
801 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
802 value = ((value * hmul / hdiv) / 8) - 5;
c5e04633 803 vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2);
681e1473
OZ		 804
805 memset_io(info->screen_base, 0x00, screen_size);
806 /* Device and screen back on */
ea770789 807 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
d907ec04 808 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
681e1473
OZ		 809
810 return 0;
811}
812
813/* Set a colour register */
814
815static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
816 u_int transp, struct fb_info *fb)
817{
818 switch (fb->var.bits_per_pixel) {
819 case 0:
820 case 4:
821 if (regno >= 16)
822 return -EINVAL;
823
824 if ((fb->var.bits_per_pixel == 4) &&
825 (fb->var.nonstd == 0)) {
826 outb(0xF0, VGA_PEL_MSK);
827 outb(regno*16, VGA_PEL_IW);
828 } else {
829 outb(0x0F, VGA_PEL_MSK);
830 outb(regno, VGA_PEL_IW);
831 }
832 outb(red >> 10, VGA_PEL_D);
833 outb(green >> 10, VGA_PEL_D);
834 outb(blue >> 10, VGA_PEL_D);
835 break;
836 case 8:
837 if (regno >= 256)
838 return -EINVAL;
839
840 outb(0xFF, VGA_PEL_MSK);
841 outb(regno, VGA_PEL_IW);
842 outb(red >> 10, VGA_PEL_D);
843 outb(green >> 10, VGA_PEL_D);
844 outb(blue >> 10, VGA_PEL_D);
845 break;
846 case 16:
847 if (regno >= 16)
848 return 0;
849
850 if (fb->var.green.length == 5)
851 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
852 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
853 else if (fb->var.green.length == 6)
854 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
855 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
856 else
857 return -EINVAL;
858 break;
859 case 24:
860 case 32:
861 if (regno >= 16)
862 return 0;
863
864 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
865 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
866 break;
867 default:
868 return -EINVAL;
869 }
870
871 return 0;
872}
873
874/* Set the display blanking state */
875
876static int arkfb_blank(int blank_mode, struct fb_info *info)
877{
d907ec04
DM		 878 struct arkfb_info *par = info->par;
879
681e1473
OZ		 880 switch (blank_mode) {
881 case FB_BLANK_UNBLANK:
882 pr_debug("fb%d: unblank\n", info->node);
d907ec04 883 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
ea770789 884 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
681e1473
OZ		 885 break;
886 case FB_BLANK_NORMAL:
887 pr_debug("fb%d: blank\n", info->node);
d907ec04 888 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
ea770789 889 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
681e1473
OZ		 890 break;
891 case FB_BLANK_POWERDOWN:
892 case FB_BLANK_HSYNC_SUSPEND:
893 case FB_BLANK_VSYNC_SUSPEND:
894 pr_debug("fb%d: sync down\n", info->node);
d907ec04 895 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
ea770789 896 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
681e1473
OZ		 897 break;
898 }
899 return 0;
900}
901
902
903/* Pan the display */
904
905static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
906{
21da386d 907 struct arkfb_info *par = info->par;
681e1473
OZ		 908 unsigned int offset;
909
910 /* Calculate the offset */
a35a9b79
LP		 911 if (info->var.bits_per_pixel == 0) {
912 offset = (var->yoffset / 16) * (info->var.xres_virtual / 2)
913 + (var->xoffset / 2);
681e1473
OZ		 914 offset = offset >> 2;
915 } else {
916 offset = (var->yoffset * info->fix.line_length) +
a35a9b79
LP		 917 (var->xoffset * info->var.bits_per_pixel / 8);
918 offset = offset >> ((info->var.bits_per_pixel == 4) ? 2 : 3);
681e1473
OZ		 919 }
920
921 /* Set the offset */
21da386d 922 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset);
681e1473
OZ		 923
924 return 0;
925}
926
927
928/* ------------------------------------------------------------------------- */
929
930
931/* Frame buffer operations */
932
933static struct fb_ops arkfb_ops = {
934 .owner = THIS_MODULE,
935 .fb_open = arkfb_open,
936 .fb_release = arkfb_release,
937 .fb_check_var = arkfb_check_var,
938 .fb_set_par = arkfb_set_par,
939 .fb_setcolreg = arkfb_setcolreg,
940 .fb_blank = arkfb_blank,
941 .fb_pan_display = arkfb_pan_display,
942 .fb_fillrect = arkfb_fillrect,
943 .fb_copyarea = cfb_copyarea,
944 .fb_imageblit = arkfb_imageblit,
5a87ede9 945 .fb_get_caps = svga_get_caps,
681e1473
OZ		 946};
947
948
949/* ------------------------------------------------------------------------- */
950
951
952/* PCI probe */
48c68c4f 953static int ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
681e1473 954{
892c24ca
DM		 955 struct pci_bus_region bus_reg;
956 struct resource vga_res;
681e1473
OZ		 957 struct fb_info *info;
958 struct arkfb_info *par;
959 int rc;
960 u8 regval;
961
962 /* Ignore secondary VGA device because there is no VGA arbitration */
963 if (! svga_primary_device(dev)) {
964 dev_info(&(dev->dev), "ignoring secondary device\n");
965 return -ENODEV;
966 }
967
968 /* Allocate and fill driver data structure */
20e061fb 969 info = framebuffer_alloc(sizeof(struct arkfb_info), &(dev->dev));
681e1473
OZ		 970 if (! info) {
971 dev_err(&(dev->dev), "cannot allocate memory\n");
972 return -ENOMEM;
973 }
974
975 par = info->par;
976 mutex_init(&par->open_lock);
977
978 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
979 info->fbops = &arkfb_ops;
980
981 /* Prepare PCI device */
982 rc = pci_enable_device(dev);
983 if (rc < 0) {
594a8819 984 dev_err(info->device, "cannot enable PCI device\n");
681e1473
OZ		 985 goto err_enable_device;
986 }
987
988 rc = pci_request_regions(dev, "arkfb");
989 if (rc < 0) {
594a8819 990 dev_err(info->device, "cannot reserve framebuffer region\n");
681e1473
OZ		 991 goto err_request_regions;
992 }
993
994 par->dac = ics5342_init(ark_dac_read_regs, ark_dac_write_regs, info);
995 if (! par->dac) {
996 rc = -ENOMEM;
594a8819 997 dev_err(info->device, "RAMDAC initialization failed\n");
681e1473
OZ		 998 goto err_dac;
999 }
1000
1001 info->fix.smem_start = pci_resource_start(dev, 0);
1002 info->fix.smem_len = pci_resource_len(dev, 0);
1003
1004 /* Map physical IO memory address into kernel space */
1005 info->screen_base = pci_iomap(dev, 0, 0);
1006 if (! info->screen_base) {
1007 rc = -ENOMEM;
594a8819 1008 dev_err(info->device, "iomap for framebuffer failed\n");
681e1473
OZ		 1009 goto err_iomap;
1010 }
1011
892c24ca
DM		 1012 bus_reg.start = 0;
1013 bus_reg.end = 64 * 1024;
1014
1015 vga_res.flags = IORESOURCE_IO;
1016
1017 pcibios_bus_to_resource(dev, &vga_res, &bus_reg);
1018
1019 par->state.vgabase = (void __iomem *) vga_res.start;
1020
681e1473 1021 /* FIXME get memsize */
c5e04633 1022 regval = vga_rseq(par->state.vgabase, 0x10);
681e1473
OZ		 1023 info->screen_size = (1 << (regval >> 6)) << 20;
1024 info->fix.smem_len = info->screen_size;
1025
1026 strcpy(info->fix.id, "ARK 2000PV");
1027 info->fix.mmio_start = 0;
1028 info->fix.mmio_len = 0;
1029 info->fix.type = FB_TYPE_PACKED_PIXELS;
1030 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1031 info->fix.ypanstep = 0;
1032 info->fix.accel = FB_ACCEL_NONE;
1033 info->pseudo_palette = (void*) (par->pseudo_palette);
1034
1035 /* Prepare startup mode */
1abf9172 1036 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
681e1473
OZ		 1037 if (! ((rc == 1) || (rc == 2))) {
1038 rc = -EINVAL;
594a8819 1039 dev_err(info->device, "mode %s not found\n", mode_option);
681e1473
OZ		 1040 goto err_find_mode;
1041 }
1042
1043 rc = fb_alloc_cmap(&info->cmap, 256, 0);
1044 if (rc < 0) {
594a8819 1045 dev_err(info->device, "cannot allocate colormap\n");
681e1473
OZ		 1046 goto err_alloc_cmap;
1047 }
1048
1049 rc = register_framebuffer(info);
1050 if (rc < 0) {
594a8819 1051 dev_err(info->device, "cannot register framebugger\n");
681e1473
OZ		 1052 goto err_reg_fb;
1053 }
1054
1055 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM\n", info->node, info->fix.id,
1056 pci_name(dev), info->fix.smem_len >> 20);
1057
1058 /* Record a reference to the driver data */
1059 pci_set_drvdata(dev, info);
1060
1061#ifdef CONFIG_MTRR
1062 if (mtrr) {
1063 par->mtrr_reg = -1;
1064 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
1065 }
1066#endif
1067
1068 return 0;
1069
1070 /* Error handling */
1071err_reg_fb:
1072 fb_dealloc_cmap(&info->cmap);
1073err_alloc_cmap:
1074err_find_mode:
1075 pci_iounmap(dev, info->screen_base);
1076err_iomap:
1077 dac_release(par->dac);
1078err_dac:
1079 pci_release_regions(dev);
1080err_request_regions:
1081/* pci_disable_device(dev); */
1082err_enable_device:
1083 framebuffer_release(info);
1084 return rc;
1085}
1086
1087/* PCI remove */
1088
48c68c4f 1089static void ark_pci_remove(struct pci_dev *dev)
681e1473
OZ		 1090{
1091 struct fb_info *info = pci_get_drvdata(dev);
681e1473
OZ		 1092
1093 if (info) {
38d473f9
OZ		 1094 struct arkfb_info *par = info->par;
1095
681e1473
OZ		 1096#ifdef CONFIG_MTRR
1097 if (par->mtrr_reg >= 0) {
1098 mtrr_del(par->mtrr_reg, 0, 0);
1099 par->mtrr_reg = -1;
1100 }
1101#endif
1102
1103 dac_release(par->dac);
1104 unregister_framebuffer(info);
1105 fb_dealloc_cmap(&info->cmap);
1106
1107 pci_iounmap(dev, info->screen_base);
1108 pci_release_regions(dev);
1109/* pci_disable_device(dev); */
1110
1111 pci_set_drvdata(dev, NULL);
1112 framebuffer_release(info);
1113 }
1114}
1115
1116
1117#ifdef CONFIG_PM
1118/* PCI suspend */
1119
1120static int ark_pci_suspend (struct pci_dev* dev, pm_message_t state)
1121{
1122 struct fb_info *info = pci_get_drvdata(dev);
1123 struct arkfb_info *par = info->par;
1124
594a8819 1125 dev_info(info->device, "suspend\n");
681e1473 1126
ac751efa 1127 console_lock();
681e1473
OZ		 1128 mutex_lock(&(par->open_lock));
1129
1130 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1131 mutex_unlock(&(par->open_lock));
ac751efa 1132 console_unlock();
681e1473
OZ		 1133 return 0;
1134 }
1135
1136 fb_set_suspend(info, 1);
1137
1138 pci_save_state(dev);
1139 pci_disable_device(dev);
1140 pci_set_power_state(dev, pci_choose_state(dev, state));
1141
1142 mutex_unlock(&(par->open_lock));
ac751efa 1143 console_unlock();
681e1473
OZ		 1144
1145 return 0;
1146}
1147
1148
1149/* PCI resume */
1150
1151static int ark_pci_resume (struct pci_dev* dev)
1152{
1153 struct fb_info *info = pci_get_drvdata(dev);
1154 struct arkfb_info *par = info->par;
1155
594a8819 1156 dev_info(info->device, "resume\n");
681e1473 1157
ac751efa 1158 console_lock();
681e1473
OZ		 1159 mutex_lock(&(par->open_lock));
1160
950d442a
JL		 1161 if (par->ref_count == 0)
1162 goto fail;
681e1473
OZ		 1163
1164 pci_set_power_state(dev, PCI_D0);
1165 pci_restore_state(dev);
1166
1167 if (pci_enable_device(dev))
1168 goto fail;
1169
1170 pci_set_master(dev);
1171
1172 arkfb_set_par(info);
1173 fb_set_suspend(info, 0);
1174
681e1473 1175fail:
950d442a 1176 mutex_unlock(&(par->open_lock));
ac751efa 1177 console_unlock();
681e1473
OZ		 1178 return 0;
1179}
1180#else
1181#define ark_pci_suspend NULL
1182#define ark_pci_resume NULL
1183#endif /* CONFIG_PM */
1184
1185/* List of boards that we are trying to support */
1186
48c68c4f 1187static struct pci_device_id ark_devices[] = {
681e1473
OZ		 1188 {PCI_DEVICE(0xEDD8, 0xA099)},
1189 {0, 0, 0, 0, 0, 0, 0}
1190};
1191
1192
1193MODULE_DEVICE_TABLE(pci, ark_devices);
1194
1195static struct pci_driver arkfb_pci_driver = {
1196 .name = "arkfb",
1197 .id_table = ark_devices,
1198 .probe = ark_pci_probe,
48c68c4f 1199 .remove = ark_pci_remove,
681e1473
OZ		 1200 .suspend = ark_pci_suspend,
1201 .resume = ark_pci_resume,
1202};
1203
1204/* Cleanup */
1205
1206static void __exit arkfb_cleanup(void)
1207{
1208 pr_debug("arkfb: cleaning up\n");
1209 pci_unregister_driver(&arkfb_pci_driver);
1210}
1211
1212/* Driver Initialisation */
1213
1214static int __init arkfb_init(void)
1215{
1216
1217#ifndef MODULE
1218 char *option = NULL;
1219
1220 if (fb_get_options("arkfb", &option))
1221 return -ENODEV;
1222
1223 if (option && *option)
1abf9172 1224 mode_option = option;
681e1473
OZ		 1225#endif
1226
1227 pr_debug("arkfb: initializing\n");
1228 return pci_register_driver(&arkfb_pci_driver);
1229}
1230
1231module_init(arkfb_init);
1232module_exit(arkfb_cleanup);
kernel source for telekom puls (alcatel/mediatek)