[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / host / xhci-dbg.c

/*
 * xHCI host controller driver
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include "xhci.h"

#define XHCI_INIT_VALUE 0x0

/* Add verbose debugging later, just print everything for now */

void xhci_dbg_regs(struct xhci_hcd *xhci)
{
	u32 temp;

	xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
			xhci->cap_regs);
	temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
	xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
			&xhci->cap_regs->hc_capbase, temp);
	xhci_dbg(xhci, "//   CAPLENGTH: 0x%x\n",
			(unsigned int) HC_LENGTH(temp));
#if 0
	xhci_dbg(xhci, "//   HCIVERSION: 0x%x\n",
			(unsigned int) HC_VERSION(temp));
#endif

	xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);

	temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
	xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
			&xhci->cap_regs->run_regs_off,
			(unsigned int) temp & RTSOFF_MASK);
	xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);

	temp = xhci_readl(xhci, &xhci->cap_regs->db_off);
	xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
	xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
}

static void xhci_print_cap_regs(struct xhci_hcd *xhci)
{
	u32 temp;

	xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);

	temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
	xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
			(unsigned int) temp);
	xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
			(unsigned int) HC_LENGTH(temp));
	xhci_dbg(xhci, "HCIVERSION: 0x%x\n",
			(unsigned int) HC_VERSION(temp));

	temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
	xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
			(unsigned int) temp);
	xhci_dbg(xhci, "  Max device slots: %u\n",
			(unsigned int) HCS_MAX_SLOTS(temp));
	xhci_dbg(xhci, "  Max interrupters: %u\n",
			(unsigned int) HCS_MAX_INTRS(temp));
	xhci_dbg(xhci, "  Max ports: %u\n",
			(unsigned int) HCS_MAX_PORTS(temp));

	temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
	xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
			(unsigned int) temp);
	xhci_dbg(xhci, "  Isoc scheduling threshold: %u\n",
			(unsigned int) HCS_IST(temp));
	xhci_dbg(xhci, "  Maximum allowed segments in event ring: %u\n",
			(unsigned int) HCS_ERST_MAX(temp));

	temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
	xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
			(unsigned int) temp);
	xhci_dbg(xhci, "  Worst case U1 device exit latency: %u\n",
			(unsigned int) HCS_U1_LATENCY(temp));
	xhci_dbg(xhci, "  Worst case U2 device exit latency: %u\n",
			(unsigned int) HCS_U2_LATENCY(temp));

	temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
	xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
	xhci_dbg(xhci, "  HC generates %s bit addresses\n",
			HCC_64BIT_ADDR(temp) ? "64" : "32");
	/* FIXME */
	xhci_dbg(xhci, "  FIXME: more HCCPARAMS debugging\n");

	temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
	xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
}

static void xhci_print_command_reg(struct xhci_hcd *xhci)
{
	u32 temp;

	temp = xhci_readl(xhci, &xhci->op_regs->command);
	xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
	xhci_dbg(xhci, "  HC is %s\n",
			(temp & CMD_RUN) ? "running" : "being stopped");
	xhci_dbg(xhci, "  HC has %sfinished hard reset\n",
			(temp & CMD_RESET) ? "not " : "");
	xhci_dbg(xhci, "  Event Interrupts %s\n",
			(temp & CMD_EIE) ? "enabled " : "disabled");
	xhci_dbg(xhci, "  Host System Error Interrupts %s\n",
			(temp & CMD_EIE) ? "enabled " : "disabled");
	xhci_dbg(xhci, "  HC has %sfinished light reset\n",
			(temp & CMD_LRESET) ? "not " : "");
}

static void xhci_print_status(struct xhci_hcd *xhci)
{
	u32 temp;

	temp = xhci_readl(xhci, &xhci->op_regs->status);
	xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
	xhci_dbg(xhci, "  Event ring is %sempty\n",
			(temp & STS_EINT) ? "not " : "");
	xhci_dbg(xhci, "  %sHost System Error\n",
			(temp & STS_FATAL) ? "WARNING: " : "No ");
	xhci_dbg(xhci, "  HC is %s\n",
			(temp & STS_HALT) ? "halted" : "running");
}

static void xhci_print_op_regs(struct xhci_hcd *xhci)
{
	xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
	xhci_print_command_reg(xhci);
	xhci_print_status(xhci);
}

static void xhci_print_ports(struct xhci_hcd *xhci)
{
	u32 __iomem *addr;
	int i, j;
	int ports;
	char *names[NUM_PORT_REGS] = {
		"status",
		"power",
		"link",
		"reserved",
	};

	ports = HCS_MAX_PORTS(xhci->hcs_params1);
	addr = &xhci->op_regs->port_status_base;
	for (i = 0; i < ports; i++) {
		for (j = 0; j < NUM_PORT_REGS; ++j) {
			xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
					addr, names[j],
					(unsigned int) xhci_readl(xhci, addr));
			addr++;
		}
	}
}

void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
{
	struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num];
	void __iomem *addr;
	u32 temp;
	u64 temp_64;

	addr = &ir_set->irq_pending;
	temp = xhci_readl(xhci, addr);
	if (temp == XHCI_INIT_VALUE)
		return;

	xhci_dbg(xhci, "  %p: ir_set[%i]\n", ir_set, set_num);

	xhci_dbg(xhci, "  %p: ir_set.pending = 0x%x\n", addr,
			(unsigned int)temp);

	addr = &ir_set->irq_control;
	temp = xhci_readl(xhci, addr);
	xhci_dbg(xhci, "  %p: ir_set.control = 0x%x\n", addr,
			(unsigned int)temp);

	addr = &ir_set->erst_size;
	temp = xhci_readl(xhci, addr);
	xhci_dbg(xhci, "  %p: ir_set.erst_size = 0x%x\n", addr,
			(unsigned int)temp);

	addr = &ir_set->rsvd;
	temp = xhci_readl(xhci, addr);
	if (temp != XHCI_INIT_VALUE)
		xhci_dbg(xhci, "  WARN: %p: ir_set.rsvd = 0x%x\n",
				addr, (unsigned int)temp);

	addr = &ir_set->erst_base;
	temp_64 = xhci_read_64(xhci, addr);
	xhci_dbg(xhci, "  %p: ir_set.erst_base = @%08llx\n",
			addr, temp_64);

	addr = &ir_set->erst_dequeue;
	temp_64 = xhci_read_64(xhci, addr);
	xhci_dbg(xhci, "  %p: ir_set.erst_dequeue = @%08llx\n",
			addr, temp_64);
}

void xhci_print_run_regs(struct xhci_hcd *xhci)
{
	u32 temp;
	int i;

	xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
	temp = xhci_readl(xhci, &xhci->run_regs->microframe_index);
	xhci_dbg(xhci, "  %p: Microframe index = 0x%x\n",
			&xhci->run_regs->microframe_index,
			(unsigned int) temp);
	for (i = 0; i < 7; ++i) {
		temp = xhci_readl(xhci, &xhci->run_regs->rsvd[i]);
		if (temp != XHCI_INIT_VALUE)
			xhci_dbg(xhci, "  WARN: %p: Rsvd[%i] = 0x%x\n",
					&xhci->run_regs->rsvd[i],
					i, (unsigned int) temp);
	}
}

void xhci_print_registers(struct xhci_hcd *xhci)
{
	xhci_print_cap_regs(xhci);
	xhci_print_op_regs(xhci);
	xhci_print_ports(xhci);
}

void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb)
{
	int i;
	for (i = 0; i < 4; ++i)
		xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
				i*4, trb->generic.field[i]);
}

/**
 * Debug a transfer request block (TRB).
 */
void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
{
	u64	address;
	u32	type = xhci_readl(xhci, &trb->link.control) & TRB_TYPE_BITMASK;

	switch (type) {
	case TRB_TYPE(TRB_LINK):
		xhci_dbg(xhci, "Link TRB:\n");
		xhci_print_trb_offsets(xhci, trb);

		address = trb->link.segment_ptr;
		xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);

		xhci_dbg(xhci, "Interrupter target = 0x%x\n",
				GET_INTR_TARGET(trb->link.intr_target));
		xhci_dbg(xhci, "Cycle bit = %u\n",
				(unsigned int) (trb->link.control & TRB_CYCLE));
		xhci_dbg(xhci, "Toggle cycle bit = %u\n",
				(unsigned int) (trb->link.control & LINK_TOGGLE));
		xhci_dbg(xhci, "No Snoop bit = %u\n",
				(unsigned int) (trb->link.control & TRB_NO_SNOOP));
		break;
	case TRB_TYPE(TRB_TRANSFER):
		address = trb->trans_event.buffer;
		/*
		 * FIXME: look at flags to figure out if it's an address or if
		 * the data is directly in the buffer field.
		 */
		xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
		break;
	case TRB_TYPE(TRB_COMPLETION):
		address = trb->event_cmd.cmd_trb;
		xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
		xhci_dbg(xhci, "Completion status = %u\n",
				(unsigned int) GET_COMP_CODE(trb->event_cmd.status));
		xhci_dbg(xhci, "Flags = 0x%x\n", (unsigned int) trb->event_cmd.flags);
		break;
	default:
		xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
				(unsigned int) type>>10);
		xhci_print_trb_offsets(xhci, trb);
		break;
	}
}

/**
 * Debug a segment with an xHCI ring.
 *
 * @return The Link TRB of the segment, or NULL if there is no Link TRB
 * (which is a bug, since all segments must have a Link TRB).
 *
 * Prints out all TRBs in the segment, even those after the Link TRB.
 *
 * XXX: should we print out TRBs that the HC owns?  As long as we don't
 * write, that should be fine...  We shouldn't expect that the memory pointed to
 * by the TRB is valid at all.  Do we care about ones the HC owns?  Probably,
 * for HC debugging.
 */
void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
{
	int i;
	u32 addr = (u32) seg->dma;
	union xhci_trb *trb = seg->trbs;

	for (i = 0; i < TRBS_PER_SEGMENT; ++i) {
		trb = &seg->trbs[i];
		xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", addr,
				lower_32_bits(trb->link.segment_ptr),
				upper_32_bits(trb->link.segment_ptr),
				(unsigned int) trb->link.intr_target,
				(unsigned int) trb->link.control);
		addr += sizeof(*trb);
	}
}

void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring)
{
	xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",
			ring->dequeue,
			(unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg,
							    ring->dequeue));
	xhci_dbg(xhci, "Ring deq updated %u times\n",
			ring->deq_updates);
	xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",
			ring->enqueue,
			(unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg,
							    ring->enqueue));
	xhci_dbg(xhci, "Ring enq updated %u times\n",
			ring->enq_updates);
}

/**
 * Debugging for an xHCI ring, which is a queue broken into multiple segments.
 *
 * Print out each segment in the ring.  Check that the DMA address in
 * each link segment actually matches the segment's stored DMA address.
 * Check that the link end bit is only set at the end of the ring.
 * Check that the dequeue and enqueue pointers point to real data in this ring
 * (not some other ring).
 */
void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring)
{
	/* FIXME: Throw an error if any segment doesn't have a Link TRB */
	struct xhci_segment *seg;
	struct xhci_segment *first_seg = ring->first_seg;
	xhci_debug_segment(xhci, first_seg);

	if (!ring->enq_updates && !ring->deq_updates) {
		xhci_dbg(xhci, "  Ring has not been updated\n");
		return;
	}
	for (seg = first_seg->next; seg != first_seg; seg = seg->next)
		xhci_debug_segment(xhci, seg);
}

void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
		unsigned int slot_id, unsigned int ep_index,
		struct xhci_virt_ep *ep)
{
	int i;
	struct xhci_ring *ring;

	if (ep->ep_state & EP_HAS_STREAMS) {
		for (i = 1; i < ep->stream_info->num_streams; i++) {
			ring = ep->stream_info->stream_rings[i];
			xhci_dbg(xhci, "Dev %d endpoint %d stream ID %d:\n",
				slot_id, ep_index, i);
			xhci_debug_segment(xhci, ring->deq_seg);
		}
	} else {
		ring = ep->ring;
		if (!ring)
			return;
		xhci_dbg(xhci, "Dev %d endpoint ring %d:\n",
				slot_id, ep_index);
		xhci_debug_segment(xhci, ring->deq_seg);
	}
}

void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
{
	u32 addr = (u32) erst->erst_dma_addr;
	int i;
	struct xhci_erst_entry *entry;

	for (i = 0; i < erst->num_entries; ++i) {
		entry = &erst->entries[i];
		xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n",
				(unsigned int) addr,
				lower_32_bits(entry->seg_addr),
				upper_32_bits(entry->seg_addr),
				(unsigned int) entry->seg_size,
				(unsigned int) entry->rsvd);
		addr += sizeof(*entry);
	}
}

void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
{
	u64 val;

	val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
	xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
			lower_32_bits(val));
	xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
			upper_32_bits(val));
}

/* Print the last 32 bytes for 64-byte contexts */
static void dbg_rsvd64(struct xhci_hcd *xhci, u64 *ctx, dma_addr_t dma)
{
	int i;
	for (i = 0; i < 4; ++i) {
		xhci_dbg(xhci, "@%p (virt) @%08llx "
			 "(dma) %#08llx - rsvd64[%d]\n",
			 &ctx[4 + i], (unsigned long long)dma,
			 ctx[4 + i], i);
		dma += 8;
	}
}

char *xhci_get_slot_state(struct xhci_hcd *xhci,
		struct xhci_container_ctx *ctx)
{
	struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);

	switch (GET_SLOT_STATE(slot_ctx->dev_state)) {
	case 0:
		return "enabled/disabled";
	case 1:
		return "default";
	case 2:
		return "addressed";
	case 3:
		return "configured";
	default:
		return "reserved";
	}
}

void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
{
	/* Fields are 32 bits wide, DMA addresses are in bytes */
	int field_size = 32 / 8;
	int i;

	struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
	dma_addr_t dma = ctx->dma +
		((unsigned long)slot_ctx - (unsigned long)ctx->bytes);
	int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);

	xhci_dbg(xhci, "Slot Context:\n");
	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",
			&slot_ctx->dev_info,
			(unsigned long long)dma, slot_ctx->dev_info);
	dma += field_size;
	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",
			&slot_ctx->dev_info2,
			(unsigned long long)dma, slot_ctx->dev_info2);
	dma += field_size;
	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",
			&slot_ctx->tt_info,
			(unsigned long long)dma, slot_ctx->tt_info);
	dma += field_size;
	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",
			&slot_ctx->dev_state,
			(unsigned long long)dma, slot_ctx->dev_state);
	dma += field_size;
	for (i = 0; i < 4; ++i) {
		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
				&slot_ctx->reserved[i], (unsigned long long)dma,
				slot_ctx->reserved[i], i);
		dma += field_size;
	}

	if (csz)
		dbg_rsvd64(xhci, (u64 *)slot_ctx, dma);
}

void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
		     struct xhci_container_ctx *ctx,
		     unsigned int last_ep)
{
	int i, j;
	int last_ep_ctx = 31;
	/* Fields are 32 bits wide, DMA addresses are in bytes */
	int field_size = 32 / 8;
	int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);

	if (last_ep < 31)
		last_ep_ctx = last_ep + 1;
	for (i = 0; i < last_ep_ctx; ++i) {
		struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i);
		dma_addr_t dma = ctx->dma +
			((unsigned long)ep_ctx - (unsigned long)ctx->bytes);

		xhci_dbg(xhci, "Endpoint %02d Context:\n", i);
		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
				&ep_ctx->ep_info,
				(unsigned long long)dma, ep_ctx->ep_info);
		dma += field_size;
		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",
				&ep_ctx->ep_info2,
				(unsigned long long)dma, ep_ctx->ep_info2);
		dma += field_size;
		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n",
				&ep_ctx->deq,
				(unsigned long long)dma, ep_ctx->deq);
		dma += 2*field_size;
		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",
				&ep_ctx->tx_info,
				(unsigned long long)dma, ep_ctx->tx_info);
		dma += field_size;
		for (j = 0; j < 3; ++j) {
			xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
					&ep_ctx->reserved[j],
					(unsigned long long)dma,
					ep_ctx->reserved[j], j);
			dma += field_size;
		}

		if (csz)
			dbg_rsvd64(xhci, (u64 *)ep_ctx, dma);
	}
}

void xhci_dbg_ctx(struct xhci_hcd *xhci,
		  struct xhci_container_ctx *ctx,
		  unsigned int last_ep)
{
	int i;
	/* Fields are 32 bits wide, DMA addresses are in bytes */
	int field_size = 32 / 8;
	struct xhci_slot_ctx *slot_ctx;
	dma_addr_t dma = ctx->dma;
	int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);

	if (ctx->type == XHCI_CTX_TYPE_INPUT) {
		struct xhci_input_control_ctx *ctrl_ctx =
			xhci_get_input_control_ctx(xhci, ctx);
		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",
			 &ctrl_ctx->drop_flags, (unsigned long long)dma,
			 ctrl_ctx->drop_flags);
		dma += field_size;
		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",
			 &ctrl_ctx->add_flags, (unsigned long long)dma,
			 ctrl_ctx->add_flags);
		dma += field_size;
		for (i = 0; i < 6; ++i) {
			xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",
				 &ctrl_ctx->rsvd2[i], (unsigned long long)dma,
				 ctrl_ctx->rsvd2[i], i);
			dma += field_size;
		}

		if (csz)
			dbg_rsvd64(xhci, (u64 *)ctrl_ctx, dma);
	}

	slot_ctx = xhci_get_slot_ctx(xhci, ctx);
	xhci_dbg_slot_ctx(xhci, ctx);
	xhci_dbg_ep_ctx(xhci, ctx, last_ep);
}
Commit	Line	Data
74c68741 SS	1	/*
	2	* xHCI host controller driver
	3	*
	4	* Copyright (C) 2008 Intel Corp.
	5	*
	6	* Author: Sarah Sharp
	7	* Some code borrowed from the Linux EHCI driver.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software Foundation,
	20	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include "xhci.h"
	24
	25	#define XHCI_INIT_VALUE 0x0
	26
	27	/* Add verbose debugging later, just print everything for now */
	28
	29	void xhci_dbg_regs(struct xhci_hcd *xhci)
	30	{
	31	u32 temp;
	32
700e2052 GKH	33	xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
700e2052 GKH	34	xhci->cap_regs);
74c68741	35	temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
700e2052 GKH	36	xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
700e2052 GKH	37	&xhci->cap_regs->hc_capbase, temp);
74c68741 SS	38	xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n",
	39	(unsigned int) HC_LENGTH(temp));
	40	#if 0
	41	xhci_dbg(xhci, "// HCIVERSION: 0x%x\n",
	42	(unsigned int) HC_VERSION(temp));
	43	#endif
	44
700e2052	45	xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
74c68741 SS	46
74c68741 SS	47	temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
700e2052 GKH	48	xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
700e2052 GKH	49	&xhci->cap_regs->run_regs_off,
74c68741	50	(unsigned int) temp & RTSOFF_MASK);
700e2052	51	xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
74c68741 SS	52
74c68741 SS	53	temp = xhci_readl(xhci, &xhci->cap_regs->db_off);
700e2052 GKH	54	xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
700e2052 GKH	55	xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
74c68741 SS	56	}
74c68741 SS	57
23e3be11	58	static void xhci_print_cap_regs(struct xhci_hcd *xhci)
74c68741 SS	59	{
	60	u32 temp;
	61
700e2052	62	xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
74c68741 SS	63
	64	temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
	65	xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
	66	(unsigned int) temp);
	67	xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
	68	(unsigned int) HC_LENGTH(temp));
	69	xhci_dbg(xhci, "HCIVERSION: 0x%x\n",
	70	(unsigned int) HC_VERSION(temp));
	71
	72	temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
	73	xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
	74	(unsigned int) temp);
	75	xhci_dbg(xhci, " Max device slots: %u\n",
	76	(unsigned int) HCS_MAX_SLOTS(temp));
	77	xhci_dbg(xhci, " Max interrupters: %u\n",
	78	(unsigned int) HCS_MAX_INTRS(temp));
	79	xhci_dbg(xhci, " Max ports: %u\n",
	80	(unsigned int) HCS_MAX_PORTS(temp));
	81
	82	temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
	83	xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
	84	(unsigned int) temp);
	85	xhci_dbg(xhci, " Isoc scheduling threshold: %u\n",
	86	(unsigned int) HCS_IST(temp));
	87	xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n",
	88	(unsigned int) HCS_ERST_MAX(temp));
	89
	90	temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
	91	xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
	92	(unsigned int) temp);
	93	xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n",
	94	(unsigned int) HCS_U1_LATENCY(temp));
	95	xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n",
	96	(unsigned int) HCS_U2_LATENCY(temp));
	97
	98	temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
	99	xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
	100	xhci_dbg(xhci, " HC generates %s bit addresses\n",
	101	HCC_64BIT_ADDR(temp) ? "64" : "32");
	102	/* FIXME */
	103	xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n");
	104
	105	temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
	106	xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
	107	}
	108
23e3be11	109	static void xhci_print_command_reg(struct xhci_hcd *xhci)
74c68741 SS	110	{
	111	u32 temp;
	112
	113	temp = xhci_readl(xhci, &xhci->op_regs->command);
	114	xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
	115	xhci_dbg(xhci, " HC is %s\n",
	116	(temp & CMD_RUN) ? "running" : "being stopped");
	117	xhci_dbg(xhci, " HC has %sfinished hard reset\n",
	118	(temp & CMD_RESET) ? "not " : "");
	119	xhci_dbg(xhci, " Event Interrupts %s\n",
	120	(temp & CMD_EIE) ? "enabled " : "disabled");
	121	xhci_dbg(xhci, " Host System Error Interrupts %s\n",
	122	(temp & CMD_EIE) ? "enabled " : "disabled");
	123	xhci_dbg(xhci, " HC has %sfinished light reset\n",
	124	(temp & CMD_LRESET) ? "not " : "");
	125	}
	126
23e3be11	127	static void xhci_print_status(struct xhci_hcd *xhci)
74c68741 SS	128	{
	129	u32 temp;
	130
	131	temp = xhci_readl(xhci, &xhci->op_regs->status);
	132	xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
	133	xhci_dbg(xhci, " Event ring is %sempty\n",
	134	(temp & STS_EINT) ? "not " : "");
	135	xhci_dbg(xhci, " %sHost System Error\n",
	136	(temp & STS_FATAL) ? "WARNING: " : "No ");
	137	xhci_dbg(xhci, " HC is %s\n",
	138	(temp & STS_HALT) ? "halted" : "running");
	139	}
	140
23e3be11	141	static void xhci_print_op_regs(struct xhci_hcd *xhci)
74c68741	142	{
700e2052	143	xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
74c68741 SS	144	xhci_print_command_reg(xhci);
	145	xhci_print_status(xhci);
	146	}
	147
23e3be11	148	static void xhci_print_ports(struct xhci_hcd *xhci)
0f2a7930 SS	149	{
	150	u32 __iomem *addr;
	151	int i, j;
	152	int ports;
	153	char *names[NUM_PORT_REGS] = {
	154	"status",
	155	"power",
	156	"link",
	157	"reserved",
	158	};
	159
	160	ports = HCS_MAX_PORTS(xhci->hcs_params1);
	161	addr = &xhci->op_regs->port_status_base;
	162	for (i = 0; i < ports; i++) {
	163	for (j = 0; j < NUM_PORT_REGS; ++j) {
700e2052 GKH	164	xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
700e2052 GKH	165	addr, names[j],
0f2a7930 SS	166	(unsigned int) xhci_readl(xhci, addr));
	167	addr++;
	168	}
	169	}
	170	}
	171
09ece30e	172	void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
74c68741	173	{
09ece30e DT	174	struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num];
09ece30e DT	175	void __iomem *addr;
74c68741	176	u32 temp;
8e595a5d	177	u64 temp_64;
74c68741 SS	178
	179	addr = &ir_set->irq_pending;
	180	temp = xhci_readl(xhci, addr);
	181	if (temp == XHCI_INIT_VALUE)
	182	return;
	183
700e2052	184	xhci_dbg(xhci, " %p: ir_set[%i]\n", ir_set, set_num);
74c68741	185
700e2052 GKH	186	xhci_dbg(xhci, " %p: ir_set.pending = 0x%x\n", addr,
700e2052 GKH	187	(unsigned int)temp);
74c68741 SS	188
	189	addr = &ir_set->irq_control;
	190	temp = xhci_readl(xhci, addr);
700e2052 GKH	191	xhci_dbg(xhci, " %p: ir_set.control = 0x%x\n", addr,
700e2052 GKH	192	(unsigned int)temp);
74c68741 SS	193
	194	addr = &ir_set->erst_size;
	195	temp = xhci_readl(xhci, addr);
700e2052 GKH	196	xhci_dbg(xhci, " %p: ir_set.erst_size = 0x%x\n", addr,
700e2052 GKH	197	(unsigned int)temp);
74c68741 SS	198
	199	addr = &ir_set->rsvd;
	200	temp = xhci_readl(xhci, addr);
	201	if (temp != XHCI_INIT_VALUE)
700e2052 GKH	202	xhci_dbg(xhci, " WARN: %p: ir_set.rsvd = 0x%x\n",
700e2052 GKH	203	addr, (unsigned int)temp);
74c68741	204
8e595a5d SS	205	addr = &ir_set->erst_base;
	206	temp_64 = xhci_read_64(xhci, addr);
	207	xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n",
	208	addr, temp_64);
74c68741	209
8e595a5d SS	210	addr = &ir_set->erst_dequeue;
	211	temp_64 = xhci_read_64(xhci, addr);
	212	xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n",
	213	addr, temp_64);
74c68741 SS	214	}
	215
	216	void xhci_print_run_regs(struct xhci_hcd *xhci)
	217	{
	218	u32 temp;
	219	int i;
	220
700e2052	221	xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
74c68741	222	temp = xhci_readl(xhci, &xhci->run_regs->microframe_index);
700e2052 GKH	223	xhci_dbg(xhci, " %p: Microframe index = 0x%x\n",
700e2052 GKH	224	&xhci->run_regs->microframe_index,
74c68741 SS	225	(unsigned int) temp);
	226	for (i = 0; i < 7; ++i) {
	227	temp = xhci_readl(xhci, &xhci->run_regs->rsvd[i]);
	228	if (temp != XHCI_INIT_VALUE)
700e2052 GKH	229	xhci_dbg(xhci, " WARN: %p: Rsvd[%i] = 0x%x\n",
700e2052 GKH	230	&xhci->run_regs->rsvd[i],
74c68741 SS	231	i, (unsigned int) temp);
	232	}
	233	}
	234
	235	void xhci_print_registers(struct xhci_hcd *xhci)
	236	{
	237	xhci_print_cap_regs(xhci);
	238	xhci_print_op_regs(xhci);
0f2a7930	239	xhci_print_ports(xhci);
74c68741	240	}
0ebbab37	241
7f84eef0 SS	242	void xhci_print_trb_offsets(struct xhci_hcd xhci, union xhci_trb trb)
	243	{
	244	int i;
	245	for (i = 0; i < 4; ++i)
	246	xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
	247	i*4, trb->generic.field[i]);
	248	}
	249
	250	/**
	251	* Debug a transfer request block (TRB).
	252	*/
	253	void xhci_debug_trb(struct xhci_hcd xhci, union xhci_trb trb)
	254	{
	255	u64 address;
	256	u32 type = xhci_readl(xhci, &trb->link.control) & TRB_TYPE_BITMASK;
	257
	258	switch (type) {
	259	case TRB_TYPE(TRB_LINK):
	260	xhci_dbg(xhci, "Link TRB:\n");
	261	xhci_print_trb_offsets(xhci, trb);
	262
8e595a5d	263	address = trb->link.segment_ptr;
7f84eef0 SS	264	xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
	265
	266	xhci_dbg(xhci, "Interrupter target = 0x%x\n",
	267	GET_INTR_TARGET(trb->link.intr_target));
	268	xhci_dbg(xhci, "Cycle bit = %u\n",
	269	(unsigned int) (trb->link.control & TRB_CYCLE));
	270	xhci_dbg(xhci, "Toggle cycle bit = %u\n",
	271	(unsigned int) (trb->link.control & LINK_TOGGLE));
	272	xhci_dbg(xhci, "No Snoop bit = %u\n",
	273	(unsigned int) (trb->link.control & TRB_NO_SNOOP));
	274	break;
	275	case TRB_TYPE(TRB_TRANSFER):
8e595a5d	276	address = trb->trans_event.buffer;
7f84eef0 SS	277	/*
	278	* FIXME: look at flags to figure out if it's an address or if
	279	* the data is directly in the buffer field.
	280	*/
	281	xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
	282	break;
	283	case TRB_TYPE(TRB_COMPLETION):
8e595a5d	284	address = trb->event_cmd.cmd_trb;
7f84eef0 SS	285	xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
	286	xhci_dbg(xhci, "Completion status = %u\n",
	287	(unsigned int) GET_COMP_CODE(trb->event_cmd.status));
	288	xhci_dbg(xhci, "Flags = 0x%x\n", (unsigned int) trb->event_cmd.flags);
	289	break;
	290	default:
	291	xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
	292	(unsigned int) type>>10);
	293	xhci_print_trb_offsets(xhci, trb);
	294	break;
	295	}
	296	}
0ebbab37 SS	297
	298	/**
	299	* Debug a segment with an xHCI ring.
	300	*
	301	* @return The Link TRB of the segment, or NULL if there is no Link TRB
	302	* (which is a bug, since all segments must have a Link TRB).
	303	*
	304	* Prints out all TRBs in the segment, even those after the Link TRB.
	305	*
	306	* XXX: should we print out TRBs that the HC owns? As long as we don't
	307	* write, that should be fine... We shouldn't expect that the memory pointed to
	308	* by the TRB is valid at all. Do we care about ones the HC owns? Probably,
	309	* for HC debugging.
	310	*/
	311	void xhci_debug_segment(struct xhci_hcd xhci, struct xhci_segment seg)
	312	{
	313	int i;
	314	u32 addr = (u32) seg->dma;
	315	union xhci_trb *trb = seg->trbs;
	316
	317	for (i = 0; i < TRBS_PER_SEGMENT; ++i) {
	318	trb = &seg->trbs[i];
	319	xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", addr,
8e595a5d SS	320	lower_32_bits(trb->link.segment_ptr),
8e595a5d SS	321	upper_32_bits(trb->link.segment_ptr),
0ebbab37 SS	322	(unsigned int) trb->link.intr_target,
	323	(unsigned int) trb->link.control);
	324	addr += sizeof(*trb);
	325	}
	326	}
	327
7f84eef0 SS	328	void xhci_dbg_ring_ptrs(struct xhci_hcd xhci, struct xhci_ring ring)
7f84eef0 SS	329	{
700e2052 GKH	330	xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",
700e2052 GKH	331	ring->dequeue,
23e3be11	332	(unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg,
700e2052	333	ring->dequeue));
7f84eef0 SS	334	xhci_dbg(xhci, "Ring deq updated %u times\n",
7f84eef0 SS	335	ring->deq_updates);
700e2052 GKH	336	xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",
700e2052 GKH	337	ring->enqueue,
23e3be11	338	(unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg,
700e2052	339	ring->enqueue));
7f84eef0 SS	340	xhci_dbg(xhci, "Ring enq updated %u times\n",
	341	ring->enq_updates);
	342	}
	343
0ebbab37 SS	344	/**
	345	* Debugging for an xHCI ring, which is a queue broken into multiple segments.
	346	*
	347	* Print out each segment in the ring. Check that the DMA address in
	348	* each link segment actually matches the segment's stored DMA address.
	349	* Check that the link end bit is only set at the end of the ring.
	350	* Check that the dequeue and enqueue pointers point to real data in this ring
	351	* (not some other ring).
	352	*/
	353	void xhci_debug_ring(struct xhci_hcd xhci, struct xhci_ring ring)
	354	{
	355	/* FIXME: Throw an error if any segment doesn't have a Link TRB */
	356	struct xhci_segment *seg;
	357	struct xhci_segment *first_seg = ring->first_seg;
	358	xhci_debug_segment(xhci, first_seg);
	359
7f84eef0 SS	360	if (!ring->enq_updates && !ring->deq_updates) {
	361	xhci_dbg(xhci, " Ring has not been updated\n");
	362	return;
	363	}
0ebbab37 SS	364	for (seg = first_seg->next; seg != first_seg; seg = seg->next)
	365	xhci_debug_segment(xhci, seg);
	366	}
	367
e9df17eb SS	368	void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
	369	unsigned int slot_id, unsigned int ep_index,
	370	struct xhci_virt_ep *ep)
	371	{
	372	int i;
	373	struct xhci_ring *ring;
	374
	375	if (ep->ep_state & EP_HAS_STREAMS) {
	376	for (i = 1; i < ep->stream_info->num_streams; i++) {
	377	ring = ep->stream_info->stream_rings[i];
	378	xhci_dbg(xhci, "Dev %d endpoint %d stream ID %d:\n",
	379	slot_id, ep_index, i);
	380	xhci_debug_segment(xhci, ring->deq_seg);
	381	}
	382	} else {
	383	ring = ep->ring;
	384	if (!ring)
	385	return;
	386	xhci_dbg(xhci, "Dev %d endpoint ring %d:\n",
	387	slot_id, ep_index);
	388	xhci_debug_segment(xhci, ring->deq_seg);
	389	}
	390	}
	391
0ebbab37 SS	392	void xhci_dbg_erst(struct xhci_hcd xhci, struct xhci_erst erst)
	393	{
	394	u32 addr = (u32) erst->erst_dma_addr;
	395	int i;
	396	struct xhci_erst_entry *entry;
	397
	398	for (i = 0; i < erst->num_entries; ++i) {
	399	entry = &erst->entries[i];
	400	xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n",
	401	(unsigned int) addr,
8e595a5d SS	402	lower_32_bits(entry->seg_addr),
8e595a5d SS	403	upper_32_bits(entry->seg_addr),
0ebbab37 SS	404	(unsigned int) entry->seg_size,
	405	(unsigned int) entry->rsvd);
	406	addr += sizeof(*entry);
	407	}
	408	}
	409
	410	void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
	411	{
8e595a5d	412	u64 val;
0ebbab37	413
8e595a5d SS	414	val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
	415	xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
	416	lower_32_bits(val));
	417	xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
	418	upper_32_bits(val));
0ebbab37	419	}
3ffbba95	420
d115b048 JY	421	/* Print the last 32 bytes for 64-byte contexts */
	422	static void dbg_rsvd64(struct xhci_hcd xhci, u64 ctx, dma_addr_t dma)
	423	{
	424	int i;
	425	for (i = 0; i < 4; ++i) {
	426	xhci_dbg(xhci, "@%p (virt) @%08llx "
	427	"(dma) %#08llx - rsvd64[%d]\n",
	428	&ctx[4 + i], (unsigned long long)dma,
	429	ctx[4 + i], i);
	430	dma += 8;
	431	}
	432	}
	433
9c9a7dbf	434	char xhci_get_slot_state(struct xhci_hcd xhci,
2a8f82c4 SS	435	struct xhci_container_ctx *ctx)
	436	{
	437	struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
	438
	439	switch (GET_SLOT_STATE(slot_ctx->dev_state)) {
	440	case 0:
	441	return "enabled/disabled";
	442	case 1:
	443	return "default";
	444	case 2:
	445	return "addressed";
	446	case 3:
	447	return "configured";
	448	default:
	449	return "reserved";
	450	}
	451	}
	452
d115b048	453	void xhci_dbg_slot_ctx(struct xhci_hcd xhci, struct xhci_container_ctx ctx)
3ffbba95	454	{
3ffbba95 SS	455	/* Fields are 32 bits wide, DMA addresses are in bytes */
3ffbba95 SS	456	int field_size = 32 / 8;
28c2d2ef	457	int i;
3ffbba95	458
d115b048	459	struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
018218d1 SS	460	dma_addr_t dma = ctx->dma +
018218d1 SS	461	((unsigned long)slot_ctx - (unsigned long)ctx->bytes);
d115b048 JY	462	int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
d115b048 JY	463
3ffbba95	464	xhci_dbg(xhci, "Slot Context:\n");
700e2052	465	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",
d115b048 JY	466	&slot_ctx->dev_info,
d115b048 JY	467	(unsigned long long)dma, slot_ctx->dev_info);
3ffbba95	468	dma += field_size;
700e2052	469	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",
d115b048 JY	470	&slot_ctx->dev_info2,
d115b048 JY	471	(unsigned long long)dma, slot_ctx->dev_info2);
3ffbba95	472	dma += field_size;
700e2052	473	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",
d115b048 JY	474	&slot_ctx->tt_info,
d115b048 JY	475	(unsigned long long)dma, slot_ctx->tt_info);
3ffbba95	476	dma += field_size;
700e2052	477	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",
d115b048 JY	478	&slot_ctx->dev_state,
d115b048 JY	479	(unsigned long long)dma, slot_ctx->dev_state);
3ffbba95	480	dma += field_size;
d8f1a5ed	481	for (i = 0; i < 4; ++i) {
700e2052	482	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
d115b048 JY	483	&slot_ctx->reserved[i], (unsigned long long)dma,
d115b048 JY	484	slot_ctx->reserved[i], i);
3ffbba95 SS	485	dma += field_size;
	486	}
	487
d115b048 JY	488	if (csz)
d115b048 JY	489	dbg_rsvd64(xhci, (u64 *)slot_ctx, dma);
28c2d2ef SS	490	}
28c2d2ef SS	491
d115b048 JY	492	void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
	493	struct xhci_container_ctx *ctx,
	494	unsigned int last_ep)
28c2d2ef SS	495	{
	496	int i, j;
	497	int last_ep_ctx = 31;
	498	/* Fields are 32 bits wide, DMA addresses are in bytes */
	499	int field_size = 32 / 8;
d115b048	500	int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
28c2d2ef	501
3ffbba95 SS	502	if (last_ep < 31)
	503	last_ep_ctx = last_ep + 1;
	504	for (i = 0; i < last_ep_ctx; ++i) {
d115b048 JY	505	struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i);
d115b048 JY	506	dma_addr_t dma = ctx->dma +
018218d1	507	((unsigned long)ep_ctx - (unsigned long)ctx->bytes);
d115b048	508
3ffbba95	509	xhci_dbg(xhci, "Endpoint %02d Context:\n", i);
700e2052	510	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
d115b048 JY	511	&ep_ctx->ep_info,
d115b048 JY	512	(unsigned long long)dma, ep_ctx->ep_info);
3ffbba95	513	dma += field_size;
700e2052	514	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",
d115b048 JY	515	&ep_ctx->ep_info2,
d115b048 JY	516	(unsigned long long)dma, ep_ctx->ep_info2);
3ffbba95	517	dma += field_size;
8e595a5d	518	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n",
d115b048 JY	519	&ep_ctx->deq,
d115b048 JY	520	(unsigned long long)dma, ep_ctx->deq);
8e595a5d	521	dma += 2*field_size;
700e2052	522	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",
d115b048 JY	523	&ep_ctx->tx_info,
d115b048 JY	524	(unsigned long long)dma, ep_ctx->tx_info);
3ffbba95 SS	525	dma += field_size;
3ffbba95 SS	526	for (j = 0; j < 3; ++j) {
700e2052	527	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
d115b048	528	&ep_ctx->reserved[j],
700e2052	529	(unsigned long long)dma,
d115b048	530	ep_ctx->reserved[j], j);
3ffbba95 SS	531	dma += field_size;
3ffbba95 SS	532	}
d115b048 JY	533
	534	if (csz)
	535	dbg_rsvd64(xhci, (u64 *)ep_ctx, dma);
3ffbba95	536	}
28c2d2ef SS	537	}
28c2d2ef SS	538
d115b048 JY	539	void xhci_dbg_ctx(struct xhci_hcd *xhci,
	540	struct xhci_container_ctx *ctx,
	541	unsigned int last_ep)
28c2d2ef SS	542	{
	543	int i;
	544	/* Fields are 32 bits wide, DMA addresses are in bytes */
	545	int field_size = 32 / 8;
d115b048 JY	546	struct xhci_slot_ctx *slot_ctx;
	547	dma_addr_t dma = ctx->dma;
	548	int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
	549
	550	if (ctx->type == XHCI_CTX_TYPE_INPUT) {
	551	struct xhci_input_control_ctx *ctrl_ctx =
	552	xhci_get_input_control_ctx(xhci, ctx);
	553	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",
	554	&ctrl_ctx->drop_flags, (unsigned long long)dma,
	555	ctrl_ctx->drop_flags);
28c2d2ef	556	dma += field_size;
d115b048 JY	557	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",
	558	&ctrl_ctx->add_flags, (unsigned long long)dma,
	559	ctrl_ctx->add_flags);
	560	dma += field_size;
	561	for (i = 0; i < 6; ++i) {
	562	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",
	563	&ctrl_ctx->rsvd2[i], (unsigned long long)dma,
	564	ctrl_ctx->rsvd2[i], i);
	565	dma += field_size;
	566	}
	567
	568	if (csz)
	569	dbg_rsvd64(xhci, (u64 *)ctrl_ctx, dma);
28c2d2ef	570	}
28c2d2ef	571
d115b048 JY	572	slot_ctx = xhci_get_slot_ctx(xhci, ctx);
	573	xhci_dbg_slot_ctx(xhci, ctx);
	574	xhci_dbg_ep_ctx(xhci, ctx, last_ep);
3ffbba95	575	}