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TTY: move low_latency to tty_port
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / synclink.c
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1da177e4 1/*
0ff1b2c8 2 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
1da177e4
LT		 3 *
4 * Device driver for Microgate SyncLink ISA and PCI
5 * high speed multiprotocol serial adapters.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 *
14 * Original release 01/11/99
15 *
16 * This code is released under the GNU General Public License (GPL)
17 *
18 * This driver is primarily intended for use in synchronous
19 * HDLC mode. Asynchronous mode is also provided.
20 *
21 * When operating in synchronous mode, each call to mgsl_write()
22 * contains exactly one complete HDLC frame. Calling mgsl_put_char
23 * will start assembling an HDLC frame that will not be sent until
24 * mgsl_flush_chars or mgsl_write is called.
25 *
26 * Synchronous receive data is reported as complete frames. To accomplish
27 * this, the TTY flip buffer is bypassed (too small to hold largest
28 * frame and may fragment frames) and the line discipline
29 * receive entry point is called directly.
30 *
31 * This driver has been tested with a slightly modified ppp.c driver
32 * for synchronous PPP.
33 *
34 * 2000/02/16
35 * Added interface for syncppp.c driver (an alternate synchronous PPP
36 * implementation that also supports Cisco HDLC). Each device instance
37 * registers as a tty device AND a network device (if dosyncppp option
38 * is set for the device). The functionality is determined by which
39 * device interface is opened.
40 *
41 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
42 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
44 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
50 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
51 * OF THE POSSIBILITY OF SUCH DAMAGE.
52 */
53
54#if defined(__i386__)
55# define BREAKPOINT() asm(" int $3");
56#else
57# define BREAKPOINT() { }
58#endif
59
60#define MAX_ISA_DEVICES 10
61#define MAX_PCI_DEVICES 10
62#define MAX_TOTAL_DEVICES 20
63
1da177e4
LT		 64#include <linux/module.h>
65#include <linux/errno.h>
66#include <linux/signal.h>
67#include <linux/sched.h>
68#include <linux/timer.h>
69#include <linux/interrupt.h>
70#include <linux/pci.h>
71#include <linux/tty.h>
72#include <linux/tty_flip.h>
73#include <linux/serial.h>
74#include <linux/major.h>
75#include <linux/string.h>
76#include <linux/fcntl.h>
77#include <linux/ptrace.h>
78#include <linux/ioport.h>
79#include <linux/mm.h>
d337829b 80#include <linux/seq_file.h>
1da177e4
LT		 81#include <linux/slab.h>
82#include <linux/delay.h>
1da177e4 83#include <linux/netdevice.h>
1da177e4
LT		 84#include <linux/vmalloc.h>
85#include <linux/init.h>
1da177e4 86#include <linux/ioctl.h>
3dd1247f 87#include <linux/synclink.h>
1da177e4 88
1da177e4
LT		 89#include <asm/io.h>
90#include <asm/irq.h>
91#include <asm/dma.h>
92#include <linux/bitops.h>
93#include <asm/types.h>
94#include <linux/termios.h>
95#include <linux/workqueue.h>
96#include <linux/hdlc.h>
0ff1b2c8 97#include <linux/dma-mapping.h>
1da177e4 98
af69c7f9
PF		 99#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
100#define SYNCLINK_GENERIC_HDLC 1
101#else
102#define SYNCLINK_GENERIC_HDLC 0
1da177e4
LT		 103#endif
104
105#define GET_USER(error,value,addr) error = get_user(value,addr)
106#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
107#define PUT_USER(error,value,addr) error = put_user(value,addr)
108#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
109
110#include <asm/uaccess.h>
111
1da177e4
LT		 112#define RCLRVALUE 0xffff
113
114static MGSL_PARAMS default_params = {
115 MGSL_MODE_HDLC, /* unsigned long mode */
116 0, /* unsigned char loopback; */
117 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
118 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
119 0, /* unsigned long clock_speed; */
120 0xff, /* unsigned char addr_filter; */
121 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
122 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
123 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
124 9600, /* unsigned long data_rate; */
125 8, /* unsigned char data_bits; */
126 1, /* unsigned char stop_bits; */
127 ASYNC_PARITY_NONE /* unsigned char parity; */
128};
129
130#define SHARED_MEM_ADDRESS_SIZE 0x40000
623a4395
PF		 131#define BUFFERLISTSIZE 4096
132#define DMABUFFERSIZE 4096
1da177e4
LT		 133#define MAXRXFRAMES 7
134
135typedef struct _DMABUFFERENTRY
136{
137 u32 phys_addr; /* 32-bit flat physical address of data buffer */
4a918bc2
PF		 138 volatile u16 count; /* buffer size/data count */
139 volatile u16 status; /* Control/status field */
140 volatile u16 rcc; /* character count field */
1da177e4
LT		 141 u16 reserved; /* padding required by 16C32 */
142 u32 link; /* 32-bit flat link to next buffer entry */
143 char *virt_addr; /* virtual address of data buffer */
144 u32 phys_entry; /* physical address of this buffer entry */
0ff1b2c8 145 dma_addr_t dma_addr;
1da177e4
LT		 146} DMABUFFERENTRY, *DMAPBUFFERENTRY;
147
148/* The queue of BH actions to be performed */
149
150#define BH_RECEIVE 1
151#define BH_TRANSMIT 2
152#define BH_STATUS 4
153
154#define IO_PIN_SHUTDOWN_LIMIT 100
155
1da177e4
LT		 156struct _input_signal_events {
157 int ri_up;
158 int ri_down;
159 int dsr_up;
160 int dsr_down;
161 int dcd_up;
162 int dcd_down;
163 int cts_up;
164 int cts_down;
165};
166
167/* transmit holding buffer definitions*/
168#define MAX_TX_HOLDING_BUFFERS 5
169struct tx_holding_buffer {
170 int buffer_size;
171 unsigned char * buffer;
172};
173
174
175/*
176 * Device instance data structure
177 */
178
179struct mgsl_struct {
180 int magic;
8fb06c77 181 struct tty_port port;
1da177e4
LT		 182 int line;
183 int hw_version;
1da177e4
LT		 184
185 struct mgsl_icount icount;
186
1da177e4
LT		 187 int timeout;
188 int x_char; /* xon/xoff character */
1da177e4
LT		 189 u16 read_status_mask;
190 u16 ignore_status_mask;
191 unsigned char *xmit_buf;
192 int xmit_head;
193 int xmit_tail;
194 int xmit_cnt;
195
1da177e4
LT		 196 wait_queue_head_t status_event_wait_q;
197 wait_queue_head_t event_wait_q;
198 struct timer_list tx_timer; /* HDLC transmit timeout timer */
199 struct mgsl_struct *next_device; /* device list link */
200
201 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
202 struct work_struct task; /* task structure for scheduling bh */
203
204 u32 EventMask; /* event trigger mask */
205 u32 RecordedEvents; /* pending events */
206
207 u32 max_frame_size; /* as set by device config */
208
209 u32 pending_bh;
210
0fab6de0 211 bool bh_running; /* Protection from multiple */
1da177e4 212 int isr_overflow;
0fab6de0 213 bool bh_requested;
1da177e4
LT		 214
215 int dcd_chkcount; /* check counts to prevent */
216 int cts_chkcount; /* too many IRQs if a signal */
217 int dsr_chkcount; /* is floating */
218 int ri_chkcount;
219
220 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
0ff1b2c8
PF		 221 u32 buffer_list_phys;
222 dma_addr_t buffer_list_dma_addr;
1da177e4
LT		 223
224 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
225 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
226 unsigned int current_rx_buffer;
227
228 int num_tx_dma_buffers; /* number of tx dma frames required */
229 int tx_dma_buffers_used;
230 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
231 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
232 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
233 int current_tx_buffer; /* next tx dma buffer to be loaded */
234
235 unsigned char *intermediate_rxbuffer;
236
237 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
238 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
239 int put_tx_holding_index; /* next tx holding buffer to store user request */
240 int tx_holding_count; /* number of tx holding buffers waiting */
241 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
242
0fab6de0
JP		 243 bool rx_enabled;
244 bool rx_overflow;
245 bool rx_rcc_underrun;
1da177e4 246
0fab6de0
JP		 247 bool tx_enabled;
248 bool tx_active;
1da177e4
LT		 249 u32 idle_mode;
250
251 u16 cmr_value;
252 u16 tcsr_value;
253
254 char device_name[25]; /* device instance name */
255
256 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
257 unsigned char bus; /* expansion bus number (zero based) */
258 unsigned char function; /* PCI device number */
259
260 unsigned int io_base; /* base I/O address of adapter */
261 unsigned int io_addr_size; /* size of the I/O address range */
0fab6de0 262 bool io_addr_requested; /* true if I/O address requested */
1da177e4
LT		 263
264 unsigned int irq_level; /* interrupt level */
265 unsigned long irq_flags;
0fab6de0 266 bool irq_requested; /* true if IRQ requested */
1da177e4
LT		 267
268 unsigned int dma_level; /* DMA channel */
0fab6de0 269 bool dma_requested; /* true if dma channel requested */
1da177e4
LT		 270
271 u16 mbre_bit;
272 u16 loopback_bits;
273 u16 usc_idle_mode;
274
275 MGSL_PARAMS params; /* communications parameters */
276
277 unsigned char serial_signals; /* current serial signal states */
278
0fab6de0 279 bool irq_occurred; /* for diagnostics use */
1da177e4
LT		 280 unsigned int init_error; /* Initialization startup error (DIAGS) */
281 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
282
283 u32 last_mem_alloc;
284 unsigned char* memory_base; /* shared memory address (PCI only) */
285 u32 phys_memory_base;
0fab6de0 286 bool shared_mem_requested;
1da177e4
LT		 287
288 unsigned char* lcr_base; /* local config registers (PCI only) */
289 u32 phys_lcr_base;
290 u32 lcr_offset;
0fab6de0 291 bool lcr_mem_requested;
1da177e4
LT		 292
293 u32 misc_ctrl_value;
a6b68a69 294 char *flag_buf;
0fab6de0 295 bool drop_rts_on_tx_done;
1da177e4 296
0fab6de0
JP		 297 bool loopmode_insert_requested;
298 bool loopmode_send_done_requested;
1da177e4
LT		 299
300 struct _input_signal_events input_signal_events;
301
302 /* generic HDLC device parts */
303 int netcount;
1da177e4
LT		 304 spinlock_t netlock;
305
af69c7f9 306#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 307 struct net_device *netdev;
308#endif
309};
310
311#define MGSL_MAGIC 0x5401
312
313/*
314 * The size of the serial xmit buffer is 1 page, or 4096 bytes
315 */
316#ifndef SERIAL_XMIT_SIZE
317#define SERIAL_XMIT_SIZE 4096
318#endif
319
320/*
321 * These macros define the offsets used in calculating the
322 * I/O address of the specified USC registers.
323 */
324
325
326#define DCPIN 2 /* Bit 1 of I/O address */
327#define SDPIN 4 /* Bit 2 of I/O address */
328
329#define DCAR 0 /* DMA command/address register */
330#define CCAR SDPIN /* channel command/address register */
331#define DATAREG DCPIN + SDPIN /* serial data register */
332#define MSBONLY 0x41
333#define LSBONLY 0x40
334
335/*
336 * These macros define the register address (ordinal number)
337 * used for writing address/value pairs to the USC.
338 */
339
340#define CMR 0x02 /* Channel mode Register */
341#define CCSR 0x04 /* Channel Command/status Register */
342#define CCR 0x06 /* Channel Control Register */
343#define PSR 0x08 /* Port status Register */
344#define PCR 0x0a /* Port Control Register */
345#define TMDR 0x0c /* Test mode Data Register */
346#define TMCR 0x0e /* Test mode Control Register */
347#define CMCR 0x10 /* Clock mode Control Register */
348#define HCR 0x12 /* Hardware Configuration Register */
349#define IVR 0x14 /* Interrupt Vector Register */
350#define IOCR 0x16 /* Input/Output Control Register */
351#define ICR 0x18 /* Interrupt Control Register */
352#define DCCR 0x1a /* Daisy Chain Control Register */
353#define MISR 0x1c /* Misc Interrupt status Register */
354#define SICR 0x1e /* status Interrupt Control Register */
355#define RDR 0x20 /* Receive Data Register */
356#define RMR 0x22 /* Receive mode Register */
357#define RCSR 0x24 /* Receive Command/status Register */
358#define RICR 0x26 /* Receive Interrupt Control Register */
359#define RSR 0x28 /* Receive Sync Register */
360#define RCLR 0x2a /* Receive count Limit Register */
361#define RCCR 0x2c /* Receive Character count Register */
362#define TC0R 0x2e /* Time Constant 0 Register */
363#define TDR 0x30 /* Transmit Data Register */
364#define TMR 0x32 /* Transmit mode Register */
365#define TCSR 0x34 /* Transmit Command/status Register */
366#define TICR 0x36 /* Transmit Interrupt Control Register */
367#define TSR 0x38 /* Transmit Sync Register */
368#define TCLR 0x3a /* Transmit count Limit Register */
369#define TCCR 0x3c /* Transmit Character count Register */
370#define TC1R 0x3e /* Time Constant 1 Register */
371
372
373/*
374 * MACRO DEFINITIONS FOR DMA REGISTERS
375 */
376
377#define DCR 0x06 /* DMA Control Register (shared) */
378#define DACR 0x08 /* DMA Array count Register (shared) */
379#define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
380#define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
381#define DICR 0x18 /* DMA Interrupt Control Register (shared) */
382#define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
383#define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
384
385#define TDMR 0x02 /* Transmit DMA mode Register */
386#define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
387#define TBCR 0x2a /* Transmit Byte count Register */
388#define TARL 0x2c /* Transmit Address Register (low) */
389#define TARU 0x2e /* Transmit Address Register (high) */
390#define NTBCR 0x3a /* Next Transmit Byte count Register */
391#define NTARL 0x3c /* Next Transmit Address Register (low) */
392#define NTARU 0x3e /* Next Transmit Address Register (high) */
393
394#define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
395#define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
396#define RBCR 0xaa /* Receive Byte count Register */
397#define RARL 0xac /* Receive Address Register (low) */
398#define RARU 0xae /* Receive Address Register (high) */
399#define NRBCR 0xba /* Next Receive Byte count Register */
400#define NRARL 0xbc /* Next Receive Address Register (low) */
401#define NRARU 0xbe /* Next Receive Address Register (high) */
402
403
404/*
405 * MACRO DEFINITIONS FOR MODEM STATUS BITS
406 */
407
408#define MODEMSTATUS_DTR 0x80
409#define MODEMSTATUS_DSR 0x40
410#define MODEMSTATUS_RTS 0x20
411#define MODEMSTATUS_CTS 0x10
412#define MODEMSTATUS_RI 0x04
413#define MODEMSTATUS_DCD 0x01
414
415
416/*
417 * Channel Command/Address Register (CCAR) Command Codes
418 */
419
420#define RTCmd_Null 0x0000
421#define RTCmd_ResetHighestIus 0x1000
422#define RTCmd_TriggerChannelLoadDma 0x2000
423#define RTCmd_TriggerRxDma 0x2800
424#define RTCmd_TriggerTxDma 0x3000
425#define RTCmd_TriggerRxAndTxDma 0x3800
426#define RTCmd_PurgeRxFifo 0x4800
427#define RTCmd_PurgeTxFifo 0x5000
428#define RTCmd_PurgeRxAndTxFifo 0x5800
429#define RTCmd_LoadRcc 0x6800
430#define RTCmd_LoadTcc 0x7000
431#define RTCmd_LoadRccAndTcc 0x7800
432#define RTCmd_LoadTC0 0x8800
433#define RTCmd_LoadTC1 0x9000
434#define RTCmd_LoadTC0AndTC1 0x9800
435#define RTCmd_SerialDataLSBFirst 0xa000
436#define RTCmd_SerialDataMSBFirst 0xa800
437#define RTCmd_SelectBigEndian 0xb000
438#define RTCmd_SelectLittleEndian 0xb800
439
440
441/*
442 * DMA Command/Address Register (DCAR) Command Codes
443 */
444
445#define DmaCmd_Null 0x0000
446#define DmaCmd_ResetTxChannel 0x1000
447#define DmaCmd_ResetRxChannel 0x1200
448#define DmaCmd_StartTxChannel 0x2000
449#define DmaCmd_StartRxChannel 0x2200
450#define DmaCmd_ContinueTxChannel 0x3000
451#define DmaCmd_ContinueRxChannel 0x3200
452#define DmaCmd_PauseTxChannel 0x4000
453#define DmaCmd_PauseRxChannel 0x4200
454#define DmaCmd_AbortTxChannel 0x5000
455#define DmaCmd_AbortRxChannel 0x5200
456#define DmaCmd_InitTxChannel 0x7000
457#define DmaCmd_InitRxChannel 0x7200
458#define DmaCmd_ResetHighestDmaIus 0x8000
459#define DmaCmd_ResetAllChannels 0x9000
460#define DmaCmd_StartAllChannels 0xa000
461#define DmaCmd_ContinueAllChannels 0xb000
462#define DmaCmd_PauseAllChannels 0xc000
463#define DmaCmd_AbortAllChannels 0xd000
464#define DmaCmd_InitAllChannels 0xf000
465
466#define TCmd_Null 0x0000
467#define TCmd_ClearTxCRC 0x2000
468#define TCmd_SelectTicrTtsaData 0x4000
469#define TCmd_SelectTicrTxFifostatus 0x5000
470#define TCmd_SelectTicrIntLevel 0x6000
471#define TCmd_SelectTicrdma_level 0x7000
472#define TCmd_SendFrame 0x8000
473#define TCmd_SendAbort 0x9000
474#define TCmd_EnableDleInsertion 0xc000
475#define TCmd_DisableDleInsertion 0xd000
476#define TCmd_ClearEofEom 0xe000
477#define TCmd_SetEofEom 0xf000
478
479#define RCmd_Null 0x0000
480#define RCmd_ClearRxCRC 0x2000
481#define RCmd_EnterHuntmode 0x3000
482#define RCmd_SelectRicrRtsaData 0x4000
483#define RCmd_SelectRicrRxFifostatus 0x5000
484#define RCmd_SelectRicrIntLevel 0x6000
485#define RCmd_SelectRicrdma_level 0x7000
486
487/*
488 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
489 */
490
491#define RECEIVE_STATUS BIT5
492#define RECEIVE_DATA BIT4
493#define TRANSMIT_STATUS BIT3
494#define TRANSMIT_DATA BIT2
495#define IO_PIN BIT1
496#define MISC BIT0
497
498
499/*
500 * Receive status Bits in Receive Command/status Register RCSR
501 */
502
503#define RXSTATUS_SHORT_FRAME BIT8
504#define RXSTATUS_CODE_VIOLATION BIT8
505#define RXSTATUS_EXITED_HUNT BIT7
506#define RXSTATUS_IDLE_RECEIVED BIT6
507#define RXSTATUS_BREAK_RECEIVED BIT5
508#define RXSTATUS_ABORT_RECEIVED BIT5
509#define RXSTATUS_RXBOUND BIT4
510#define RXSTATUS_CRC_ERROR BIT3
511#define RXSTATUS_FRAMING_ERROR BIT3
512#define RXSTATUS_ABORT BIT2
513#define RXSTATUS_PARITY_ERROR BIT2
514#define RXSTATUS_OVERRUN BIT1
515#define RXSTATUS_DATA_AVAILABLE BIT0
516#define RXSTATUS_ALL 0x01f6
517#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
518
519/*
520 * Values for setting transmit idle mode in
521 * Transmit Control/status Register (TCSR)
522 */
523#define IDLEMODE_FLAGS 0x0000
524#define IDLEMODE_ALT_ONE_ZERO 0x0100
525#define IDLEMODE_ZERO 0x0200
526#define IDLEMODE_ONE 0x0300
527#define IDLEMODE_ALT_MARK_SPACE 0x0500
528#define IDLEMODE_SPACE 0x0600
529#define IDLEMODE_MARK 0x0700
530#define IDLEMODE_MASK 0x0700
531
532/*
533 * IUSC revision identifiers
534 */
535#define IUSC_SL1660 0x4d44
536#define IUSC_PRE_SL1660 0x4553
537
538/*
539 * Transmit status Bits in Transmit Command/status Register (TCSR)
540 */
541
542#define TCSR_PRESERVE 0x0F00
543
544#define TCSR_UNDERWAIT BIT11
545#define TXSTATUS_PREAMBLE_SENT BIT7
546#define TXSTATUS_IDLE_SENT BIT6
547#define TXSTATUS_ABORT_SENT BIT5
548#define TXSTATUS_EOF_SENT BIT4
549#define TXSTATUS_EOM_SENT BIT4
550#define TXSTATUS_CRC_SENT BIT3
551#define TXSTATUS_ALL_SENT BIT2
552#define TXSTATUS_UNDERRUN BIT1
553#define TXSTATUS_FIFO_EMPTY BIT0
554#define TXSTATUS_ALL 0x00fa
555#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
556
557
558#define MISCSTATUS_RXC_LATCHED BIT15
559#define MISCSTATUS_RXC BIT14
560#define MISCSTATUS_TXC_LATCHED BIT13
561#define MISCSTATUS_TXC BIT12
562#define MISCSTATUS_RI_LATCHED BIT11
563#define MISCSTATUS_RI BIT10
564#define MISCSTATUS_DSR_LATCHED BIT9
565#define MISCSTATUS_DSR BIT8
566#define MISCSTATUS_DCD_LATCHED BIT7
567#define MISCSTATUS_DCD BIT6
568#define MISCSTATUS_CTS_LATCHED BIT5
569#define MISCSTATUS_CTS BIT4
570#define MISCSTATUS_RCC_UNDERRUN BIT3
571#define MISCSTATUS_DPLL_NO_SYNC BIT2
572#define MISCSTATUS_BRG1_ZERO BIT1
573#define MISCSTATUS_BRG0_ZERO BIT0
574
575#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
576#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
577
578#define SICR_RXC_ACTIVE BIT15
579#define SICR_RXC_INACTIVE BIT14
580#define SICR_RXC (BIT15+BIT14)
581#define SICR_TXC_ACTIVE BIT13
582#define SICR_TXC_INACTIVE BIT12
583#define SICR_TXC (BIT13+BIT12)
584#define SICR_RI_ACTIVE BIT11
585#define SICR_RI_INACTIVE BIT10
586#define SICR_RI (BIT11+BIT10)
587#define SICR_DSR_ACTIVE BIT9
588#define SICR_DSR_INACTIVE BIT8
589#define SICR_DSR (BIT9+BIT8)
590#define SICR_DCD_ACTIVE BIT7
591#define SICR_DCD_INACTIVE BIT6
592#define SICR_DCD (BIT7+BIT6)
593#define SICR_CTS_ACTIVE BIT5
594#define SICR_CTS_INACTIVE BIT4
595#define SICR_CTS (BIT5+BIT4)
596#define SICR_RCC_UNDERFLOW BIT3
597#define SICR_DPLL_NO_SYNC BIT2
598#define SICR_BRG1_ZERO BIT1
599#define SICR_BRG0_ZERO BIT0
600
601void usc_DisableMasterIrqBit( struct mgsl_struct *info );
602void usc_EnableMasterIrqBit( struct mgsl_struct *info );
603void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
604void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
605void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
606
607#define usc_EnableInterrupts( a, b ) \
608 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
609
610#define usc_DisableInterrupts( a, b ) \
611 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
612
613#define usc_EnableMasterIrqBit(a) \
614 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
615
616#define usc_DisableMasterIrqBit(a) \
617 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
618
619#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
620
621/*
622 * Transmit status Bits in Transmit Control status Register (TCSR)
623 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
624 */
625
626#define TXSTATUS_PREAMBLE_SENT BIT7
627#define TXSTATUS_IDLE_SENT BIT6
628#define TXSTATUS_ABORT_SENT BIT5
629#define TXSTATUS_EOF BIT4
630#define TXSTATUS_CRC_SENT BIT3
631#define TXSTATUS_ALL_SENT BIT2
632#define TXSTATUS_UNDERRUN BIT1
633#define TXSTATUS_FIFO_EMPTY BIT0
634
635#define DICR_MASTER BIT15
636#define DICR_TRANSMIT BIT0
637#define DICR_RECEIVE BIT1
638
639#define usc_EnableDmaInterrupts(a,b) \
640 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
641
642#define usc_DisableDmaInterrupts(a,b) \
643 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
644
645#define usc_EnableStatusIrqs(a,b) \
646 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
647
648#define usc_DisablestatusIrqs(a,b) \
649 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
650
651/* Transmit status Bits in Transmit Control status Register (TCSR) */
652/* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
653
654
655#define DISABLE_UNCONDITIONAL 0
656#define DISABLE_END_OF_FRAME 1
657#define ENABLE_UNCONDITIONAL 2
658#define ENABLE_AUTO_CTS 3
659#define ENABLE_AUTO_DCD 3
660#define usc_EnableTransmitter(a,b) \
661 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
662#define usc_EnableReceiver(a,b) \
663 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
664
665static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
666static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
667static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
668
669static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
670static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
671static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
672void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
673void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
674
675#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
676#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
677
678#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
679
680static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
681static void usc_start_receiver( struct mgsl_struct *info );
682static void usc_stop_receiver( struct mgsl_struct *info );
683
684static void usc_start_transmitter( struct mgsl_struct *info );
685static void usc_stop_transmitter( struct mgsl_struct *info );
686static void usc_set_txidle( struct mgsl_struct *info );
687static void usc_load_txfifo( struct mgsl_struct *info );
688
689static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
690static void usc_enable_loopback( struct mgsl_struct *info, int enable );
691
692static void usc_get_serial_signals( struct mgsl_struct *info );
693static void usc_set_serial_signals( struct mgsl_struct *info );
694
695static void usc_reset( struct mgsl_struct *info );
696
697static void usc_set_sync_mode( struct mgsl_struct *info );
698static void usc_set_sdlc_mode( struct mgsl_struct *info );
699static void usc_set_async_mode( struct mgsl_struct *info );
700static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
701
702static void usc_loopback_frame( struct mgsl_struct *info );
703
704static void mgsl_tx_timeout(unsigned long context);
705
706
707static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
708static void usc_loopmode_insert_request( struct mgsl_struct * info );
709static int usc_loopmode_active( struct mgsl_struct * info);
710static void usc_loopmode_send_done( struct mgsl_struct * info );
711
712static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
713
af69c7f9 714#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 715#define dev_to_port(D) (dev_to_hdlc(D)->priv)
716static void hdlcdev_tx_done(struct mgsl_struct *info);
717static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
718static int hdlcdev_init(struct mgsl_struct *info);
719static void hdlcdev_exit(struct mgsl_struct *info);
720#endif
721
722/*
723 * Defines a BUS descriptor value for the PCI adapter
724 * local bus address ranges.
725 */
726
727#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
728(0x00400020 + \
729((WrHold) << 30) + \
730((WrDly) << 28) + \
731((RdDly) << 26) + \
732((Nwdd) << 20) + \
733((Nwad) << 15) + \
734((Nxda) << 13) + \
735((Nrdd) << 11) + \
736((Nrad) << 6) )
737
738static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
739
740/*
741 * Adapter diagnostic routines
742 */
0fab6de0
JP		 743static bool mgsl_register_test( struct mgsl_struct *info );
744static bool mgsl_irq_test( struct mgsl_struct *info );
745static bool mgsl_dma_test( struct mgsl_struct *info );
746static bool mgsl_memory_test( struct mgsl_struct *info );
1da177e4
LT		 747static int mgsl_adapter_test( struct mgsl_struct *info );
748
749/*
750 * device and resource management routines
751 */
752static int mgsl_claim_resources(struct mgsl_struct *info);
753static void mgsl_release_resources(struct mgsl_struct *info);
754static void mgsl_add_device(struct mgsl_struct *info);
755static struct mgsl_struct* mgsl_allocate_device(void);
756
757/*
758 * DMA buffer manupulation functions.
759 */
760static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
0fab6de0
JP		 761static bool mgsl_get_rx_frame( struct mgsl_struct *info );
762static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
1da177e4
LT		 763static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
764static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
765static int num_free_tx_dma_buffers(struct mgsl_struct *info);
766static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
767static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
768
769/*
770 * DMA and Shared Memory buffer allocation and formatting
771 */
772static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
773static void mgsl_free_dma_buffers(struct mgsl_struct *info);
774static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
775static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
776static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
777static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
778static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
779static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
780static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
781static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
0fab6de0 782static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
1da177e4
LT		 783static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
784
785/*
786 * Bottom half interrupt handlers
787 */
c4028958 788static void mgsl_bh_handler(struct work_struct *work);
1da177e4
LT		 789static void mgsl_bh_receive(struct mgsl_struct *info);
790static void mgsl_bh_transmit(struct mgsl_struct *info);
791static void mgsl_bh_status(struct mgsl_struct *info);
792
793/*
794 * Interrupt handler routines and dispatch table.
795 */
796static void mgsl_isr_null( struct mgsl_struct *info );
797static void mgsl_isr_transmit_data( struct mgsl_struct *info );
798static void mgsl_isr_receive_data( struct mgsl_struct *info );
799static void mgsl_isr_receive_status( struct mgsl_struct *info );
800static void mgsl_isr_transmit_status( struct mgsl_struct *info );
801static void mgsl_isr_io_pin( struct mgsl_struct *info );
802static void mgsl_isr_misc( struct mgsl_struct *info );
803static void mgsl_isr_receive_dma( struct mgsl_struct *info );
804static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
805
806typedef void (*isr_dispatch_func)(struct mgsl_struct *);
807
808static isr_dispatch_func UscIsrTable[7] =
809{
810 mgsl_isr_null,
811 mgsl_isr_misc,
812 mgsl_isr_io_pin,
813 mgsl_isr_transmit_data,
814 mgsl_isr_transmit_status,
815 mgsl_isr_receive_data,
816 mgsl_isr_receive_status
817};
818
819/*
820 * ioctl call handlers
821 */
60b33c13 822static int tiocmget(struct tty_struct *tty);
20b9d177 823static int tiocmset(struct tty_struct *tty,
1da177e4
LT		 824 unsigned int set, unsigned int clear);
825static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
826 __user *user_icount);
827static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
828static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
829static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
830static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
831static int mgsl_txenable(struct mgsl_struct * info, int enable);
832static int mgsl_txabort(struct mgsl_struct * info);
833static int mgsl_rxenable(struct mgsl_struct * info, int enable);
834static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
835static int mgsl_loopmode_send_done( struct mgsl_struct * info );
836
837/* set non-zero on successful registration with PCI subsystem */
0fab6de0 838static bool pci_registered;
1da177e4
LT		 839
840/*
841 * Global linked list of SyncLink devices
842 */
843static struct mgsl_struct *mgsl_device_list;
844static int mgsl_device_count;
845
846/*
847 * Set this param to non-zero to load eax with the
848 * .text section address and breakpoint on module load.
849 * This is useful for use with gdb and add-symbol-file command.
850 */
90ab5ee9 851static bool break_on_load;
1da177e4
LT		 852
853/*
854 * Driver major number, defaults to zero to get auto
855 * assigned major number. May be forced as module parameter.
856 */
857static int ttymajor;
858
859/*
860 * Array of user specified options for ISA adapters.
861 */
862static int io[MAX_ISA_DEVICES];
863static int irq[MAX_ISA_DEVICES];
864static int dma[MAX_ISA_DEVICES];
865static int debug_level;
866static int maxframe[MAX_TOTAL_DEVICES];
1da177e4
LT		 867static int txdmabufs[MAX_TOTAL_DEVICES];
868static int txholdbufs[MAX_TOTAL_DEVICES];
869
870module_param(break_on_load, bool, 0);
871module_param(ttymajor, int, 0);
872module_param_array(io, int, NULL, 0);
873module_param_array(irq, int, NULL, 0);
874module_param_array(dma, int, NULL, 0);
875module_param(debug_level, int, 0);
876module_param_array(maxframe, int, NULL, 0);
1da177e4
LT		 877module_param_array(txdmabufs, int, NULL, 0);
878module_param_array(txholdbufs, int, NULL, 0);
879
880static char *driver_name = "SyncLink serial driver";
0ff1b2c8 881static char *driver_version = "$Revision: 4.38 $";
1da177e4
LT		 882
883static int synclink_init_one (struct pci_dev *dev,
884 const struct pci_device_id *ent);
885static void synclink_remove_one (struct pci_dev *dev);
886
887static struct pci_device_id synclink_pci_tbl[] = {
888 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
889 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
890 { 0, }, /* terminate list */
891};
892MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
893
894MODULE_LICENSE("GPL");
895
896static struct pci_driver synclink_pci_driver = {
897 .name = "synclink",
898 .id_table = synclink_pci_tbl,
899 .probe = synclink_init_one,
91116cba 900 .remove = synclink_remove_one,
1da177e4
LT		 901};
902
903static struct tty_driver *serial_driver;
904
905/* number of characters left in xmit buffer before we ask for more */
906#define WAKEUP_CHARS 256
907
908
909static void mgsl_change_params(struct mgsl_struct *info);
910static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
911
912/*
913 * 1st function defined in .text section. Calling this function in
914 * init_module() followed by a breakpoint allows a remote debugger
915 * (gdb) to get the .text address for the add-symbol-file command.
916 * This allows remote debugging of dynamically loadable modules.
917 */
918static void* mgsl_get_text_ptr(void)
919{
920 return mgsl_get_text_ptr;
921}
922
1da177e4
LT		 923static inline int mgsl_paranoia_check(struct mgsl_struct *info,
924 char *name, const char *routine)
925{
926#ifdef MGSL_PARANOIA_CHECK
927 static const char *badmagic =
928 "Warning: bad magic number for mgsl struct (%s) in %s\n";
929 static const char *badinfo =
930 "Warning: null mgsl_struct for (%s) in %s\n";
931
932 if (!info) {
933 printk(badinfo, name, routine);
934 return 1;
935 }
936 if (info->magic != MGSL_MAGIC) {
937 printk(badmagic, name, routine);
938 return 1;
939 }
940#else
941 if (!info)
942 return 1;
943#endif
944 return 0;
945}
946
947/**
948 * line discipline callback wrappers
949 *
950 * The wrappers maintain line discipline references
951 * while calling into the line discipline.
952 *
953 * ldisc_receive_buf - pass receive data to line discipline
954 */
955
956static void ldisc_receive_buf(struct tty_struct *tty,
957 const __u8 *data, char *flags, int count)
958{
959 struct tty_ldisc *ld;
960 if (!tty)
961 return;
962 ld = tty_ldisc_ref(tty);
963 if (ld) {
a352def2
AC		 964 if (ld->ops->receive_buf)
965 ld->ops->receive_buf(tty, data, flags, count);
1da177e4
LT		 966 tty_ldisc_deref(ld);
967 }
968}
969
970/* mgsl_stop() throttle (stop) transmitter
971 *
972 * Arguments: tty pointer to tty info structure
973 * Return Value: None
974 */
975static void mgsl_stop(struct tty_struct *tty)
976{
c9f19e96 977 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 978 unsigned long flags;
979
980 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
981 return;
982
983 if ( debug_level >= DEBUG_LEVEL_INFO )
984 printk("mgsl_stop(%s)\n",info->device_name);
985
986 spin_lock_irqsave(&info->irq_spinlock,flags);
987 if (info->tx_enabled)
988 usc_stop_transmitter(info);
989 spin_unlock_irqrestore(&info->irq_spinlock,flags);
990
991} /* end of mgsl_stop() */
992
993/* mgsl_start() release (start) transmitter
994 *
995 * Arguments: tty pointer to tty info structure
996 * Return Value: None
997 */
998static void mgsl_start(struct tty_struct *tty)
999{
c9f19e96 1000 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 1001 unsigned long flags;
1002
1003 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1004 return;
1005
1006 if ( debug_level >= DEBUG_LEVEL_INFO )
1007 printk("mgsl_start(%s)\n",info->device_name);
1008
1009 spin_lock_irqsave(&info->irq_spinlock,flags);
1010 if (!info->tx_enabled)
1011 usc_start_transmitter(info);
1012 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1013
1014} /* end of mgsl_start() */
1015
1016/*
1017 * Bottom half work queue access functions
1018 */
1019
1020/* mgsl_bh_action() Return next bottom half action to perform.
1021 * Return Value: BH action code or 0 if nothing to do.
1022 */
1023static int mgsl_bh_action(struct mgsl_struct *info)
1024{
1025 unsigned long flags;
1026 int rc = 0;
1027
1028 spin_lock_irqsave(&info->irq_spinlock,flags);
1029
1030 if (info->pending_bh & BH_RECEIVE) {
1031 info->pending_bh &= ~BH_RECEIVE;
1032 rc = BH_RECEIVE;
1033 } else if (info->pending_bh & BH_TRANSMIT) {
1034 info->pending_bh &= ~BH_TRANSMIT;
1035 rc = BH_TRANSMIT;
1036 } else if (info->pending_bh & BH_STATUS) {
1037 info->pending_bh &= ~BH_STATUS;
1038 rc = BH_STATUS;
1039 }
1040
1041 if (!rc) {
1042 /* Mark BH routine as complete */
0fab6de0
JP		 1043 info->bh_running = false;
1044 info->bh_requested = false;
1da177e4
LT		 1045 }
1046
1047 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1048
1049 return rc;
1050}
1051
1052/*
1053 * Perform bottom half processing of work items queued by ISR.
1054 */
c4028958 1055static void mgsl_bh_handler(struct work_struct *work)
1da177e4 1056{
c4028958
DH		 1057 struct mgsl_struct *info =
1058 container_of(work, struct mgsl_struct, task);
1da177e4
LT		 1059 int action;
1060
1061 if (!info)
1062 return;
1063
1064 if ( debug_level >= DEBUG_LEVEL_BH )
1065 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1066 __FILE__,__LINE__,info->device_name);
1067
0fab6de0 1068 info->bh_running = true;
1da177e4
LT		 1069
1070 while((action = mgsl_bh_action(info)) != 0) {
1071
1072 /* Process work item */
1073 if ( debug_level >= DEBUG_LEVEL_BH )
1074 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1075 __FILE__,__LINE__,action);
1076
1077 switch (action) {
1078
1079 case BH_RECEIVE:
1080 mgsl_bh_receive(info);
1081 break;
1082 case BH_TRANSMIT:
1083 mgsl_bh_transmit(info);
1084 break;
1085 case BH_STATUS:
1086 mgsl_bh_status(info);
1087 break;
1088 default:
1089 /* unknown work item ID */
1090 printk("Unknown work item ID=%08X!\n", action);
1091 break;
1092 }
1093 }
1094
1095 if ( debug_level >= DEBUG_LEVEL_BH )
1096 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1097 __FILE__,__LINE__,info->device_name);
1098}
1099
1100static void mgsl_bh_receive(struct mgsl_struct *info)
1101{
0fab6de0 1102 bool (*get_rx_frame)(struct mgsl_struct *info) =
1da177e4
LT		 1103 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1104
1105 if ( debug_level >= DEBUG_LEVEL_BH )
1106 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1107 __FILE__,__LINE__,info->device_name);
1108
1109 do
1110 {
1111 if (info->rx_rcc_underrun) {
1112 unsigned long flags;
1113 spin_lock_irqsave(&info->irq_spinlock,flags);
1114 usc_start_receiver(info);
1115 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1116 return;
1117 }
1118 } while(get_rx_frame(info));
1119}
1120
1121static void mgsl_bh_transmit(struct mgsl_struct *info)
1122{
8fb06c77 1123 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 1124 unsigned long flags;
1125
1126 if ( debug_level >= DEBUG_LEVEL_BH )
1127 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1128 __FILE__,__LINE__,info->device_name);
1129
b963a844 1130 if (tty)
1da177e4 1131 tty_wakeup(tty);
1da177e4
LT		 1132
1133 /* if transmitter idle and loopmode_send_done_requested
1134 * then start echoing RxD to TxD
1135 */
1136 spin_lock_irqsave(&info->irq_spinlock,flags);
1137 if ( !info->tx_active && info->loopmode_send_done_requested )
1138 usc_loopmode_send_done( info );
1139 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1140}
1141
1142static void mgsl_bh_status(struct mgsl_struct *info)
1143{
1144 if ( debug_level >= DEBUG_LEVEL_BH )
1145 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1146 __FILE__,__LINE__,info->device_name);
1147
1148 info->ri_chkcount = 0;
1149 info->dsr_chkcount = 0;
1150 info->dcd_chkcount = 0;
1151 info->cts_chkcount = 0;
1152}
1153
1154/* mgsl_isr_receive_status()
1155 *
1156 * Service a receive status interrupt. The type of status
1157 * interrupt is indicated by the state of the RCSR.
1158 * This is only used for HDLC mode.
1159 *
1160 * Arguments: info pointer to device instance data
1161 * Return Value: None
1162 */
1163static void mgsl_isr_receive_status( struct mgsl_struct *info )
1164{
1165 u16 status = usc_InReg( info, RCSR );
1166
1167 if ( debug_level >= DEBUG_LEVEL_ISR )
1168 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1169 __FILE__,__LINE__,status);
1170
1171 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1172 info->loopmode_insert_requested &&
1173 usc_loopmode_active(info) )
1174 {
1175 ++info->icount.rxabort;
0fab6de0 1176 info->loopmode_insert_requested = false;
1da177e4
LT		 1177
1178 /* clear CMR:13 to start echoing RxD to TxD */
1179 info->cmr_value &= ~BIT13;
1180 usc_OutReg(info, CMR, info->cmr_value);
1181
1182 /* disable received abort irq (no longer required) */
1183 usc_OutReg(info, RICR,
1184 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1185 }
1186
1187 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1188 if (status & RXSTATUS_EXITED_HUNT)
1189 info->icount.exithunt++;
1190 if (status & RXSTATUS_IDLE_RECEIVED)
1191 info->icount.rxidle++;
1192 wake_up_interruptible(&info->event_wait_q);
1193 }
1194
1195 if (status & RXSTATUS_OVERRUN){
1196 info->icount.rxover++;
1197 usc_process_rxoverrun_sync( info );
1198 }
1199
1200 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1201 usc_UnlatchRxstatusBits( info, status );
1202
1203} /* end of mgsl_isr_receive_status() */
1204
1205/* mgsl_isr_transmit_status()
1206 *
1207 * Service a transmit status interrupt
1208 * HDLC mode :end of transmit frame
1209 * Async mode:all data is sent
1210 * transmit status is indicated by bits in the TCSR.
1211 *
1212 * Arguments: info pointer to device instance data
1213 * Return Value: None
1214 */
1215static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1216{
1217 u16 status = usc_InReg( info, TCSR );
1218
1219 if ( debug_level >= DEBUG_LEVEL_ISR )
1220 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1221 __FILE__,__LINE__,status);
1222
1223 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1224 usc_UnlatchTxstatusBits( info, status );
1225
1226 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1227 {
1228 /* finished sending HDLC abort. This may leave */
1229 /* the TxFifo with data from the aborted frame */
1230 /* so purge the TxFifo. Also shutdown the DMA */
1231 /* channel in case there is data remaining in */
1232 /* the DMA buffer */
1233 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1234 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1235 }
1236
1237 if ( status & TXSTATUS_EOF_SENT )
1238 info->icount.txok++;
1239 else if ( status & TXSTATUS_UNDERRUN )
1240 info->icount.txunder++;
1241 else if ( status & TXSTATUS_ABORT_SENT )
1242 info->icount.txabort++;
1243 else
1244 info->icount.txunder++;
1245
0fab6de0 1246 info->tx_active = false;
1da177e4
LT		 1247 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1248 del_timer(&info->tx_timer);
1249
1250 if ( info->drop_rts_on_tx_done ) {
1251 usc_get_serial_signals( info );
1252 if ( info->serial_signals & SerialSignal_RTS ) {
1253 info->serial_signals &= ~SerialSignal_RTS;
1254 usc_set_serial_signals( info );
1255 }
0fab6de0 1256 info->drop_rts_on_tx_done = false;
1da177e4
LT		 1257 }
1258
af69c7f9 1259#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 1260 if (info->netcount)
1261 hdlcdev_tx_done(info);
1262 else
1263#endif
1264 {
8fb06c77 1265 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1da177e4
LT		 1266 usc_stop_transmitter(info);
1267 return;
1268 }
1269 info->pending_bh |= BH_TRANSMIT;
1270 }
1271
1272} /* end of mgsl_isr_transmit_status() */
1273
1274/* mgsl_isr_io_pin()
1275 *
1276 * Service an Input/Output pin interrupt. The type of
1277 * interrupt is indicated by bits in the MISR
1278 *
1279 * Arguments: info pointer to device instance data
1280 * Return Value: None
1281 */
1282static void mgsl_isr_io_pin( struct mgsl_struct *info )
1283{
1284 struct mgsl_icount *icount;
1285 u16 status = usc_InReg( info, MISR );
1286
1287 if ( debug_level >= DEBUG_LEVEL_ISR )
1288 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1289 __FILE__,__LINE__,status);
1290
1291 usc_ClearIrqPendingBits( info, IO_PIN );
1292 usc_UnlatchIostatusBits( info, status );
1293
1294 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1295 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1296 icount = &info->icount;
1297 /* update input line counters */
1298 if (status & MISCSTATUS_RI_LATCHED) {
1299 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1300 usc_DisablestatusIrqs(info,SICR_RI);
1301 icount->rng++;
1302 if ( status & MISCSTATUS_RI )
1303 info->input_signal_events.ri_up++;
1304 else
1305 info->input_signal_events.ri_down++;
1306 }
1307 if (status & MISCSTATUS_DSR_LATCHED) {
1308 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1309 usc_DisablestatusIrqs(info,SICR_DSR);
1310 icount->dsr++;
1311 if ( status & MISCSTATUS_DSR )
1312 info->input_signal_events.dsr_up++;
1313 else
1314 info->input_signal_events.dsr_down++;
1315 }
1316 if (status & MISCSTATUS_DCD_LATCHED) {
1317 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1318 usc_DisablestatusIrqs(info,SICR_DCD);
1319 icount->dcd++;
1320 if (status & MISCSTATUS_DCD) {
1321 info->input_signal_events.dcd_up++;
1322 } else
1323 info->input_signal_events.dcd_down++;
af69c7f9 1324#if SYNCLINK_GENERIC_HDLC
fbeff3c1
KH		 1325 if (info->netcount) {
1326 if (status & MISCSTATUS_DCD)
1327 netif_carrier_on(info->netdev);
1328 else
1329 netif_carrier_off(info->netdev);
1330 }
1da177e4
LT		 1331#endif
1332 }
1333 if (status & MISCSTATUS_CTS_LATCHED)
1334 {
1335 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1336 usc_DisablestatusIrqs(info,SICR_CTS);
1337 icount->cts++;
1338 if ( status & MISCSTATUS_CTS )
1339 info->input_signal_events.cts_up++;
1340 else
1341 info->input_signal_events.cts_down++;
1342 }
1343 wake_up_interruptible(&info->status_event_wait_q);
1344 wake_up_interruptible(&info->event_wait_q);
1345
8fb06c77 1346 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1da177e4
LT		 1347 (status & MISCSTATUS_DCD_LATCHED) ) {
1348 if ( debug_level >= DEBUG_LEVEL_ISR )
1349 printk("%s CD now %s...", info->device_name,
1350 (status & MISCSTATUS_DCD) ? "on" : "off");
1351 if (status & MISCSTATUS_DCD)
8fb06c77 1352 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1353 else {
1354 if ( debug_level >= DEBUG_LEVEL_ISR )
1355 printk("doing serial hangup...");
8fb06c77
AC		 1356 if (info->port.tty)
1357 tty_hangup(info->port.tty);
1da177e4
LT		 1358 }
1359 }
1360
f21ec3d2 1361 if (tty_port_cts_enabled(&info->port) &&
1da177e4 1362 (status & MISCSTATUS_CTS_LATCHED) ) {
8fb06c77 1363 if (info->port.tty->hw_stopped) {
1da177e4
LT		 1364 if (status & MISCSTATUS_CTS) {
1365 if ( debug_level >= DEBUG_LEVEL_ISR )
1366 printk("CTS tx start...");
8fb06c77
AC		 1367 if (info->port.tty)
1368 info->port.tty->hw_stopped = 0;
1da177e4
LT		 1369 usc_start_transmitter(info);
1370 info->pending_bh |= BH_TRANSMIT;
1371 return;
1372 }
1373 } else {
1374 if (!(status & MISCSTATUS_CTS)) {
1375 if ( debug_level >= DEBUG_LEVEL_ISR )
1376 printk("CTS tx stop...");
8fb06c77
AC		 1377 if (info->port.tty)
1378 info->port.tty->hw_stopped = 1;
1da177e4
LT		 1379 usc_stop_transmitter(info);
1380 }
1381 }
1382 }
1383 }
1384
1385 info->pending_bh |= BH_STATUS;
1386
1387 /* for diagnostics set IRQ flag */
1388 if ( status & MISCSTATUS_TXC_LATCHED ){
1389 usc_OutReg( info, SICR,
1390 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1391 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
0fab6de0 1392 info->irq_occurred = true;
1da177e4
LT		 1393 }
1394
1395} /* end of mgsl_isr_io_pin() */
1396
1397/* mgsl_isr_transmit_data()
1398 *
1399 * Service a transmit data interrupt (async mode only).
1400 *
1401 * Arguments: info pointer to device instance data
1402 * Return Value: None
1403 */
1404static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1405{
1406 if ( debug_level >= DEBUG_LEVEL_ISR )
1407 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1408 __FILE__,__LINE__,info->xmit_cnt);
1409
1410 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1411
8fb06c77 1412 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1da177e4
LT		 1413 usc_stop_transmitter(info);
1414 return;
1415 }
1416
1417 if ( info->xmit_cnt )
1418 usc_load_txfifo( info );
1419 else
0fab6de0 1420 info->tx_active = false;
1da177e4
LT		 1421
1422 if (info->xmit_cnt < WAKEUP_CHARS)
1423 info->pending_bh |= BH_TRANSMIT;
1424
1425} /* end of mgsl_isr_transmit_data() */
1426
1427/* mgsl_isr_receive_data()
1428 *
1429 * Service a receive data interrupt. This occurs
1430 * when operating in asynchronous interrupt transfer mode.
1431 * The receive data FIFO is flushed to the receive data buffers.
1432 *
1433 * Arguments: info pointer to device instance data
1434 * Return Value: None
1435 */
1436static void mgsl_isr_receive_data( struct mgsl_struct *info )
1437{
1438 int Fifocount;
1439 u16 status;
33f0f88f 1440 int work = 0;
1da177e4 1441 unsigned char DataByte;
8fb06c77 1442 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 1443 struct mgsl_icount *icount = &info->icount;
1444
1445 if ( debug_level >= DEBUG_LEVEL_ISR )
1446 printk("%s(%d):mgsl_isr_receive_data\n",
1447 __FILE__,__LINE__);
1448
1449 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1450
1451 /* select FIFO status for RICR readback */
1452 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1453
1454 /* clear the Wordstatus bit so that status readback */
1455 /* only reflects the status of this byte */
1456 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1457
1458 /* flush the receive FIFO */
1459
1460 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
33f0f88f
AC		 1461 int flag;
1462
1da177e4
LT		 1463 /* read one byte from RxFIFO */
1464 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1465 info->io_base + CCAR );
1466 DataByte = inb( info->io_base + CCAR );
1467
1468 /* get the status of the received byte */
1469 status = usc_InReg(info, RCSR);
1470 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1471 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1472 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1473
1da177e4
LT		 1474 icount->rx++;
1475
33f0f88f 1476 flag = 0;
1da177e4
LT		 1477 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1478 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1479 printk("rxerr=%04X\n",status);
1480 /* update error statistics */
1481 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1482 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1483 icount->brk++;
1484 } else if (status & RXSTATUS_PARITY_ERROR)
1485 icount->parity++;
1486 else if (status & RXSTATUS_FRAMING_ERROR)
1487 icount->frame++;
1488 else if (status & RXSTATUS_OVERRUN) {
1489 /* must issue purge fifo cmd before */
1490 /* 16C32 accepts more receive chars */
1491 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1492 icount->overrun++;
1493 }
1494
1495 /* discard char if tty control flags say so */
1496 if (status & info->ignore_status_mask)
1497 continue;
1498
1499 status &= info->read_status_mask;
1500
1501 if (status & RXSTATUS_BREAK_RECEIVED) {
33f0f88f 1502 flag = TTY_BREAK;
8fb06c77 1503 if (info->port.flags & ASYNC_SAK)
1da177e4
LT		 1504 do_SAK(tty);
1505 } else if (status & RXSTATUS_PARITY_ERROR)
33f0f88f 1506 flag = TTY_PARITY;
1da177e4 1507 else if (status & RXSTATUS_FRAMING_ERROR)
33f0f88f 1508 flag = TTY_FRAME;
1da177e4 1509 } /* end of if (error) */
92a19f9c 1510 tty_insert_flip_char(&info->port, DataByte, flag);
33f0f88f
AC		 1511 if (status & RXSTATUS_OVERRUN) {
1512 /* Overrun is special, since it's
1513 * reported immediately, and doesn't
1514 * affect the current character
1515 */
92a19f9c 1516 work += tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
33f0f88f 1517 }
1da177e4
LT		 1518 }
1519
1520 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1da177e4
LT		 1521 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1522 __FILE__,__LINE__,icount->rx,icount->brk,
1523 icount->parity,icount->frame,icount->overrun);
1524 }
1525
33f0f88f 1526 if(work)
1da177e4
LT		 1527 tty_flip_buffer_push(tty);
1528}
1529
1530/* mgsl_isr_misc()
1531 *
8dfba4d7 1532 * Service a miscellaneous interrupt source.
1da177e4
LT		 1533 *
1534 * Arguments: info pointer to device extension (instance data)
1535 * Return Value: None
1536 */
1537static void mgsl_isr_misc( struct mgsl_struct *info )
1538{
1539 u16 status = usc_InReg( info, MISR );
1540
1541 if ( debug_level >= DEBUG_LEVEL_ISR )
1542 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1543 __FILE__,__LINE__,status);
1544
1545 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1546 (info->params.mode == MGSL_MODE_HDLC)) {
1547
1548 /* turn off receiver and rx DMA */
1549 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1550 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1551 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1552 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1553 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1554
1555 /* schedule BH handler to restart receiver */
1556 info->pending_bh |= BH_RECEIVE;
0fab6de0 1557 info->rx_rcc_underrun = true;
1da177e4
LT		 1558 }
1559
1560 usc_ClearIrqPendingBits( info, MISC );
1561 usc_UnlatchMiscstatusBits( info, status );
1562
1563} /* end of mgsl_isr_misc() */
1564
1565/* mgsl_isr_null()
1566 *
1567 * Services undefined interrupt vectors from the
1568 * USC. (hence this function SHOULD never be called)
1569 *
1570 * Arguments: info pointer to device extension (instance data)
1571 * Return Value: None
1572 */
1573static void mgsl_isr_null( struct mgsl_struct *info )
1574{
1575
1576} /* end of mgsl_isr_null() */
1577
1578/* mgsl_isr_receive_dma()
1579 *
1580 * Service a receive DMA channel interrupt.
1581 * For this driver there are two sources of receive DMA interrupts
1582 * as identified in the Receive DMA mode Register (RDMR):
1583 *
1584 * BIT3 EOA/EOL End of List, all receive buffers in receive
1585 * buffer list have been filled (no more free buffers
1586 * available). The DMA controller has shut down.
1587 *
1588 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1589 * DMA buffer is terminated in response to completion
1590 * of a good frame or a frame with errors. The status
1591 * of the frame is stored in the buffer entry in the
1592 * list of receive buffer entries.
1593 *
1594 * Arguments: info pointer to device instance data
1595 * Return Value: None
1596 */
1597static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1598{
1599 u16 status;
1600
1601 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1602 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1603
1604 /* Read the receive DMA status to identify interrupt type. */
1605 /* This also clears the status bits. */
1606 status = usc_InDmaReg( info, RDMR );
1607
1608 if ( debug_level >= DEBUG_LEVEL_ISR )
1609 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1610 __FILE__,__LINE__,info->device_name,status);
1611
1612 info->pending_bh |= BH_RECEIVE;
1613
1614 if ( status & BIT3 ) {
0fab6de0 1615 info->rx_overflow = true;
1da177e4
LT		 1616 info->icount.buf_overrun++;
1617 }
1618
1619} /* end of mgsl_isr_receive_dma() */
1620
1621/* mgsl_isr_transmit_dma()
1622 *
1623 * This function services a transmit DMA channel interrupt.
1624 *
1625 * For this driver there is one source of transmit DMA interrupts
1626 * as identified in the Transmit DMA Mode Register (TDMR):
1627 *
1628 * BIT2 EOB End of Buffer. This interrupt occurs when a
1629 * transmit DMA buffer has been emptied.
1630 *
1631 * The driver maintains enough transmit DMA buffers to hold at least
1632 * one max frame size transmit frame. When operating in a buffered
1633 * transmit mode, there may be enough transmit DMA buffers to hold at
1634 * least two or more max frame size frames. On an EOB condition,
1635 * determine if there are any queued transmit buffers and copy into
1636 * transmit DMA buffers if we have room.
1637 *
1638 * Arguments: info pointer to device instance data
1639 * Return Value: None
1640 */
1641static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1642{
1643 u16 status;
1644
1645 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1646 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1647
1648 /* Read the transmit DMA status to identify interrupt type. */
1649 /* This also clears the status bits. */
1650
1651 status = usc_InDmaReg( info, TDMR );
1652
1653 if ( debug_level >= DEBUG_LEVEL_ISR )
1654 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1655 __FILE__,__LINE__,info->device_name,status);
1656
1657 if ( status & BIT2 ) {
1658 --info->tx_dma_buffers_used;
1659
1660 /* if there are transmit frames queued,
1661 * try to load the next one
1662 */
1663 if ( load_next_tx_holding_buffer(info) ) {
1664 /* if call returns non-zero value, we have
1665 * at least one free tx holding buffer
1666 */
1667 info->pending_bh |= BH_TRANSMIT;
1668 }
1669 }
1670
1671} /* end of mgsl_isr_transmit_dma() */
1672
1673/* mgsl_interrupt()
1674 *
1675 * Interrupt service routine entry point.
1676 *
1677 * Arguments:
1678 *
1679 * irq interrupt number that caused interrupt
1680 * dev_id device ID supplied during interrupt registration
1da177e4
LT		 1681 *
1682 * Return Value: None
1683 */
a6f97b29 1684static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1da177e4 1685{
a6f97b29 1686 struct mgsl_struct *info = dev_id;
1da177e4
LT		 1687 u16 UscVector;
1688 u16 DmaVector;
1689
1690 if ( debug_level >= DEBUG_LEVEL_ISR )
a6f97b29
JG		 1691 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1692 __FILE__, __LINE__, info->irq_level);
1da177e4 1693
1da177e4
LT		 1694 spin_lock(&info->irq_spinlock);
1695
1696 for(;;) {
1697 /* Read the interrupt vectors from hardware. */
1698 UscVector = usc_InReg(info, IVR) >> 9;
1699 DmaVector = usc_InDmaReg(info, DIVR);
1700
1701 if ( debug_level >= DEBUG_LEVEL_ISR )
1702 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1703 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1704
1705 if ( !UscVector && !DmaVector )
1706 break;
1707
1708 /* Dispatch interrupt vector */
1709 if ( UscVector )
1710 (*UscIsrTable[UscVector])(info);
1711 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1712 mgsl_isr_transmit_dma(info);
1713 else
1714 mgsl_isr_receive_dma(info);
1715
1716 if ( info->isr_overflow ) {
a6f97b29
JG		 1717 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1718 __FILE__, __LINE__, info->device_name, info->irq_level);
1da177e4
LT		 1719 usc_DisableMasterIrqBit(info);
1720 usc_DisableDmaInterrupts(info,DICR_MASTER);
1721 break;
1722 }
1723 }
1724
1725 /* Request bottom half processing if there's something
1726 * for it to do and the bh is not already running
1727 */
1728
1729 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1730 if ( debug_level >= DEBUG_LEVEL_ISR )
1731 printk("%s(%d):%s queueing bh task.\n",
1732 __FILE__,__LINE__,info->device_name);
1733 schedule_work(&info->task);
0fab6de0 1734 info->bh_requested = true;
1da177e4
LT		 1735 }
1736
1737 spin_unlock(&info->irq_spinlock);
1738
1739 if ( debug_level >= DEBUG_LEVEL_ISR )
a6f97b29
JG		 1740 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1741 __FILE__, __LINE__, info->irq_level);
1742
1da177e4
LT		 1743 return IRQ_HANDLED;
1744} /* end of mgsl_interrupt() */
1745
1746/* startup()
1747 *
1748 * Initialize and start device.
1749 *
1750 * Arguments: info pointer to device instance data
1751 * Return Value: 0 if success, otherwise error code
1752 */
1753static int startup(struct mgsl_struct * info)
1754{
1755 int retval = 0;
1756
1757 if ( debug_level >= DEBUG_LEVEL_INFO )
1758 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1759
8fb06c77 1760 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4
LT		 1761 return 0;
1762
1763 if (!info->xmit_buf) {
1764 /* allocate a page of memory for a transmit buffer */
1765 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1766 if (!info->xmit_buf) {
1767 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1768 __FILE__,__LINE__,info->device_name);
1769 return -ENOMEM;
1770 }
1771 }
1772
1773 info->pending_bh = 0;
1774
9661239f
PF		 1775 memset(&info->icount, 0, sizeof(info->icount));
1776
40565f19 1777 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1da177e4
LT		 1778
1779 /* Allocate and claim adapter resources */
1780 retval = mgsl_claim_resources(info);
1781
1782 /* perform existence check and diagnostics */
1783 if ( !retval )
1784 retval = mgsl_adapter_test(info);
1785
1786 if ( retval ) {
8fb06c77
AC		 1787 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1788 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 1789 mgsl_release_resources(info);
1790 return retval;
1791 }
1792
1793 /* program hardware for current parameters */
1794 mgsl_change_params(info);
1795
8fb06c77
AC		 1796 if (info->port.tty)
1797 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 1798
8fb06c77 1799 info->port.flags |= ASYNC_INITIALIZED;
1da177e4
LT		 1800
1801 return 0;
1802
1803} /* end of startup() */
1804
1805/* shutdown()
1806 *
1807 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1808 *
1809 * Arguments: info pointer to device instance data
1810 * Return Value: None
1811 */
1812static void shutdown(struct mgsl_struct * info)
1813{
1814 unsigned long flags;
1815
8fb06c77 1816 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 1817 return;
1818
1819 if (debug_level >= DEBUG_LEVEL_INFO)
1820 printk("%s(%d):mgsl_shutdown(%s)\n",
1821 __FILE__,__LINE__, info->device_name );
1822
1823 /* clear status wait queue because status changes */
1824 /* can't happen after shutting down the hardware */
1825 wake_up_interruptible(&info->status_event_wait_q);
1826 wake_up_interruptible(&info->event_wait_q);
1827
40565f19 1828 del_timer_sync(&info->tx_timer);
1da177e4
LT		 1829
1830 if (info->xmit_buf) {
1831 free_page((unsigned long) info->xmit_buf);
1832 info->xmit_buf = NULL;
1833 }
1834
1835 spin_lock_irqsave(&info->irq_spinlock,flags);
1836 usc_DisableMasterIrqBit(info);
1837 usc_stop_receiver(info);
1838 usc_stop_transmitter(info);
1839 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1840 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1841 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
adc8d746 1842
1da177e4
LT		 1843 /* Disable DMAEN (Port 7, Bit 14) */
1844 /* This disconnects the DMA request signal from the ISA bus */
1845 /* on the ISA adapter. This has no effect for the PCI adapter */
1846 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
adc8d746 1847
1da177e4
LT		 1848 /* Disable INTEN (Port 6, Bit12) */
1849 /* This disconnects the IRQ request signal to the ISA bus */
1850 /* on the ISA adapter. This has no effect for the PCI adapter */
1851 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
adc8d746
AC		 1852
1853 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
1da177e4
LT		 1854 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1855 usc_set_serial_signals(info);
1856 }
adc8d746 1857
1da177e4
LT		 1858 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1859
1860 mgsl_release_resources(info);
1861
8fb06c77
AC		 1862 if (info->port.tty)
1863 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 1864
8fb06c77 1865 info->port.flags &= ~ASYNC_INITIALIZED;
1da177e4
LT		 1866
1867} /* end of shutdown() */
1868
1869static void mgsl_program_hw(struct mgsl_struct *info)
1870{
1871 unsigned long flags;
1872
1873 spin_lock_irqsave(&info->irq_spinlock,flags);
1874
1875 usc_stop_receiver(info);
1876 usc_stop_transmitter(info);
1877 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1878
1879 if (info->params.mode == MGSL_MODE_HDLC ||
1880 info->params.mode == MGSL_MODE_RAW ||
1881 info->netcount)
1882 usc_set_sync_mode(info);
1883 else
1884 usc_set_async_mode(info);
1885
1886 usc_set_serial_signals(info);
1887
1888 info->dcd_chkcount = 0;
1889 info->cts_chkcount = 0;
1890 info->ri_chkcount = 0;
1891 info->dsr_chkcount = 0;
1892
1893 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1894 usc_EnableInterrupts(info, IO_PIN);
1895 usc_get_serial_signals(info);
1896
adc8d746 1897 if (info->netcount || info->port.tty->termios.c_cflag & CREAD)
1da177e4
LT		 1898 usc_start_receiver(info);
1899
1900 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1901}
1902
1903/* Reconfigure adapter based on new parameters
1904 */
1905static void mgsl_change_params(struct mgsl_struct *info)
1906{
1907 unsigned cflag;
1908 int bits_per_char;
1909
adc8d746 1910 if (!info->port.tty)
1da177e4
LT		 1911 return;
1912
1913 if (debug_level >= DEBUG_LEVEL_INFO)
1914 printk("%s(%d):mgsl_change_params(%s)\n",
1915 __FILE__,__LINE__, info->device_name );
1916
adc8d746 1917 cflag = info->port.tty->termios.c_cflag;
1da177e4
LT		 1918
1919 /* if B0 rate (hangup) specified then negate DTR and RTS */
1920 /* otherwise assert DTR and RTS */
1921 if (cflag & CBAUD)
1922 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1923 else
1924 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1925
1926 /* byte size and parity */
1927
1928 switch (cflag & CSIZE) {
1929 case CS5: info->params.data_bits = 5; break;
1930 case CS6: info->params.data_bits = 6; break;
1931 case CS7: info->params.data_bits = 7; break;
1932 case CS8: info->params.data_bits = 8; break;
1933 /* Never happens, but GCC is too dumb to figure it out */
1934 default: info->params.data_bits = 7; break;
1935 }
1936
1937 if (cflag & CSTOPB)
1938 info->params.stop_bits = 2;
1939 else
1940 info->params.stop_bits = 1;
1941
1942 info->params.parity = ASYNC_PARITY_NONE;
1943 if (cflag & PARENB) {
1944 if (cflag & PARODD)
1945 info->params.parity = ASYNC_PARITY_ODD;
1946 else
1947 info->params.parity = ASYNC_PARITY_EVEN;
1948#ifdef CMSPAR
1949 if (cflag & CMSPAR)
1950 info->params.parity = ASYNC_PARITY_SPACE;
1951#endif
1952 }
1953
1954 /* calculate number of jiffies to transmit a full
1955 * FIFO (32 bytes) at specified data rate
1956 */
1957 bits_per_char = info->params.data_bits +
1958 info->params.stop_bits + 1;
1959
1960 /* if port data rate is set to 460800 or less then
1961 * allow tty settings to override, otherwise keep the
1962 * current data rate.
1963 */
1964 if (info->params.data_rate <= 460800)
8fb06c77 1965 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1da177e4
LT		 1966
1967 if ( info->params.data_rate ) {
1968 info->timeout = (32*HZ*bits_per_char) /
1969 info->params.data_rate;
1970 }
1971 info->timeout += HZ/50; /* Add .02 seconds of slop */
1972
1973 if (cflag & CRTSCTS)
8fb06c77 1974 info->port.flags |= ASYNC_CTS_FLOW;
1da177e4 1975 else
8fb06c77 1976 info->port.flags &= ~ASYNC_CTS_FLOW;
1da177e4
LT		 1977
1978 if (cflag & CLOCAL)
8fb06c77 1979 info->port.flags &= ~ASYNC_CHECK_CD;
1da177e4 1980 else
8fb06c77 1981 info->port.flags |= ASYNC_CHECK_CD;
1da177e4
LT		 1982
1983 /* process tty input control flags */
1984
1985 info->read_status_mask = RXSTATUS_OVERRUN;
8fb06c77 1986 if (I_INPCK(info->port.tty))
1da177e4 1987 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
8fb06c77 1988 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1da177e4
LT		 1989 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1990
8fb06c77 1991 if (I_IGNPAR(info->port.tty))
1da177e4 1992 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
8fb06c77 1993 if (I_IGNBRK(info->port.tty)) {
1da177e4
LT		 1994 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1995 /* If ignoring parity and break indicators, ignore
1996 * overruns too. (For real raw support).
1997 */
8fb06c77 1998 if (I_IGNPAR(info->port.tty))
1da177e4
LT		 1999 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2000 }
2001
2002 mgsl_program_hw(info);
2003
2004} /* end of mgsl_change_params() */
2005
2006/* mgsl_put_char()
2007 *
2008 * Add a character to the transmit buffer.
2009 *
2010 * Arguments: tty pointer to tty information structure
2011 * ch character to add to transmit buffer
2012 *
2013 * Return Value: None
2014 */
55da7789 2015static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 2016{
07648230 2017 struct mgsl_struct *info = tty->driver_data;
1da177e4 2018 unsigned long flags;
07648230 2019 int ret = 0;
1da177e4 2020
07648230 2021 if (debug_level >= DEBUG_LEVEL_INFO) {
5098021e 2022 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
07648230 2023 __FILE__, __LINE__, ch, info->device_name);
1da177e4
LT		 2024 }
2025
2026 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
55da7789 2027 return 0;
1da177e4 2028
ca1cce49 2029 if (!info->xmit_buf)
55da7789 2030 return 0;
1da177e4 2031
07648230 2032 spin_lock_irqsave(&info->irq_spinlock, flags);
1da177e4 2033
07648230 2034 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
1da177e4
LT		 2035 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2036 info->xmit_buf[info->xmit_head++] = ch;
2037 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2038 info->xmit_cnt++;
55da7789 2039 ret = 1;
1da177e4
LT		 2040 }
2041 }
07648230 2042 spin_unlock_irqrestore(&info->irq_spinlock, flags);
55da7789 2043 return ret;
1da177e4
LT		 2044
2045} /* end of mgsl_put_char() */
2046
2047/* mgsl_flush_chars()
2048 *
2049 * Enable transmitter so remaining characters in the
2050 * transmit buffer are sent.
2051 *
2052 * Arguments: tty pointer to tty information structure
2053 * Return Value: None
2054 */
2055static void mgsl_flush_chars(struct tty_struct *tty)
2056{
c9f19e96 2057 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2058 unsigned long flags;
2059
2060 if ( debug_level >= DEBUG_LEVEL_INFO )
2061 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2062 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2063
2064 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2065 return;
2066
2067 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2068 !info->xmit_buf)
2069 return;
2070
2071 if ( debug_level >= DEBUG_LEVEL_INFO )
2072 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2073 __FILE__,__LINE__,info->device_name );
2074
2075 spin_lock_irqsave(&info->irq_spinlock,flags);
2076
2077 if (!info->tx_active) {
2078 if ( (info->params.mode == MGSL_MODE_HDLC ||
2079 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2080 /* operating in synchronous (frame oriented) mode */
2081 /* copy data from circular xmit_buf to */
2082 /* transmit DMA buffer. */
2083 mgsl_load_tx_dma_buffer(info,
2084 info->xmit_buf,info->xmit_cnt);
2085 }
2086 usc_start_transmitter(info);
2087 }
2088
2089 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2090
2091} /* end of mgsl_flush_chars() */
2092
2093/* mgsl_write()
2094 *
2095 * Send a block of data
2096 *
2097 * Arguments:
2098 *
2099 * tty pointer to tty information structure
2100 * buf pointer to buffer containing send data
2101 * count size of send data in bytes
2102 *
2103 * Return Value: number of characters written
2104 */
2105static int mgsl_write(struct tty_struct * tty,
2106 const unsigned char *buf, int count)
2107{
2108 int c, ret = 0;
c9f19e96 2109 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2110 unsigned long flags;
2111
2112 if ( debug_level >= DEBUG_LEVEL_INFO )
2113 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2114 __FILE__,__LINE__,info->device_name,count);
2115
2116 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2117 goto cleanup;
2118
ca1cce49 2119 if (!info->xmit_buf)
1da177e4
LT		 2120 goto cleanup;
2121
2122 if ( info->params.mode == MGSL_MODE_HDLC ||
2123 info->params.mode == MGSL_MODE_RAW ) {
2124 /* operating in synchronous (frame oriented) mode */
1da177e4
LT		 2125 if (info->tx_active) {
2126
2127 if ( info->params.mode == MGSL_MODE_HDLC ) {
2128 ret = 0;
2129 goto cleanup;
2130 }
2131 /* transmitter is actively sending data -
2132 * if we have multiple transmit dma and
2133 * holding buffers, attempt to queue this
2134 * frame for transmission at a later time.
2135 */
2136 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2137 /* no tx holding buffers available */
2138 ret = 0;
2139 goto cleanup;
2140 }
2141
2142 /* queue transmit frame request */
2143 ret = count;
2144 save_tx_buffer_request(info,buf,count);
2145
2146 /* if we have sufficient tx dma buffers,
2147 * load the next buffered tx request
2148 */
2149 spin_lock_irqsave(&info->irq_spinlock,flags);
2150 load_next_tx_holding_buffer(info);
2151 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2152 goto cleanup;
2153 }
2154
2155 /* if operating in HDLC LoopMode and the adapter */
2156 /* has yet to be inserted into the loop, we can't */
2157 /* transmit */
2158
2159 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2160 !usc_loopmode_active(info) )
2161 {
2162 ret = 0;
2163 goto cleanup;
2164 }
2165
2166 if ( info->xmit_cnt ) {
2167 /* Send accumulated from send_char() calls */
2168 /* as frame and wait before accepting more data. */
2169 ret = 0;
2170
2171 /* copy data from circular xmit_buf to */
2172 /* transmit DMA buffer. */
2173 mgsl_load_tx_dma_buffer(info,
2174 info->xmit_buf,info->xmit_cnt);
2175 if ( debug_level >= DEBUG_LEVEL_INFO )
2176 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2177 __FILE__,__LINE__,info->device_name);
2178 } else {
2179 if ( debug_level >= DEBUG_LEVEL_INFO )
2180 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2181 __FILE__,__LINE__,info->device_name);
2182 ret = count;
2183 info->xmit_cnt = count;
2184 mgsl_load_tx_dma_buffer(info,buf,count);
2185 }
2186 } else {
2187 while (1) {
2188 spin_lock_irqsave(&info->irq_spinlock,flags);
2189 c = min_t(int, count,
2190 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2191 SERIAL_XMIT_SIZE - info->xmit_head));
2192 if (c <= 0) {
2193 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2194 break;
2195 }
2196 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2197 info->xmit_head = ((info->xmit_head + c) &
2198 (SERIAL_XMIT_SIZE-1));
2199 info->xmit_cnt += c;
2200 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2201 buf += c;
2202 count -= c;
2203 ret += c;
2204 }
2205 }
2206
2207 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2208 spin_lock_irqsave(&info->irq_spinlock,flags);
2209 if (!info->tx_active)
2210 usc_start_transmitter(info);
2211 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2212 }
2213cleanup:
2214 if ( debug_level >= DEBUG_LEVEL_INFO )
2215 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2216 __FILE__,__LINE__,info->device_name,ret);
2217
2218 return ret;
2219
2220} /* end of mgsl_write() */
2221
2222/* mgsl_write_room()
2223 *
2224 * Return the count of free bytes in transmit buffer
2225 *
2226 * Arguments: tty pointer to tty info structure
2227 * Return Value: None
2228 */
2229static int mgsl_write_room(struct tty_struct *tty)
2230{
c9f19e96 2231 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2232 int ret;
2233
2234 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2235 return 0;
2236 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2237 if (ret < 0)
2238 ret = 0;
2239
2240 if (debug_level >= DEBUG_LEVEL_INFO)
2241 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2242 __FILE__,__LINE__, info->device_name,ret );
2243
2244 if ( info->params.mode == MGSL_MODE_HDLC ||
2245 info->params.mode == MGSL_MODE_RAW ) {
2246 /* operating in synchronous (frame oriented) mode */
2247 if ( info->tx_active )
2248 return 0;
2249 else
2250 return HDLC_MAX_FRAME_SIZE;
2251 }
2252
2253 return ret;
2254
2255} /* end of mgsl_write_room() */
2256
2257/* mgsl_chars_in_buffer()
2258 *
2259 * Return the count of bytes in transmit buffer
2260 *
2261 * Arguments: tty pointer to tty info structure
2262 * Return Value: None
2263 */
2264static int mgsl_chars_in_buffer(struct tty_struct *tty)
2265{
c9f19e96 2266 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2267
2268 if (debug_level >= DEBUG_LEVEL_INFO)
2269 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2270 __FILE__,__LINE__, info->device_name );
2271
2272 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2273 return 0;
2274
2275 if (debug_level >= DEBUG_LEVEL_INFO)
2276 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2277 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2278
2279 if ( info->params.mode == MGSL_MODE_HDLC ||
2280 info->params.mode == MGSL_MODE_RAW ) {
2281 /* operating in synchronous (frame oriented) mode */
2282 if ( info->tx_active )
2283 return info->max_frame_size;
2284 else
2285 return 0;
2286 }
2287
2288 return info->xmit_cnt;
2289} /* end of mgsl_chars_in_buffer() */
2290
2291/* mgsl_flush_buffer()
2292 *
2293 * Discard all data in the send buffer
2294 *
2295 * Arguments: tty pointer to tty info structure
2296 * Return Value: None
2297 */
2298static void mgsl_flush_buffer(struct tty_struct *tty)
2299{
c9f19e96 2300 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2301 unsigned long flags;
2302
2303 if (debug_level >= DEBUG_LEVEL_INFO)
2304 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2305 __FILE__,__LINE__, info->device_name );
2306
2307 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2308 return;
2309
2310 spin_lock_irqsave(&info->irq_spinlock,flags);
2311 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2312 del_timer(&info->tx_timer);
2313 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2314
1da177e4
LT		 2315 tty_wakeup(tty);
2316}
2317
2318/* mgsl_send_xchar()
2319 *
2320 * Send a high-priority XON/XOFF character
2321 *
2322 * Arguments: tty pointer to tty info structure
2323 * ch character to send
2324 * Return Value: None
2325 */
2326static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2327{
c9f19e96 2328 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2329 unsigned long flags;
2330
2331 if (debug_level >= DEBUG_LEVEL_INFO)
2332 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2333 __FILE__,__LINE__, info->device_name, ch );
2334
2335 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2336 return;
2337
2338 info->x_char = ch;
2339 if (ch) {
2340 /* Make sure transmit interrupts are on */
2341 spin_lock_irqsave(&info->irq_spinlock,flags);
2342 if (!info->tx_enabled)
2343 usc_start_transmitter(info);
2344 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2345 }
2346} /* end of mgsl_send_xchar() */
2347
2348/* mgsl_throttle()
2349 *
2350 * Signal remote device to throttle send data (our receive data)
2351 *
2352 * Arguments: tty pointer to tty info structure
2353 * Return Value: None
2354 */
2355static void mgsl_throttle(struct tty_struct * tty)
2356{
c9f19e96 2357 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2358 unsigned long flags;
2359
2360 if (debug_level >= DEBUG_LEVEL_INFO)
2361 printk("%s(%d):mgsl_throttle(%s) entry\n",
2362 __FILE__,__LINE__, info->device_name );
2363
2364 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2365 return;
2366
2367 if (I_IXOFF(tty))
2368 mgsl_send_xchar(tty, STOP_CHAR(tty));
adc8d746
AC		 2369
2370 if (tty->termios.c_cflag & CRTSCTS) {
1da177e4
LT		 2371 spin_lock_irqsave(&info->irq_spinlock,flags);
2372 info->serial_signals &= ~SerialSignal_RTS;
2373 usc_set_serial_signals(info);
2374 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2375 }
2376} /* end of mgsl_throttle() */
2377
2378/* mgsl_unthrottle()
2379 *
2380 * Signal remote device to stop throttling send data (our receive data)
2381 *
2382 * Arguments: tty pointer to tty info structure
2383 * Return Value: None
2384 */
2385static void mgsl_unthrottle(struct tty_struct * tty)
2386{
c9f19e96 2387 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2388 unsigned long flags;
2389
2390 if (debug_level >= DEBUG_LEVEL_INFO)
2391 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2392 __FILE__,__LINE__, info->device_name );
2393
2394 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2395 return;
2396
2397 if (I_IXOFF(tty)) {
2398 if (info->x_char)
2399 info->x_char = 0;
2400 else
2401 mgsl_send_xchar(tty, START_CHAR(tty));
2402 }
adc8d746
AC		 2403
2404 if (tty->termios.c_cflag & CRTSCTS) {
1da177e4
LT		 2405 spin_lock_irqsave(&info->irq_spinlock,flags);
2406 info->serial_signals |= SerialSignal_RTS;
2407 usc_set_serial_signals(info);
2408 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2409 }
2410
2411} /* end of mgsl_unthrottle() */
2412
2413/* mgsl_get_stats()
2414 *
2415 * get the current serial parameters information
2416 *
2417 * Arguments: info pointer to device instance data
2418 * user_icount pointer to buffer to hold returned stats
2419 *
2420 * Return Value: 0 if success, otherwise error code
2421 */
2422static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2423{
2424 int err;
2425
2426 if (debug_level >= DEBUG_LEVEL_INFO)
2427 printk("%s(%d):mgsl_get_params(%s)\n",
2428 __FILE__,__LINE__, info->device_name);
2429
9661239f
PF		 2430 if (!user_icount) {
2431 memset(&info->icount, 0, sizeof(info->icount));
2432 } else {
f602501d 2433 mutex_lock(&info->port.mutex);
9661239f 2434 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
f602501d 2435 mutex_unlock(&info->port.mutex);
9661239f
PF		 2436 if (err)
2437 return -EFAULT;
1da177e4
LT		 2438 }
2439
2440 return 0;
2441
2442} /* end of mgsl_get_stats() */
2443
2444/* mgsl_get_params()
2445 *
2446 * get the current serial parameters information
2447 *
2448 * Arguments: info pointer to device instance data
2449 * user_params pointer to buffer to hold returned params
2450 *
2451 * Return Value: 0 if success, otherwise error code
2452 */
2453static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2454{
2455 int err;
2456 if (debug_level >= DEBUG_LEVEL_INFO)
2457 printk("%s(%d):mgsl_get_params(%s)\n",
2458 __FILE__,__LINE__, info->device_name);
2459
f602501d 2460 mutex_lock(&info->port.mutex);
1da177e4 2461 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
f602501d 2462 mutex_unlock(&info->port.mutex);
1da177e4
LT		 2463 if (err) {
2464 if ( debug_level >= DEBUG_LEVEL_INFO )
2465 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2466 __FILE__,__LINE__,info->device_name);
2467 return -EFAULT;
2468 }
2469
2470 return 0;
2471
2472} /* end of mgsl_get_params() */
2473
2474/* mgsl_set_params()
2475 *
2476 * set the serial parameters
2477 *
2478 * Arguments:
2479 *
2480 * info pointer to device instance data
2481 * new_params user buffer containing new serial params
2482 *
2483 * Return Value: 0 if success, otherwise error code
2484 */
2485static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2486{
2487 unsigned long flags;
2488 MGSL_PARAMS tmp_params;
2489 int err;
2490
2491 if (debug_level >= DEBUG_LEVEL_INFO)
2492 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2493 info->device_name );
2494 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2495 if (err) {
2496 if ( debug_level >= DEBUG_LEVEL_INFO )
2497 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2498 __FILE__,__LINE__,info->device_name);
2499 return -EFAULT;
2500 }
2501
f602501d 2502 mutex_lock(&info->port.mutex);
1da177e4
LT		 2503 spin_lock_irqsave(&info->irq_spinlock,flags);
2504 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2505 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2506
2507 mgsl_change_params(info);
f602501d 2508 mutex_unlock(&info->port.mutex);
1da177e4
LT		 2509
2510 return 0;
2511
2512} /* end of mgsl_set_params() */
2513
2514/* mgsl_get_txidle()
2515 *
2516 * get the current transmit idle mode
2517 *
2518 * Arguments: info pointer to device instance data
2519 * idle_mode pointer to buffer to hold returned idle mode
2520 *
2521 * Return Value: 0 if success, otherwise error code
2522 */
2523static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2524{
2525 int err;
2526
2527 if (debug_level >= DEBUG_LEVEL_INFO)
2528 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2529 __FILE__,__LINE__, info->device_name, info->idle_mode);
2530
2531 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2532 if (err) {
2533 if ( debug_level >= DEBUG_LEVEL_INFO )
2534 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2535 __FILE__,__LINE__,info->device_name);
2536 return -EFAULT;
2537 }
2538
2539 return 0;
2540
2541} /* end of mgsl_get_txidle() */
2542
2543/* mgsl_set_txidle() service ioctl to set transmit idle mode
2544 *
2545 * Arguments: info pointer to device instance data
2546 * idle_mode new idle mode
2547 *
2548 * Return Value: 0 if success, otherwise error code
2549 */
2550static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2551{
2552 unsigned long flags;
2553
2554 if (debug_level >= DEBUG_LEVEL_INFO)
2555 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2556 info->device_name, idle_mode );
2557
2558 spin_lock_irqsave(&info->irq_spinlock,flags);
2559 info->idle_mode = idle_mode;
2560 usc_set_txidle( info );
2561 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2562 return 0;
2563
2564} /* end of mgsl_set_txidle() */
2565
2566/* mgsl_txenable()
2567 *
2568 * enable or disable the transmitter
2569 *
2570 * Arguments:
2571 *
2572 * info pointer to device instance data
2573 * enable 1 = enable, 0 = disable
2574 *
2575 * Return Value: 0 if success, otherwise error code
2576 */
2577static int mgsl_txenable(struct mgsl_struct * info, int enable)
2578{
2579 unsigned long flags;
2580
2581 if (debug_level >= DEBUG_LEVEL_INFO)
2582 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2583 info->device_name, enable);
2584
2585 spin_lock_irqsave(&info->irq_spinlock,flags);
2586 if ( enable ) {
2587 if ( !info->tx_enabled ) {
2588
2589 usc_start_transmitter(info);
2590 /*--------------------------------------------------
2591 * if HDLC/SDLC Loop mode, attempt to insert the
2592 * station in the 'loop' by setting CMR:13. Upon
2593 * receipt of the next GoAhead (RxAbort) sequence,
2594 * the OnLoop indicator (CCSR:7) should go active
2595 * to indicate that we are on the loop
2596 *--------------------------------------------------*/
2597 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2598 usc_loopmode_insert_request( info );
2599 }
2600 } else {
2601 if ( info->tx_enabled )
2602 usc_stop_transmitter(info);
2603 }
2604 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2605 return 0;
2606
2607} /* end of mgsl_txenable() */
2608
2609/* mgsl_txabort() abort send HDLC frame
2610 *
2611 * Arguments: info pointer to device instance data
2612 * Return Value: 0 if success, otherwise error code
2613 */
2614static int mgsl_txabort(struct mgsl_struct * info)
2615{
2616 unsigned long flags;
2617
2618 if (debug_level >= DEBUG_LEVEL_INFO)
2619 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2620 info->device_name);
2621
2622 spin_lock_irqsave(&info->irq_spinlock,flags);
2623 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2624 {
2625 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2626 usc_loopmode_cancel_transmit( info );
2627 else
2628 usc_TCmd(info,TCmd_SendAbort);
2629 }
2630 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2631 return 0;
2632
2633} /* end of mgsl_txabort() */
2634
2635/* mgsl_rxenable() enable or disable the receiver
2636 *
2637 * Arguments: info pointer to device instance data
2638 * enable 1 = enable, 0 = disable
2639 * Return Value: 0 if success, otherwise error code
2640 */
2641static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2642{
2643 unsigned long flags;
2644
2645 if (debug_level >= DEBUG_LEVEL_INFO)
2646 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2647 info->device_name, enable);
2648
2649 spin_lock_irqsave(&info->irq_spinlock,flags);
2650 if ( enable ) {
2651 if ( !info->rx_enabled )
2652 usc_start_receiver(info);
2653 } else {
2654 if ( info->rx_enabled )
2655 usc_stop_receiver(info);
2656 }
2657 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2658 return 0;
2659
2660} /* end of mgsl_rxenable() */
2661
2662/* mgsl_wait_event() wait for specified event to occur
2663 *
2664 * Arguments: info pointer to device instance data
2665 * mask pointer to bitmask of events to wait for
2666 * Return Value: 0 if successful and bit mask updated with
2667 * of events triggerred,
2668 * otherwise error code
2669 */
2670static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2671{
2672 unsigned long flags;
2673 int s;
2674 int rc=0;
2675 struct mgsl_icount cprev, cnow;
2676 int events;
2677 int mask;
2678 struct _input_signal_events oldsigs, newsigs;
2679 DECLARE_WAITQUEUE(wait, current);
2680
2681 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2682 if (rc) {
2683 return -EFAULT;
2684 }
2685
2686 if (debug_level >= DEBUG_LEVEL_INFO)
2687 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2688 info->device_name, mask);
2689
2690 spin_lock_irqsave(&info->irq_spinlock,flags);
2691
2692 /* return immediately if state matches requested events */
2693 usc_get_serial_signals(info);
2694 s = info->serial_signals;
2695 events = mask &
2696 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2697 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2698 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2699 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2700 if (events) {
2701 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2702 goto exit;
2703 }
2704
2705 /* save current irq counts */
2706 cprev = info->icount;
2707 oldsigs = info->input_signal_events;
2708
2709 /* enable hunt and idle irqs if needed */
2710 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2711 u16 oldreg = usc_InReg(info,RICR);
2712 u16 newreg = oldreg +
2713 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2714 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2715 if (oldreg != newreg)
2716 usc_OutReg(info, RICR, newreg);
2717 }
2718
2719 set_current_state(TASK_INTERRUPTIBLE);
2720 add_wait_queue(&info->event_wait_q, &wait);
2721
2722 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2723
2724
2725 for(;;) {
2726 schedule();
2727 if (signal_pending(current)) {
2728 rc = -ERESTARTSYS;
2729 break;
2730 }
2731
2732 /* get current irq counts */
2733 spin_lock_irqsave(&info->irq_spinlock,flags);
2734 cnow = info->icount;
2735 newsigs = info->input_signal_events;
2736 set_current_state(TASK_INTERRUPTIBLE);
2737 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2738
2739 /* if no change, wait aborted for some reason */
2740 if (newsigs.dsr_up == oldsigs.dsr_up &&
2741 newsigs.dsr_down == oldsigs.dsr_down &&
2742 newsigs.dcd_up == oldsigs.dcd_up &&
2743 newsigs.dcd_down == oldsigs.dcd_down &&
2744 newsigs.cts_up == oldsigs.cts_up &&
2745 newsigs.cts_down == oldsigs.cts_down &&
2746 newsigs.ri_up == oldsigs.ri_up &&
2747 newsigs.ri_down == oldsigs.ri_down &&
2748 cnow.exithunt == cprev.exithunt &&
2749 cnow.rxidle == cprev.rxidle) {
2750 rc = -EIO;
2751 break;
2752 }
2753
2754 events = mask &
2755 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2756 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2757 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2758 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2759 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2760 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2761 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2762 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2763 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2764 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2765 if (events)
2766 break;
2767
2768 cprev = cnow;
2769 oldsigs = newsigs;
2770 }
2771
2772 remove_wait_queue(&info->event_wait_q, &wait);
2773 set_current_state(TASK_RUNNING);
2774
2775 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2776 spin_lock_irqsave(&info->irq_spinlock,flags);
2777 if (!waitqueue_active(&info->event_wait_q)) {
2778 /* disable enable exit hunt mode/idle rcvd IRQs */
2779 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2780 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2781 }
2782 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2783 }
2784exit:
2785 if ( rc == 0 )
2786 PUT_USER(rc, events, mask_ptr);
2787
2788 return rc;
2789
2790} /* end of mgsl_wait_event() */
2791
2792static int modem_input_wait(struct mgsl_struct *info,int arg)
2793{
2794 unsigned long flags;
2795 int rc;
2796 struct mgsl_icount cprev, cnow;
2797 DECLARE_WAITQUEUE(wait, current);
2798
2799 /* save current irq counts */
2800 spin_lock_irqsave(&info->irq_spinlock,flags);
2801 cprev = info->icount;
2802 add_wait_queue(&info->status_event_wait_q, &wait);
2803 set_current_state(TASK_INTERRUPTIBLE);
2804 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2805
2806 for(;;) {
2807 schedule();
2808 if (signal_pending(current)) {
2809 rc = -ERESTARTSYS;
2810 break;
2811 }
2812
2813 /* get new irq counts */
2814 spin_lock_irqsave(&info->irq_spinlock,flags);
2815 cnow = info->icount;
2816 set_current_state(TASK_INTERRUPTIBLE);
2817 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2818
2819 /* if no change, wait aborted for some reason */
2820 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2821 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2822 rc = -EIO;
2823 break;
2824 }
2825
2826 /* check for change in caller specified modem input */
2827 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2828 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2829 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2830 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2831 rc = 0;
2832 break;
2833 }
2834
2835 cprev = cnow;
2836 }
2837 remove_wait_queue(&info->status_event_wait_q, &wait);
2838 set_current_state(TASK_RUNNING);
2839 return rc;
2840}
2841
2842/* return the state of the serial control and status signals
2843 */
60b33c13 2844static int tiocmget(struct tty_struct *tty)
1da177e4 2845{
c9f19e96 2846 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2847 unsigned int result;
2848 unsigned long flags;
2849
2850 spin_lock_irqsave(&info->irq_spinlock,flags);
2851 usc_get_serial_signals(info);
2852 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2853
2854 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2855 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2856 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2857 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2858 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2859 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2860
2861 if (debug_level >= DEBUG_LEVEL_INFO)
2862 printk("%s(%d):%s tiocmget() value=%08X\n",
2863 __FILE__,__LINE__, info->device_name, result );
2864 return result;
2865}
2866
2867/* set modem control signals (DTR/RTS)
2868 */
20b9d177
AC		 2869static int tiocmset(struct tty_struct *tty,
2870 unsigned int set, unsigned int clear)
1da177e4 2871{
c9f19e96 2872 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2873 unsigned long flags;
2874
2875 if (debug_level >= DEBUG_LEVEL_INFO)
2876 printk("%s(%d):%s tiocmset(%x,%x)\n",
2877 __FILE__,__LINE__,info->device_name, set, clear);
2878
2879 if (set & TIOCM_RTS)
2880 info->serial_signals |= SerialSignal_RTS;
2881 if (set & TIOCM_DTR)
2882 info->serial_signals |= SerialSignal_DTR;
2883 if (clear & TIOCM_RTS)
2884 info->serial_signals &= ~SerialSignal_RTS;
2885 if (clear & TIOCM_DTR)
2886 info->serial_signals &= ~SerialSignal_DTR;
2887
2888 spin_lock_irqsave(&info->irq_spinlock,flags);
2889 usc_set_serial_signals(info);
2890 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2891
2892 return 0;
2893}
2894
2895/* mgsl_break() Set or clear transmit break condition
2896 *
2897 * Arguments: tty pointer to tty instance data
2898 * break_state -1=set break condition, 0=clear
9e98966c 2899 * Return Value: error code
1da177e4 2900 */
9e98966c 2901static int mgsl_break(struct tty_struct *tty, int break_state)
1da177e4 2902{
c9f19e96 2903 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 2904 unsigned long flags;
2905
2906 if (debug_level >= DEBUG_LEVEL_INFO)
2907 printk("%s(%d):mgsl_break(%s,%d)\n",
2908 __FILE__,__LINE__, info->device_name, break_state);
2909
2910 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
9e98966c 2911 return -EINVAL;
1da177e4
LT		 2912
2913 spin_lock_irqsave(&info->irq_spinlock,flags);
2914 if (break_state == -1)
2915 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2916 else
2917 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2918 spin_unlock_irqrestore(&info->irq_spinlock,flags);
9e98966c 2919 return 0;
1da177e4
LT		 2920
2921} /* end of mgsl_break() */
2922
0587102c
AC		 2923/*
2924 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2925 * Return: write counters to the user passed counter struct
2926 * NB: both 1->0 and 0->1 transitions are counted except for
2927 * RI where only 0->1 is counted.
2928 */
2929static int msgl_get_icount(struct tty_struct *tty,
2930 struct serial_icounter_struct *icount)
2931
2932{
2933 struct mgsl_struct * info = tty->driver_data;
2934 struct mgsl_icount cnow; /* kernel counter temps */
2935 unsigned long flags;
2936
2937 spin_lock_irqsave(&info->irq_spinlock,flags);
2938 cnow = info->icount;
2939 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2940
2941 icount->cts = cnow.cts;
2942 icount->dsr = cnow.dsr;
2943 icount->rng = cnow.rng;
2944 icount->dcd = cnow.dcd;
2945 icount->rx = cnow.rx;
2946 icount->tx = cnow.tx;
2947 icount->frame = cnow.frame;
2948 icount->overrun = cnow.overrun;
2949 icount->parity = cnow.parity;
2950 icount->brk = cnow.brk;
2951 icount->buf_overrun = cnow.buf_overrun;
2952 return 0;
2953}
2954
1da177e4
LT		 2955/* mgsl_ioctl() Service an IOCTL request
2956 *
2957 * Arguments:
2958 *
2959 * tty pointer to tty instance data
1da177e4
LT		 2960 * cmd IOCTL command code
2961 * arg command argument/context
2962 *
2963 * Return Value: 0 if success, otherwise error code
2964 */
6caa76b7 2965static int mgsl_ioctl(struct tty_struct *tty,
1da177e4
LT		 2966 unsigned int cmd, unsigned long arg)
2967{
c9f19e96 2968 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 2969
2970 if (debug_level >= DEBUG_LEVEL_INFO)
2971 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2972 info->device_name, cmd );
2973
2974 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2975 return -ENODEV;
2976
2977 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
0587102c 2978 (cmd != TIOCMIWAIT)) {
1da177e4
LT		 2979 if (tty->flags & (1 << TTY_IO_ERROR))
2980 return -EIO;
2981 }
2982
f602501d 2983 return mgsl_ioctl_common(info, cmd, arg);
1da177e4
LT		 2984}
2985
2986static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2987{
1da177e4 2988 void __user *argp = (void __user *)arg;
1da177e4
LT		 2989
2990 switch (cmd) {
2991 case MGSL_IOCGPARAMS:
2992 return mgsl_get_params(info, argp);
2993 case MGSL_IOCSPARAMS:
2994 return mgsl_set_params(info, argp);
2995 case MGSL_IOCGTXIDLE:
2996 return mgsl_get_txidle(info, argp);
2997 case MGSL_IOCSTXIDLE:
2998 return mgsl_set_txidle(info,(int)arg);
2999 case MGSL_IOCTXENABLE:
3000 return mgsl_txenable(info,(int)arg);
3001 case MGSL_IOCRXENABLE:
3002 return mgsl_rxenable(info,(int)arg);
3003 case MGSL_IOCTXABORT:
3004 return mgsl_txabort(info);
3005 case MGSL_IOCGSTATS:
3006 return mgsl_get_stats(info, argp);
3007 case MGSL_IOCWAITEVENT:
3008 return mgsl_wait_event(info, argp);
3009 case MGSL_IOCLOOPTXDONE:
3010 return mgsl_loopmode_send_done(info);
3011 /* Wait for modem input (DCD,RI,DSR,CTS) change
3012 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3013 */
3014 case TIOCMIWAIT:
3015 return modem_input_wait(info,(int)arg);
3016
1da177e4
LT		 3017 default:
3018 return -ENOIOCTLCMD;
3019 }
3020 return 0;
3021}
3022
3023/* mgsl_set_termios()
3024 *
3025 * Set new termios settings
3026 *
3027 * Arguments:
3028 *
3029 * tty pointer to tty structure
3030 * termios pointer to buffer to hold returned old termios
3031 *
3032 * Return Value: None
3033 */
606d099c 3034static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4 3035{
c9f19e96 3036 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 3037 unsigned long flags;
3038
3039 if (debug_level >= DEBUG_LEVEL_INFO)
3040 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3041 tty->driver->name );
3042
1da177e4
LT		 3043 mgsl_change_params(info);
3044
3045 /* Handle transition to B0 status */
3046 if (old_termios->c_cflag & CBAUD &&
adc8d746 3047 !(tty->termios.c_cflag & CBAUD)) {
1da177e4
LT		 3048 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3049 spin_lock_irqsave(&info->irq_spinlock,flags);
3050 usc_set_serial_signals(info);
3051 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3052 }
3053
3054 /* Handle transition away from B0 status */
3055 if (!(old_termios->c_cflag & CBAUD) &&
adc8d746 3056 tty->termios.c_cflag & CBAUD) {
1da177e4 3057 info->serial_signals |= SerialSignal_DTR;
adc8d746 3058 if (!(tty->termios.c_cflag & CRTSCTS) ||
1da177e4
LT		 3059 !test_bit(TTY_THROTTLED, &tty->flags)) {
3060 info->serial_signals |= SerialSignal_RTS;
3061 }
3062 spin_lock_irqsave(&info->irq_spinlock,flags);
3063 usc_set_serial_signals(info);
3064 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3065 }
3066
3067 /* Handle turning off CRTSCTS */
3068 if (old_termios->c_cflag & CRTSCTS &&
adc8d746 3069 !(tty->termios.c_cflag & CRTSCTS)) {
1da177e4
LT		 3070 tty->hw_stopped = 0;
3071 mgsl_start(tty);
3072 }
3073
3074} /* end of mgsl_set_termios() */
3075
3076/* mgsl_close()
3077 *
3078 * Called when port is closed. Wait for remaining data to be
3079 * sent. Disable port and free resources.
3080 *
3081 * Arguments:
3082 *
3083 * tty pointer to open tty structure
3084 * filp pointer to open file object
3085 *
3086 * Return Value: None
3087 */
3088static void mgsl_close(struct tty_struct *tty, struct file * filp)
3089{
c9f19e96 3090 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 3091
3092 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3093 return;
3094
3095 if (debug_level >= DEBUG_LEVEL_INFO)
3096 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
8fb06c77 3097 __FILE__,__LINE__, info->device_name, info->port.count);
1da177e4 3098
a6614999 3099 if (tty_port_close_start(&info->port, tty, filp) == 0)
1da177e4 3100 goto cleanup;
f602501d
AC		 3101
3102 mutex_lock(&info->port.mutex);
8fb06c77 3103 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4 3104 mgsl_wait_until_sent(tty, info->timeout);
978e595f 3105 mgsl_flush_buffer(tty);
1da177e4 3106 tty_ldisc_flush(tty);
1da177e4 3107 shutdown(info);
f602501d 3108 mutex_unlock(&info->port.mutex);
a6614999
AC		 3109
3110 tty_port_close_end(&info->port, tty);
8fb06c77 3111 info->port.tty = NULL;
1da177e4
LT		 3112cleanup:
3113 if (debug_level >= DEBUG_LEVEL_INFO)
3114 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
8fb06c77 3115 tty->driver->name, info->port.count);
1da177e4
LT		 3116
3117} /* end of mgsl_close() */
3118
3119/* mgsl_wait_until_sent()
3120 *
3121 * Wait until the transmitter is empty.
3122 *
3123 * Arguments:
3124 *
3125 * tty pointer to tty info structure
3126 * timeout time to wait for send completion
3127 *
3128 * Return Value: None
3129 */
3130static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3131{
c9f19e96 3132 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 3133 unsigned long orig_jiffies, char_time;
3134
3135 if (!info )
3136 return;
3137
3138 if (debug_level >= DEBUG_LEVEL_INFO)
3139 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3140 __FILE__,__LINE__, info->device_name );
3141
3142 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3143 return;
3144
8fb06c77 3145 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 3146 goto exit;
3147
3148 orig_jiffies = jiffies;
3149
3150 /* Set check interval to 1/5 of estimated time to
3151 * send a character, and make it at least 1. The check
3152 * interval should also be less than the timeout.
3153 * Note: use tight timings here to satisfy the NIST-PCTS.
3154 */
978e595f 3155
1da177e4
LT		 3156 if ( info->params.data_rate ) {
3157 char_time = info->timeout/(32 * 5);
3158 if (!char_time)
3159 char_time++;
3160 } else
3161 char_time = 1;
3162
3163 if (timeout)
3164 char_time = min_t(unsigned long, char_time, timeout);
3165
3166 if ( info->params.mode == MGSL_MODE_HDLC ||
3167 info->params.mode == MGSL_MODE_RAW ) {
3168 while (info->tx_active) {
3169 msleep_interruptible(jiffies_to_msecs(char_time));
3170 if (signal_pending(current))
3171 break;
3172 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3173 break;
3174 }
3175 } else {
3176 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3177 info->tx_enabled) {
3178 msleep_interruptible(jiffies_to_msecs(char_time));
3179 if (signal_pending(current))
3180 break;
3181 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3182 break;
3183 }
3184 }
3185
3186exit:
3187 if (debug_level >= DEBUG_LEVEL_INFO)
3188 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3189 __FILE__,__LINE__, info->device_name );
3190
3191} /* end of mgsl_wait_until_sent() */
3192
3193/* mgsl_hangup()
3194 *
3195 * Called by tty_hangup() when a hangup is signaled.
3196 * This is the same as to closing all open files for the port.
3197 *
3198 * Arguments: tty pointer to associated tty object
3199 * Return Value: None
3200 */
3201static void mgsl_hangup(struct tty_struct *tty)
3202{
c9f19e96 3203 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 3204
3205 if (debug_level >= DEBUG_LEVEL_INFO)
3206 printk("%s(%d):mgsl_hangup(%s)\n",
3207 __FILE__,__LINE__, info->device_name );
3208
3209 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3210 return;
3211
3212 mgsl_flush_buffer(tty);
3213 shutdown(info);
3214
8fb06c77
AC		 3215 info->port.count = 0;
3216 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3217 info->port.tty = NULL;
1da177e4 3218
8fb06c77 3219 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 3220
3221} /* end of mgsl_hangup() */
3222
31f35939
AC		 3223/*
3224 * carrier_raised()
3225 *
3226 * Return true if carrier is raised
3227 */
3228
3229static int carrier_raised(struct tty_port *port)
3230{
3231 unsigned long flags;
3232 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3233
3234 spin_lock_irqsave(&info->irq_spinlock, flags);
3235 usc_get_serial_signals(info);
3236 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3237 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3238}
3239
fcc8ac18 3240static void dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 3241{
3242 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3243 unsigned long flags;
3244
3245 spin_lock_irqsave(&info->irq_spinlock,flags);
fcc8ac18
AC		 3246 if (on)
3247 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3248 else
3249 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
5d951fb4
AC		 3250 usc_set_serial_signals(info);
3251 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3252}
3253
3254
1da177e4
LT		 3255/* block_til_ready()
3256 *
3257 * Block the current process until the specified port
3258 * is ready to be opened.
3259 *
3260 * Arguments:
3261 *
3262 * tty pointer to tty info structure
3263 * filp pointer to open file object
3264 * info pointer to device instance data
3265 *
3266 * Return Value: 0 if success, otherwise error code
3267 */
3268static int block_til_ready(struct tty_struct *tty, struct file * filp,
3269 struct mgsl_struct *info)
3270{
3271 DECLARE_WAITQUEUE(wait, current);
3272 int retval;
0fab6de0
JP		 3273 bool do_clocal = false;
3274 bool extra_count = false;
1da177e4 3275 unsigned long flags;
31f35939
AC		 3276 int dcd;
3277 struct tty_port *port = &info->port;
1da177e4
LT		 3278
3279 if (debug_level >= DEBUG_LEVEL_INFO)
3280 printk("%s(%d):block_til_ready on %s\n",
3281 __FILE__,__LINE__, tty->driver->name );
3282
3283 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3284 /* nonblock mode is set or port is not enabled */
31f35939 3285 port->flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 3286 return 0;
3287 }
3288
adc8d746 3289 if (tty->termios.c_cflag & CLOCAL)
0fab6de0 3290 do_clocal = true;
1da177e4
LT		 3291
3292 /* Wait for carrier detect and the line to become
3293 * free (i.e., not in use by the callout). While we are in
31f35939 3294 * this loop, port->count is dropped by one, so that
1da177e4
LT		 3295 * mgsl_close() knows when to free things. We restore it upon
3296 * exit, either normal or abnormal.
3297 */
3298
3299 retval = 0;
31f35939 3300 add_wait_queue(&port->open_wait, &wait);
1da177e4
LT		 3301
3302 if (debug_level >= DEBUG_LEVEL_INFO)
3303 printk("%s(%d):block_til_ready before block on %s count=%d\n",
31f35939 3304 __FILE__,__LINE__, tty->driver->name, port->count );
1da177e4
LT		 3305
3306 spin_lock_irqsave(&info->irq_spinlock, flags);
3307 if (!tty_hung_up_p(filp)) {
0fab6de0 3308 extra_count = true;
31f35939 3309 port->count--;
1da177e4
LT		 3310 }
3311 spin_unlock_irqrestore(&info->irq_spinlock, flags);
31f35939 3312 port->blocked_open++;
1da177e4
LT		 3313
3314 while (1) {
adc8d746 3315 if (tty->termios.c_cflag & CBAUD)
5d951fb4 3316 tty_port_raise_dtr_rts(port);
1da177e4
LT		 3317
3318 set_current_state(TASK_INTERRUPTIBLE);
3319
31f35939
AC		 3320 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3321 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 3322 -EAGAIN : -ERESTARTSYS;
3323 break;
3324 }
3325
31f35939 3326 dcd = tty_port_carrier_raised(&info->port);
1da177e4 3327
31f35939 3328 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
1da177e4 3329 break;
1da177e4
LT		 3330
3331 if (signal_pending(current)) {
3332 retval = -ERESTARTSYS;
3333 break;
3334 }
3335
3336 if (debug_level >= DEBUG_LEVEL_INFO)
3337 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
31f35939 3338 __FILE__,__LINE__, tty->driver->name, port->count );
1da177e4 3339
89c8d91e 3340 tty_unlock(tty);
1da177e4 3341 schedule();
89c8d91e 3342 tty_lock(tty);
1da177e4
LT		 3343 }
3344
3345 set_current_state(TASK_RUNNING);
31f35939 3346 remove_wait_queue(&port->open_wait, &wait);
1da177e4 3347
36c621d8 3348 /* FIXME: Racy on hangup during close wait */
1da177e4 3349 if (extra_count)
31f35939
AC		 3350 port->count++;
3351 port->blocked_open--;
1da177e4
LT		 3352
3353 if (debug_level >= DEBUG_LEVEL_INFO)
3354 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
31f35939 3355 __FILE__,__LINE__, tty->driver->name, port->count );
1da177e4
LT		 3356
3357 if (!retval)
31f35939 3358 port->flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 3359
3360 return retval;
3361
3362} /* end of block_til_ready() */
3363
8a3ad104
JS		 3364static int mgsl_install(struct tty_driver *driver, struct tty_struct *tty)
3365{
3366 struct mgsl_struct *info;
3367 int line = tty->index;
3368
3369 /* verify range of specified line number */
3370 if (line >= mgsl_device_count) {
3371 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3372 __FILE__, __LINE__, line);
3373 return -ENODEV;
3374 }
3375
3376 /* find the info structure for the specified line */
3377 info = mgsl_device_list;
3378 while (info && info->line != line)
3379 info = info->next_device;
3380 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3381 return -ENODEV;
3382 tty->driver_data = info;
3383
3384 return tty_port_install(&info->port, driver, tty);
3385}
3386
1da177e4
LT		 3387/* mgsl_open()
3388 *
3389 * Called when a port is opened. Init and enable port.
3390 * Perform serial-specific initialization for the tty structure.
3391 *
3392 * Arguments: tty pointer to tty info structure
3393 * filp associated file pointer
3394 *
3395 * Return Value: 0 if success, otherwise error code
3396 */
3397static int mgsl_open(struct tty_struct *tty, struct file * filp)
3398{
8a3ad104 3399 struct mgsl_struct *info = tty->driver_data;
1da177e4 3400 unsigned long flags;
8a3ad104 3401 int retval;
1da177e4 3402
8fb06c77 3403 info->port.tty = tty;
1da177e4
LT		 3404
3405 if (debug_level >= DEBUG_LEVEL_INFO)
3406 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
8fb06c77 3407 __FILE__,__LINE__,tty->driver->name, info->port.count);
1da177e4
LT		 3408
3409 /* If port is closing, signal caller to try again */
8fb06c77
AC		 3410 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3411 if (info->port.flags & ASYNC_CLOSING)
3412 interruptible_sleep_on(&info->port.close_wait);
3413 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 3414 -EAGAIN : -ERESTARTSYS);
3415 goto cleanup;
3416 }
3417
d6c53c0e 3418 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 3419
3420 spin_lock_irqsave(&info->netlock, flags);
3421 if (info->netcount) {
3422 retval = -EBUSY;
3423 spin_unlock_irqrestore(&info->netlock, flags);
3424 goto cleanup;
3425 }
8fb06c77 3426 info->port.count++;
1da177e4
LT		 3427 spin_unlock_irqrestore(&info->netlock, flags);
3428
8fb06c77 3429 if (info->port.count == 1) {
1da177e4
LT		 3430 /* 1st open on this device, init hardware */
3431 retval = startup(info);
3432 if (retval < 0)
3433 goto cleanup;
3434 }
3435
3436 retval = block_til_ready(tty, filp, info);
3437 if (retval) {
3438 if (debug_level >= DEBUG_LEVEL_INFO)
3439 printk("%s(%d):block_til_ready(%s) returned %d\n",
3440 __FILE__,__LINE__, info->device_name, retval);
3441 goto cleanup;
3442 }
3443
3444 if (debug_level >= DEBUG_LEVEL_INFO)
3445 printk("%s(%d):mgsl_open(%s) success\n",
3446 __FILE__,__LINE__, info->device_name);
3447 retval = 0;
3448
3449cleanup:
3450 if (retval) {
3451 if (tty->count == 1)
8fb06c77
AC		 3452 info->port.tty = NULL; /* tty layer will release tty struct */
3453 if(info->port.count)
3454 info->port.count--;
1da177e4
LT		 3455 }
3456
3457 return retval;
3458
3459} /* end of mgsl_open() */
3460
3461/*
3462 * /proc fs routines....
3463 */
3464
d337829b 3465static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
1da177e4
LT		 3466{
3467 char stat_buf[30];
1da177e4
LT		 3468 unsigned long flags;
3469
3470 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
d337829b 3471 seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
1da177e4
LT		 3472 info->device_name, info->io_base, info->irq_level,
3473 info->phys_memory_base, info->phys_lcr_base);
3474 } else {
d337829b 3475 seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
1da177e4
LT		 3476 info->device_name, info->io_base,
3477 info->irq_level, info->dma_level);
3478 }
3479
3480 /* output current serial signal states */
3481 spin_lock_irqsave(&info->irq_spinlock,flags);
3482 usc_get_serial_signals(info);
3483 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3484
3485 stat_buf[0] = 0;
3486 stat_buf[1] = 0;
3487 if (info->serial_signals & SerialSignal_RTS)
3488 strcat(stat_buf, "|RTS");
3489 if (info->serial_signals & SerialSignal_CTS)
3490 strcat(stat_buf, "|CTS");
3491 if (info->serial_signals & SerialSignal_DTR)
3492 strcat(stat_buf, "|DTR");
3493 if (info->serial_signals & SerialSignal_DSR)
3494 strcat(stat_buf, "|DSR");
3495 if (info->serial_signals & SerialSignal_DCD)
3496 strcat(stat_buf, "|CD");
3497 if (info->serial_signals & SerialSignal_RI)
3498 strcat(stat_buf, "|RI");
3499
3500 if (info->params.mode == MGSL_MODE_HDLC ||
3501 info->params.mode == MGSL_MODE_RAW ) {
d337829b 3502 seq_printf(m, " HDLC txok:%d rxok:%d",
1da177e4
LT		 3503 info->icount.txok, info->icount.rxok);
3504 if (info->icount.txunder)
d337829b 3505 seq_printf(m, " txunder:%d", info->icount.txunder);
1da177e4 3506 if (info->icount.txabort)
d337829b 3507 seq_printf(m, " txabort:%d", info->icount.txabort);
1da177e4 3508 if (info->icount.rxshort)
d337829b 3509 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1da177e4 3510 if (info->icount.rxlong)
d337829b 3511 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1da177e4 3512 if (info->icount.rxover)
d337829b 3513 seq_printf(m, " rxover:%d", info->icount.rxover);
1da177e4 3514 if (info->icount.rxcrc)
d337829b 3515 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1da177e4 3516 } else {
d337829b 3517 seq_printf(m, " ASYNC tx:%d rx:%d",
1da177e4
LT		 3518 info->icount.tx, info->icount.rx);
3519 if (info->icount.frame)
d337829b 3520 seq_printf(m, " fe:%d", info->icount.frame);
1da177e4 3521 if (info->icount.parity)
d337829b 3522 seq_printf(m, " pe:%d", info->icount.parity);
1da177e4 3523 if (info->icount.brk)
d337829b 3524 seq_printf(m, " brk:%d", info->icount.brk);
1da177e4 3525 if (info->icount.overrun)
d337829b 3526 seq_printf(m, " oe:%d", info->icount.overrun);
1da177e4
LT		 3527 }
3528
3529 /* Append serial signal status to end */
d337829b 3530 seq_printf(m, " %s\n", stat_buf+1);
1da177e4 3531
d337829b 3532 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1da177e4
LT		 3533 info->tx_active,info->bh_requested,info->bh_running,
3534 info->pending_bh);
3535
3536 spin_lock_irqsave(&info->irq_spinlock,flags);
3537 {
3538 u16 Tcsr = usc_InReg( info, TCSR );
3539 u16 Tdmr = usc_InDmaReg( info, TDMR );
3540 u16 Ticr = usc_InReg( info, TICR );
3541 u16 Rscr = usc_InReg( info, RCSR );
3542 u16 Rdmr = usc_InDmaReg( info, RDMR );
3543 u16 Ricr = usc_InReg( info, RICR );
3544 u16 Icr = usc_InReg( info, ICR );
3545 u16 Dccr = usc_InReg( info, DCCR );
3546 u16 Tmr = usc_InReg( info, TMR );
3547 u16 Tccr = usc_InReg( info, TCCR );
3548 u16 Ccar = inw( info->io_base + CCAR );
d337829b 3549 seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
1da177e4
LT		 3550 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3551 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3552 }
3553 spin_unlock_irqrestore(&info->irq_spinlock,flags);
d337829b 3554}
1da177e4 3555
d337829b
AD		 3556/* Called to print information about devices */
3557static int mgsl_proc_show(struct seq_file *m, void *v)
1da177e4 3558{
1da177e4
LT		 3559 struct mgsl_struct *info;
3560
d337829b 3561 seq_printf(m, "synclink driver:%s\n", driver_version);
1da177e4
LT		 3562
3563 info = mgsl_device_list;
3564 while( info ) {
d337829b 3565 line_info(m, info);
1da177e4
LT		 3566 info = info->next_device;
3567 }
d337829b
AD		 3568 return 0;
3569}
1da177e4 3570
d337829b
AD		 3571static int mgsl_proc_open(struct inode *inode, struct file *file)
3572{
3573 return single_open(file, mgsl_proc_show, NULL);
3574}
3575
3576static const struct file_operations mgsl_proc_fops = {
3577 .owner = THIS_MODULE,
3578 .open = mgsl_proc_open,
3579 .read = seq_read,
3580 .llseek = seq_lseek,
3581 .release = single_release,
3582};
1da177e4
LT		 3583
3584/* mgsl_allocate_dma_buffers()
3585 *
3586 * Allocate and format DMA buffers (ISA adapter)
3587 * or format shared memory buffers (PCI adapter).
3588 *
3589 * Arguments: info pointer to device instance data
3590 * Return Value: 0 if success, otherwise error
3591 */
3592static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3593{
3594 unsigned short BuffersPerFrame;
3595
3596 info->last_mem_alloc = 0;
3597
3598 /* Calculate the number of DMA buffers necessary to hold the */
3599 /* largest allowable frame size. Note: If the max frame size is */
3600 /* not an even multiple of the DMA buffer size then we need to */
3601 /* round the buffer count per frame up one. */
3602
3603 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3604 if ( info->max_frame_size % DMABUFFERSIZE )
3605 BuffersPerFrame++;
3606
3607 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3608 /*
3609 * The PCI adapter has 256KBytes of shared memory to use.
3610 * This is 64 PAGE_SIZE buffers.
3611 *
3612 * The first page is used for padding at this time so the
3613 * buffer list does not begin at offset 0 of the PCI
3614 * adapter's shared memory.
3615 *
3616 * The 2nd page is used for the buffer list. A 4K buffer
3617 * list can hold 128 DMA_BUFFER structures at 32 bytes
3618 * each.
3619 *
3620 * This leaves 62 4K pages.
3621 *
3622 * The next N pages are used for transmit frame(s). We
3623 * reserve enough 4K page blocks to hold the required
3624 * number of transmit dma buffers (num_tx_dma_buffers),
3625 * each of MaxFrameSize size.
3626 *
3627 * Of the remaining pages (62-N), determine how many can
3628 * be used to receive full MaxFrameSize inbound frames
3629 */
3630 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3631 info->rx_buffer_count = 62 - info->tx_buffer_count;
3632 } else {
3633 /* Calculate the number of PAGE_SIZE buffers needed for */
3634 /* receive and transmit DMA buffers. */
3635
3636
3637 /* Calculate the number of DMA buffers necessary to */
3638 /* hold 7 max size receive frames and one max size transmit frame. */
3639 /* The receive buffer count is bumped by one so we avoid an */
3640 /* End of List condition if all receive buffers are used when */
3641 /* using linked list DMA buffers. */
3642
3643 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3644 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3645
3646 /*
3647 * limit total TxBuffers & RxBuffers to 62 4K total
3648 * (ala PCI Allocation)
3649 */
3650
3651 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3652 info->rx_buffer_count = 62 - info->tx_buffer_count;
3653
3654 }
3655
3656 if ( debug_level >= DEBUG_LEVEL_INFO )
3657 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3658 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3659
3660 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3661 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3662 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3663 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3664 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3665 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3666 return -ENOMEM;
3667 }
3668
3669 mgsl_reset_rx_dma_buffers( info );
3670 mgsl_reset_tx_dma_buffers( info );
3671
3672 return 0;
3673
3674} /* end of mgsl_allocate_dma_buffers() */
3675
3676/*
3677 * mgsl_alloc_buffer_list_memory()
3678 *
3679 * Allocate a common DMA buffer for use as the
3680 * receive and transmit buffer lists.
3681 *
3682 * A buffer list is a set of buffer entries where each entry contains
3683 * a pointer to an actual buffer and a pointer to the next buffer entry
3684 * (plus some other info about the buffer).
3685 *
3686 * The buffer entries for a list are built to form a circular list so
3687 * that when the entire list has been traversed you start back at the
3688 * beginning.
3689 *
3690 * This function allocates memory for just the buffer entries.
3691 * The links (pointer to next entry) are filled in with the physical
3692 * address of the next entry so the adapter can navigate the list
3693 * using bus master DMA. The pointers to the actual buffers are filled
3694 * out later when the actual buffers are allocated.
3695 *
3696 * Arguments: info pointer to device instance data
3697 * Return Value: 0 if success, otherwise error
3698 */
3699static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3700{
3701 unsigned int i;
3702
3703 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3704 /* PCI adapter uses shared memory. */
3705 info->buffer_list = info->memory_base + info->last_mem_alloc;
3706 info->buffer_list_phys = info->last_mem_alloc;
3707 info->last_mem_alloc += BUFFERLISTSIZE;
3708 } else {
3709 /* ISA adapter uses system memory. */
3710 /* The buffer lists are allocated as a common buffer that both */
3711 /* the processor and adapter can access. This allows the driver to */
3712 /* inspect portions of the buffer while other portions are being */
3713 /* updated by the adapter using Bus Master DMA. */
3714
0ff1b2c8
PF		 3715 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3716 if (info->buffer_list == NULL)
1da177e4 3717 return -ENOMEM;
0ff1b2c8 3718 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
1da177e4
LT		 3719 }
3720
3721 /* We got the memory for the buffer entry lists. */
3722 /* Initialize the memory block to all zeros. */
3723 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3724
3725 /* Save virtual address pointers to the receive and */
3726 /* transmit buffer lists. (Receive 1st). These pointers will */
3727 /* be used by the processor to access the lists. */
3728 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3729 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3730 info->tx_buffer_list += info->rx_buffer_count;
3731
3732 /*
3733 * Build the links for the buffer entry lists such that
3734 * two circular lists are built. (Transmit and Receive).
3735 *
3736 * Note: the links are physical addresses
3737 * which are read by the adapter to determine the next
3738 * buffer entry to use.
3739 */
3740
3741 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3742 /* calculate and store physical address of this buffer entry */
3743 info->rx_buffer_list[i].phys_entry =
3744 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3745
3746 /* calculate and store physical address of */
3747 /* next entry in cirular list of entries */
3748
3749 info->rx_buffer_list[i].link = info->buffer_list_phys;
3750
3751 if ( i < info->rx_buffer_count - 1 )
3752 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3753 }
3754
3755 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3756 /* calculate and store physical address of this buffer entry */
3757 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3758 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3759
3760 /* calculate and store physical address of */
3761 /* next entry in cirular list of entries */
3762
3763 info->tx_buffer_list[i].link = info->buffer_list_phys +
3764 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3765
3766 if ( i < info->tx_buffer_count - 1 )
3767 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3768 }
3769
3770 return 0;
3771
3772} /* end of mgsl_alloc_buffer_list_memory() */
3773
3774/* Free DMA buffers allocated for use as the
3775 * receive and transmit buffer lists.
3776 * Warning:
3777 *
3778 * The data transfer buffers associated with the buffer list
3779 * MUST be freed before freeing the buffer list itself because
3780 * the buffer list contains the information necessary to free
3781 * the individual buffers!
3782 */
3783static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3784{
0ff1b2c8
PF		 3785 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3786 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
1da177e4
LT		 3787
3788 info->buffer_list = NULL;
3789 info->rx_buffer_list = NULL;
3790 info->tx_buffer_list = NULL;
3791
3792} /* end of mgsl_free_buffer_list_memory() */
3793
3794/*
3795 * mgsl_alloc_frame_memory()
3796 *
3797 * Allocate the frame DMA buffers used by the specified buffer list.
3798 * Each DMA buffer will be one memory page in size. This is necessary
3799 * because memory can fragment enough that it may be impossible
3800 * contiguous pages.
3801 *
3802 * Arguments:
3803 *
3804 * info pointer to device instance data
3805 * BufferList pointer to list of buffer entries
3806 * Buffercount count of buffer entries in buffer list
3807 *
3808 * Return Value: 0 if success, otherwise -ENOMEM
3809 */
3810static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3811{
3812 int i;
0ff1b2c8 3813 u32 phys_addr;
1da177e4
LT		 3814
3815 /* Allocate page sized buffers for the receive buffer list */
3816
3817 for ( i = 0; i < Buffercount; i++ ) {
3818 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3819 /* PCI adapter uses shared memory buffers. */
3820 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3821 phys_addr = info->last_mem_alloc;
3822 info->last_mem_alloc += DMABUFFERSIZE;
3823 } else {
3824 /* ISA adapter uses system memory. */
0ff1b2c8
PF		 3825 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3826 if (BufferList[i].virt_addr == NULL)
1da177e4 3827 return -ENOMEM;
0ff1b2c8 3828 phys_addr = (u32)(BufferList[i].dma_addr);
1da177e4
LT		 3829 }
3830 BufferList[i].phys_addr = phys_addr;
3831 }
3832
3833 return 0;
3834
3835} /* end of mgsl_alloc_frame_memory() */
3836
3837/*
3838 * mgsl_free_frame_memory()
3839 *
3840 * Free the buffers associated with
3841 * each buffer entry of a buffer list.
3842 *
3843 * Arguments:
3844 *
3845 * info pointer to device instance data
3846 * BufferList pointer to list of buffer entries
3847 * Buffercount count of buffer entries in buffer list
3848 *
3849 * Return Value: None
3850 */
3851static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3852{
3853 int i;
3854
3855 if ( BufferList ) {
3856 for ( i = 0 ; i < Buffercount ; i++ ) {
3857 if ( BufferList[i].virt_addr ) {
3858 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
0ff1b2c8 3859 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
1da177e4
LT		 3860 BufferList[i].virt_addr = NULL;
3861 }
3862 }
3863 }
3864
3865} /* end of mgsl_free_frame_memory() */
3866
3867/* mgsl_free_dma_buffers()
3868 *
3869 * Free DMA buffers
3870 *
3871 * Arguments: info pointer to device instance data
3872 * Return Value: None
3873 */
3874static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3875{
3876 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3877 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3878 mgsl_free_buffer_list_memory( info );
3879
3880} /* end of mgsl_free_dma_buffers() */
3881
3882
3883/*
3884 * mgsl_alloc_intermediate_rxbuffer_memory()
3885 *
3886 * Allocate a buffer large enough to hold max_frame_size. This buffer
3887 * is used to pass an assembled frame to the line discipline.
3888 *
3889 * Arguments:
3890 *
3891 * info pointer to device instance data
3892 *
3893 * Return Value: 0 if success, otherwise -ENOMEM
3894 */
3895static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3896{
3897 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3898 if ( info->intermediate_rxbuffer == NULL )
3899 return -ENOMEM;
a6b68a69
PF		 3900 /* unused flag buffer to satisfy receive_buf calling interface */
3901 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3902 if (!info->flag_buf) {
3903 kfree(info->intermediate_rxbuffer);
3904 info->intermediate_rxbuffer = NULL;
3905 return -ENOMEM;
3906 }
1da177e4
LT		 3907 return 0;
3908
3909} /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3910
3911/*
3912 * mgsl_free_intermediate_rxbuffer_memory()
3913 *
3914 *
3915 * Arguments:
3916 *
3917 * info pointer to device instance data
3918 *
3919 * Return Value: None
3920 */
3921static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3922{
735d5661 3923 kfree(info->intermediate_rxbuffer);
1da177e4 3924 info->intermediate_rxbuffer = NULL;
a6b68a69
PF		 3925 kfree(info->flag_buf);
3926 info->flag_buf = NULL;
1da177e4
LT		 3927
3928} /* end of mgsl_free_intermediate_rxbuffer_memory() */
3929
3930/*
3931 * mgsl_alloc_intermediate_txbuffer_memory()
3932 *
3933 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3934 * This buffer is used to load transmit frames into the adapter's dma transfer
3935 * buffers when there is sufficient space.
3936 *
3937 * Arguments:
3938 *
3939 * info pointer to device instance data
3940 *
3941 * Return Value: 0 if success, otherwise -ENOMEM
3942 */
3943static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3944{
3945 int i;
3946
3947 if ( debug_level >= DEBUG_LEVEL_INFO )
3948 printk("%s %s(%d) allocating %d tx holding buffers\n",
3949 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3950
3951 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3952
3953 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3954 info->tx_holding_buffers[i].buffer =
3955 kmalloc(info->max_frame_size, GFP_KERNEL);
d9a2f4a4
AC		 3956 if (info->tx_holding_buffers[i].buffer == NULL) {
3957 for (--i; i >= 0; i--) {
3958 kfree(info->tx_holding_buffers[i].buffer);
3959 info->tx_holding_buffers[i].buffer = NULL;
3960 }
1da177e4 3961 return -ENOMEM;
d9a2f4a4 3962 }
1da177e4
LT		 3963 }
3964
3965 return 0;
3966
3967} /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3968
3969/*
3970 * mgsl_free_intermediate_txbuffer_memory()
3971 *
3972 *
3973 * Arguments:
3974 *
3975 * info pointer to device instance data
3976 *
3977 * Return Value: None
3978 */
3979static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3980{
3981 int i;
3982
3983 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
735d5661
JJ		 3984 kfree(info->tx_holding_buffers[i].buffer);
3985 info->tx_holding_buffers[i].buffer = NULL;
1da177e4
LT		 3986 }
3987
3988 info->get_tx_holding_index = 0;
3989 info->put_tx_holding_index = 0;
3990 info->tx_holding_count = 0;
3991
3992} /* end of mgsl_free_intermediate_txbuffer_memory() */
3993
3994
3995/*
3996 * load_next_tx_holding_buffer()
3997 *
3998 * attempts to load the next buffered tx request into the
3999 * tx dma buffers
4000 *
4001 * Arguments:
4002 *
4003 * info pointer to device instance data
4004 *
0fab6de0 4005 * Return Value: true if next buffered tx request loaded
1da177e4 4006 * into adapter's tx dma buffer,
0fab6de0 4007 * false otherwise
1da177e4 4008 */
0fab6de0 4009static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
1da177e4 4010{
0fab6de0 4011 bool ret = false;
1da177e4
LT		 4012
4013 if ( info->tx_holding_count ) {
4014 /* determine if we have enough tx dma buffers
4015 * to accommodate the next tx frame
4016 */
4017 struct tx_holding_buffer *ptx =
4018 &info->tx_holding_buffers[info->get_tx_holding_index];
4019 int num_free = num_free_tx_dma_buffers(info);
4020 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4021 if ( ptx->buffer_size % DMABUFFERSIZE )
4022 ++num_needed;
4023
4024 if (num_needed <= num_free) {
4025 info->xmit_cnt = ptx->buffer_size;
4026 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4027
4028 --info->tx_holding_count;
4029 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4030 info->get_tx_holding_index=0;
4031
4032 /* restart transmit timer */
4033 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4034
0fab6de0 4035 ret = true;
1da177e4
LT		 4036 }
4037 }
4038
4039 return ret;
4040}
4041
4042/*
4043 * save_tx_buffer_request()
4044 *
4045 * attempt to store transmit frame request for later transmission
4046 *
4047 * Arguments:
4048 *
4049 * info pointer to device instance data
4050 * Buffer pointer to buffer containing frame to load
4051 * BufferSize size in bytes of frame in Buffer
4052 *
4053 * Return Value: 1 if able to store, 0 otherwise
4054 */
4055static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4056{
4057 struct tx_holding_buffer *ptx;
4058
4059 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4060 return 0; /* all buffers in use */
4061 }
4062
4063 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4064 ptx->buffer_size = BufferSize;
4065 memcpy( ptx->buffer, Buffer, BufferSize);
4066
4067 ++info->tx_holding_count;
4068 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4069 info->put_tx_holding_index=0;
4070
4071 return 1;
4072}
4073
4074static int mgsl_claim_resources(struct mgsl_struct *info)
4075{
4076 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4077 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4078 __FILE__,__LINE__,info->device_name, info->io_base);
4079 return -ENODEV;
4080 }
0fab6de0 4081 info->io_addr_requested = true;
1da177e4
LT		 4082
4083 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4084 info->device_name, info ) < 0 ) {
25985edc 4085 printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
1da177e4
LT		 4086 __FILE__,__LINE__,info->device_name, info->irq_level );
4087 goto errout;
4088 }
0fab6de0 4089 info->irq_requested = true;
1da177e4
LT		 4090
4091 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4092 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4093 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4094 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4095 goto errout;
4096 }
0fab6de0 4097 info->shared_mem_requested = true;
1da177e4
LT		 4098 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4099 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4100 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4101 goto errout;
4102 }
0fab6de0 4103 info->lcr_mem_requested = true;
1da177e4 4104
24cb2335
AC		 4105 info->memory_base = ioremap_nocache(info->phys_memory_base,
4106 0x40000);
1da177e4 4107 if (!info->memory_base) {
25985edc 4108 printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
1da177e4
LT		 4109 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4110 goto errout;
4111 }
4112
4113 if ( !mgsl_memory_test(info) ) {
4114 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4115 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4116 goto errout;
4117 }
4118
24cb2335
AC		 4119 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4120 PAGE_SIZE);
1da177e4 4121 if (!info->lcr_base) {
25985edc 4122 printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
1da177e4
LT		 4123 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4124 goto errout;
4125 }
24cb2335 4126 info->lcr_base += info->lcr_offset;
1da177e4
LT		 4127
4128 } else {
4129 /* claim DMA channel */
4130
4131 if (request_dma(info->dma_level,info->device_name) < 0){
25985edc 4132 printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
1da177e4
LT		 4133 __FILE__,__LINE__,info->device_name, info->dma_level );
4134 mgsl_release_resources( info );
4135 return -ENODEV;
4136 }
0fab6de0 4137 info->dma_requested = true;
1da177e4
LT		 4138
4139 /* ISA adapter uses bus master DMA */
4140 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4141 enable_dma(info->dma_level);
4142 }
4143
4144 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
25985edc 4145 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
1da177e4
LT		 4146 __FILE__,__LINE__,info->device_name, info->dma_level );
4147 goto errout;
4148 }
4149
4150 return 0;
4151errout:
4152 mgsl_release_resources(info);
4153 return -ENODEV;
4154
4155} /* end of mgsl_claim_resources() */
4156
4157static void mgsl_release_resources(struct mgsl_struct *info)
4158{
4159 if ( debug_level >= DEBUG_LEVEL_INFO )
4160 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4161 __FILE__,__LINE__,info->device_name );
4162
4163 if ( info->irq_requested ) {
4164 free_irq(info->irq_level, info);
0fab6de0 4165 info->irq_requested = false;
1da177e4
LT		 4166 }
4167 if ( info->dma_requested ) {
4168 disable_dma(info->dma_level);
4169 free_dma(info->dma_level);
0fab6de0 4170 info->dma_requested = false;
1da177e4
LT		 4171 }
4172 mgsl_free_dma_buffers(info);
4173 mgsl_free_intermediate_rxbuffer_memory(info);
4174 mgsl_free_intermediate_txbuffer_memory(info);
4175
4176 if ( info->io_addr_requested ) {
4177 release_region(info->io_base,info->io_addr_size);
0fab6de0 4178 info->io_addr_requested = false;
1da177e4
LT		 4179 }
4180 if ( info->shared_mem_requested ) {
4181 release_mem_region(info->phys_memory_base,0x40000);
0fab6de0 4182 info->shared_mem_requested = false;
1da177e4
LT		 4183 }
4184 if ( info->lcr_mem_requested ) {
4185 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
0fab6de0 4186 info->lcr_mem_requested = false;
1da177e4
LT		 4187 }
4188 if (info->memory_base){
4189 iounmap(info->memory_base);
4190 info->memory_base = NULL;
4191 }
4192 if (info->lcr_base){
4193 iounmap(info->lcr_base - info->lcr_offset);
4194 info->lcr_base = NULL;
4195 }
4196
4197 if ( debug_level >= DEBUG_LEVEL_INFO )
4198 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4199 __FILE__,__LINE__,info->device_name );
4200
4201} /* end of mgsl_release_resources() */
4202
4203/* mgsl_add_device()
4204 *
4205 * Add the specified device instance data structure to the
4206 * global linked list of devices and increment the device count.
4207 *
4208 * Arguments: info pointer to device instance data
4209 * Return Value: None
4210 */
4211static void mgsl_add_device( struct mgsl_struct *info )
4212{
4213 info->next_device = NULL;
4214 info->line = mgsl_device_count;
4215 sprintf(info->device_name,"ttySL%d",info->line);
4216
4217 if (info->line < MAX_TOTAL_DEVICES) {
4218 if (maxframe[info->line])
4219 info->max_frame_size = maxframe[info->line];
1da177e4
LT		 4220
4221 if (txdmabufs[info->line]) {
4222 info->num_tx_dma_buffers = txdmabufs[info->line];
4223 if (info->num_tx_dma_buffers < 1)
4224 info->num_tx_dma_buffers = 1;
4225 }
4226
4227 if (txholdbufs[info->line]) {
4228 info->num_tx_holding_buffers = txholdbufs[info->line];
4229 if (info->num_tx_holding_buffers < 1)
4230 info->num_tx_holding_buffers = 1;
4231 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4232 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4233 }
4234 }
4235
4236 mgsl_device_count++;
4237
4238 if ( !mgsl_device_list )
4239 mgsl_device_list = info;
4240 else {
4241 struct mgsl_struct *current_dev = mgsl_device_list;
4242 while( current_dev->next_device )
4243 current_dev = current_dev->next_device;
4244 current_dev->next_device = info;
4245 }
4246
4247 if ( info->max_frame_size < 4096 )
4248 info->max_frame_size = 4096;
4249 else if ( info->max_frame_size > 65535 )
4250 info->max_frame_size = 65535;
4251
4252 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4253 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4254 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4255 info->phys_memory_base, info->phys_lcr_base,
4256 info->max_frame_size );
4257 } else {
4258 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4259 info->device_name, info->io_base, info->irq_level, info->dma_level,
4260 info->max_frame_size );
4261 }
4262
af69c7f9 4263#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 4264 hdlcdev_init(info);
4265#endif
4266
4267} /* end of mgsl_add_device() */
4268
31f35939
AC		 4269static const struct tty_port_operations mgsl_port_ops = {
4270 .carrier_raised = carrier_raised,
fcc8ac18 4271 .dtr_rts = dtr_rts,
31f35939
AC		 4272};
4273
4274
1da177e4
LT		 4275/* mgsl_allocate_device()
4276 *
4277 * Allocate and initialize a device instance structure
4278 *
4279 * Arguments: none
4280 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4281 */
4282static struct mgsl_struct* mgsl_allocate_device(void)
4283{
4284 struct mgsl_struct *info;
4285
dd00cc48 4286 info = kzalloc(sizeof(struct mgsl_struct),
1da177e4
LT		 4287 GFP_KERNEL);
4288
4289 if (!info) {
4290 printk("Error can't allocate device instance data\n");
4291 } else {
44b7d1b3 4292 tty_port_init(&info->port);
31f35939 4293 info->port.ops = &mgsl_port_ops;
1da177e4 4294 info->magic = MGSL_MAGIC;
c4028958 4295 INIT_WORK(&info->task, mgsl_bh_handler);
1da177e4 4296 info->max_frame_size = 4096;
44b7d1b3
AC		 4297 info->port.close_delay = 5*HZ/10;
4298 info->port.closing_wait = 30*HZ;
1da177e4
LT		 4299 init_waitqueue_head(&info->status_event_wait_q);
4300 init_waitqueue_head(&info->event_wait_q);
4301 spin_lock_init(&info->irq_spinlock);
4302 spin_lock_init(&info->netlock);
4303 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4304 info->idle_mode = HDLC_TXIDLE_FLAGS;
4305 info->num_tx_dma_buffers = 1;
4306 info->num_tx_holding_buffers = 0;
4307 }
4308
4309 return info;
4310
4311} /* end of mgsl_allocate_device()*/
4312
b68e31d0 4313static const struct tty_operations mgsl_ops = {
8a3ad104 4314 .install = mgsl_install,
1da177e4
LT		 4315 .open = mgsl_open,
4316 .close = mgsl_close,
4317 .write = mgsl_write,
4318 .put_char = mgsl_put_char,
4319 .flush_chars = mgsl_flush_chars,
4320 .write_room = mgsl_write_room,
4321 .chars_in_buffer = mgsl_chars_in_buffer,
4322 .flush_buffer = mgsl_flush_buffer,
4323 .ioctl = mgsl_ioctl,
4324 .throttle = mgsl_throttle,
4325 .unthrottle = mgsl_unthrottle,
4326 .send_xchar = mgsl_send_xchar,
4327 .break_ctl = mgsl_break,
4328 .wait_until_sent = mgsl_wait_until_sent,
1da177e4
LT		 4329 .set_termios = mgsl_set_termios,
4330 .stop = mgsl_stop,
4331 .start = mgsl_start,
4332 .hangup = mgsl_hangup,
4333 .tiocmget = tiocmget,
4334 .tiocmset = tiocmset,
0587102c 4335 .get_icount = msgl_get_icount,
d337829b 4336 .proc_fops = &mgsl_proc_fops,
1da177e4
LT		 4337};
4338
4339/*
4340 * perform tty device initialization
4341 */
4342static int mgsl_init_tty(void)
4343{
4344 int rc;
4345
4346 serial_driver = alloc_tty_driver(128);
4347 if (!serial_driver)
4348 return -ENOMEM;
4349
1da177e4
LT		 4350 serial_driver->driver_name = "synclink";
4351 serial_driver->name = "ttySL";
4352 serial_driver->major = ttymajor;
4353 serial_driver->minor_start = 64;
4354 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4355 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4356 serial_driver->init_termios = tty_std_termios;
4357 serial_driver->init_termios.c_cflag =
4358 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 4359 serial_driver->init_termios.c_ispeed = 9600;
4360 serial_driver->init_termios.c_ospeed = 9600;
1da177e4
LT		 4361 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4362 tty_set_operations(serial_driver, &mgsl_ops);
4363 if ((rc = tty_register_driver(serial_driver)) < 0) {
4364 printk("%s(%d):Couldn't register serial driver\n",
4365 __FILE__,__LINE__);
4366 put_tty_driver(serial_driver);
4367 serial_driver = NULL;
4368 return rc;
4369 }
4370
4371 printk("%s %s, tty major#%d\n",
4372 driver_name, driver_version,
4373 serial_driver->major);
4374 return 0;
4375}
4376
4377/* enumerate user specified ISA adapters
4378 */
4379static void mgsl_enum_isa_devices(void)
4380{
4381 struct mgsl_struct *info;
4382 int i;
4383
4384 /* Check for user specified ISA devices */
4385
4386 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4387 if ( debug_level >= DEBUG_LEVEL_INFO )
4388 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4389 io[i], irq[i], dma[i] );
4390
4391 info = mgsl_allocate_device();
4392 if ( !info ) {
4393 /* error allocating device instance data */
4394 if ( debug_level >= DEBUG_LEVEL_ERROR )
4395 printk( "can't allocate device instance data.\n");
4396 continue;
4397 }
4398
4399 /* Copy user configuration info to device instance data */
4400 info->io_base = (unsigned int)io[i];
4401 info->irq_level = (unsigned int)irq[i];
4402 info->irq_level = irq_canonicalize(info->irq_level);
4403 info->dma_level = (unsigned int)dma[i];
4404 info->bus_type = MGSL_BUS_TYPE_ISA;
4405 info->io_addr_size = 16;
4406 info->irq_flags = 0;
4407
4408 mgsl_add_device( info );
4409 }
4410}
4411
4412static void synclink_cleanup(void)
4413{
4414 int rc;
4415 struct mgsl_struct *info;
4416 struct mgsl_struct *tmp;
4417
4418 printk("Unloading %s: %s\n", driver_name, driver_version);
4419
4420 if (serial_driver) {
4421 if ((rc = tty_unregister_driver(serial_driver)))
4422 printk("%s(%d) failed to unregister tty driver err=%d\n",
4423 __FILE__,__LINE__,rc);
4424 put_tty_driver(serial_driver);
4425 }
4426
4427 info = mgsl_device_list;
4428 while(info) {
af69c7f9 4429#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 4430 hdlcdev_exit(info);
4431#endif
4432 mgsl_release_resources(info);
4433 tmp = info;
4434 info = info->next_device;
191c5f10 4435 tty_port_destroy(&tmp->port);
1da177e4
LT		 4436 kfree(tmp);
4437 }
4438
1da177e4
LT		 4439 if (pci_registered)
4440 pci_unregister_driver(&synclink_pci_driver);
4441}
4442
4443static int __init synclink_init(void)
4444{
4445 int rc;
4446
4447 if (break_on_load) {
4448 mgsl_get_text_ptr();
4449 BREAKPOINT();
4450 }
4451
4452 printk("%s %s\n", driver_name, driver_version);
4453
4454 mgsl_enum_isa_devices();
4455 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4456 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4457 else
0fab6de0 4458 pci_registered = true;
1da177e4
LT		 4459
4460 if ((rc = mgsl_init_tty()) < 0)
4461 goto error;
4462
4463 return 0;
4464
4465error:
4466 synclink_cleanup();
4467 return rc;
4468}
4469
4470static void __exit synclink_exit(void)
4471{
4472 synclink_cleanup();
4473}
4474
4475module_init(synclink_init);
4476module_exit(synclink_exit);
4477
4478/*
4479 * usc_RTCmd()
4480 *
4481 * Issue a USC Receive/Transmit command to the
4482 * Channel Command/Address Register (CCAR).
4483 *
4484 * Notes:
4485 *
4486 * The command is encoded in the most significant 5 bits <15..11>
4487 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4488 * and Bits <6..0> must be written as zeros.
4489 *
4490 * Arguments:
4491 *
4492 * info pointer to device information structure
4493 * Cmd command mask (use symbolic macros)
4494 *
4495 * Return Value:
4496 *
4497 * None
4498 */
4499static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4500{
4501 /* output command to CCAR in bits <15..11> */
4502 /* preserve bits <10..7>, bits <6..0> must be zero */
4503
4504 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4505
4506 /* Read to flush write to CCAR */
4507 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4508 inw( info->io_base + CCAR );
4509
4510} /* end of usc_RTCmd() */
4511
4512/*
4513 * usc_DmaCmd()
4514 *
4515 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4516 *
4517 * Arguments:
4518 *
4519 * info pointer to device information structure
4520 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4521 *
4522 * Return Value:
4523 *
4524 * None
4525 */
4526static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4527{
4528 /* write command mask to DCAR */
4529 outw( Cmd + info->mbre_bit, info->io_base );
4530
4531 /* Read to flush write to DCAR */
4532 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4533 inw( info->io_base );
4534
4535} /* end of usc_DmaCmd() */
4536
4537/*
4538 * usc_OutDmaReg()
4539 *
4540 * Write a 16-bit value to a USC DMA register
4541 *
4542 * Arguments:
4543 *
4544 * info pointer to device info structure
4545 * RegAddr register address (number) for write
4546 * RegValue 16-bit value to write to register
4547 *
4548 * Return Value:
4549 *
4550 * None
4551 *
4552 */
4553static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4554{
4555 /* Note: The DCAR is located at the adapter base address */
4556 /* Note: must preserve state of BIT8 in DCAR */
4557
4558 outw( RegAddr + info->mbre_bit, info->io_base );
4559 outw( RegValue, info->io_base );
4560
4561 /* Read to flush write to DCAR */
4562 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4563 inw( info->io_base );
4564
4565} /* end of usc_OutDmaReg() */
4566
4567/*
4568 * usc_InDmaReg()
4569 *
4570 * Read a 16-bit value from a DMA register
4571 *
4572 * Arguments:
4573 *
4574 * info pointer to device info structure
4575 * RegAddr register address (number) to read from
4576 *
4577 * Return Value:
4578 *
4579 * The 16-bit value read from register
4580 *
4581 */
4582static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4583{
4584 /* Note: The DCAR is located at the adapter base address */
4585 /* Note: must preserve state of BIT8 in DCAR */
4586
4587 outw( RegAddr + info->mbre_bit, info->io_base );
4588 return inw( info->io_base );
4589
4590} /* end of usc_InDmaReg() */
4591
4592/*
4593 *
4594 * usc_OutReg()
4595 *
4596 * Write a 16-bit value to a USC serial channel register
4597 *
4598 * Arguments:
4599 *
4600 * info pointer to device info structure
4601 * RegAddr register address (number) to write to
4602 * RegValue 16-bit value to write to register
4603 *
4604 * Return Value:
4605 *
4606 * None
4607 *
4608 */
4609static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4610{
4611 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4612 outw( RegValue, info->io_base + CCAR );
4613
4614 /* Read to flush write to CCAR */
4615 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4616 inw( info->io_base + CCAR );
4617
4618} /* end of usc_OutReg() */
4619
4620/*
4621 * usc_InReg()
4622 *
4623 * Reads a 16-bit value from a USC serial channel register
4624 *
4625 * Arguments:
4626 *
4627 * info pointer to device extension
4628 * RegAddr register address (number) to read from
4629 *
4630 * Return Value:
4631 *
4632 * 16-bit value read from register
4633 */
4634static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4635{
4636 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4637 return inw( info->io_base + CCAR );
4638
4639} /* end of usc_InReg() */
4640
4641/* usc_set_sdlc_mode()
4642 *
4643 * Set up the adapter for SDLC DMA communications.
4644 *
4645 * Arguments: info pointer to device instance data
4646 * Return Value: NONE
4647 */
4648static void usc_set_sdlc_mode( struct mgsl_struct *info )
4649{
4650 u16 RegValue;
0fab6de0 4651 bool PreSL1660;
1da177e4
LT		 4652
4653 /*
4654 * determine if the IUSC on the adapter is pre-SL1660. If
4655 * not, take advantage of the UnderWait feature of more
4656 * modern chips. If an underrun occurs and this bit is set,
4657 * the transmitter will idle the programmed idle pattern
4658 * until the driver has time to service the underrun. Otherwise,
4659 * the dma controller may get the cycles previously requested
4660 * and begin transmitting queued tx data.
4661 */
4662 usc_OutReg(info,TMCR,0x1f);
4663 RegValue=usc_InReg(info,TMDR);
0fab6de0 4664 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
1da177e4
LT		 4665
4666 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4667 {
4668 /*
4669 ** Channel Mode Register (CMR)
4670 **
4671 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4672 ** <13> 0 0 = Transmit Disabled (initially)
4673 ** <12> 0 1 = Consecutive Idles share common 0
4674 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4675 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4676 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4677 **
4678 ** 1000 1110 0000 0110 = 0x8e06
4679 */
4680 RegValue = 0x8e06;
4681
4682 /*--------------------------------------------------
4683 * ignore user options for UnderRun Actions and
4684 * preambles
4685 *--------------------------------------------------*/
4686 }
4687 else
4688 {
4689 /* Channel mode Register (CMR)
4690 *
4691 * <15..14> 00 Tx Sub modes, Underrun Action
4692 * <13> 0 1 = Send Preamble before opening flag
4693 * <12> 0 1 = Consecutive Idles share common 0
4694 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4695 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4696 * <3..0> 0110 Receiver mode = HDLC/SDLC
4697 *
4698 * 0000 0110 0000 0110 = 0x0606
4699 */
4700 if (info->params.mode == MGSL_MODE_RAW) {
4701 RegValue = 0x0001; /* Set Receive mode = external sync */
4702
4703 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4704 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4705
4706 /*
4707 * TxSubMode:
4708 * CMR <15> 0 Don't send CRC on Tx Underrun
4709 * CMR <14> x undefined
4710 * CMR <13> 0 Send preamble before openning sync
4711 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4712 *
4713 * TxMode:
4714 * CMR <11-8) 0100 MonoSync
4715 *
4716 * 0x00 0100 xxxx xxxx 04xx
4717 */
4718 RegValue |= 0x0400;
4719 }
4720 else {
4721
4722 RegValue = 0x0606;
4723
4724 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4725 RegValue |= BIT14;
4726 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4727 RegValue |= BIT15;
4728 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4729 RegValue |= BIT15 + BIT14;
4730 }
4731
4732 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4733 RegValue |= BIT13;
4734 }
4735
4736 if ( info->params.mode == MGSL_MODE_HDLC &&
4737 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4738 RegValue |= BIT12;
4739
4740 if ( info->params.addr_filter != 0xff )
4741 {
4742 /* set up receive address filtering */
4743 usc_OutReg( info, RSR, info->params.addr_filter );
4744 RegValue |= BIT4;
4745 }
4746
4747 usc_OutReg( info, CMR, RegValue );
4748 info->cmr_value = RegValue;
4749
4750 /* Receiver mode Register (RMR)
4751 *
4752 * <15..13> 000 encoding
4753 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4754 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4755 * <9> 0 1 = Include Receive chars in CRC
4756 * <8> 1 1 = Use Abort/PE bit as abort indicator
4757 * <7..6> 00 Even parity
4758 * <5> 0 parity disabled
4759 * <4..2> 000 Receive Char Length = 8 bits
4760 * <1..0> 00 Disable Receiver
4761 *
4762 * 0000 0101 0000 0000 = 0x0500
4763 */
4764
4765 RegValue = 0x0500;
4766
4767 switch ( info->params.encoding ) {
4768 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4769 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4770 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4771 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4772 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4773 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4774 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4775 }
4776
4777 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4778 RegValue |= BIT9;
4779 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4780 RegValue |= ( BIT12 | BIT10 | BIT9 );
4781
4782 usc_OutReg( info, RMR, RegValue );
4783
4784 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4785 /* When an opening flag of an SDLC frame is recognized the */
4786 /* Receive Character count (RCC) is loaded with the value in */
4787 /* RCLR. The RCC is decremented for each received byte. The */
4788 /* value of RCC is stored after the closing flag of the frame */
4789 /* allowing the frame size to be computed. */
4790
4791 usc_OutReg( info, RCLR, RCLRVALUE );
4792
4793 usc_RCmd( info, RCmd_SelectRicrdma_level );
4794
4795 /* Receive Interrupt Control Register (RICR)
4796 *
4797 * <15..8> ? RxFIFO DMA Request Level
4798 * <7> 0 Exited Hunt IA (Interrupt Arm)
4799 * <6> 0 Idle Received IA
4800 * <5> 0 Break/Abort IA
4801 * <4> 0 Rx Bound IA
4802 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4803 * <2> 0 Abort/PE IA
4804 * <1> 1 Rx Overrun IA
4805 * <0> 0 Select TC0 value for readback
4806 *
4807 * 0000 0000 0000 1000 = 0x000a
4808 */
4809
4810 /* Carry over the Exit Hunt and Idle Received bits */
4811 /* in case they have been armed by usc_ArmEvents. */
4812
4813 RegValue = usc_InReg( info, RICR ) & 0xc0;
4814
4815 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4816 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4817 else
4818 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4819
4820 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4821
4822 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4823 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4824
4825 /* Transmit mode Register (TMR)
4826 *
4827 * <15..13> 000 encoding
4828 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4829 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4830 * <9> 0 1 = Tx CRC Enabled
4831 * <8> 0 1 = Append CRC to end of transmit frame
4832 * <7..6> 00 Transmit parity Even
4833 * <5> 0 Transmit parity Disabled
4834 * <4..2> 000 Tx Char Length = 8 bits
4835 * <1..0> 00 Disable Transmitter
4836 *
4837 * 0000 0100 0000 0000 = 0x0400
4838 */
4839
4840 RegValue = 0x0400;
4841
4842 switch ( info->params.encoding ) {
4843 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4844 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4845 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4846 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4847 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4848 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4849 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4850 }
4851
4852 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4853 RegValue |= BIT9 + BIT8;
4854 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4855 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4856
4857 usc_OutReg( info, TMR, RegValue );
4858
4859 usc_set_txidle( info );
4860
4861
4862 usc_TCmd( info, TCmd_SelectTicrdma_level );
4863
4864 /* Transmit Interrupt Control Register (TICR)
4865 *
4866 * <15..8> ? Transmit FIFO DMA Level
4867 * <7> 0 Present IA (Interrupt Arm)
4868 * <6> 0 Idle Sent IA
4869 * <5> 1 Abort Sent IA
4870 * <4> 1 EOF/EOM Sent IA
4871 * <3> 0 CRC Sent IA
4872 * <2> 1 1 = Wait for SW Trigger to Start Frame
4873 * <1> 1 Tx Underrun IA
4874 * <0> 0 TC0 constant on read back
4875 *
4876 * 0000 0000 0011 0110 = 0x0036
4877 */
4878
4879 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4880 usc_OutReg( info, TICR, 0x0736 );
4881 else
4882 usc_OutReg( info, TICR, 0x1436 );
4883
4884 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4885 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4886
4887 /*
4888 ** Transmit Command/Status Register (TCSR)
4889 **
4890 ** <15..12> 0000 TCmd
4891 ** <11> 0/1 UnderWait
4892 ** <10..08> 000 TxIdle
4893 ** <7> x PreSent
4894 ** <6> x IdleSent
4895 ** <5> x AbortSent
4896 ** <4> x EOF/EOM Sent
4897 ** <3> x CRC Sent
4898 ** <2> x All Sent
4899 ** <1> x TxUnder
4900 ** <0> x TxEmpty
4901 **
4902 ** 0000 0000 0000 0000 = 0x0000
4903 */
4904 info->tcsr_value = 0;
4905
4906 if ( !PreSL1660 )
4907 info->tcsr_value |= TCSR_UNDERWAIT;
4908
4909 usc_OutReg( info, TCSR, info->tcsr_value );
4910
4911 /* Clock mode Control Register (CMCR)
4912 *
4913 * <15..14> 00 counter 1 Source = Disabled
4914 * <13..12> 00 counter 0 Source = Disabled
4915 * <11..10> 11 BRG1 Input is TxC Pin
4916 * <9..8> 11 BRG0 Input is TxC Pin
4917 * <7..6> 01 DPLL Input is BRG1 Output
4918 * <5..3> XXX TxCLK comes from Port 0
4919 * <2..0> XXX RxCLK comes from Port 1
4920 *
4921 * 0000 1111 0111 0111 = 0x0f77
4922 */
4923
4924 RegValue = 0x0f40;
4925
4926 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4927 RegValue |= 0x0003; /* RxCLK from DPLL */
4928 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4929 RegValue |= 0x0004; /* RxCLK from BRG0 */
4930 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4931 RegValue |= 0x0006; /* RxCLK from TXC Input */
4932 else
4933 RegValue |= 0x0007; /* RxCLK from Port1 */
4934
4935 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4936 RegValue |= 0x0018; /* TxCLK from DPLL */
4937 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4938 RegValue |= 0x0020; /* TxCLK from BRG0 */
4939 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4940 RegValue |= 0x0038; /* RxCLK from TXC Input */
4941 else
4942 RegValue |= 0x0030; /* TxCLK from Port0 */
4943
4944 usc_OutReg( info, CMCR, RegValue );
4945
4946
4947 /* Hardware Configuration Register (HCR)
4948 *
4949 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4950 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4951 * <12> 0 CVOK:0=report code violation in biphase
4952 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4953 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4954 * <7..6> 00 reserved
4955 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4956 * <4> X BRG1 Enable
4957 * <3..2> 00 reserved
4958 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4959 * <0> 0 BRG0 Enable
4960 */
4961
4962 RegValue = 0x0000;
4963
4964 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4965 u32 XtalSpeed;
4966 u32 DpllDivisor;
4967 u16 Tc;
4968
4969 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4970 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4971
4972 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4973 XtalSpeed = 11059200;
4974 else
4975 XtalSpeed = 14745600;
4976
4977 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4978 DpllDivisor = 16;
4979 RegValue |= BIT10;
4980 }
4981 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4982 DpllDivisor = 8;
4983 RegValue |= BIT11;
4984 }
4985 else
4986 DpllDivisor = 32;
4987
4988 /* Tc = (Xtal/Speed) - 1 */
4989 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4990 /* then rounding up gives a more precise time constant. Instead */
4991 /* of rounding up and then subtracting 1 we just don't subtract */
4992 /* the one in this case. */
4993
4994 /*--------------------------------------------------
4995 * ejz: for DPLL mode, application should use the
4996 * same clock speed as the partner system, even
4997 * though clocking is derived from the input RxData.
4998 * In case the user uses a 0 for the clock speed,
4999 * default to 0xffffffff and don't try to divide by
5000 * zero
5001 *--------------------------------------------------*/
5002 if ( info->params.clock_speed )
5003 {
5004 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5005 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5006 / info->params.clock_speed) )
5007 Tc--;
5008 }
5009 else
5010 Tc = -1;
5011
5012
5013 /* Write 16-bit Time Constant for BRG1 */
5014 usc_OutReg( info, TC1R, Tc );
5015
5016 RegValue |= BIT4; /* enable BRG1 */
5017
5018 switch ( info->params.encoding ) {
5019 case HDLC_ENCODING_NRZ:
5020 case HDLC_ENCODING_NRZB:
5021 case HDLC_ENCODING_NRZI_MARK:
5022 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5023 case HDLC_ENCODING_BIPHASE_MARK:
5024 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5025 case HDLC_ENCODING_BIPHASE_LEVEL:
5026 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5027 }
5028 }
5029
5030 usc_OutReg( info, HCR, RegValue );
5031
5032
5033 /* Channel Control/status Register (CCSR)
5034 *
5035 * <15> X RCC FIFO Overflow status (RO)
5036 * <14> X RCC FIFO Not Empty status (RO)
5037 * <13> 0 1 = Clear RCC FIFO (WO)
5038 * <12> X DPLL Sync (RW)
5039 * <11> X DPLL 2 Missed Clocks status (RO)
5040 * <10> X DPLL 1 Missed Clock status (RO)
5041 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5042 * <7> X SDLC Loop On status (RO)
5043 * <6> X SDLC Loop Send status (RO)
5044 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5045 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5046 * <1..0> 00 reserved
5047 *
5048 * 0000 0000 0010 0000 = 0x0020
5049 */
5050
5051 usc_OutReg( info, CCSR, 0x1020 );
5052
5053
5054 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5055 usc_OutReg( info, SICR,
5056 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5057 }
5058
5059
5060 /* enable Master Interrupt Enable bit (MIE) */
5061 usc_EnableMasterIrqBit( info );
5062
5063 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5064 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5065
5066 /* arm RCC underflow interrupt */
5067 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5068 usc_EnableInterrupts(info, MISC);
5069
5070 info->mbre_bit = 0;
5071 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5072 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5073 info->mbre_bit = BIT8;
5074 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5075
5076 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5077 /* Enable DMAEN (Port 7, Bit 14) */
5078 /* This connects the DMA request signal to the ISA bus */
5079 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5080 }
5081
5082 /* DMA Control Register (DCR)
5083 *
5084 * <15..14> 10 Priority mode = Alternating Tx/Rx
5085 * 01 Rx has priority
5086 * 00 Tx has priority
5087 *
5088 * <13> 1 Enable Priority Preempt per DCR<15..14>
5089 * (WARNING DCR<11..10> must be 00 when this is 1)
5090 * 0 Choose activate channel per DCR<11..10>
5091 *
5092 * <12> 0 Little Endian for Array/List
5093 * <11..10> 00 Both Channels can use each bus grant
5094 * <9..6> 0000 reserved
5095 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5096 * <4> 0 1 = drive D/C and S/D pins
5097 * <3> 1 1 = Add one wait state to all DMA cycles.
5098 * <2> 0 1 = Strobe /UAS on every transfer.
5099 * <1..0> 11 Addr incrementing only affects LS24 bits
5100 *
5101 * 0110 0000 0000 1011 = 0x600b
5102 */
5103
5104 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5105 /* PCI adapter does not need DMA wait state */
5106 usc_OutDmaReg( info, DCR, 0xa00b );
5107 }
5108 else
5109 usc_OutDmaReg( info, DCR, 0x800b );
5110
5111
5112 /* Receive DMA mode Register (RDMR)
5113 *
5114 * <15..14> 11 DMA mode = Linked List Buffer mode
5115 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5116 * <12> 1 Clear count of List Entry after fetching
5117 * <11..10> 00 Address mode = Increment
5118 * <9> 1 Terminate Buffer on RxBound
5119 * <8> 0 Bus Width = 16bits
5120 * <7..0> ? status Bits (write as 0s)
5121 *
5122 * 1111 0010 0000 0000 = 0xf200
5123 */
5124
5125 usc_OutDmaReg( info, RDMR, 0xf200 );
5126
5127
5128 /* Transmit DMA mode Register (TDMR)
5129 *
5130 * <15..14> 11 DMA mode = Linked List Buffer mode
5131 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5132 * <12> 1 Clear count of List Entry after fetching
5133 * <11..10> 00 Address mode = Increment
5134 * <9> 1 Terminate Buffer on end of frame
5135 * <8> 0 Bus Width = 16bits
5136 * <7..0> ? status Bits (Read Only so write as 0)
5137 *
5138 * 1111 0010 0000 0000 = 0xf200
5139 */
5140
5141 usc_OutDmaReg( info, TDMR, 0xf200 );
5142
5143
5144 /* DMA Interrupt Control Register (DICR)
5145 *
5146 * <15> 1 DMA Interrupt Enable
5147 * <14> 0 1 = Disable IEO from USC
5148 * <13> 0 1 = Don't provide vector during IntAck
5149 * <12> 1 1 = Include status in Vector
5150 * <10..2> 0 reserved, Must be 0s
5151 * <1> 0 1 = Rx DMA Interrupt Enabled
5152 * <0> 0 1 = Tx DMA Interrupt Enabled
5153 *
5154 * 1001 0000 0000 0000 = 0x9000
5155 */
5156
5157 usc_OutDmaReg( info, DICR, 0x9000 );
5158
5159 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5160 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5161 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5162
5163 /* Channel Control Register (CCR)
5164 *
5165 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5166 * <13> 0 Trigger Tx on SW Command Disabled
5167 * <12> 0 Flag Preamble Disabled
5168 * <11..10> 00 Preamble Length
5169 * <9..8> 00 Preamble Pattern
5170 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5171 * <5> 0 Trigger Rx on SW Command Disabled
5172 * <4..0> 0 reserved
5173 *
5174 * 1000 0000 1000 0000 = 0x8080
5175 */
5176
5177 RegValue = 0x8080;
5178
5179 switch ( info->params.preamble_length ) {
5180 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5181 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5182 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5183 }
5184
5185 switch ( info->params.preamble ) {
5186 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5187 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5188 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5189 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5190 }
5191
5192 usc_OutReg( info, CCR, RegValue );
5193
5194
5195 /*
5196 * Burst/Dwell Control Register
5197 *
5198 * <15..8> 0x20 Maximum number of transfers per bus grant
5199 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5200 */
5201
5202 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5203 /* don't limit bus occupancy on PCI adapter */
5204 usc_OutDmaReg( info, BDCR, 0x0000 );
5205 }
5206 else
5207 usc_OutDmaReg( info, BDCR, 0x2000 );
5208
5209 usc_stop_transmitter(info);
5210 usc_stop_receiver(info);
5211
5212} /* end of usc_set_sdlc_mode() */
5213
5214/* usc_enable_loopback()
5215 *
5216 * Set the 16C32 for internal loopback mode.
5217 * The TxCLK and RxCLK signals are generated from the BRG0 and
5218 * the TxD is looped back to the RxD internally.
5219 *
5220 * Arguments: info pointer to device instance data
5221 * enable 1 = enable loopback, 0 = disable
5222 * Return Value: None
5223 */
5224static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5225{
5226 if (enable) {
5227 /* blank external TXD output */
5228 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5229
5230 /* Clock mode Control Register (CMCR)
5231 *
5232 * <15..14> 00 counter 1 Disabled
5233 * <13..12> 00 counter 0 Disabled
5234 * <11..10> 11 BRG1 Input is TxC Pin
5235 * <9..8> 11 BRG0 Input is TxC Pin
5236 * <7..6> 01 DPLL Input is BRG1 Output
5237 * <5..3> 100 TxCLK comes from BRG0
5238 * <2..0> 100 RxCLK comes from BRG0
5239 *
5240 * 0000 1111 0110 0100 = 0x0f64
5241 */
5242
5243 usc_OutReg( info, CMCR, 0x0f64 );
5244
5245 /* Write 16-bit Time Constant for BRG0 */
5246 /* use clock speed if available, otherwise use 8 for diagnostics */
5247 if (info->params.clock_speed) {
5248 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5249 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5250 else
5251 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5252 } else
5253 usc_OutReg(info, TC0R, (u16)8);
5254
5255 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5256 mode = Continuous Set Bit 0 to enable BRG0. */
5257 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5258
5259 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5260 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5261
5262 /* set Internal Data loopback mode */
5263 info->loopback_bits = 0x300;
5264 outw( 0x0300, info->io_base + CCAR );
5265 } else {
5266 /* enable external TXD output */
5267 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5268
5269 /* clear Internal Data loopback mode */
5270 info->loopback_bits = 0;
5271 outw( 0,info->io_base + CCAR );
5272 }
5273
5274} /* end of usc_enable_loopback() */
5275
5276/* usc_enable_aux_clock()
5277 *
5278 * Enabled the AUX clock output at the specified frequency.
5279 *
5280 * Arguments:
5281 *
5282 * info pointer to device extension
5283 * data_rate data rate of clock in bits per second
5284 * A data rate of 0 disables the AUX clock.
5285 *
5286 * Return Value: None
5287 */
5288static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5289{
5290 u32 XtalSpeed;
5291 u16 Tc;
5292
5293 if ( data_rate ) {
5294 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5295 XtalSpeed = 11059200;
5296 else
5297 XtalSpeed = 14745600;
5298
5299
5300 /* Tc = (Xtal/Speed) - 1 */
5301 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5302 /* then rounding up gives a more precise time constant. Instead */
5303 /* of rounding up and then subtracting 1 we just don't subtract */
5304 /* the one in this case. */
5305
5306
5307 Tc = (u16)(XtalSpeed/data_rate);
5308 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5309 Tc--;
5310
5311 /* Write 16-bit Time Constant for BRG0 */
5312 usc_OutReg( info, TC0R, Tc );
5313
5314 /*
5315 * Hardware Configuration Register (HCR)
5316 * Clear Bit 1, BRG0 mode = Continuous
5317 * Set Bit 0 to enable BRG0.
5318 */
5319
5320 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5321
5322 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5323 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5324 } else {
5325 /* data rate == 0 so turn off BRG0 */
5326 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5327 }
5328
5329} /* end of usc_enable_aux_clock() */
5330
5331/*
5332 *
5333 * usc_process_rxoverrun_sync()
5334 *
5335 * This function processes a receive overrun by resetting the
5336 * receive DMA buffers and issuing a Purge Rx FIFO command
5337 * to allow the receiver to continue receiving.
5338 *
5339 * Arguments:
5340 *
5341 * info pointer to device extension
5342 *
5343 * Return Value: None
5344 */
5345static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5346{
5347 int start_index;
5348 int end_index;
5349 int frame_start_index;
0fab6de0
JP		 5350 bool start_of_frame_found = false;
5351 bool end_of_frame_found = false;
5352 bool reprogram_dma = false;
1da177e4
LT		 5353
5354 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5355 u32 phys_addr;
5356
5357 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5358 usc_RCmd( info, RCmd_EnterHuntmode );
5359 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5360
5361 /* CurrentRxBuffer points to the 1st buffer of the next */
5362 /* possibly available receive frame. */
5363
5364 frame_start_index = start_index = end_index = info->current_rx_buffer;
5365
5366 /* Search for an unfinished string of buffers. This means */
5367 /* that a receive frame started (at least one buffer with */
5368 /* count set to zero) but there is no terminiting buffer */
5369 /* (status set to non-zero). */
5370
5371 while( !buffer_list[end_index].count )
5372 {
5373 /* Count field has been reset to zero by 16C32. */
5374 /* This buffer is currently in use. */
5375
5376 if ( !start_of_frame_found )
5377 {
0fab6de0 5378 start_of_frame_found = true;
1da177e4 5379 frame_start_index = end_index;
0fab6de0 5380 end_of_frame_found = false;
1da177e4
LT		 5381 }
5382
5383 if ( buffer_list[end_index].status )
5384 {
5385 /* Status field has been set by 16C32. */
5386 /* This is the last buffer of a received frame. */
5387
5388 /* We want to leave the buffers for this frame intact. */
5389 /* Move on to next possible frame. */
5390
0fab6de0
JP		 5391 start_of_frame_found = false;
5392 end_of_frame_found = true;
1da177e4
LT		 5393 }
5394
5395 /* advance to next buffer entry in linked list */
5396 end_index++;
5397 if ( end_index == info->rx_buffer_count )
5398 end_index = 0;
5399
5400 if ( start_index == end_index )
5401 {
5402 /* The entire list has been searched with all Counts == 0 and */
5403 /* all Status == 0. The receive buffers are */
5404 /* completely screwed, reset all receive buffers! */
5405 mgsl_reset_rx_dma_buffers( info );
5406 frame_start_index = 0;
0fab6de0
JP		 5407 start_of_frame_found = false;
5408 reprogram_dma = true;
1da177e4
LT		 5409 break;
5410 }
5411 }
5412
5413 if ( start_of_frame_found && !end_of_frame_found )
5414 {
5415 /* There is an unfinished string of receive DMA buffers */
5416 /* as a result of the receiver overrun. */
5417
5418 /* Reset the buffers for the unfinished frame */
5419 /* and reprogram the receive DMA controller to start */
5420 /* at the 1st buffer of unfinished frame. */
5421
5422 start_index = frame_start_index;
5423
5424 do
5425 {
5426 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5427
5428 /* Adjust index for wrap around. */
5429 if ( start_index == info->rx_buffer_count )
5430 start_index = 0;
5431
5432 } while( start_index != end_index );
5433
0fab6de0 5434 reprogram_dma = true;
1da177e4
LT		 5435 }
5436
5437 if ( reprogram_dma )
5438 {
5439 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5440 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5441 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5442
5443 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5444
5445 /* This empties the receive FIFO and loads the RCC with RCLR */
5446 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5447
5448 /* program 16C32 with physical address of 1st DMA buffer entry */
5449 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5450 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5451 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5452
5453 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5454 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5455 usc_EnableInterrupts( info, RECEIVE_STATUS );
5456
5457 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5458 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5459
5460 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5461 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5462 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5463 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5464 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5465 else
5466 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5467 }
5468 else
5469 {
5470 /* This empties the receive FIFO and loads the RCC with RCLR */
5471 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5472 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5473 }
5474
5475} /* end of usc_process_rxoverrun_sync() */
5476
5477/* usc_stop_receiver()
5478 *
5479 * Disable USC receiver
5480 *
5481 * Arguments: info pointer to device instance data
5482 * Return Value: None
5483 */
5484static void usc_stop_receiver( struct mgsl_struct *info )
5485{
5486 if (debug_level >= DEBUG_LEVEL_ISR)
5487 printk("%s(%d):usc_stop_receiver(%s)\n",
5488 __FILE__,__LINE__, info->device_name );
5489
5490 /* Disable receive DMA channel. */
5491 /* This also disables receive DMA channel interrupts */
5492 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5493
5494 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5495 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5496 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5497
5498 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5499
5500 /* This empties the receive FIFO and loads the RCC with RCLR */
5501 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5502 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5503
0fab6de0
JP		 5504 info->rx_enabled = false;
5505 info->rx_overflow = false;
5506 info->rx_rcc_underrun = false;
1da177e4
LT		 5507
5508} /* end of stop_receiver() */
5509
5510/* usc_start_receiver()
5511 *
5512 * Enable the USC receiver
5513 *
5514 * Arguments: info pointer to device instance data
5515 * Return Value: None
5516 */
5517static void usc_start_receiver( struct mgsl_struct *info )
5518{
5519 u32 phys_addr;
5520
5521 if (debug_level >= DEBUG_LEVEL_ISR)
5522 printk("%s(%d):usc_start_receiver(%s)\n",
5523 __FILE__,__LINE__, info->device_name );
5524
5525 mgsl_reset_rx_dma_buffers( info );
5526 usc_stop_receiver( info );
5527
5528 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5529 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5530
5531 if ( info->params.mode == MGSL_MODE_HDLC ||
5532 info->params.mode == MGSL_MODE_RAW ) {
5533 /* DMA mode Transfers */
5534 /* Program the DMA controller. */
5535 /* Enable the DMA controller end of buffer interrupt. */
5536
5537 /* program 16C32 with physical address of 1st DMA buffer entry */
5538 phys_addr = info->rx_buffer_list[0].phys_entry;
5539 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5540 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5541
5542 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5543 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5544 usc_EnableInterrupts( info, RECEIVE_STATUS );
5545
5546 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5547 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5548
5549 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5550 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5551 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5552 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5553 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5554 else
5555 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5556 } else {
5557 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5558 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5559 usc_EnableInterrupts(info, RECEIVE_DATA);
5560
5561 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5562 usc_RCmd( info, RCmd_EnterHuntmode );
5563
5564 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5565 }
5566
5567 usc_OutReg( info, CCSR, 0x1020 );
5568
0fab6de0 5569 info->rx_enabled = true;
1da177e4
LT		 5570
5571} /* end of usc_start_receiver() */
5572
5573/* usc_start_transmitter()
5574 *
5575 * Enable the USC transmitter and send a transmit frame if
5576 * one is loaded in the DMA buffers.
5577 *
5578 * Arguments: info pointer to device instance data
5579 * Return Value: None
5580 */
5581static void usc_start_transmitter( struct mgsl_struct *info )
5582{
5583 u32 phys_addr;
5584 unsigned int FrameSize;
5585
5586 if (debug_level >= DEBUG_LEVEL_ISR)
5587 printk("%s(%d):usc_start_transmitter(%s)\n",
5588 __FILE__,__LINE__, info->device_name );
5589
5590 if ( info->xmit_cnt ) {
5591
5592 /* If auto RTS enabled and RTS is inactive, then assert */
5593 /* RTS and set a flag indicating that the driver should */
5594 /* negate RTS when the transmission completes. */
5595
0fab6de0 5596 info->drop_rts_on_tx_done = false;
1da177e4
LT		 5597
5598 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5599 usc_get_serial_signals( info );
5600 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5601 info->serial_signals |= SerialSignal_RTS;
5602 usc_set_serial_signals( info );
0fab6de0 5603 info->drop_rts_on_tx_done = true;
1da177e4
LT		 5604 }
5605 }
5606
5607
5608 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5609 if ( !info->tx_active ) {
5610 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5611 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5612 usc_EnableInterrupts(info, TRANSMIT_DATA);
5613 usc_load_txfifo(info);
5614 }
5615 } else {
5616 /* Disable transmit DMA controller while programming. */
5617 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5618
5619 /* Transmit DMA buffer is loaded, so program USC */
5620 /* to send the frame contained in the buffers. */
5621
5622 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5623
5624 /* if operating in Raw sync mode, reset the rcc component
5625 * of the tx dma buffer entry, otherwise, the serial controller
5626 * will send a closing sync char after this count.
5627 */
5628 if ( info->params.mode == MGSL_MODE_RAW )
5629 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5630
5631 /* Program the Transmit Character Length Register (TCLR) */
5632 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5633 usc_OutReg( info, TCLR, (u16)FrameSize );
5634
5635 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5636
5637 /* Program the address of the 1st DMA Buffer Entry in linked list */
5638 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5639 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5640 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5641
5642 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5643 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5644 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5645
5646 if ( info->params.mode == MGSL_MODE_RAW &&
5647 info->num_tx_dma_buffers > 1 ) {
5648 /* When running external sync mode, attempt to 'stream' transmit */
5649 /* by filling tx dma buffers as they become available. To do this */
5650 /* we need to enable Tx DMA EOB Status interrupts : */
5651 /* */
5652 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5653 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5654
5655 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5656 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5657 }
5658
5659 /* Initialize Transmit DMA Channel */
5660 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5661
5662 usc_TCmd( info, TCmd_SendFrame );
5663
40565f19
JS		 5664 mod_timer(&info->tx_timer, jiffies +
5665 msecs_to_jiffies(5000));
1da177e4 5666 }
0fab6de0 5667 info->tx_active = true;
1da177e4
LT		 5668 }
5669
5670 if ( !info->tx_enabled ) {
0fab6de0 5671 info->tx_enabled = true;
1da177e4
LT		 5672 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5673 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5674 else
5675 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5676 }
5677
5678} /* end of usc_start_transmitter() */
5679
5680/* usc_stop_transmitter()
5681 *
5682 * Stops the transmitter and DMA
5683 *
5684 * Arguments: info pointer to device isntance data
5685 * Return Value: None
5686 */
5687static void usc_stop_transmitter( struct mgsl_struct *info )
5688{
5689 if (debug_level >= DEBUG_LEVEL_ISR)
5690 printk("%s(%d):usc_stop_transmitter(%s)\n",
5691 __FILE__,__LINE__, info->device_name );
5692
5693 del_timer(&info->tx_timer);
5694
5695 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5696 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5697 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5698
5699 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5700 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5701 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5702
0fab6de0
JP		 5703 info->tx_enabled = false;
5704 info->tx_active = false;
1da177e4
LT		 5705
5706} /* end of usc_stop_transmitter() */
5707
5708/* usc_load_txfifo()
5709 *
5710 * Fill the transmit FIFO until the FIFO is full or
5711 * there is no more data to load.
5712 *
5713 * Arguments: info pointer to device extension (instance data)
5714 * Return Value: None
5715 */
5716static void usc_load_txfifo( struct mgsl_struct *info )
5717{
5718 int Fifocount;
5719 u8 TwoBytes[2];
5720
5721 if ( !info->xmit_cnt && !info->x_char )
5722 return;
5723
5724 /* Select transmit FIFO status readback in TICR */
5725 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5726
5727 /* load the Transmit FIFO until FIFOs full or all data sent */
5728
5729 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5730 /* there is more space in the transmit FIFO and */
5731 /* there is more data in transmit buffer */
5732
5733 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5734 /* write a 16-bit word from transmit buffer to 16C32 */
5735
5736 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5737 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5738 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5739 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5740
5741 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5742
5743 info->xmit_cnt -= 2;
5744 info->icount.tx += 2;
5745 } else {
5746 /* only 1 byte left to transmit or 1 FIFO slot left */
5747
5748 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5749 info->io_base + CCAR );
5750
5751 if (info->x_char) {
5752 /* transmit pending high priority char */
5753 outw( info->x_char,info->io_base + CCAR );
5754 info->x_char = 0;
5755 } else {
5756 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5757 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5758 info->xmit_cnt--;
5759 }
5760 info->icount.tx++;
5761 }
5762 }
5763
5764} /* end of usc_load_txfifo() */
5765
5766/* usc_reset()
5767 *
5768 * Reset the adapter to a known state and prepare it for further use.
5769 *
5770 * Arguments: info pointer to device instance data
5771 * Return Value: None
5772 */
5773static void usc_reset( struct mgsl_struct *info )
5774{
5775 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5776 int i;
5777 u32 readval;
5778
5779 /* Set BIT30 of Misc Control Register */
5780 /* (Local Control Register 0x50) to force reset of USC. */
5781
5782 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5783 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5784
5785 info->misc_ctrl_value |= BIT30;
5786 *MiscCtrl = info->misc_ctrl_value;
5787
5788 /*
5789 * Force at least 170ns delay before clearing
5790 * reset bit. Each read from LCR takes at least
5791 * 30ns so 10 times for 300ns to be safe.
5792 */
5793 for(i=0;i<10;i++)
5794 readval = *MiscCtrl;
5795
5796 info->misc_ctrl_value &= ~BIT30;
5797 *MiscCtrl = info->misc_ctrl_value;
5798
5799 *LCR0BRDR = BUS_DESCRIPTOR(
5800 1, // Write Strobe Hold (0-3)
5801 2, // Write Strobe Delay (0-3)
5802 2, // Read Strobe Delay (0-3)
5803 0, // NWDD (Write data-data) (0-3)
5804 4, // NWAD (Write Addr-data) (0-31)
5805 0, // NXDA (Read/Write Data-Addr) (0-3)
5806 0, // NRDD (Read Data-Data) (0-3)
5807 5 // NRAD (Read Addr-Data) (0-31)
5808 );
5809 } else {
5810 /* do HW reset */
5811 outb( 0,info->io_base + 8 );
5812 }
5813
5814 info->mbre_bit = 0;
5815 info->loopback_bits = 0;
5816 info->usc_idle_mode = 0;
5817
5818 /*
5819 * Program the Bus Configuration Register (BCR)
5820 *
5821 * <15> 0 Don't use separate address
5822 * <14..6> 0 reserved
5823 * <5..4> 00 IAckmode = Default, don't care
5824 * <3> 1 Bus Request Totem Pole output
5825 * <2> 1 Use 16 Bit data bus
5826 * <1> 0 IRQ Totem Pole output
5827 * <0> 0 Don't Shift Right Addr
5828 *
5829 * 0000 0000 0000 1100 = 0x000c
5830 *
5831 * By writing to io_base + SDPIN the Wait/Ack pin is
5832 * programmed to work as a Wait pin.
5833 */
5834
5835 outw( 0x000c,info->io_base + SDPIN );
5836
5837
5838 outw( 0,info->io_base );
5839 outw( 0,info->io_base + CCAR );
5840
5841 /* select little endian byte ordering */
5842 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5843
5844
5845 /* Port Control Register (PCR)
5846 *
5847 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5848 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5849 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5850 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5851 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5852 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5853 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5854 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5855 *
5856 * 1111 0000 1111 0101 = 0xf0f5
5857 */
5858
5859 usc_OutReg( info, PCR, 0xf0f5 );
5860
5861
5862 /*
5863 * Input/Output Control Register
5864 *
5865 * <15..14> 00 CTS is active low input
5866 * <13..12> 00 DCD is active low input
5867 * <11..10> 00 TxREQ pin is input (DSR)
5868 * <9..8> 00 RxREQ pin is input (RI)
5869 * <7..6> 00 TxD is output (Transmit Data)
5870 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5871 * <2..0> 100 RxC is Output (drive with BRG0)
5872 *
5873 * 0000 0000 0000 0100 = 0x0004
5874 */
5875
5876 usc_OutReg( info, IOCR, 0x0004 );
5877
5878} /* end of usc_reset() */
5879
5880/* usc_set_async_mode()
5881 *
5882 * Program adapter for asynchronous communications.
5883 *
5884 * Arguments: info pointer to device instance data
5885 * Return Value: None
5886 */
5887static void usc_set_async_mode( struct mgsl_struct *info )
5888{
5889 u16 RegValue;
5890
5891 /* disable interrupts while programming USC */
5892 usc_DisableMasterIrqBit( info );
5893
5894 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5895 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5896
5897 usc_loopback_frame( info );
5898
5899 /* Channel mode Register (CMR)
5900 *
5901 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5902 * <13..12> 00 00 = 16X Clock
5903 * <11..8> 0000 Transmitter mode = Asynchronous
5904 * <7..6> 00 reserved?
5905 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5906 * <3..0> 0000 Receiver mode = Asynchronous
5907 *
5908 * 0000 0000 0000 0000 = 0x0
5909 */
5910
5911 RegValue = 0;
5912 if ( info->params.stop_bits != 1 )
5913 RegValue |= BIT14;
5914 usc_OutReg( info, CMR, RegValue );
5915
5916
5917 /* Receiver mode Register (RMR)
5918 *
5919 * <15..13> 000 encoding = None
5920 * <12..08> 00000 reserved (Sync Only)
5921 * <7..6> 00 Even parity
5922 * <5> 0 parity disabled
5923 * <4..2> 000 Receive Char Length = 8 bits
5924 * <1..0> 00 Disable Receiver
5925 *
5926 * 0000 0000 0000 0000 = 0x0
5927 */
5928
5929 RegValue = 0;
5930
5931 if ( info->params.data_bits != 8 )
5932 RegValue |= BIT4+BIT3+BIT2;
5933
5934 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5935 RegValue |= BIT5;
5936 if ( info->params.parity != ASYNC_PARITY_ODD )
5937 RegValue |= BIT6;
5938 }
5939
5940 usc_OutReg( info, RMR, RegValue );
5941
5942
5943 /* Set IRQ trigger level */
5944
5945 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5946
5947
5948 /* Receive Interrupt Control Register (RICR)
5949 *
5950 * <15..8> ? RxFIFO IRQ Request Level
5951 *
5952 * Note: For async mode the receive FIFO level must be set
7f927fcc 5953 * to 0 to avoid the situation where the FIFO contains fewer bytes
1da177e4
LT		 5954 * than the trigger level and no more data is expected.
5955 *
5956 * <7> 0 Exited Hunt IA (Interrupt Arm)
5957 * <6> 0 Idle Received IA
5958 * <5> 0 Break/Abort IA
5959 * <4> 0 Rx Bound IA
5960 * <3> 0 Queued status reflects oldest byte in FIFO
5961 * <2> 0 Abort/PE IA
5962 * <1> 0 Rx Overrun IA
5963 * <0> 0 Select TC0 value for readback
5964 *
5965 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5966 */
5967
5968 usc_OutReg( info, RICR, 0x0000 );
5969
5970 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5971 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5972
5973
5974 /* Transmit mode Register (TMR)
5975 *
5976 * <15..13> 000 encoding = None
5977 * <12..08> 00000 reserved (Sync Only)
5978 * <7..6> 00 Transmit parity Even
5979 * <5> 0 Transmit parity Disabled
5980 * <4..2> 000 Tx Char Length = 8 bits
5981 * <1..0> 00 Disable Transmitter
5982 *
5983 * 0000 0000 0000 0000 = 0x0
5984 */
5985
5986 RegValue = 0;
5987
5988 if ( info->params.data_bits != 8 )
5989 RegValue |= BIT4+BIT3+BIT2;
5990
5991 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5992 RegValue |= BIT5;
5993 if ( info->params.parity != ASYNC_PARITY_ODD )
5994 RegValue |= BIT6;
5995 }
5996
5997 usc_OutReg( info, TMR, RegValue );
5998
5999 usc_set_txidle( info );
6000
6001
6002 /* Set IRQ trigger level */
6003
6004 usc_TCmd( info, TCmd_SelectTicrIntLevel );
6005
6006
6007 /* Transmit Interrupt Control Register (TICR)
6008 *
6009 * <15..8> ? Transmit FIFO IRQ Level
6010 * <7> 0 Present IA (Interrupt Arm)
6011 * <6> 1 Idle Sent IA
6012 * <5> 0 Abort Sent IA
6013 * <4> 0 EOF/EOM Sent IA
6014 * <3> 0 CRC Sent IA
6015 * <2> 0 1 = Wait for SW Trigger to Start Frame
6016 * <1> 0 Tx Underrun IA
6017 * <0> 0 TC0 constant on read back
6018 *
6019 * 0000 0000 0100 0000 = 0x0040
6020 */
6021
6022 usc_OutReg( info, TICR, 0x1f40 );
6023
6024 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6025 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6026
6027 usc_enable_async_clock( info, info->params.data_rate );
6028
6029
6030 /* Channel Control/status Register (CCSR)
6031 *
6032 * <15> X RCC FIFO Overflow status (RO)
6033 * <14> X RCC FIFO Not Empty status (RO)
6034 * <13> 0 1 = Clear RCC FIFO (WO)
6035 * <12> X DPLL in Sync status (RO)
6036 * <11> X DPLL 2 Missed Clocks status (RO)
6037 * <10> X DPLL 1 Missed Clock status (RO)
6038 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6039 * <7> X SDLC Loop On status (RO)
6040 * <6> X SDLC Loop Send status (RO)
6041 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6042 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6043 * <1..0> 00 reserved
6044 *
6045 * 0000 0000 0010 0000 = 0x0020
6046 */
6047
6048 usc_OutReg( info, CCSR, 0x0020 );
6049
6050 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6051 RECEIVE_DATA + RECEIVE_STATUS );
6052
6053 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6054 RECEIVE_DATA + RECEIVE_STATUS );
6055
6056 usc_EnableMasterIrqBit( info );
6057
6058 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6059 /* Enable INTEN (Port 6, Bit12) */
6060 /* This connects the IRQ request signal to the ISA bus */
6061 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6062 }
6063
7c1fff58
PF		 6064 if (info->params.loopback) {
6065 info->loopback_bits = 0x300;
6066 outw(0x0300, info->io_base + CCAR);
6067 }
6068
1da177e4
LT		 6069} /* end of usc_set_async_mode() */
6070
6071/* usc_loopback_frame()
6072 *
6073 * Loop back a small (2 byte) dummy SDLC frame.
6074 * Interrupts and DMA are NOT used. The purpose of this is to
6075 * clear any 'stale' status info left over from running in async mode.
6076 *
6077 * The 16C32 shows the strange behaviour of marking the 1st
6078 * received SDLC frame with a CRC error even when there is no
6079 * CRC error. To get around this a small dummy from of 2 bytes
6080 * is looped back when switching from async to sync mode.
6081 *
6082 * Arguments: info pointer to device instance data
6083 * Return Value: None
6084 */
6085static void usc_loopback_frame( struct mgsl_struct *info )
6086{
6087 int i;
6088 unsigned long oldmode = info->params.mode;
6089
6090 info->params.mode = MGSL_MODE_HDLC;
6091
6092 usc_DisableMasterIrqBit( info );
6093
6094 usc_set_sdlc_mode( info );
6095 usc_enable_loopback( info, 1 );
6096
6097 /* Write 16-bit Time Constant for BRG0 */
6098 usc_OutReg( info, TC0R, 0 );
6099
6100 /* Channel Control Register (CCR)
6101 *
6102 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6103 * <13> 0 Trigger Tx on SW Command Disabled
6104 * <12> 0 Flag Preamble Disabled
6105 * <11..10> 00 Preamble Length = 8-Bits
6106 * <9..8> 01 Preamble Pattern = flags
6107 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6108 * <5> 0 Trigger Rx on SW Command Disabled
6109 * <4..0> 0 reserved
6110 *
6111 * 0000 0001 0000 0000 = 0x0100
6112 */
6113
6114 usc_OutReg( info, CCR, 0x0100 );
6115
6116 /* SETUP RECEIVER */
6117 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6118 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6119
6120 /* SETUP TRANSMITTER */
6121 /* Program the Transmit Character Length Register (TCLR) */
6122 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6123 usc_OutReg( info, TCLR, 2 );
6124 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6125
6126 /* unlatch Tx status bits, and start transmit channel. */
6127 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6128 outw(0,info->io_base + DATAREG);
6129
6130 /* ENABLE TRANSMITTER */
6131 usc_TCmd( info, TCmd_SendFrame );
6132 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6133
6134 /* WAIT FOR RECEIVE COMPLETE */
6135 for (i=0 ; i<1000 ; i++)
6136 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6137 break;
6138
6139 /* clear Internal Data loopback mode */
6140 usc_enable_loopback(info, 0);
6141
6142 usc_EnableMasterIrqBit(info);
6143
6144 info->params.mode = oldmode;
6145
6146} /* end of usc_loopback_frame() */
6147
6148/* usc_set_sync_mode() Programs the USC for SDLC communications.
6149 *
6150 * Arguments: info pointer to adapter info structure
6151 * Return Value: None
6152 */
6153static void usc_set_sync_mode( struct mgsl_struct *info )
6154{
6155 usc_loopback_frame( info );
6156 usc_set_sdlc_mode( info );
6157
6158 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6159 /* Enable INTEN (Port 6, Bit12) */
6160 /* This connects the IRQ request signal to the ISA bus */
6161 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6162 }
6163
6164 usc_enable_aux_clock(info, info->params.clock_speed);
6165
6166 if (info->params.loopback)
6167 usc_enable_loopback(info,1);
6168
6169} /* end of mgsl_set_sync_mode() */
6170
6171/* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6172 *
6173 * Arguments: info pointer to device instance data
6174 * Return Value: None
6175 */
6176static void usc_set_txidle( struct mgsl_struct *info )
6177{
6178 u16 usc_idle_mode = IDLEMODE_FLAGS;
6179
6180 /* Map API idle mode to USC register bits */
6181
6182 switch( info->idle_mode ){
6183 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6184 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6185 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6186 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6187 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6188 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6189 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6190 }
6191
6192 info->usc_idle_mode = usc_idle_mode;
6193 //usc_OutReg(info, TCSR, usc_idle_mode);
6194 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6195 info->tcsr_value += usc_idle_mode;
6196 usc_OutReg(info, TCSR, info->tcsr_value);
6197
6198 /*
6199 * if SyncLink WAN adapter is running in external sync mode, the
6200 * transmitter has been set to Monosync in order to try to mimic
6201 * a true raw outbound bit stream. Monosync still sends an open/close
6202 * sync char at the start/end of a frame. Try to match those sync
6203 * patterns to the idle mode set here
6204 */
6205 if ( info->params.mode == MGSL_MODE_RAW ) {
6206 unsigned char syncpat = 0;
6207 switch( info->idle_mode ) {
6208 case HDLC_TXIDLE_FLAGS:
6209 syncpat = 0x7e;
6210 break;
6211 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6212 syncpat = 0x55;
6213 break;
6214 case HDLC_TXIDLE_ZEROS:
6215 case HDLC_TXIDLE_SPACE:
6216 syncpat = 0x00;
6217 break;
6218 case HDLC_TXIDLE_ONES:
6219 case HDLC_TXIDLE_MARK:
6220 syncpat = 0xff;
6221 break;
6222 case HDLC_TXIDLE_ALT_MARK_SPACE:
6223 syncpat = 0xaa;
6224 break;
6225 }
6226
6227 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6228 }
6229
6230} /* end of usc_set_txidle() */
6231
6232/* usc_get_serial_signals()
6233 *
6234 * Query the adapter for the state of the V24 status (input) signals.
6235 *
6236 * Arguments: info pointer to device instance data
6237 * Return Value: None
6238 */
6239static void usc_get_serial_signals( struct mgsl_struct *info )
6240{
6241 u16 status;
6242
6243 /* clear all serial signals except DTR and RTS */
6244 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6245
6246 /* Read the Misc Interrupt status Register (MISR) to get */
6247 /* the V24 status signals. */
6248
6249 status = usc_InReg( info, MISR );
6250
6251 /* set serial signal bits to reflect MISR */
6252
6253 if ( status & MISCSTATUS_CTS )
6254 info->serial_signals |= SerialSignal_CTS;
6255
6256 if ( status & MISCSTATUS_DCD )
6257 info->serial_signals |= SerialSignal_DCD;
6258
6259 if ( status & MISCSTATUS_RI )
6260 info->serial_signals |= SerialSignal_RI;
6261
6262 if ( status & MISCSTATUS_DSR )
6263 info->serial_signals |= SerialSignal_DSR;
6264
6265} /* end of usc_get_serial_signals() */
6266
6267/* usc_set_serial_signals()
6268 *
6269 * Set the state of DTR and RTS based on contents of
6270 * serial_signals member of device extension.
6271 *
6272 * Arguments: info pointer to device instance data
6273 * Return Value: None
6274 */
6275static void usc_set_serial_signals( struct mgsl_struct *info )
6276{
6277 u16 Control;
6278 unsigned char V24Out = info->serial_signals;
6279
6280 /* get the current value of the Port Control Register (PCR) */
6281
6282 Control = usc_InReg( info, PCR );
6283
6284 if ( V24Out & SerialSignal_RTS )
6285 Control &= ~(BIT6);
6286 else
6287 Control |= BIT6;
6288
6289 if ( V24Out & SerialSignal_DTR )
6290 Control &= ~(BIT4);
6291 else
6292 Control |= BIT4;
6293
6294 usc_OutReg( info, PCR, Control );
6295
6296} /* end of usc_set_serial_signals() */
6297
6298/* usc_enable_async_clock()
6299 *
6300 * Enable the async clock at the specified frequency.
6301 *
6302 * Arguments: info pointer to device instance data
6303 * data_rate data rate of clock in bps
6304 * 0 disables the AUX clock.
6305 * Return Value: None
6306 */
6307static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6308{
6309 if ( data_rate ) {
6310 /*
6311 * Clock mode Control Register (CMCR)
6312 *
6313 * <15..14> 00 counter 1 Disabled
6314 * <13..12> 00 counter 0 Disabled
6315 * <11..10> 11 BRG1 Input is TxC Pin
6316 * <9..8> 11 BRG0 Input is TxC Pin
6317 * <7..6> 01 DPLL Input is BRG1 Output
6318 * <5..3> 100 TxCLK comes from BRG0
6319 * <2..0> 100 RxCLK comes from BRG0
6320 *
6321 * 0000 1111 0110 0100 = 0x0f64
6322 */
6323
6324 usc_OutReg( info, CMCR, 0x0f64 );
6325
6326
6327 /*
6328 * Write 16-bit Time Constant for BRG0
6329 * Time Constant = (ClkSpeed / data_rate) - 1
6330 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6331 */
6332
6333 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6334 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6335 else
6336 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6337
6338
6339 /*
6340 * Hardware Configuration Register (HCR)
6341 * Clear Bit 1, BRG0 mode = Continuous
6342 * Set Bit 0 to enable BRG0.
6343 */
6344
6345 usc_OutReg( info, HCR,
6346 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6347
6348
6349 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6350
6351 usc_OutReg( info, IOCR,
6352 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6353 } else {
6354 /* data rate == 0 so turn off BRG0 */
6355 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6356 }
6357
6358} /* end of usc_enable_async_clock() */
6359
6360/*
6361 * Buffer Structures:
6362 *
6363 * Normal memory access uses virtual addresses that can make discontiguous
6364 * physical memory pages appear to be contiguous in the virtual address
6365 * space (the processors memory mapping handles the conversions).
6366 *
6367 * DMA transfers require physically contiguous memory. This is because
6368 * the DMA system controller and DMA bus masters deal with memory using
6369 * only physical addresses.
6370 *
6371 * This causes a problem under Windows NT when large DMA buffers are
6372 * needed. Fragmentation of the nonpaged pool prevents allocations of
6373 * physically contiguous buffers larger than the PAGE_SIZE.
6374 *
6375 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6376 * allows DMA transfers to physically discontiguous buffers. Information
6377 * about each data transfer buffer is contained in a memory structure
6378 * called a 'buffer entry'. A list of buffer entries is maintained
6379 * to track and control the use of the data transfer buffers.
6380 *
6381 * To support this strategy we will allocate sufficient PAGE_SIZE
6382 * contiguous memory buffers to allow for the total required buffer
6383 * space.
6384 *
6385 * The 16C32 accesses the list of buffer entries using Bus Master
6386 * DMA. Control information is read from the buffer entries by the
6387 * 16C32 to control data transfers. status information is written to
6388 * the buffer entries by the 16C32 to indicate the status of completed
6389 * transfers.
6390 *
6391 * The CPU writes control information to the buffer entries to control
6392 * the 16C32 and reads status information from the buffer entries to
6393 * determine information about received and transmitted frames.
6394 *
6395 * Because the CPU and 16C32 (adapter) both need simultaneous access
6396 * to the buffer entries, the buffer entry memory is allocated with
6397 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6398 * entry list to PAGE_SIZE.
6399 *
6400 * The actual data buffers on the other hand will only be accessed
6401 * by the CPU or the adapter but not by both simultaneously. This allows
6402 * Scatter/Gather packet based DMA procedures for using physically
6403 * discontiguous pages.
6404 */
6405
6406/*
6407 * mgsl_reset_tx_dma_buffers()
6408 *
6409 * Set the count for all transmit buffers to 0 to indicate the
6410 * buffer is available for use and set the current buffer to the
6411 * first buffer. This effectively makes all buffers free and
6412 * discards any data in buffers.
6413 *
6414 * Arguments: info pointer to device instance data
6415 * Return Value: None
6416 */
6417static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6418{
6419 unsigned int i;
6420
6421 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6422 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6423 }
6424
6425 info->current_tx_buffer = 0;
6426 info->start_tx_dma_buffer = 0;
6427 info->tx_dma_buffers_used = 0;
6428
6429 info->get_tx_holding_index = 0;
6430 info->put_tx_holding_index = 0;
6431 info->tx_holding_count = 0;
6432
6433} /* end of mgsl_reset_tx_dma_buffers() */
6434
6435/*
6436 * num_free_tx_dma_buffers()
6437 *
6438 * returns the number of free tx dma buffers available
6439 *
6440 * Arguments: info pointer to device instance data
6441 * Return Value: number of free tx dma buffers
6442 */
6443static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6444{
6445 return info->tx_buffer_count - info->tx_dma_buffers_used;
6446}
6447
6448/*
6449 * mgsl_reset_rx_dma_buffers()
6450 *
6451 * Set the count for all receive buffers to DMABUFFERSIZE
6452 * and set the current buffer to the first buffer. This effectively
6453 * makes all buffers free and discards any data in buffers.
6454 *
6455 * Arguments: info pointer to device instance data
6456 * Return Value: None
6457 */
6458static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6459{
6460 unsigned int i;
6461
6462 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6463 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6464// info->rx_buffer_list[i].count = DMABUFFERSIZE;
6465// info->rx_buffer_list[i].status = 0;
6466 }
6467
6468 info->current_rx_buffer = 0;
6469
6470} /* end of mgsl_reset_rx_dma_buffers() */
6471
6472/*
6473 * mgsl_free_rx_frame_buffers()
6474 *
6475 * Free the receive buffers used by a received SDLC
6476 * frame such that the buffers can be reused.
6477 *
6478 * Arguments:
6479 *
6480 * info pointer to device instance data
6481 * StartIndex index of 1st receive buffer of frame
6482 * EndIndex index of last receive buffer of frame
6483 *
6484 * Return Value: None
6485 */
6486static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6487{
0fab6de0 6488 bool Done = false;
1da177e4
LT		 6489 DMABUFFERENTRY *pBufEntry;
6490 unsigned int Index;
6491
6492 /* Starting with 1st buffer entry of the frame clear the status */
6493 /* field and set the count field to DMA Buffer Size. */
6494
6495 Index = StartIndex;
6496
6497 while( !Done ) {
6498 pBufEntry = &(info->rx_buffer_list[Index]);
6499
6500 if ( Index == EndIndex ) {
6501 /* This is the last buffer of the frame! */
0fab6de0 6502 Done = true;
1da177e4
LT		 6503 }
6504
6505 /* reset current buffer for reuse */
6506// pBufEntry->status = 0;
6507// pBufEntry->count = DMABUFFERSIZE;
6508 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6509
6510 /* advance to next buffer entry in linked list */
6511 Index++;
6512 if ( Index == info->rx_buffer_count )
6513 Index = 0;
6514 }
6515
6516 /* set current buffer to next buffer after last buffer of frame */
6517 info->current_rx_buffer = Index;
6518
6519} /* end of free_rx_frame_buffers() */
6520
6521/* mgsl_get_rx_frame()
6522 *
6523 * This function attempts to return a received SDLC frame from the
6524 * receive DMA buffers. Only frames received without errors are returned.
6525 *
6526 * Arguments: info pointer to device extension
0fab6de0 6527 * Return Value: true if frame returned, otherwise false
1da177e4 6528 */
0fab6de0 6529static bool mgsl_get_rx_frame(struct mgsl_struct *info)
1da177e4
LT		 6530{
6531 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6532 unsigned short status;
6533 DMABUFFERENTRY *pBufEntry;
6534 unsigned int framesize = 0;
0fab6de0 6535 bool ReturnCode = false;
1da177e4 6536 unsigned long flags;
8fb06c77 6537 struct tty_struct *tty = info->port.tty;
0fab6de0 6538 bool return_frame = false;
1da177e4
LT		 6539
6540 /*
6541 * current_rx_buffer points to the 1st buffer of the next available
6542 * receive frame. To find the last buffer of the frame look for
6543 * a non-zero status field in the buffer entries. (The status
6544 * field is set by the 16C32 after completing a receive frame.
6545 */
6546
6547 StartIndex = EndIndex = info->current_rx_buffer;
6548
6549 while( !info->rx_buffer_list[EndIndex].status ) {
6550 /*
6551 * If the count field of the buffer entry is non-zero then
6552 * this buffer has not been used. (The 16C32 clears the count
6553 * field when it starts using the buffer.) If an unused buffer
6554 * is encountered then there are no frames available.
6555 */
6556
6557 if ( info->rx_buffer_list[EndIndex].count )
6558 goto Cleanup;
6559
6560 /* advance to next buffer entry in linked list */
6561 EndIndex++;
6562 if ( EndIndex == info->rx_buffer_count )
6563 EndIndex = 0;
6564
6565 /* if entire list searched then no frame available */
6566 if ( EndIndex == StartIndex ) {
6567 /* If this occurs then something bad happened,
6568 * all buffers have been 'used' but none mark
6569 * the end of a frame. Reset buffers and receiver.
6570 */
6571
6572 if ( info->rx_enabled ){
6573 spin_lock_irqsave(&info->irq_spinlock,flags);
6574 usc_start_receiver(info);
6575 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6576 }
6577 goto Cleanup;
6578 }
6579 }
6580
6581
6582 /* check status of receive frame */
6583
6584 status = info->rx_buffer_list[EndIndex].status;
6585
6586 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6587 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6588 if ( status & RXSTATUS_SHORT_FRAME )
6589 info->icount.rxshort++;
6590 else if ( status & RXSTATUS_ABORT )
6591 info->icount.rxabort++;
6592 else if ( status & RXSTATUS_OVERRUN )
6593 info->icount.rxover++;
6594 else {
6595 info->icount.rxcrc++;
6596 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
0fab6de0 6597 return_frame = true;
1da177e4
LT		 6598 }
6599 framesize = 0;
af69c7f9 6600#if SYNCLINK_GENERIC_HDLC
1da177e4 6601 {
198191c4
KH		 6602 info->netdev->stats.rx_errors++;
6603 info->netdev->stats.rx_frame_errors++;
1da177e4
LT		 6604 }
6605#endif
6606 } else
0fab6de0 6607 return_frame = true;
1da177e4
LT		 6608
6609 if ( return_frame ) {
6610 /* receive frame has no errors, get frame size.
6611 * The frame size is the starting value of the RCC (which was
6612 * set to 0xffff) minus the ending value of the RCC (decremented
6613 * once for each receive character) minus 2 for the 16-bit CRC.
6614 */
6615
6616 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6617
6618 /* adjust frame size for CRC if any */
6619 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6620 framesize -= 2;
6621 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6622 framesize -= 4;
6623 }
6624
6625 if ( debug_level >= DEBUG_LEVEL_BH )
6626 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6627 __FILE__,__LINE__,info->device_name,status,framesize);
6628
6629 if ( debug_level >= DEBUG_LEVEL_DATA )
6630 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6631 min_t(int, framesize, DMABUFFERSIZE),0);
6632
6633 if (framesize) {
6634 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6635 ((framesize+1) > info->max_frame_size) ) ||
6636 (framesize > info->max_frame_size) )
6637 info->icount.rxlong++;
6638 else {
6639 /* copy dma buffer(s) to contiguous intermediate buffer */
6640 int copy_count = framesize;
6641 int index = StartIndex;
6642 unsigned char *ptmp = info->intermediate_rxbuffer;
6643
6644 if ( !(status & RXSTATUS_CRC_ERROR))
6645 info->icount.rxok++;
6646
6647 while(copy_count) {
6648 int partial_count;
6649 if ( copy_count > DMABUFFERSIZE )
6650 partial_count = DMABUFFERSIZE;
6651 else
6652 partial_count = copy_count;
6653
6654 pBufEntry = &(info->rx_buffer_list[index]);
6655 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6656 ptmp += partial_count;
6657 copy_count -= partial_count;
6658
6659 if ( ++index == info->rx_buffer_count )
6660 index = 0;
6661 }
6662
6663 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6664 ++framesize;
6665 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6666 RX_CRC_ERROR :
6667 RX_OK);
6668
6669 if ( debug_level >= DEBUG_LEVEL_DATA )
6670 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6671 __FILE__,__LINE__,info->device_name,
6672 *ptmp);
6673 }
6674
af69c7f9 6675#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 6676 if (info->netcount)
6677 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6678 else
6679#endif
6680 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6681 }
6682 }
6683 /* Free the buffers used by this frame. */
6684 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6685
0fab6de0 6686 ReturnCode = true;
1da177e4
LT		 6687
6688Cleanup:
6689
6690 if ( info->rx_enabled && info->rx_overflow ) {
6691 /* The receiver needs to restarted because of
6692 * a receive overflow (buffer or FIFO). If the
6693 * receive buffers are now empty, then restart receiver.
6694 */
6695
6696 if ( !info->rx_buffer_list[EndIndex].status &&
6697 info->rx_buffer_list[EndIndex].count ) {
6698 spin_lock_irqsave(&info->irq_spinlock,flags);
6699 usc_start_receiver(info);
6700 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6701 }
6702 }
6703
6704 return ReturnCode;
6705
6706} /* end of mgsl_get_rx_frame() */
6707
6708/* mgsl_get_raw_rx_frame()
6709 *
6710 * This function attempts to return a received frame from the
6711 * receive DMA buffers when running in external loop mode. In this mode,
6712 * we will return at most one DMABUFFERSIZE frame to the application.
6713 * The USC receiver is triggering off of DCD going active to start a new
6714 * frame, and DCD going inactive to terminate the frame (similar to
6715 * processing a closing flag character).
6716 *
6717 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6718 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6719 * status field and the RCC field will indicate the length of the
6720 * entire received frame. We take this RCC field and get the modulus
6721 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6722 * last Rx DMA buffer and return that last portion of the frame.
6723 *
6724 * Arguments: info pointer to device extension
0fab6de0 6725 * Return Value: true if frame returned, otherwise false
1da177e4 6726 */
0fab6de0 6727static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
1da177e4
LT		 6728{
6729 unsigned int CurrentIndex, NextIndex;
6730 unsigned short status;
6731 DMABUFFERENTRY *pBufEntry;
6732 unsigned int framesize = 0;
0fab6de0 6733 bool ReturnCode = false;
1da177e4 6734 unsigned long flags;
8fb06c77 6735 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 6736
6737 /*
6738 * current_rx_buffer points to the 1st buffer of the next available
6739 * receive frame. The status field is set by the 16C32 after
6740 * completing a receive frame. If the status field of this buffer
6741 * is zero, either the USC is still filling this buffer or this
6742 * is one of a series of buffers making up a received frame.
6743 *
6744 * If the count field of this buffer is zero, the USC is either
6745 * using this buffer or has used this buffer. Look at the count
6746 * field of the next buffer. If that next buffer's count is
6747 * non-zero, the USC is still actively using the current buffer.
6748 * Otherwise, if the next buffer's count field is zero, the
6749 * current buffer is complete and the USC is using the next
6750 * buffer.
6751 */
6752 CurrentIndex = NextIndex = info->current_rx_buffer;
6753 ++NextIndex;
6754 if ( NextIndex == info->rx_buffer_count )
6755 NextIndex = 0;
6756
6757 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6758 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6759 info->rx_buffer_list[NextIndex].count == 0)) {
6760 /*
6761 * Either the status field of this dma buffer is non-zero
6762 * (indicating the last buffer of a receive frame) or the next
6763 * buffer is marked as in use -- implying this buffer is complete
6764 * and an intermediate buffer for this received frame.
6765 */
6766
6767 status = info->rx_buffer_list[CurrentIndex].status;
6768
6769 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6770 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6771 if ( status & RXSTATUS_SHORT_FRAME )
6772 info->icount.rxshort++;
6773 else if ( status & RXSTATUS_ABORT )
6774 info->icount.rxabort++;
6775 else if ( status & RXSTATUS_OVERRUN )
6776 info->icount.rxover++;
6777 else
6778 info->icount.rxcrc++;
6779 framesize = 0;
6780 } else {
6781 /*
6782 * A receive frame is available, get frame size and status.
6783 *
6784 * The frame size is the starting value of the RCC (which was
6785 * set to 0xffff) minus the ending value of the RCC (decremented
6786 * once for each receive character) minus 2 or 4 for the 16-bit
6787 * or 32-bit CRC.
6788 *
6789 * If the status field is zero, this is an intermediate buffer.
6790 * It's size is 4K.
6791 *
6792 * If the DMA Buffer Entry's Status field is non-zero, the
6793 * receive operation completed normally (ie: DCD dropped). The
6794 * RCC field is valid and holds the received frame size.
6795 * It is possible that the RCC field will be zero on a DMA buffer
6796 * entry with a non-zero status. This can occur if the total
6797 * frame size (number of bytes between the time DCD goes active
6798 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6799 * case the 16C32 has underrun on the RCC count and appears to
6800 * stop updating this counter to let us know the actual received
6801 * frame size. If this happens (non-zero status and zero RCC),
6802 * simply return the entire RxDMA Buffer
6803 */
6804 if ( status ) {
6805 /*
6806 * In the event that the final RxDMA Buffer is
6807 * terminated with a non-zero status and the RCC
6808 * field is zero, we interpret this as the RCC
6809 * having underflowed (received frame > 65535 bytes).
6810 *
6811 * Signal the event to the user by passing back
6812 * a status of RxStatus_CrcError returning the full
6813 * buffer and let the app figure out what data is
6814 * actually valid
6815 */
6816 if ( info->rx_buffer_list[CurrentIndex].rcc )
6817 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6818 else
6819 framesize = DMABUFFERSIZE;
6820 }
6821 else
6822 framesize = DMABUFFERSIZE;
6823 }
6824
6825 if ( framesize > DMABUFFERSIZE ) {
6826 /*
6827 * if running in raw sync mode, ISR handler for
6828 * End Of Buffer events terminates all buffers at 4K.
6829 * If this frame size is said to be >4K, get the
6830 * actual number of bytes of the frame in this buffer.
6831 */
6832 framesize = framesize % DMABUFFERSIZE;
6833 }
6834
6835
6836 if ( debug_level >= DEBUG_LEVEL_BH )
6837 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6838 __FILE__,__LINE__,info->device_name,status,framesize);
6839
6840 if ( debug_level >= DEBUG_LEVEL_DATA )
6841 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6842 min_t(int, framesize, DMABUFFERSIZE),0);
6843
6844 if (framesize) {
6845 /* copy dma buffer(s) to contiguous intermediate buffer */
6846 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6847
6848 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6849 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6850 info->icount.rxok++;
6851
6852 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6853 }
6854
6855 /* Free the buffers used by this frame. */
6856 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6857
0fab6de0 6858 ReturnCode = true;
1da177e4
LT		 6859 }
6860
6861
6862 if ( info->rx_enabled && info->rx_overflow ) {
6863 /* The receiver needs to restarted because of
6864 * a receive overflow (buffer or FIFO). If the
6865 * receive buffers are now empty, then restart receiver.
6866 */
6867
6868 if ( !info->rx_buffer_list[CurrentIndex].status &&
6869 info->rx_buffer_list[CurrentIndex].count ) {
6870 spin_lock_irqsave(&info->irq_spinlock,flags);
6871 usc_start_receiver(info);
6872 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6873 }
6874 }
6875
6876 return ReturnCode;
6877
6878} /* end of mgsl_get_raw_rx_frame() */
6879
6880/* mgsl_load_tx_dma_buffer()
6881 *
6882 * Load the transmit DMA buffer with the specified data.
6883 *
6884 * Arguments:
6885 *
6886 * info pointer to device extension
6887 * Buffer pointer to buffer containing frame to load
6888 * BufferSize size in bytes of frame in Buffer
6889 *
6890 * Return Value: None
6891 */
6892static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6893 const char *Buffer, unsigned int BufferSize)
6894{
6895 unsigned short Copycount;
6896 unsigned int i = 0;
6897 DMABUFFERENTRY *pBufEntry;
6898
6899 if ( debug_level >= DEBUG_LEVEL_DATA )
6900 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6901
6902 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6903 /* set CMR:13 to start transmit when
6904 * next GoAhead (abort) is received
6905 */
6906 info->cmr_value |= BIT13;
6907 }
6908
6909 /* begin loading the frame in the next available tx dma
6910 * buffer, remember it's starting location for setting
6911 * up tx dma operation
6912 */
6913 i = info->current_tx_buffer;
6914 info->start_tx_dma_buffer = i;
6915
6916 /* Setup the status and RCC (Frame Size) fields of the 1st */
6917 /* buffer entry in the transmit DMA buffer list. */
6918
6919 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6920 info->tx_buffer_list[i].rcc = BufferSize;
6921 info->tx_buffer_list[i].count = BufferSize;
6922
6923 /* Copy frame data from 1st source buffer to the DMA buffers. */
6924 /* The frame data may span multiple DMA buffers. */
6925
6926 while( BufferSize ){
6927 /* Get a pointer to next DMA buffer entry. */
6928 pBufEntry = &info->tx_buffer_list[i++];
6929
6930 if ( i == info->tx_buffer_count )
6931 i=0;
6932
6933 /* Calculate the number of bytes that can be copied from */
6934 /* the source buffer to this DMA buffer. */
6935 if ( BufferSize > DMABUFFERSIZE )
6936 Copycount = DMABUFFERSIZE;
6937 else
6938 Copycount = BufferSize;
6939
6940 /* Actually copy data from source buffer to DMA buffer. */
6941 /* Also set the data count for this individual DMA buffer. */
6942 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6943 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6944 else
6945 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6946
6947 pBufEntry->count = Copycount;
6948
6949 /* Advance source pointer and reduce remaining data count. */
6950 Buffer += Copycount;
6951 BufferSize -= Copycount;
6952
6953 ++info->tx_dma_buffers_used;
6954 }
6955
6956 /* remember next available tx dma buffer */
6957 info->current_tx_buffer = i;
6958
6959} /* end of mgsl_load_tx_dma_buffer() */
6960
6961/*
6962 * mgsl_register_test()
6963 *
6964 * Performs a register test of the 16C32.
6965 *
6966 * Arguments: info pointer to device instance data
0fab6de0 6967 * Return Value: true if test passed, otherwise false
1da177e4 6968 */
0fab6de0 6969static bool mgsl_register_test( struct mgsl_struct *info )
1da177e4
LT		 6970{
6971 static unsigned short BitPatterns[] =
6972 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
fe971071 6973 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
1da177e4 6974 unsigned int i;
0fab6de0 6975 bool rc = true;
1da177e4
LT		 6976 unsigned long flags;
6977
6978 spin_lock_irqsave(&info->irq_spinlock,flags);
6979 usc_reset(info);
6980
6981 /* Verify the reset state of some registers. */
6982
6983 if ( (usc_InReg( info, SICR ) != 0) ||
6984 (usc_InReg( info, IVR ) != 0) ||
6985 (usc_InDmaReg( info, DIVR ) != 0) ){
0fab6de0 6986 rc = false;
1da177e4
LT		 6987 }
6988
0fab6de0 6989 if ( rc ){
1da177e4
LT		 6990 /* Write bit patterns to various registers but do it out of */
6991 /* sync, then read back and verify values. */
6992
6993 for ( i = 0 ; i < Patterncount ; i++ ) {
6994 usc_OutReg( info, TC0R, BitPatterns[i] );
6995 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6996 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6997 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6998 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6999 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
7000
7001 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
7002 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
7003 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
7004 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
7005 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
7006 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
0fab6de0 7007 rc = false;
1da177e4
LT		 7008 break;
7009 }
7010 }
7011 }
7012
7013 usc_reset(info);
7014 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7015
7016 return rc;
7017
7018} /* end of mgsl_register_test() */
7019
7020/* mgsl_irq_test() Perform interrupt test of the 16C32.
7021 *
7022 * Arguments: info pointer to device instance data
0fab6de0 7023 * Return Value: true if test passed, otherwise false
1da177e4 7024 */
0fab6de0 7025static bool mgsl_irq_test( struct mgsl_struct *info )
1da177e4
LT		 7026{
7027 unsigned long EndTime;
7028 unsigned long flags;
7029
7030 spin_lock_irqsave(&info->irq_spinlock,flags);
7031 usc_reset(info);
7032
7033 /*
7034 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
0fab6de0 7035 * The ISR sets irq_occurred to true.
1da177e4
LT		 7036 */
7037
0fab6de0 7038 info->irq_occurred = false;
1da177e4
LT		 7039
7040 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7041 /* Enable INTEN (Port 6, Bit12) */
7042 /* This connects the IRQ request signal to the ISA bus */
7043 /* on the ISA adapter. This has no effect for the PCI adapter */
7044 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7045
7046 usc_EnableMasterIrqBit(info);
7047 usc_EnableInterrupts(info, IO_PIN);
7048 usc_ClearIrqPendingBits(info, IO_PIN);
7049
7050 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7051 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7052
7053 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7054
7055 EndTime=100;
7056 while( EndTime-- && !info->irq_occurred ) {
7057 msleep_interruptible(10);
7058 }
7059
7060 spin_lock_irqsave(&info->irq_spinlock,flags);
7061 usc_reset(info);
7062 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7063
0fab6de0 7064 return info->irq_occurred;
1da177e4
LT		 7065
7066} /* end of mgsl_irq_test() */
7067
7068/* mgsl_dma_test()
7069 *
7070 * Perform a DMA test of the 16C32. A small frame is
7071 * transmitted via DMA from a transmit buffer to a receive buffer
7072 * using single buffer DMA mode.
7073 *
7074 * Arguments: info pointer to device instance data
0fab6de0 7075 * Return Value: true if test passed, otherwise false
1da177e4 7076 */
0fab6de0 7077static bool mgsl_dma_test( struct mgsl_struct *info )
1da177e4
LT		 7078{
7079 unsigned short FifoLevel;
7080 unsigned long phys_addr;
7081 unsigned int FrameSize;
7082 unsigned int i;
7083 char *TmpPtr;
0fab6de0 7084 bool rc = true;
1da177e4
LT		 7085 unsigned short status=0;
7086 unsigned long EndTime;
7087 unsigned long flags;
7088 MGSL_PARAMS tmp_params;
7089
7090 /* save current port options */
7091 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7092 /* load default port options */
7093 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7094
7095#define TESTFRAMESIZE 40
7096
7097 spin_lock_irqsave(&info->irq_spinlock,flags);
7098
7099 /* setup 16C32 for SDLC DMA transfer mode */
7100
7101 usc_reset(info);
7102 usc_set_sdlc_mode(info);
7103 usc_enable_loopback(info,1);
7104
7105 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7106 * field of the buffer entry after fetching buffer address. This
7107 * way we can detect a DMA failure for a DMA read (which should be
7108 * non-destructive to system memory) before we try and write to
7109 * memory (where a failure could corrupt system memory).
7110 */
7111
7112 /* Receive DMA mode Register (RDMR)
7113 *
7114 * <15..14> 11 DMA mode = Linked List Buffer mode
7115 * <13> 1 RSBinA/L = store Rx status Block in List entry
7116 * <12> 0 1 = Clear count of List Entry after fetching
7117 * <11..10> 00 Address mode = Increment
7118 * <9> 1 Terminate Buffer on RxBound
7119 * <8> 0 Bus Width = 16bits
7120 * <7..0> ? status Bits (write as 0s)
7121 *
7122 * 1110 0010 0000 0000 = 0xe200
7123 */
7124
7125 usc_OutDmaReg( info, RDMR, 0xe200 );
7126
7127 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7128
7129
7130 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7131
7132 FrameSize = TESTFRAMESIZE;
7133
7134 /* setup 1st transmit buffer entry: */
7135 /* with frame size and transmit control word */
7136
7137 info->tx_buffer_list[0].count = FrameSize;
7138 info->tx_buffer_list[0].rcc = FrameSize;
7139 info->tx_buffer_list[0].status = 0x4000;
7140
7141 /* build a transmit frame in 1st transmit DMA buffer */
7142
7143 TmpPtr = info->tx_buffer_list[0].virt_addr;
7144 for (i = 0; i < FrameSize; i++ )
7145 *TmpPtr++ = i;
7146
7147 /* setup 1st receive buffer entry: */
7148 /* clear status, set max receive buffer size */
7149
7150 info->rx_buffer_list[0].status = 0;
7151 info->rx_buffer_list[0].count = FrameSize + 4;
7152
7153 /* zero out the 1st receive buffer */
7154
7155 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7156
7157 /* Set count field of next buffer entries to prevent */
7158 /* 16C32 from using buffers after the 1st one. */
7159
7160 info->tx_buffer_list[1].count = 0;
7161 info->rx_buffer_list[1].count = 0;
7162
7163
7164 /***************************/
7165 /* Program 16C32 receiver. */
7166 /***************************/
7167
7168 spin_lock_irqsave(&info->irq_spinlock,flags);
7169
7170 /* setup DMA transfers */
7171 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7172
7173 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7174 phys_addr = info->rx_buffer_list[0].phys_entry;
7175 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7176 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7177
7178 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7179 usc_InDmaReg( info, RDMR );
7180 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7181
7182 /* Enable Receiver (RMR <1..0> = 10) */
7183 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7184
7185 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7186
7187
7188 /*************************************************************/
7189 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7190 /*************************************************************/
7191
7192 /* Wait 100ms for interrupt. */
7193 EndTime = jiffies + msecs_to_jiffies(100);
7194
7195 for(;;) {
7196 if (time_after(jiffies, EndTime)) {
0fab6de0 7197 rc = false;
1da177e4
LT		 7198 break;
7199 }
7200
7201 spin_lock_irqsave(&info->irq_spinlock,flags);
7202 status = usc_InDmaReg( info, RDMR );
7203 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7204
7205 if ( !(status & BIT4) && (status & BIT5) ) {
7206 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7207 /* BUSY (BIT 5) is active (channel still active). */
7208 /* This means the buffer entry read has completed. */
7209 break;
7210 }
7211 }
7212
7213
7214 /******************************/
7215 /* Program 16C32 transmitter. */
7216 /******************************/
7217
7218 spin_lock_irqsave(&info->irq_spinlock,flags);
7219
7220 /* Program the Transmit Character Length Register (TCLR) */
7221 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7222
7223 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7224 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7225
7226 /* Program the address of the 1st DMA Buffer Entry in linked list */
7227
7228 phys_addr = info->tx_buffer_list[0].phys_entry;
7229 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7230 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7231
7232 /* unlatch Tx status bits, and start transmit channel. */
7233
7234 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7235 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7236
7237 /* wait for DMA controller to fill transmit FIFO */
7238
7239 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7240
7241 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7242
7243
7244 /**********************************/
7245 /* WAIT FOR TRANSMIT FIFO TO FILL */
7246 /**********************************/
7247
7248 /* Wait 100ms */
7249 EndTime = jiffies + msecs_to_jiffies(100);
7250
7251 for(;;) {
7252 if (time_after(jiffies, EndTime)) {
0fab6de0 7253 rc = false;
1da177e4
LT		 7254 break;
7255 }
7256
7257 spin_lock_irqsave(&info->irq_spinlock,flags);
7258 FifoLevel = usc_InReg(info, TICR) >> 8;
7259 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7260
7261 if ( FifoLevel < 16 )
7262 break;
7263 else
7264 if ( FrameSize < 32 ) {
7265 /* This frame is smaller than the entire transmit FIFO */
7266 /* so wait for the entire frame to be loaded. */
7267 if ( FifoLevel <= (32 - FrameSize) )
7268 break;
7269 }
7270 }
7271
7272
0fab6de0 7273 if ( rc )
1da177e4
LT		 7274 {
7275 /* Enable 16C32 transmitter. */
7276
7277 spin_lock_irqsave(&info->irq_spinlock,flags);
7278
7279 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7280 usc_TCmd( info, TCmd_SendFrame );
7281 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7282
7283 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7284
7285
7286 /******************************/
7287 /* WAIT FOR TRANSMIT COMPLETE */
7288 /******************************/
7289
7290 /* Wait 100ms */
7291 EndTime = jiffies + msecs_to_jiffies(100);
7292
7293 /* While timer not expired wait for transmit complete */
7294
7295 spin_lock_irqsave(&info->irq_spinlock,flags);
7296 status = usc_InReg( info, TCSR );
7297 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7298
7299 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7300 if (time_after(jiffies, EndTime)) {
0fab6de0 7301 rc = false;
1da177e4
LT		 7302 break;
7303 }
7304
7305 spin_lock_irqsave(&info->irq_spinlock,flags);
7306 status = usc_InReg( info, TCSR );
7307 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7308 }
7309 }
7310
7311
0fab6de0 7312 if ( rc ){
1da177e4
LT		 7313 /* CHECK FOR TRANSMIT ERRORS */
7314 if ( status & (BIT5 + BIT1) )
0fab6de0 7315 rc = false;
1da177e4
LT		 7316 }
7317
0fab6de0 7318 if ( rc ) {
1da177e4
LT		 7319 /* WAIT FOR RECEIVE COMPLETE */
7320
7321 /* Wait 100ms */
7322 EndTime = jiffies + msecs_to_jiffies(100);
7323
7324 /* Wait for 16C32 to write receive status to buffer entry. */
7325 status=info->rx_buffer_list[0].status;
7326 while ( status == 0 ) {
7327 if (time_after(jiffies, EndTime)) {
0fab6de0 7328 rc = false;
1da177e4
LT		 7329 break;
7330 }
7331 status=info->rx_buffer_list[0].status;
7332 }
7333 }
7334
7335
0fab6de0 7336 if ( rc ) {
1da177e4
LT		 7337 /* CHECK FOR RECEIVE ERRORS */
7338 status = info->rx_buffer_list[0].status;
7339
7340 if ( status & (BIT8 + BIT3 + BIT1) ) {
7341 /* receive error has occurred */
0fab6de0 7342 rc = false;
1da177e4
LT		 7343 } else {
7344 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7345 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
0fab6de0 7346 rc = false;
1da177e4
LT		 7347 }
7348 }
7349 }
7350
7351 spin_lock_irqsave(&info->irq_spinlock,flags);
7352 usc_reset( info );
7353 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7354
7355 /* restore current port options */
7356 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7357
7358 return rc;
7359
7360} /* end of mgsl_dma_test() */
7361
7362/* mgsl_adapter_test()
7363 *
7364 * Perform the register, IRQ, and DMA tests for the 16C32.
7365 *
7366 * Arguments: info pointer to device instance data
7367 * Return Value: 0 if success, otherwise -ENODEV
7368 */
7369static int mgsl_adapter_test( struct mgsl_struct *info )
7370{
7371 if ( debug_level >= DEBUG_LEVEL_INFO )
7372 printk( "%s(%d):Testing device %s\n",
7373 __FILE__,__LINE__,info->device_name );
7374
7375 if ( !mgsl_register_test( info ) ) {
7376 info->init_error = DiagStatus_AddressFailure;
7377 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7378 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7379 return -ENODEV;
7380 }
7381
7382 if ( !mgsl_irq_test( info ) ) {
7383 info->init_error = DiagStatus_IrqFailure;
7384 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7385 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7386 return -ENODEV;
7387 }
7388
7389 if ( !mgsl_dma_test( info ) ) {
7390 info->init_error = DiagStatus_DmaFailure;
7391 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7392 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7393 return -ENODEV;
7394 }
7395
7396 if ( debug_level >= DEBUG_LEVEL_INFO )
7397 printk( "%s(%d):device %s passed diagnostics\n",
7398 __FILE__,__LINE__,info->device_name );
7399
7400 return 0;
7401
7402} /* end of mgsl_adapter_test() */
7403
7404/* mgsl_memory_test()
7405 *
7406 * Test the shared memory on a PCI adapter.
7407 *
7408 * Arguments: info pointer to device instance data
0fab6de0 7409 * Return Value: true if test passed, otherwise false
1da177e4 7410 */
0fab6de0 7411static bool mgsl_memory_test( struct mgsl_struct *info )
1da177e4 7412{
fe971071
TK		 7413 static unsigned long BitPatterns[] =
7414 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7415 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
1da177e4
LT		 7416 unsigned long i;
7417 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7418 unsigned long * TestAddr;
7419
7420 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
0fab6de0 7421 return true;
1da177e4
LT		 7422
7423 TestAddr = (unsigned long *)info->memory_base;
7424
7425 /* Test data lines with test pattern at one location. */
7426
7427 for ( i = 0 ; i < Patterncount ; i++ ) {
7428 *TestAddr = BitPatterns[i];
7429 if ( *TestAddr != BitPatterns[i] )
0fab6de0 7430 return false;
1da177e4
LT		 7431 }
7432
7433 /* Test address lines with incrementing pattern over */
7434 /* entire address range. */
7435
7436 for ( i = 0 ; i < TestLimit ; i++ ) {
7437 *TestAddr = i * 4;
7438 TestAddr++;
7439 }
7440
7441 TestAddr = (unsigned long *)info->memory_base;
7442
7443 for ( i = 0 ; i < TestLimit ; i++ ) {
7444 if ( *TestAddr != i * 4 )
0fab6de0 7445 return false;
1da177e4
LT		 7446 TestAddr++;
7447 }
7448
7449 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7450
0fab6de0 7451 return true;
1da177e4
LT		 7452
7453} /* End Of mgsl_memory_test() */
7454
7455
7456/* mgsl_load_pci_memory()
7457 *
7458 * Load a large block of data into the PCI shared memory.
7459 * Use this instead of memcpy() or memmove() to move data
7460 * into the PCI shared memory.
7461 *
7462 * Notes:
7463 *
7464 * This function prevents the PCI9050 interface chip from hogging
7465 * the adapter local bus, which can starve the 16C32 by preventing
7466 * 16C32 bus master cycles.
7467 *
7468 * The PCI9050 documentation says that the 9050 will always release
7469 * control of the local bus after completing the current read
7470 * or write operation.
7471 *
7472 * It appears that as long as the PCI9050 write FIFO is full, the
7473 * PCI9050 treats all of the writes as a single burst transaction
7474 * and will not release the bus. This causes DMA latency problems
7475 * at high speeds when copying large data blocks to the shared
7476 * memory.
7477 *
7478 * This function in effect, breaks the a large shared memory write
7479 * into multiple transations by interleaving a shared memory read
7480 * which will flush the write FIFO and 'complete' the write
7481 * transation. This allows any pending DMA request to gain control
7482 * of the local bus in a timely fasion.
7483 *
7484 * Arguments:
7485 *
7486 * TargetPtr pointer to target address in PCI shared memory
7487 * SourcePtr pointer to source buffer for data
7488 * count count in bytes of data to copy
7489 *
7490 * Return Value: None
7491 */
7492static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7493 unsigned short count )
7494{
7495 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7496#define PCI_LOAD_INTERVAL 64
7497
7498 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7499 unsigned short Index;
7500 unsigned long Dummy;
7501
7502 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7503 {
7504 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7505 Dummy = *((volatile unsigned long *)TargetPtr);
7506 TargetPtr += PCI_LOAD_INTERVAL;
7507 SourcePtr += PCI_LOAD_INTERVAL;
7508 }
7509
7510 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7511
7512} /* End Of mgsl_load_pci_memory() */
7513
7514static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7515{
7516 int i;
7517 int linecount;
7518 if (xmit)
7519 printk("%s tx data:\n",info->device_name);
7520 else
7521 printk("%s rx data:\n",info->device_name);
7522
7523 while(count) {
7524 if (count > 16)
7525 linecount = 16;
7526 else
7527 linecount = count;
7528
7529 for(i=0;i<linecount;i++)
7530 printk("%02X ",(unsigned char)data[i]);
7531 for(;i<17;i++)
7532 printk(" ");
7533 for(i=0;i<linecount;i++) {
7534 if (data[i]>=040 && data[i]<=0176)
7535 printk("%c",data[i]);
7536 else
7537 printk(".");
7538 }
7539 printk("\n");
7540
7541 data += linecount;
7542 count -= linecount;
7543 }
7544} /* end of mgsl_trace_block() */
7545
7546/* mgsl_tx_timeout()
7547 *
7548 * called when HDLC frame times out
7549 * update stats and do tx completion processing
7550 *
7551 * Arguments: context pointer to device instance data
7552 * Return Value: None
7553 */
7554static void mgsl_tx_timeout(unsigned long context)
7555{
7556 struct mgsl_struct *info = (struct mgsl_struct*)context;
7557 unsigned long flags;
7558
7559 if ( debug_level >= DEBUG_LEVEL_INFO )
7560 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7561 __FILE__,__LINE__,info->device_name);
7562 if(info->tx_active &&
7563 (info->params.mode == MGSL_MODE_HDLC ||
7564 info->params.mode == MGSL_MODE_RAW) ) {
7565 info->icount.txtimeout++;
7566 }
7567 spin_lock_irqsave(&info->irq_spinlock,flags);
0fab6de0 7568 info->tx_active = false;
1da177e4
LT		 7569 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7570
7571 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7572 usc_loopmode_cancel_transmit( info );
7573
7574 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7575
af69c7f9 7576#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 7577 if (info->netcount)
7578 hdlcdev_tx_done(info);
7579 else
7580#endif
7581 mgsl_bh_transmit(info);
7582
7583} /* end of mgsl_tx_timeout() */
7584
7585/* signal that there are no more frames to send, so that
7586 * line is 'released' by echoing RxD to TxD when current
7587 * transmission is complete (or immediately if no tx in progress).
7588 */
7589static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7590{
7591 unsigned long flags;
7592
7593 spin_lock_irqsave(&info->irq_spinlock,flags);
7594 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7595 if (info->tx_active)
0fab6de0 7596 info->loopmode_send_done_requested = true;
1da177e4
LT		 7597 else
7598 usc_loopmode_send_done(info);
7599 }
7600 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7601
7602 return 0;
7603}
7604
7605/* release the line by echoing RxD to TxD
7606 * upon completion of a transmit frame
7607 */
7608static void usc_loopmode_send_done( struct mgsl_struct * info )
7609{
0fab6de0 7610 info->loopmode_send_done_requested = false;
1da177e4
LT		 7611 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7612 info->cmr_value &= ~BIT13;
7613 usc_OutReg(info, CMR, info->cmr_value);
7614}
7615
7616/* abort a transmit in progress while in HDLC LoopMode
7617 */
7618static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7619{
7620 /* reset tx dma channel and purge TxFifo */
7621 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7622 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7623 usc_loopmode_send_done( info );
7624}
7625
7626/* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7627 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7628 * we must clear CMR:13 to begin repeating TxData to RxData
7629 */
7630static void usc_loopmode_insert_request( struct mgsl_struct * info )
7631{
0fab6de0 7632 info->loopmode_insert_requested = true;
1da177e4
LT		 7633
7634 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7635 * begin repeating TxData on RxData (complete insertion)
7636 */
7637 usc_OutReg( info, RICR,
7638 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7639
7640 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7641 info->cmr_value |= BIT13;
7642 usc_OutReg(info, CMR, info->cmr_value);
7643}
7644
7645/* return 1 if station is inserted into the loop, otherwise 0
7646 */
7647static int usc_loopmode_active( struct mgsl_struct * info)
7648{
7649 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7650}
7651
af69c7f9 7652#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 7653
7654/**
7655 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7656 * set encoding and frame check sequence (FCS) options
7657 *
7658 * dev pointer to network device structure
7659 * encoding serial encoding setting
7660 * parity FCS setting
7661 *
7662 * returns 0 if success, otherwise error code
7663 */
7664static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7665 unsigned short parity)
7666{
7667 struct mgsl_struct *info = dev_to_port(dev);
7668 unsigned char new_encoding;
7669 unsigned short new_crctype;
7670
7671 /* return error if TTY interface open */
8fb06c77 7672 if (info->port.count)
1da177e4
LT		 7673 return -EBUSY;
7674
7675 switch (encoding)
7676 {
7677 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7678 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7679 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7680 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7681 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7682 default: return -EINVAL;
7683 }
7684
7685 switch (parity)
7686 {
7687 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7688 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7689 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7690 default: return -EINVAL;
7691 }
7692
7693 info->params.encoding = new_encoding;
53b3531b 7694 info->params.crc_type = new_crctype;
1da177e4
LT		 7695
7696 /* if network interface up, reprogram hardware */
7697 if (info->netcount)
7698 mgsl_program_hw(info);
7699
7700 return 0;
7701}
7702
7703/**
7704 * called by generic HDLC layer to send frame
7705 *
7706 * skb socket buffer containing HDLC frame
7707 * dev pointer to network device structure
1da177e4 7708 */
4c5d502d
SH		 7709static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
7710 struct net_device *dev)
1da177e4
LT		 7711{
7712 struct mgsl_struct *info = dev_to_port(dev);
1da177e4
LT		 7713 unsigned long flags;
7714
7715 if (debug_level >= DEBUG_LEVEL_INFO)
7716 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7717
7718 /* stop sending until this frame completes */
7719 netif_stop_queue(dev);
7720
7721 /* copy data to device buffers */
7722 info->xmit_cnt = skb->len;
7723 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7724
7725 /* update network statistics */
198191c4
KH		 7726 dev->stats.tx_packets++;
7727 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 7728
7729 /* done with socket buffer, so free it */
7730 dev_kfree_skb(skb);
7731
7732 /* save start time for transmit timeout detection */
7733 dev->trans_start = jiffies;
7734
7735 /* start hardware transmitter if necessary */
7736 spin_lock_irqsave(&info->irq_spinlock,flags);
7737 if (!info->tx_active)
7738 usc_start_transmitter(info);
7739 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7740
4c5d502d 7741 return NETDEV_TX_OK;
1da177e4
LT		 7742}
7743
7744/**
7745 * called by network layer when interface enabled
7746 * claim resources and initialize hardware
7747 *
7748 * dev pointer to network device structure
7749 *
7750 * returns 0 if success, otherwise error code
7751 */
7752static int hdlcdev_open(struct net_device *dev)
7753{
7754 struct mgsl_struct *info = dev_to_port(dev);
7755 int rc;
7756 unsigned long flags;
7757
7758 if (debug_level >= DEBUG_LEVEL_INFO)
7759 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7760
7761 /* generic HDLC layer open processing */
7762 if ((rc = hdlc_open(dev)))
7763 return rc;
7764
7765 /* arbitrate between network and tty opens */
7766 spin_lock_irqsave(&info->netlock, flags);
8fb06c77 7767 if (info->port.count != 0 || info->netcount != 0) {
1da177e4
LT		 7768 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7769 spin_unlock_irqrestore(&info->netlock, flags);
7770 return -EBUSY;
7771 }
7772 info->netcount=1;
7773 spin_unlock_irqrestore(&info->netlock, flags);
7774
7775 /* claim resources and init adapter */
7776 if ((rc = startup(info)) != 0) {
7777 spin_lock_irqsave(&info->netlock, flags);
7778 info->netcount=0;
7779 spin_unlock_irqrestore(&info->netlock, flags);
7780 return rc;
7781 }
7782
7783 /* assert DTR and RTS, apply hardware settings */
7784 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7785 mgsl_program_hw(info);
7786
7787 /* enable network layer transmit */
7788 dev->trans_start = jiffies;
7789 netif_start_queue(dev);
7790
7791 /* inform generic HDLC layer of current DCD status */
7792 spin_lock_irqsave(&info->irq_spinlock, flags);
7793 usc_get_serial_signals(info);
7794 spin_unlock_irqrestore(&info->irq_spinlock, flags);
fbeff3c1
KH		 7795 if (info->serial_signals & SerialSignal_DCD)
7796 netif_carrier_on(dev);
7797 else
7798 netif_carrier_off(dev);
1da177e4
LT		 7799 return 0;
7800}
7801
7802/**
7803 * called by network layer when interface is disabled
7804 * shutdown hardware and release resources
7805 *
7806 * dev pointer to network device structure
7807 *
7808 * returns 0 if success, otherwise error code
7809 */
7810static int hdlcdev_close(struct net_device *dev)
7811{
7812 struct mgsl_struct *info = dev_to_port(dev);
7813 unsigned long flags;
7814
7815 if (debug_level >= DEBUG_LEVEL_INFO)
7816 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7817
7818 netif_stop_queue(dev);
7819
7820 /* shutdown adapter and release resources */
7821 shutdown(info);
7822
7823 hdlc_close(dev);
7824
7825 spin_lock_irqsave(&info->netlock, flags);
7826 info->netcount=0;
7827 spin_unlock_irqrestore(&info->netlock, flags);
7828
7829 return 0;
7830}
7831
7832/**
7833 * called by network layer to process IOCTL call to network device
7834 *
7835 * dev pointer to network device structure
7836 * ifr pointer to network interface request structure
7837 * cmd IOCTL command code
7838 *
7839 * returns 0 if success, otherwise error code
7840 */
7841static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7842{
7843 const size_t size = sizeof(sync_serial_settings);
7844 sync_serial_settings new_line;
7845 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7846 struct mgsl_struct *info = dev_to_port(dev);
7847 unsigned int flags;
7848
7849 if (debug_level >= DEBUG_LEVEL_INFO)
7850 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7851
7852 /* return error if TTY interface open */
8fb06c77 7853 if (info->port.count)
1da177e4
LT		 7854 return -EBUSY;
7855
7856 if (cmd != SIOCWANDEV)
7857 return hdlc_ioctl(dev, ifr, cmd);
7858
7859 switch(ifr->ifr_settings.type) {
7860 case IF_GET_IFACE: /* return current sync_serial_settings */
7861
7862 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7863 if (ifr->ifr_settings.size < size) {
7864 ifr->ifr_settings.size = size; /* data size wanted */
7865 return -ENOBUFS;
7866 }
7867
7868 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7869 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7870 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7871 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7872
7873 switch (flags){
7874 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7875 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7876 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7877 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7878 default: new_line.clock_type = CLOCK_DEFAULT;
7879 }
7880
7881 new_line.clock_rate = info->params.clock_speed;
7882 new_line.loopback = info->params.loopback ? 1:0;
7883
7884 if (copy_to_user(line, &new_line, size))
7885 return -EFAULT;
7886 return 0;
7887
7888 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7889
7890 if(!capable(CAP_NET_ADMIN))
7891 return -EPERM;
7892 if (copy_from_user(&new_line, line, size))
7893 return -EFAULT;
7894
7895 switch (new_line.clock_type)
7896 {
7897 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7898 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7899 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7900 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7901 case CLOCK_DEFAULT: flags = info->params.flags &
7902 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7903 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7904 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7905 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7906 default: return -EINVAL;
7907 }
7908
7909 if (new_line.loopback != 0 && new_line.loopback != 1)
7910 return -EINVAL;
7911
7912 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7913 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7914 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7915 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7916 info->params.flags |= flags;
7917
7918 info->params.loopback = new_line.loopback;
7919
7920 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7921 info->params.clock_speed = new_line.clock_rate;
7922 else
7923 info->params.clock_speed = 0;
7924
7925 /* if network interface up, reprogram hardware */
7926 if (info->netcount)
7927 mgsl_program_hw(info);
7928 return 0;
7929
7930 default:
7931 return hdlc_ioctl(dev, ifr, cmd);
7932 }
7933}
7934
7935/**
7936 * called by network layer when transmit timeout is detected
7937 *
7938 * dev pointer to network device structure
7939 */
7940static void hdlcdev_tx_timeout(struct net_device *dev)
7941{
7942 struct mgsl_struct *info = dev_to_port(dev);
1da177e4
LT		 7943 unsigned long flags;
7944
7945 if (debug_level >= DEBUG_LEVEL_INFO)
7946 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7947
198191c4
KH		 7948 dev->stats.tx_errors++;
7949 dev->stats.tx_aborted_errors++;
1da177e4
LT		 7950
7951 spin_lock_irqsave(&info->irq_spinlock,flags);
7952 usc_stop_transmitter(info);
7953 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7954
7955 netif_wake_queue(dev);
7956}
7957
7958/**
7959 * called by device driver when transmit completes
7960 * reenable network layer transmit if stopped
7961 *
7962 * info pointer to device instance information
7963 */
7964static void hdlcdev_tx_done(struct mgsl_struct *info)
7965{
7966 if (netif_queue_stopped(info->netdev))
7967 netif_wake_queue(info->netdev);
7968}
7969
7970/**
7971 * called by device driver when frame received
7972 * pass frame to network layer
7973 *
7974 * info pointer to device instance information
7975 * buf pointer to buffer contianing frame data
7976 * size count of data bytes in buf
7977 */
7978static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
7979{
7980 struct sk_buff *skb = dev_alloc_skb(size);
7981 struct net_device *dev = info->netdev;
1da177e4
LT		 7982
7983 if (debug_level >= DEBUG_LEVEL_INFO)
198191c4 7984 printk("hdlcdev_rx(%s)\n", dev->name);
1da177e4
LT		 7985
7986 if (skb == NULL) {
198191c4
KH		 7987 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7988 dev->name);
7989 dev->stats.rx_dropped++;
1da177e4
LT		 7990 return;
7991 }
7992
198191c4 7993 memcpy(skb_put(skb, size), buf, size);
1da177e4 7994
198191c4 7995 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4 7996
198191c4
KH		 7997 dev->stats.rx_packets++;
7998 dev->stats.rx_bytes += size;
1da177e4
LT		 7999
8000 netif_rx(skb);
1da177e4
LT		 8001}
8002
991990a1
KH		 8003static const struct net_device_ops hdlcdev_ops = {
8004 .ndo_open = hdlcdev_open,
8005 .ndo_stop = hdlcdev_close,
8006 .ndo_change_mtu = hdlc_change_mtu,
8007 .ndo_start_xmit = hdlc_start_xmit,
8008 .ndo_do_ioctl = hdlcdev_ioctl,
8009 .ndo_tx_timeout = hdlcdev_tx_timeout,
8010};
8011
1da177e4
LT		 8012/**
8013 * called by device driver when adding device instance
8014 * do generic HDLC initialization
8015 *
8016 * info pointer to device instance information
8017 *
8018 * returns 0 if success, otherwise error code
8019 */
8020static int hdlcdev_init(struct mgsl_struct *info)
8021{
8022 int rc;
8023 struct net_device *dev;
8024 hdlc_device *hdlc;
8025
8026 /* allocate and initialize network and HDLC layer objects */
8027
8028 if (!(dev = alloc_hdlcdev(info))) {
8029 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8030 return -ENOMEM;
8031 }
8032
8033 /* for network layer reporting purposes only */
8034 dev->base_addr = info->io_base;
8035 dev->irq = info->irq_level;
8036 dev->dma = info->dma_level;
8037
8038 /* network layer callbacks and settings */
991990a1
KH		 8039 dev->netdev_ops = &hdlcdev_ops;
8040 dev->watchdog_timeo = 10 * HZ;
1da177e4
LT		 8041 dev->tx_queue_len = 50;
8042
8043 /* generic HDLC layer callbacks and settings */
8044 hdlc = dev_to_hdlc(dev);
8045 hdlc->attach = hdlcdev_attach;
8046 hdlc->xmit = hdlcdev_xmit;
8047
8048 /* register objects with HDLC layer */
8049 if ((rc = register_hdlc_device(dev))) {
8050 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8051 free_netdev(dev);
8052 return rc;
8053 }
8054
8055 info->netdev = dev;
8056 return 0;
8057}
8058
8059/**
8060 * called by device driver when removing device instance
8061 * do generic HDLC cleanup
8062 *
8063 * info pointer to device instance information
8064 */
8065static void hdlcdev_exit(struct mgsl_struct *info)
8066{
8067 unregister_hdlc_device(info->netdev);
8068 free_netdev(info->netdev);
8069 info->netdev = NULL;
8070}
8071
8072#endif /* CONFIG_HDLC */
8073
8074
9671f099 8075static int synclink_init_one (struct pci_dev *dev,
1da177e4
LT		 8076 const struct pci_device_id *ent)
8077{
8078 struct mgsl_struct *info;
8079
8080 if (pci_enable_device(dev)) {
8081 printk("error enabling pci device %p\n", dev);
8082 return -EIO;
8083 }
8084
8085 if (!(info = mgsl_allocate_device())) {
8086 printk("can't allocate device instance data.\n");
8087 return -EIO;
8088 }
8089
8090 /* Copy user configuration info to device instance data */
8091
8092 info->io_base = pci_resource_start(dev, 2);
8093 info->irq_level = dev->irq;
8094 info->phys_memory_base = pci_resource_start(dev, 3);
8095
8096 /* Because veremap only works on page boundaries we must map
8097 * a larger area than is actually implemented for the LCR
8098 * memory range. We map a full page starting at the page boundary.
8099 */
8100 info->phys_lcr_base = pci_resource_start(dev, 0);
8101 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8102 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8103
8104 info->bus_type = MGSL_BUS_TYPE_PCI;
8105 info->io_addr_size = 8;
0f2ed4c6 8106 info->irq_flags = IRQF_SHARED;
1da177e4
LT		 8107
8108 if (dev->device == 0x0210) {
8109 /* Version 1 PCI9030 based universal PCI adapter */
8110 info->misc_ctrl_value = 0x007c4080;
8111 info->hw_version = 1;
8112 } else {
8113 /* Version 0 PCI9050 based 5V PCI adapter
8114 * A PCI9050 bug prevents reading LCR registers if
8115 * LCR base address bit 7 is set. Maintain shadow
8116 * value so we can write to LCR misc control reg.
8117 */
8118 info->misc_ctrl_value = 0x087e4546;
8119 info->hw_version = 0;
8120 }
8121
8122 mgsl_add_device(info);
8123
8124 return 0;
8125}
8126
ae8d8a14 8127static void synclink_remove_one (struct pci_dev *dev)
1da177e4
LT		 8128{
8129}
8130
kernel source for telekom puls (alcatel/mediatek)