Commit | Line | Data |
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1e6c9c28 | 1 | /* |
7192f92c | 2 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
3 | * Copyright (C) 2003 Rick Bronson |
4 | * | |
5 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
a6670615 CC |
8 | * DMA support added by Chip Coldwell. |
9 | * | |
1e6c9c28 AV |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
1e6c9c28 AV |
25 | #include <linux/module.h> |
26 | #include <linux/tty.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/serial.h> | |
afefc415 | 31 | #include <linux/clk.h> |
1e6c9c28 AV |
32 | #include <linux/console.h> |
33 | #include <linux/sysrq.h> | |
34 | #include <linux/tty_flip.h> | |
afefc415 | 35 | #include <linux/platform_device.h> |
5fbe46b6 NF |
36 | #include <linux/of.h> |
37 | #include <linux/of_device.h> | |
a6670615 | 38 | #include <linux/dma-mapping.h> |
93a3ddc2 | 39 | #include <linux/atmel_pdc.h> |
fa3218d8 | 40 | #include <linux/atmel_serial.h> |
e8faff73 | 41 | #include <linux/uaccess.h> |
784557de | 42 | #include <linux/pinctrl/consumer.h> |
1e6c9c28 AV |
43 | |
44 | #include <asm/io.h> | |
f7512e7c | 45 | #include <asm/ioctls.h> |
1e6c9c28 | 46 | |
afefc415 | 47 | #include <asm/mach/serial_at91.h> |
a09e64fb | 48 | #include <mach/board.h> |
93a3ddc2 | 49 | |
acca9b83 | 50 | #ifdef CONFIG_ARM |
a09e64fb | 51 | #include <mach/cpu.h> |
60e8972d | 52 | #include <asm/gpio.h> |
acca9b83 | 53 | #endif |
1e6c9c28 | 54 | |
a6670615 CC |
55 | #define PDC_BUFFER_SIZE 512 |
56 | /* Revisit: We should calculate this based on the actual port settings */ | |
57 | #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ | |
58 | ||
749c4e60 | 59 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
60 | #define SUPPORT_SYSRQ |
61 | #endif | |
62 | ||
63 | #include <linux/serial_core.h> | |
64 | ||
e8faff73 CS |
65 | static void atmel_start_rx(struct uart_port *port); |
66 | static void atmel_stop_rx(struct uart_port *port); | |
67 | ||
749c4e60 | 68 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
69 | |
70 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
71 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
72 | * UART. */ | |
7192f92c | 73 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 74 | #define MINOR_START 154 |
7192f92c | 75 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
76 | |
77 | #else | |
78 | ||
79 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
80 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 81 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 82 | #define MINOR_START 64 |
7192f92c | 83 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
84 | |
85 | #endif | |
86 | ||
7192f92c | 87 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 88 | |
b843aa21 | 89 | /* UART registers. CR is write-only, hence no GET macro */ |
544fc728 HS |
90 | #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) |
91 | #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) | |
92 | #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) | |
93 | #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) | |
94 | #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) | |
95 | #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) | |
96 | #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) | |
97 | #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) | |
98 | #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) | |
99 | #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) | |
100 | #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) | |
101 | #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) | |
e8faff73 | 102 | #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) |
544fc728 | 103 | |
1e6c9c28 | 104 | /* PDC registers */ |
544fc728 HS |
105 | #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) |
106 | #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) | |
107 | ||
108 | #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) | |
109 | #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) | |
110 | #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) | |
111 | #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) | |
112 | #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) | |
113 | ||
114 | #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) | |
115 | #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) | |
39d4c922 | 116 | #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) |
1e6c9c28 | 117 | |
71f2e2b8 HS |
118 | static int (*atmel_open_hook)(struct uart_port *); |
119 | static void (*atmel_close_hook)(struct uart_port *); | |
1e6c9c28 | 120 | |
a6670615 CC |
121 | struct atmel_dma_buffer { |
122 | unsigned char *buf; | |
123 | dma_addr_t dma_addr; | |
124 | unsigned int dma_size; | |
125 | unsigned int ofs; | |
126 | }; | |
127 | ||
1ecc26bd RB |
128 | struct atmel_uart_char { |
129 | u16 status; | |
130 | u16 ch; | |
131 | }; | |
132 | ||
133 | #define ATMEL_SERIAL_RINGSIZE 1024 | |
134 | ||
afefc415 AV |
135 | /* |
136 | * We wrap our port structure around the generic uart_port. | |
137 | */ | |
7192f92c | 138 | struct atmel_uart_port { |
afefc415 AV |
139 | struct uart_port uart; /* uart */ |
140 | struct clk *clk; /* uart clock */ | |
f05596db AS |
141 | int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ |
142 | u32 backup_imr; /* IMR saved during suspend */ | |
9e6077bd | 143 | int break_active; /* break being received */ |
1ecc26bd | 144 | |
a6670615 CC |
145 | short use_dma_rx; /* enable PDC receiver */ |
146 | short pdc_rx_idx; /* current PDC RX buffer */ | |
147 | struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ | |
148 | ||
149 | short use_dma_tx; /* enable PDC transmitter */ | |
150 | struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ | |
151 | ||
1ecc26bd RB |
152 | struct tasklet_struct tasklet; |
153 | unsigned int irq_status; | |
154 | unsigned int irq_status_prev; | |
155 | ||
156 | struct circ_buf rx_ring; | |
e8faff73 CS |
157 | |
158 | struct serial_rs485 rs485; /* rs485 settings */ | |
159 | unsigned int tx_done_mask; | |
afefc415 AV |
160 | }; |
161 | ||
7192f92c | 162 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
4cbf9f48 | 163 | static unsigned long atmel_ports_in_use; |
afefc415 | 164 | |
1e6c9c28 | 165 | #ifdef SUPPORT_SYSRQ |
7192f92c | 166 | static struct console atmel_console; |
1e6c9c28 AV |
167 | #endif |
168 | ||
5fbe46b6 NF |
169 | #if defined(CONFIG_OF) |
170 | static const struct of_device_id atmel_serial_dt_ids[] = { | |
171 | { .compatible = "atmel,at91rm9200-usart" }, | |
172 | { .compatible = "atmel,at91sam9260-usart" }, | |
173 | { /* sentinel */ } | |
174 | }; | |
175 | ||
176 | MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); | |
177 | #endif | |
178 | ||
c811ab8c HS |
179 | static inline struct atmel_uart_port * |
180 | to_atmel_uart_port(struct uart_port *uart) | |
181 | { | |
182 | return container_of(uart, struct atmel_uart_port, uart); | |
183 | } | |
184 | ||
a6670615 CC |
185 | #ifdef CONFIG_SERIAL_ATMEL_PDC |
186 | static bool atmel_use_dma_rx(struct uart_port *port) | |
187 | { | |
c811ab8c | 188 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
189 | |
190 | return atmel_port->use_dma_rx; | |
191 | } | |
192 | ||
193 | static bool atmel_use_dma_tx(struct uart_port *port) | |
194 | { | |
c811ab8c | 195 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
196 | |
197 | return atmel_port->use_dma_tx; | |
198 | } | |
199 | #else | |
200 | static bool atmel_use_dma_rx(struct uart_port *port) | |
201 | { | |
202 | return false; | |
203 | } | |
204 | ||
205 | static bool atmel_use_dma_tx(struct uart_port *port) | |
206 | { | |
207 | return false; | |
208 | } | |
209 | #endif | |
210 | ||
e8faff73 CS |
211 | /* Enable or disable the rs485 support */ |
212 | void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf) | |
213 | { | |
214 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
215 | unsigned int mode; | |
dbf1115d | 216 | unsigned long flags; |
e8faff73 | 217 | |
dbf1115d | 218 | spin_lock_irqsave(&port->lock, flags); |
e8faff73 CS |
219 | |
220 | /* Disable interrupts */ | |
221 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
222 | ||
223 | mode = UART_GET_MR(port); | |
224 | ||
225 | /* Resetting serial mode to RS232 (0x0) */ | |
226 | mode &= ~ATMEL_US_USMODE; | |
227 | ||
228 | atmel_port->rs485 = *rs485conf; | |
229 | ||
230 | if (rs485conf->flags & SER_RS485_ENABLED) { | |
231 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
232 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; | |
93f3350c | 233 | if ((rs485conf->delay_rts_after_send) > 0) |
1b633184 | 234 | UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); |
e8faff73 CS |
235 | mode |= ATMEL_US_USMODE_RS485; |
236 | } else { | |
237 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
238 | if (atmel_use_dma_tx(port)) | |
239 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | | |
240 | ATMEL_US_TXBUFE; | |
241 | else | |
242 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
243 | } | |
244 | UART_PUT_MR(port, mode); | |
245 | ||
246 | /* Enable interrupts */ | |
247 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
248 | ||
dbf1115d | 249 | spin_unlock_irqrestore(&port->lock, flags); |
e8faff73 CS |
250 | |
251 | } | |
252 | ||
1e6c9c28 AV |
253 | /* |
254 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
255 | */ | |
7192f92c | 256 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 257 | { |
7192f92c | 258 | return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; |
1e6c9c28 AV |
259 | } |
260 | ||
261 | /* | |
262 | * Set state of the modem control output lines | |
263 | */ | |
7192f92c | 264 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
265 | { |
266 | unsigned int control = 0; | |
afefc415 | 267 | unsigned int mode; |
e8faff73 | 268 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 269 | |
c2f5ccfb | 270 | #ifdef CONFIG_ARCH_AT91RM9200 |
79da7a61 | 271 | if (cpu_is_at91rm9200()) { |
afefc415 | 272 | /* |
b843aa21 RB |
273 | * AT91RM9200 Errata #39: RTS0 is not internally connected |
274 | * to PA21. We need to drive the pin manually. | |
afefc415 | 275 | */ |
72729910 | 276 | if (port->mapbase == AT91RM9200_BASE_US0) { |
afefc415 | 277 | if (mctrl & TIOCM_RTS) |
20e65276 | 278 | at91_set_gpio_value(AT91_PIN_PA21, 0); |
afefc415 | 279 | else |
20e65276 | 280 | at91_set_gpio_value(AT91_PIN_PA21, 1); |
afefc415 | 281 | } |
1e6c9c28 | 282 | } |
acca9b83 | 283 | #endif |
1e6c9c28 AV |
284 | |
285 | if (mctrl & TIOCM_RTS) | |
7192f92c | 286 | control |= ATMEL_US_RTSEN; |
1e6c9c28 | 287 | else |
7192f92c | 288 | control |= ATMEL_US_RTSDIS; |
1e6c9c28 AV |
289 | |
290 | if (mctrl & TIOCM_DTR) | |
7192f92c | 291 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 292 | else |
7192f92c | 293 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 294 | |
afefc415 AV |
295 | UART_PUT_CR(port, control); |
296 | ||
297 | /* Local loopback mode? */ | |
7192f92c | 298 | mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; |
afefc415 | 299 | if (mctrl & TIOCM_LOOP) |
7192f92c | 300 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 301 | else |
7192f92c | 302 | mode |= ATMEL_US_CHMODE_NORMAL; |
e8faff73 CS |
303 | |
304 | /* Resetting serial mode to RS232 (0x0) */ | |
305 | mode &= ~ATMEL_US_USMODE; | |
306 | ||
307 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) { | |
308 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
93f3350c | 309 | if ((atmel_port->rs485.delay_rts_after_send) > 0) |
1b633184 CS |
310 | UART_PUT_TTGR(port, |
311 | atmel_port->rs485.delay_rts_after_send); | |
e8faff73 CS |
312 | mode |= ATMEL_US_USMODE_RS485; |
313 | } else { | |
314 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
315 | } | |
afefc415 | 316 | UART_PUT_MR(port, mode); |
1e6c9c28 AV |
317 | } |
318 | ||
319 | /* | |
320 | * Get state of the modem control input lines | |
321 | */ | |
7192f92c | 322 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 AV |
323 | { |
324 | unsigned int status, ret = 0; | |
325 | ||
326 | status = UART_GET_CSR(port); | |
327 | ||
328 | /* | |
329 | * The control signals are active low. | |
330 | */ | |
7192f92c | 331 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 332 | ret |= TIOCM_CD; |
7192f92c | 333 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 334 | ret |= TIOCM_CTS; |
7192f92c | 335 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 336 | ret |= TIOCM_DSR; |
7192f92c | 337 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
338 | ret |= TIOCM_RI; |
339 | ||
340 | return ret; | |
341 | } | |
342 | ||
343 | /* | |
344 | * Stop transmitting. | |
345 | */ | |
7192f92c | 346 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 347 | { |
e8faff73 CS |
348 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
349 | ||
a6670615 CC |
350 | if (atmel_use_dma_tx(port)) { |
351 | /* disable PDC transmit */ | |
352 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
e8faff73 CS |
353 | } |
354 | /* Disable interrupts */ | |
355 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
356 | ||
83cac9f3 BR |
357 | if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && |
358 | !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 | 359 | atmel_start_rx(port); |
1e6c9c28 AV |
360 | } |
361 | ||
362 | /* | |
363 | * Start transmitting. | |
364 | */ | |
7192f92c | 365 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 366 | { |
e8faff73 CS |
367 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
368 | ||
a6670615 CC |
369 | if (atmel_use_dma_tx(port)) { |
370 | if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) | |
371 | /* The transmitter is already running. Yes, we | |
372 | really need this.*/ | |
373 | return; | |
374 | ||
83cac9f3 BR |
375 | if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && |
376 | !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 CS |
377 | atmel_stop_rx(port); |
378 | ||
a6670615 CC |
379 | /* re-enable PDC transmit */ |
380 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
e8faff73 CS |
381 | } |
382 | /* Enable interrupts */ | |
383 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
384 | } | |
385 | ||
386 | /* | |
387 | * start receiving - port is in process of being opened. | |
388 | */ | |
389 | static void atmel_start_rx(struct uart_port *port) | |
390 | { | |
391 | UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ | |
392 | ||
57c36868 SG |
393 | UART_PUT_CR(port, ATMEL_US_RXEN); |
394 | ||
e8faff73 CS |
395 | if (atmel_use_dma_rx(port)) { |
396 | /* enable PDC controller */ | |
397 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | | |
398 | port->read_status_mask); | |
399 | UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); | |
400 | } else { | |
401 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
402 | } | |
1e6c9c28 AV |
403 | } |
404 | ||
405 | /* | |
406 | * Stop receiving - port is in process of being closed. | |
407 | */ | |
7192f92c | 408 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 409 | { |
57c36868 SG |
410 | UART_PUT_CR(port, ATMEL_US_RXDIS); |
411 | ||
a6670615 CC |
412 | if (atmel_use_dma_rx(port)) { |
413 | /* disable PDC receive */ | |
414 | UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); | |
e8faff73 CS |
415 | UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | |
416 | port->read_status_mask); | |
417 | } else { | |
a6670615 | 418 | UART_PUT_IDR(port, ATMEL_US_RXRDY); |
e8faff73 | 419 | } |
1e6c9c28 AV |
420 | } |
421 | ||
422 | /* | |
423 | * Enable modem status interrupts | |
424 | */ | |
7192f92c | 425 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 426 | { |
b843aa21 RB |
427 | UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC |
428 | | ATMEL_US_DCDIC | ATMEL_US_CTSIC); | |
1e6c9c28 AV |
429 | } |
430 | ||
431 | /* | |
432 | * Control the transmission of a break signal | |
433 | */ | |
7192f92c | 434 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
435 | { |
436 | if (break_state != 0) | |
7192f92c | 437 | UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ |
1e6c9c28 | 438 | else |
7192f92c | 439 | UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ |
1e6c9c28 AV |
440 | } |
441 | ||
1ecc26bd RB |
442 | /* |
443 | * Stores the incoming character in the ring buffer | |
444 | */ | |
445 | static void | |
446 | atmel_buffer_rx_char(struct uart_port *port, unsigned int status, | |
447 | unsigned int ch) | |
448 | { | |
c811ab8c | 449 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
450 | struct circ_buf *ring = &atmel_port->rx_ring; |
451 | struct atmel_uart_char *c; | |
452 | ||
453 | if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) | |
454 | /* Buffer overflow, ignore char */ | |
455 | return; | |
456 | ||
457 | c = &((struct atmel_uart_char *)ring->buf)[ring->head]; | |
458 | c->status = status; | |
459 | c->ch = ch; | |
460 | ||
461 | /* Make sure the character is stored before we update head. */ | |
462 | smp_wmb(); | |
463 | ||
464 | ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
465 | } | |
466 | ||
a6670615 CC |
467 | /* |
468 | * Deal with parity, framing and overrun errors. | |
469 | */ | |
470 | static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) | |
471 | { | |
472 | /* clear error */ | |
473 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
474 | ||
475 | if (status & ATMEL_US_RXBRK) { | |
476 | /* ignore side-effect */ | |
477 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
478 | port->icount.brk++; | |
479 | } | |
480 | if (status & ATMEL_US_PARE) | |
481 | port->icount.parity++; | |
482 | if (status & ATMEL_US_FRAME) | |
483 | port->icount.frame++; | |
484 | if (status & ATMEL_US_OVRE) | |
485 | port->icount.overrun++; | |
486 | } | |
487 | ||
1e6c9c28 AV |
488 | /* |
489 | * Characters received (called from interrupt handler) | |
490 | */ | |
7d12e780 | 491 | static void atmel_rx_chars(struct uart_port *port) |
1e6c9c28 | 492 | { |
c811ab8c | 493 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 494 | unsigned int status, ch; |
1e6c9c28 | 495 | |
afefc415 | 496 | status = UART_GET_CSR(port); |
7192f92c | 497 | while (status & ATMEL_US_RXRDY) { |
1e6c9c28 AV |
498 | ch = UART_GET_CHAR(port); |
499 | ||
1e6c9c28 AV |
500 | /* |
501 | * note that the error handling code is | |
502 | * out of the main execution path | |
503 | */ | |
9e6077bd HS |
504 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME |
505 | | ATMEL_US_OVRE | ATMEL_US_RXBRK) | |
506 | || atmel_port->break_active)) { | |
1ecc26bd | 507 | |
b843aa21 RB |
508 | /* clear error */ |
509 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
1ecc26bd | 510 | |
9e6077bd HS |
511 | if (status & ATMEL_US_RXBRK |
512 | && !atmel_port->break_active) { | |
9e6077bd HS |
513 | atmel_port->break_active = 1; |
514 | UART_PUT_IER(port, ATMEL_US_RXBRK); | |
9e6077bd HS |
515 | } else { |
516 | /* | |
517 | * This is either the end-of-break | |
518 | * condition or we've received at | |
519 | * least one character without RXBRK | |
520 | * being set. In both cases, the next | |
521 | * RXBRK will indicate start-of-break. | |
522 | */ | |
523 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
524 | status &= ~ATMEL_US_RXBRK; | |
525 | atmel_port->break_active = 0; | |
afefc415 | 526 | } |
1e6c9c28 AV |
527 | } |
528 | ||
1ecc26bd | 529 | atmel_buffer_rx_char(port, status, ch); |
afefc415 | 530 | status = UART_GET_CSR(port); |
1e6c9c28 AV |
531 | } |
532 | ||
1ecc26bd | 533 | tasklet_schedule(&atmel_port->tasklet); |
1e6c9c28 AV |
534 | } |
535 | ||
536 | /* | |
1ecc26bd RB |
537 | * Transmit characters (called from tasklet with TXRDY interrupt |
538 | * disabled) | |
1e6c9c28 | 539 | */ |
7192f92c | 540 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 | 541 | { |
ebd2c8f6 | 542 | struct circ_buf *xmit = &port->state->xmit; |
e8faff73 | 543 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 544 | |
e8faff73 | 545 | if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { |
1e6c9c28 AV |
546 | UART_PUT_CHAR(port, port->x_char); |
547 | port->icount.tx++; | |
548 | port->x_char = 0; | |
1e6c9c28 | 549 | } |
1ecc26bd | 550 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
1e6c9c28 | 551 | return; |
1e6c9c28 | 552 | |
e8faff73 | 553 | while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { |
1e6c9c28 AV |
554 | UART_PUT_CHAR(port, xmit->buf[xmit->tail]); |
555 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
556 | port->icount.tx++; | |
557 | if (uart_circ_empty(xmit)) | |
558 | break; | |
559 | } | |
560 | ||
561 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
562 | uart_write_wakeup(port); | |
563 | ||
1ecc26bd | 564 | if (!uart_circ_empty(xmit)) |
e8faff73 CS |
565 | /* Enable interrupts */ |
566 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
1e6c9c28 AV |
567 | } |
568 | ||
b843aa21 RB |
569 | /* |
570 | * receive interrupt handler. | |
571 | */ | |
572 | static void | |
573 | atmel_handle_receive(struct uart_port *port, unsigned int pending) | |
574 | { | |
c811ab8c | 575 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
b843aa21 | 576 | |
a6670615 CC |
577 | if (atmel_use_dma_rx(port)) { |
578 | /* | |
579 | * PDC receive. Just schedule the tasklet and let it | |
580 | * figure out the details. | |
581 | * | |
582 | * TODO: We're not handling error flags correctly at | |
583 | * the moment. | |
584 | */ | |
585 | if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { | |
586 | UART_PUT_IDR(port, (ATMEL_US_ENDRX | |
587 | | ATMEL_US_TIMEOUT)); | |
588 | tasklet_schedule(&atmel_port->tasklet); | |
589 | } | |
590 | ||
591 | if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | | |
592 | ATMEL_US_FRAME | ATMEL_US_PARE)) | |
593 | atmel_pdc_rxerr(port, pending); | |
594 | } | |
595 | ||
b843aa21 RB |
596 | /* Interrupt receive */ |
597 | if (pending & ATMEL_US_RXRDY) | |
598 | atmel_rx_chars(port); | |
599 | else if (pending & ATMEL_US_RXBRK) { | |
600 | /* | |
601 | * End of break detected. If it came along with a | |
602 | * character, atmel_rx_chars will handle it. | |
603 | */ | |
604 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
605 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
606 | atmel_port->break_active = 0; | |
607 | } | |
608 | } | |
609 | ||
610 | /* | |
1ecc26bd | 611 | * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) |
b843aa21 RB |
612 | */ |
613 | static void | |
614 | atmel_handle_transmit(struct uart_port *port, unsigned int pending) | |
615 | { | |
c811ab8c | 616 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 617 | |
e8faff73 CS |
618 | if (pending & atmel_port->tx_done_mask) { |
619 | /* Either PDC or interrupt transmission */ | |
620 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
621 | tasklet_schedule(&atmel_port->tasklet); | |
1ecc26bd | 622 | } |
b843aa21 RB |
623 | } |
624 | ||
625 | /* | |
626 | * status flags interrupt handler. | |
627 | */ | |
628 | static void | |
629 | atmel_handle_status(struct uart_port *port, unsigned int pending, | |
630 | unsigned int status) | |
631 | { | |
c811ab8c | 632 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 633 | |
b843aa21 | 634 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC |
1ecc26bd RB |
635 | | ATMEL_US_CTSIC)) { |
636 | atmel_port->irq_status = status; | |
637 | tasklet_schedule(&atmel_port->tasklet); | |
638 | } | |
b843aa21 RB |
639 | } |
640 | ||
1e6c9c28 AV |
641 | /* |
642 | * Interrupt handler | |
643 | */ | |
7d12e780 | 644 | static irqreturn_t atmel_interrupt(int irq, void *dev_id) |
1e6c9c28 AV |
645 | { |
646 | struct uart_port *port = dev_id; | |
647 | unsigned int status, pending, pass_counter = 0; | |
648 | ||
a6670615 CC |
649 | do { |
650 | status = UART_GET_CSR(port); | |
651 | pending = status & UART_GET_IMR(port); | |
652 | if (!pending) | |
653 | break; | |
654 | ||
b843aa21 RB |
655 | atmel_handle_receive(port, pending); |
656 | atmel_handle_status(port, pending, status); | |
657 | atmel_handle_transmit(port, pending); | |
a6670615 | 658 | } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); |
afefc415 | 659 | |
0400b697 | 660 | return pass_counter ? IRQ_HANDLED : IRQ_NONE; |
a6670615 | 661 | } |
1e6c9c28 | 662 | |
a6670615 CC |
663 | /* |
664 | * Called from tasklet with ENDTX and TXBUFE interrupts disabled. | |
665 | */ | |
666 | static void atmel_tx_dma(struct uart_port *port) | |
667 | { | |
c811ab8c | 668 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 669 | struct circ_buf *xmit = &port->state->xmit; |
a6670615 CC |
670 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; |
671 | int count; | |
672 | ||
ba0657ff MT |
673 | /* nothing left to transmit? */ |
674 | if (UART_GET_TCR(port)) | |
675 | return; | |
676 | ||
a6670615 CC |
677 | xmit->tail += pdc->ofs; |
678 | xmit->tail &= UART_XMIT_SIZE - 1; | |
679 | ||
680 | port->icount.tx += pdc->ofs; | |
681 | pdc->ofs = 0; | |
682 | ||
ba0657ff | 683 | /* more to transmit - setup next transfer */ |
a6670615 | 684 | |
ba0657ff MT |
685 | /* disable PDC transmit */ |
686 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
687 | ||
1f14081d | 688 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { |
a6670615 CC |
689 | dma_sync_single_for_device(port->dev, |
690 | pdc->dma_addr, | |
691 | pdc->dma_size, | |
692 | DMA_TO_DEVICE); | |
693 | ||
694 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
695 | pdc->ofs = count; | |
696 | ||
697 | UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); | |
698 | UART_PUT_TCR(port, count); | |
e8faff73 | 699 | /* re-enable PDC transmit */ |
a6670615 | 700 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); |
e8faff73 CS |
701 | /* Enable interrupts */ |
702 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
703 | } else { | |
83cac9f3 BR |
704 | if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && |
705 | !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) { | |
e8faff73 CS |
706 | /* DMA done, stop TX, start RX for RS485 */ |
707 | atmel_start_rx(port); | |
708 | } | |
1e6c9c28 | 709 | } |
a6670615 CC |
710 | |
711 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
712 | uart_write_wakeup(port); | |
1e6c9c28 AV |
713 | } |
714 | ||
1ecc26bd RB |
715 | static void atmel_rx_from_ring(struct uart_port *port) |
716 | { | |
c811ab8c | 717 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
718 | struct circ_buf *ring = &atmel_port->rx_ring; |
719 | unsigned int flg; | |
720 | unsigned int status; | |
721 | ||
722 | while (ring->head != ring->tail) { | |
723 | struct atmel_uart_char c; | |
724 | ||
725 | /* Make sure c is loaded after head. */ | |
726 | smp_rmb(); | |
727 | ||
728 | c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; | |
729 | ||
730 | ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
731 | ||
732 | port->icount.rx++; | |
733 | status = c.status; | |
734 | flg = TTY_NORMAL; | |
735 | ||
736 | /* | |
737 | * note that the error handling code is | |
738 | * out of the main execution path | |
739 | */ | |
740 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | |
741 | | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { | |
742 | if (status & ATMEL_US_RXBRK) { | |
743 | /* ignore side-effect */ | |
744 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
745 | ||
746 | port->icount.brk++; | |
747 | if (uart_handle_break(port)) | |
748 | continue; | |
749 | } | |
750 | if (status & ATMEL_US_PARE) | |
751 | port->icount.parity++; | |
752 | if (status & ATMEL_US_FRAME) | |
753 | port->icount.frame++; | |
754 | if (status & ATMEL_US_OVRE) | |
755 | port->icount.overrun++; | |
756 | ||
757 | status &= port->read_status_mask; | |
758 | ||
759 | if (status & ATMEL_US_RXBRK) | |
760 | flg = TTY_BREAK; | |
761 | else if (status & ATMEL_US_PARE) | |
762 | flg = TTY_PARITY; | |
763 | else if (status & ATMEL_US_FRAME) | |
764 | flg = TTY_FRAME; | |
765 | } | |
766 | ||
767 | ||
768 | if (uart_handle_sysrq_char(port, c.ch)) | |
769 | continue; | |
770 | ||
771 | uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); | |
772 | } | |
773 | ||
774 | /* | |
775 | * Drop the lock here since it might end up calling | |
776 | * uart_start(), which takes the lock. | |
777 | */ | |
778 | spin_unlock(&port->lock); | |
ebd2c8f6 | 779 | tty_flip_buffer_push(port->state->port.tty); |
1ecc26bd RB |
780 | spin_lock(&port->lock); |
781 | } | |
782 | ||
a6670615 CC |
783 | static void atmel_rx_from_dma(struct uart_port *port) |
784 | { | |
c811ab8c | 785 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 786 | struct tty_struct *tty = port->state->port.tty; |
a6670615 CC |
787 | struct atmel_dma_buffer *pdc; |
788 | int rx_idx = atmel_port->pdc_rx_idx; | |
789 | unsigned int head; | |
790 | unsigned int tail; | |
791 | unsigned int count; | |
792 | ||
793 | do { | |
794 | /* Reset the UART timeout early so that we don't miss one */ | |
795 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
796 | ||
797 | pdc = &atmel_port->pdc_rx[rx_idx]; | |
798 | head = UART_GET_RPR(port) - pdc->dma_addr; | |
799 | tail = pdc->ofs; | |
800 | ||
801 | /* If the PDC has switched buffers, RPR won't contain | |
802 | * any address within the current buffer. Since head | |
803 | * is unsigned, we just need a one-way comparison to | |
804 | * find out. | |
805 | * | |
806 | * In this case, we just need to consume the entire | |
807 | * buffer and resubmit it for DMA. This will clear the | |
808 | * ENDRX bit as well, so that we can safely re-enable | |
809 | * all interrupts below. | |
810 | */ | |
811 | head = min(head, pdc->dma_size); | |
812 | ||
813 | if (likely(head != tail)) { | |
814 | dma_sync_single_for_cpu(port->dev, pdc->dma_addr, | |
815 | pdc->dma_size, DMA_FROM_DEVICE); | |
816 | ||
817 | /* | |
818 | * head will only wrap around when we recycle | |
819 | * the DMA buffer, and when that happens, we | |
820 | * explicitly set tail to 0. So head will | |
821 | * always be greater than tail. | |
822 | */ | |
823 | count = head - tail; | |
824 | ||
825 | tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count); | |
826 | ||
827 | dma_sync_single_for_device(port->dev, pdc->dma_addr, | |
828 | pdc->dma_size, DMA_FROM_DEVICE); | |
829 | ||
830 | port->icount.rx += count; | |
831 | pdc->ofs = head; | |
832 | } | |
833 | ||
834 | /* | |
835 | * If the current buffer is full, we need to check if | |
836 | * the next one contains any additional data. | |
837 | */ | |
838 | if (head >= pdc->dma_size) { | |
839 | pdc->ofs = 0; | |
840 | UART_PUT_RNPR(port, pdc->dma_addr); | |
841 | UART_PUT_RNCR(port, pdc->dma_size); | |
842 | ||
843 | rx_idx = !rx_idx; | |
844 | atmel_port->pdc_rx_idx = rx_idx; | |
845 | } | |
846 | } while (head >= pdc->dma_size); | |
847 | ||
848 | /* | |
849 | * Drop the lock here since it might end up calling | |
850 | * uart_start(), which takes the lock. | |
851 | */ | |
852 | spin_unlock(&port->lock); | |
853 | tty_flip_buffer_push(tty); | |
854 | spin_lock(&port->lock); | |
855 | ||
856 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
857 | } | |
858 | ||
1ecc26bd RB |
859 | /* |
860 | * tasklet handling tty stuff outside the interrupt handler. | |
861 | */ | |
862 | static void atmel_tasklet_func(unsigned long data) | |
863 | { | |
864 | struct uart_port *port = (struct uart_port *)data; | |
c811ab8c | 865 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
866 | unsigned int status; |
867 | unsigned int status_change; | |
868 | ||
869 | /* The interrupt handler does not take the lock */ | |
870 | spin_lock(&port->lock); | |
871 | ||
a6670615 CC |
872 | if (atmel_use_dma_tx(port)) |
873 | atmel_tx_dma(port); | |
874 | else | |
875 | atmel_tx_chars(port); | |
1ecc26bd RB |
876 | |
877 | status = atmel_port->irq_status; | |
878 | status_change = status ^ atmel_port->irq_status_prev; | |
879 | ||
880 | if (status_change & (ATMEL_US_RI | ATMEL_US_DSR | |
881 | | ATMEL_US_DCD | ATMEL_US_CTS)) { | |
882 | /* TODO: All reads to CSR will clear these interrupts! */ | |
883 | if (status_change & ATMEL_US_RI) | |
884 | port->icount.rng++; | |
885 | if (status_change & ATMEL_US_DSR) | |
886 | port->icount.dsr++; | |
887 | if (status_change & ATMEL_US_DCD) | |
888 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
889 | if (status_change & ATMEL_US_CTS) | |
890 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
891 | ||
bdc04e31 | 892 | wake_up_interruptible(&port->state->port.delta_msr_wait); |
1ecc26bd RB |
893 | |
894 | atmel_port->irq_status_prev = status; | |
895 | } | |
896 | ||
a6670615 CC |
897 | if (atmel_use_dma_rx(port)) |
898 | atmel_rx_from_dma(port); | |
899 | else | |
900 | atmel_rx_from_ring(port); | |
1ecc26bd RB |
901 | |
902 | spin_unlock(&port->lock); | |
903 | } | |
904 | ||
1e6c9c28 AV |
905 | /* |
906 | * Perform initialization and enable port for reception | |
907 | */ | |
7192f92c | 908 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 | 909 | { |
c811ab8c | 910 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 911 | struct tty_struct *tty = port->state->port.tty; |
1e6c9c28 AV |
912 | int retval; |
913 | ||
914 | /* | |
915 | * Ensure that no interrupts are enabled otherwise when | |
916 | * request_irq() is called we could get stuck trying to | |
917 | * handle an unexpected interrupt | |
918 | */ | |
919 | UART_PUT_IDR(port, -1); | |
920 | ||
921 | /* | |
922 | * Allocate the IRQ | |
923 | */ | |
b843aa21 | 924 | retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, |
ae161068 | 925 | tty ? tty->name : "atmel_serial", port); |
1e6c9c28 | 926 | if (retval) { |
7192f92c | 927 | printk("atmel_serial: atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
928 | return retval; |
929 | } | |
930 | ||
a6670615 CC |
931 | /* |
932 | * Initialize DMA (if necessary) | |
933 | */ | |
934 | if (atmel_use_dma_rx(port)) { | |
935 | int i; | |
936 | ||
937 | for (i = 0; i < 2; i++) { | |
938 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
939 | ||
940 | pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); | |
941 | if (pdc->buf == NULL) { | |
942 | if (i != 0) { | |
943 | dma_unmap_single(port->dev, | |
944 | atmel_port->pdc_rx[0].dma_addr, | |
945 | PDC_BUFFER_SIZE, | |
946 | DMA_FROM_DEVICE); | |
947 | kfree(atmel_port->pdc_rx[0].buf); | |
948 | } | |
949 | free_irq(port->irq, port); | |
950 | return -ENOMEM; | |
951 | } | |
952 | pdc->dma_addr = dma_map_single(port->dev, | |
953 | pdc->buf, | |
954 | PDC_BUFFER_SIZE, | |
955 | DMA_FROM_DEVICE); | |
956 | pdc->dma_size = PDC_BUFFER_SIZE; | |
957 | pdc->ofs = 0; | |
958 | } | |
959 | ||
960 | atmel_port->pdc_rx_idx = 0; | |
961 | ||
962 | UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); | |
963 | UART_PUT_RCR(port, PDC_BUFFER_SIZE); | |
964 | ||
965 | UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); | |
966 | UART_PUT_RNCR(port, PDC_BUFFER_SIZE); | |
967 | } | |
968 | if (atmel_use_dma_tx(port)) { | |
969 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
ebd2c8f6 | 970 | struct circ_buf *xmit = &port->state->xmit; |
a6670615 CC |
971 | |
972 | pdc->buf = xmit->buf; | |
973 | pdc->dma_addr = dma_map_single(port->dev, | |
974 | pdc->buf, | |
975 | UART_XMIT_SIZE, | |
976 | DMA_TO_DEVICE); | |
977 | pdc->dma_size = UART_XMIT_SIZE; | |
978 | pdc->ofs = 0; | |
979 | } | |
980 | ||
1e6c9c28 AV |
981 | /* |
982 | * If there is a specific "open" function (to register | |
983 | * control line interrupts) | |
984 | */ | |
71f2e2b8 HS |
985 | if (atmel_open_hook) { |
986 | retval = atmel_open_hook(port); | |
1e6c9c28 AV |
987 | if (retval) { |
988 | free_irq(port->irq, port); | |
989 | return retval; | |
990 | } | |
991 | } | |
992 | ||
27c0c8e5 AN |
993 | /* Save current CSR for comparison in atmel_tasklet_func() */ |
994 | atmel_port->irq_status_prev = UART_GET_CSR(port); | |
995 | atmel_port->irq_status = atmel_port->irq_status_prev; | |
996 | ||
1e6c9c28 AV |
997 | /* |
998 | * Finally, enable the serial port | |
999 | */ | |
7192f92c | 1000 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
b843aa21 RB |
1001 | /* enable xmit & rcvr */ |
1002 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
afefc415 | 1003 | |
a6670615 CC |
1004 | if (atmel_use_dma_rx(port)) { |
1005 | /* set UART timeout */ | |
1006 | UART_PUT_RTOR(port, PDC_RX_TIMEOUT); | |
1007 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
1008 | ||
1009 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
1010 | /* enable PDC controller */ | |
1011 | UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); | |
1012 | } else { | |
1013 | /* enable receive only */ | |
1014 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
1015 | } | |
afefc415 | 1016 | |
1e6c9c28 AV |
1017 | return 0; |
1018 | } | |
1019 | ||
1020 | /* | |
1021 | * Disable the port | |
1022 | */ | |
7192f92c | 1023 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 | 1024 | { |
c811ab8c | 1025 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
1026 | /* |
1027 | * Ensure everything is stopped. | |
1028 | */ | |
1029 | atmel_stop_rx(port); | |
1030 | atmel_stop_tx(port); | |
1031 | ||
1032 | /* | |
1033 | * Shut-down the DMA. | |
1034 | */ | |
1035 | if (atmel_use_dma_rx(port)) { | |
1036 | int i; | |
1037 | ||
1038 | for (i = 0; i < 2; i++) { | |
1039 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
1040 | ||
1041 | dma_unmap_single(port->dev, | |
1042 | pdc->dma_addr, | |
1043 | pdc->dma_size, | |
1044 | DMA_FROM_DEVICE); | |
1045 | kfree(pdc->buf); | |
1046 | } | |
1047 | } | |
1048 | if (atmel_use_dma_tx(port)) { | |
1049 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
1050 | ||
1051 | dma_unmap_single(port->dev, | |
1052 | pdc->dma_addr, | |
1053 | pdc->dma_size, | |
1054 | DMA_TO_DEVICE); | |
1055 | } | |
1056 | ||
1e6c9c28 AV |
1057 | /* |
1058 | * Disable all interrupts, port and break condition. | |
1059 | */ | |
7192f92c | 1060 | UART_PUT_CR(port, ATMEL_US_RSTSTA); |
1e6c9c28 AV |
1061 | UART_PUT_IDR(port, -1); |
1062 | ||
1063 | /* | |
1064 | * Free the interrupt | |
1065 | */ | |
1066 | free_irq(port->irq, port); | |
1067 | ||
1068 | /* | |
1069 | * If there is a specific "close" function (to unregister | |
1070 | * control line interrupts) | |
1071 | */ | |
71f2e2b8 HS |
1072 | if (atmel_close_hook) |
1073 | atmel_close_hook(port); | |
1e6c9c28 AV |
1074 | } |
1075 | ||
9afd561a HS |
1076 | /* |
1077 | * Flush any TX data submitted for DMA. Called when the TX circular | |
1078 | * buffer is reset. | |
1079 | */ | |
1080 | static void atmel_flush_buffer(struct uart_port *port) | |
1081 | { | |
1082 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1083 | ||
1084 | if (atmel_use_dma_tx(port)) { | |
1085 | UART_PUT_TCR(port, 0); | |
1086 | atmel_port->pdc_tx.ofs = 0; | |
1087 | } | |
1088 | } | |
1089 | ||
1e6c9c28 AV |
1090 | /* |
1091 | * Power / Clock management. | |
1092 | */ | |
b843aa21 RB |
1093 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, |
1094 | unsigned int oldstate) | |
1e6c9c28 | 1095 | { |
c811ab8c | 1096 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 1097 | |
1e6c9c28 | 1098 | switch (state) { |
b843aa21 RB |
1099 | case 0: |
1100 | /* | |
1101 | * Enable the peripheral clock for this serial port. | |
1102 | * This is called on uart_open() or a resume event. | |
1103 | */ | |
1104 | clk_enable(atmel_port->clk); | |
f05596db AS |
1105 | |
1106 | /* re-enable interrupts if we disabled some on suspend */ | |
1107 | UART_PUT_IER(port, atmel_port->backup_imr); | |
b843aa21 RB |
1108 | break; |
1109 | case 3: | |
f05596db AS |
1110 | /* Back up the interrupt mask and disable all interrupts */ |
1111 | atmel_port->backup_imr = UART_GET_IMR(port); | |
1112 | UART_PUT_IDR(port, -1); | |
1113 | ||
b843aa21 RB |
1114 | /* |
1115 | * Disable the peripheral clock for this serial port. | |
1116 | * This is called on uart_close() or a suspend event. | |
1117 | */ | |
1118 | clk_disable(atmel_port->clk); | |
1119 | break; | |
1120 | default: | |
1121 | printk(KERN_ERR "atmel_serial: unknown pm %d\n", state); | |
1e6c9c28 AV |
1122 | } |
1123 | } | |
1124 | ||
1125 | /* | |
1126 | * Change the port parameters | |
1127 | */ | |
b843aa21 RB |
1128 | static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, |
1129 | struct ktermios *old) | |
1e6c9c28 AV |
1130 | { |
1131 | unsigned long flags; | |
1132 | unsigned int mode, imr, quot, baud; | |
e8faff73 | 1133 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 1134 | |
03abeac0 | 1135 | /* Get current mode register */ |
b843aa21 | 1136 | mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL |
8e706c4d PM |
1137 | | ATMEL_US_NBSTOP | ATMEL_US_PAR |
1138 | | ATMEL_US_USMODE); | |
03abeac0 | 1139 | |
b843aa21 | 1140 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
1e6c9c28 AV |
1141 | quot = uart_get_divisor(port, baud); |
1142 | ||
b843aa21 | 1143 | if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ |
03abeac0 AV |
1144 | quot /= 8; |
1145 | mode |= ATMEL_US_USCLKS_MCK_DIV8; | |
1146 | } | |
1e6c9c28 AV |
1147 | |
1148 | /* byte size */ | |
1149 | switch (termios->c_cflag & CSIZE) { | |
1150 | case CS5: | |
7192f92c | 1151 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
1152 | break; |
1153 | case CS6: | |
7192f92c | 1154 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
1155 | break; |
1156 | case CS7: | |
7192f92c | 1157 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
1158 | break; |
1159 | default: | |
7192f92c | 1160 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
1161 | break; |
1162 | } | |
1163 | ||
1164 | /* stop bits */ | |
1165 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 1166 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
1167 | |
1168 | /* parity */ | |
1169 | if (termios->c_cflag & PARENB) { | |
b843aa21 RB |
1170 | /* Mark or Space parity */ |
1171 | if (termios->c_cflag & CMSPAR) { | |
1e6c9c28 | 1172 | if (termios->c_cflag & PARODD) |
7192f92c | 1173 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 1174 | else |
7192f92c | 1175 | mode |= ATMEL_US_PAR_SPACE; |
b843aa21 | 1176 | } else if (termios->c_cflag & PARODD) |
7192f92c | 1177 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 1178 | else |
7192f92c | 1179 | mode |= ATMEL_US_PAR_EVEN; |
b843aa21 | 1180 | } else |
7192f92c | 1181 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 | 1182 | |
8e706c4d PM |
1183 | /* hardware handshake (RTS/CTS) */ |
1184 | if (termios->c_cflag & CRTSCTS) | |
1185 | mode |= ATMEL_US_USMODE_HWHS; | |
1186 | else | |
1187 | mode |= ATMEL_US_USMODE_NORMAL; | |
1188 | ||
1e6c9c28 AV |
1189 | spin_lock_irqsave(&port->lock, flags); |
1190 | ||
7192f92c | 1191 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 1192 | if (termios->c_iflag & INPCK) |
7192f92c | 1193 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 1194 | if (termios->c_iflag & (BRKINT | PARMRK)) |
7192f92c | 1195 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 | 1196 | |
a6670615 CC |
1197 | if (atmel_use_dma_rx(port)) |
1198 | /* need to enable error interrupts */ | |
1199 | UART_PUT_IER(port, port->read_status_mask); | |
1200 | ||
1e6c9c28 AV |
1201 | /* |
1202 | * Characters to ignore | |
1203 | */ | |
1204 | port->ignore_status_mask = 0; | |
1205 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 1206 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 1207 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 1208 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
1209 | /* |
1210 | * If we're ignoring parity and break indicators, | |
1211 | * ignore overruns too (for real raw support). | |
1212 | */ | |
1213 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 1214 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 | 1215 | } |
b843aa21 | 1216 | /* TODO: Ignore all characters if CREAD is set.*/ |
1e6c9c28 AV |
1217 | |
1218 | /* update the per-port timeout */ | |
1219 | uart_update_timeout(port, termios->c_cflag, baud); | |
1220 | ||
0ccad870 HS |
1221 | /* |
1222 | * save/disable interrupts. The tty layer will ensure that the | |
1223 | * transmitter is empty if requested by the caller, so there's | |
1224 | * no need to wait for it here. | |
1225 | */ | |
b843aa21 RB |
1226 | imr = UART_GET_IMR(port); |
1227 | UART_PUT_IDR(port, -1); | |
1e6c9c28 AV |
1228 | |
1229 | /* disable receiver and transmitter */ | |
7192f92c | 1230 | UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 | 1231 | |
e8faff73 CS |
1232 | /* Resetting serial mode to RS232 (0x0) */ |
1233 | mode &= ~ATMEL_US_USMODE; | |
1234 | ||
1235 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) { | |
1236 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
93f3350c | 1237 | if ((atmel_port->rs485.delay_rts_after_send) > 0) |
1b633184 CS |
1238 | UART_PUT_TTGR(port, |
1239 | atmel_port->rs485.delay_rts_after_send); | |
e8faff73 CS |
1240 | mode |= ATMEL_US_USMODE_RS485; |
1241 | } else { | |
1242 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
1243 | } | |
1244 | ||
1e6c9c28 AV |
1245 | /* set the parity, stop bits and data size */ |
1246 | UART_PUT_MR(port, mode); | |
1247 | ||
1248 | /* set the baud rate */ | |
1249 | UART_PUT_BRGR(port, quot); | |
7192f92c HS |
1250 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
1251 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
1252 | |
1253 | /* restore interrupts */ | |
1254 | UART_PUT_IER(port, imr); | |
1255 | ||
1256 | /* CTS flow-control and modem-status interrupts */ | |
1257 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1258 | port->ops->enable_ms(port); | |
1259 | ||
1260 | spin_unlock_irqrestore(&port->lock, flags); | |
1261 | } | |
1262 | ||
42bd7a4f VP |
1263 | static void atmel_set_ldisc(struct uart_port *port, int new) |
1264 | { | |
b54bf3b2 | 1265 | if (new == N_PPS) { |
42bd7a4f VP |
1266 | port->flags |= UPF_HARDPPS_CD; |
1267 | atmel_enable_ms(port); | |
1268 | } else { | |
1269 | port->flags &= ~UPF_HARDPPS_CD; | |
1270 | } | |
1271 | } | |
1272 | ||
1e6c9c28 AV |
1273 | /* |
1274 | * Return string describing the specified port | |
1275 | */ | |
7192f92c | 1276 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 1277 | { |
9ab4f88b | 1278 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
1279 | } |
1280 | ||
1281 | /* | |
1282 | * Release the memory region(s) being used by 'port'. | |
1283 | */ | |
7192f92c | 1284 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 1285 | { |
afefc415 AV |
1286 | struct platform_device *pdev = to_platform_device(port->dev); |
1287 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
1288 | ||
1289 | release_mem_region(port->mapbase, size); | |
1290 | ||
1291 | if (port->flags & UPF_IOREMAP) { | |
1292 | iounmap(port->membase); | |
1293 | port->membase = NULL; | |
1294 | } | |
1e6c9c28 AV |
1295 | } |
1296 | ||
1297 | /* | |
1298 | * Request the memory region(s) being used by 'port'. | |
1299 | */ | |
7192f92c | 1300 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 1301 | { |
afefc415 AV |
1302 | struct platform_device *pdev = to_platform_device(port->dev); |
1303 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
1304 | ||
7192f92c | 1305 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
1306 | return -EBUSY; |
1307 | ||
1308 | if (port->flags & UPF_IOREMAP) { | |
1309 | port->membase = ioremap(port->mapbase, size); | |
1310 | if (port->membase == NULL) { | |
1311 | release_mem_region(port->mapbase, size); | |
1312 | return -ENOMEM; | |
1313 | } | |
1314 | } | |
1e6c9c28 | 1315 | |
afefc415 | 1316 | return 0; |
1e6c9c28 AV |
1317 | } |
1318 | ||
1319 | /* | |
1320 | * Configure/autoconfigure the port. | |
1321 | */ | |
7192f92c | 1322 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
1323 | { |
1324 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 1325 | port->type = PORT_ATMEL; |
7192f92c | 1326 | atmel_request_port(port); |
1e6c9c28 AV |
1327 | } |
1328 | } | |
1329 | ||
1330 | /* | |
1331 | * Verify the new serial_struct (for TIOCSSERIAL). | |
1332 | */ | |
7192f92c | 1333 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
1334 | { |
1335 | int ret = 0; | |
9ab4f88b | 1336 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
1337 | ret = -EINVAL; |
1338 | if (port->irq != ser->irq) | |
1339 | ret = -EINVAL; | |
1340 | if (ser->io_type != SERIAL_IO_MEM) | |
1341 | ret = -EINVAL; | |
1342 | if (port->uartclk / 16 != ser->baud_base) | |
1343 | ret = -EINVAL; | |
1344 | if ((void *)port->mapbase != ser->iomem_base) | |
1345 | ret = -EINVAL; | |
1346 | if (port->iobase != ser->port) | |
1347 | ret = -EINVAL; | |
1348 | if (ser->hub6 != 0) | |
1349 | ret = -EINVAL; | |
1350 | return ret; | |
1351 | } | |
1352 | ||
8fe2d541 AT |
1353 | #ifdef CONFIG_CONSOLE_POLL |
1354 | static int atmel_poll_get_char(struct uart_port *port) | |
1355 | { | |
1356 | while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) | |
1357 | cpu_relax(); | |
1358 | ||
1359 | return UART_GET_CHAR(port); | |
1360 | } | |
1361 | ||
1362 | static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) | |
1363 | { | |
1364 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) | |
1365 | cpu_relax(); | |
1366 | ||
1367 | UART_PUT_CHAR(port, ch); | |
1368 | } | |
1369 | #endif | |
1370 | ||
e8faff73 CS |
1371 | static int |
1372 | atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg) | |
1373 | { | |
1374 | struct serial_rs485 rs485conf; | |
1375 | ||
1376 | switch (cmd) { | |
1377 | case TIOCSRS485: | |
1378 | if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg, | |
1379 | sizeof(rs485conf))) | |
1380 | return -EFAULT; | |
1381 | ||
1382 | atmel_config_rs485(port, &rs485conf); | |
1383 | break; | |
1384 | ||
1385 | case TIOCGRS485: | |
1386 | if (copy_to_user((struct serial_rs485 *) arg, | |
1387 | &(to_atmel_uart_port(port)->rs485), | |
1388 | sizeof(rs485conf))) | |
1389 | return -EFAULT; | |
1390 | break; | |
1391 | ||
1392 | default: | |
1393 | return -ENOIOCTLCMD; | |
1394 | } | |
1395 | return 0; | |
1396 | } | |
1397 | ||
1398 | ||
1399 | ||
7192f92c HS |
1400 | static struct uart_ops atmel_pops = { |
1401 | .tx_empty = atmel_tx_empty, | |
1402 | .set_mctrl = atmel_set_mctrl, | |
1403 | .get_mctrl = atmel_get_mctrl, | |
1404 | .stop_tx = atmel_stop_tx, | |
1405 | .start_tx = atmel_start_tx, | |
1406 | .stop_rx = atmel_stop_rx, | |
1407 | .enable_ms = atmel_enable_ms, | |
1408 | .break_ctl = atmel_break_ctl, | |
1409 | .startup = atmel_startup, | |
1410 | .shutdown = atmel_shutdown, | |
9afd561a | 1411 | .flush_buffer = atmel_flush_buffer, |
7192f92c | 1412 | .set_termios = atmel_set_termios, |
42bd7a4f | 1413 | .set_ldisc = atmel_set_ldisc, |
7192f92c HS |
1414 | .type = atmel_type, |
1415 | .release_port = atmel_release_port, | |
1416 | .request_port = atmel_request_port, | |
1417 | .config_port = atmel_config_port, | |
1418 | .verify_port = atmel_verify_port, | |
1419 | .pm = atmel_serial_pm, | |
e8faff73 | 1420 | .ioctl = atmel_ioctl, |
8fe2d541 AT |
1421 | #ifdef CONFIG_CONSOLE_POLL |
1422 | .poll_get_char = atmel_poll_get_char, | |
1423 | .poll_put_char = atmel_poll_put_char, | |
1424 | #endif | |
1e6c9c28 AV |
1425 | }; |
1426 | ||
5fbe46b6 NF |
1427 | static void __devinit atmel_of_init_port(struct atmel_uart_port *atmel_port, |
1428 | struct device_node *np) | |
1429 | { | |
1430 | u32 rs485_delay[2]; | |
1431 | ||
1432 | /* DMA/PDC usage specification */ | |
1433 | if (of_get_property(np, "atmel,use-dma-rx", NULL)) | |
1434 | atmel_port->use_dma_rx = 1; | |
1435 | else | |
1436 | atmel_port->use_dma_rx = 0; | |
1437 | if (of_get_property(np, "atmel,use-dma-tx", NULL)) | |
1438 | atmel_port->use_dma_tx = 1; | |
1439 | else | |
1440 | atmel_port->use_dma_tx = 0; | |
1441 | ||
1442 | /* rs485 properties */ | |
1443 | if (of_property_read_u32_array(np, "rs485-rts-delay", | |
1444 | rs485_delay, 2) == 0) { | |
1445 | struct serial_rs485 *rs485conf = &atmel_port->rs485; | |
1446 | ||
1447 | rs485conf->delay_rts_before_send = rs485_delay[0]; | |
1448 | rs485conf->delay_rts_after_send = rs485_delay[1]; | |
1449 | rs485conf->flags = 0; | |
1450 | ||
5fbe46b6 NF |
1451 | if (of_get_property(np, "rs485-rx-during-tx", NULL)) |
1452 | rs485conf->flags |= SER_RS485_RX_DURING_TX; | |
1453 | ||
1454 | if (of_get_property(np, "linux,rs485-enabled-at-boot-time", NULL)) | |
1455 | rs485conf->flags |= SER_RS485_ENABLED; | |
1456 | } | |
1457 | } | |
1458 | ||
afefc415 AV |
1459 | /* |
1460 | * Configure the port from the platform device resource info. | |
1461 | */ | |
b843aa21 RB |
1462 | static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, |
1463 | struct platform_device *pdev) | |
1e6c9c28 | 1464 | { |
7192f92c | 1465 | struct uart_port *port = &atmel_port->uart; |
1acfc7ec | 1466 | struct atmel_uart_data *pdata = pdev->dev.platform_data; |
afefc415 | 1467 | |
5fbe46b6 NF |
1468 | if (pdev->dev.of_node) { |
1469 | atmel_of_init_port(atmel_port, pdev->dev.of_node); | |
1470 | } else { | |
1471 | atmel_port->use_dma_rx = pdata->use_dma_rx; | |
1472 | atmel_port->use_dma_tx = pdata->use_dma_tx; | |
1473 | atmel_port->rs485 = pdata->rs485; | |
1474 | } | |
afefc415 | 1475 | |
e8faff73 CS |
1476 | port->iotype = UPIO_MEM; |
1477 | port->flags = UPF_BOOT_AUTOCONF; | |
1478 | port->ops = &atmel_pops; | |
1479 | port->fifosize = 1; | |
e8faff73 | 1480 | port->dev = &pdev->dev; |
afefc415 AV |
1481 | port->mapbase = pdev->resource[0].start; |
1482 | port->irq = pdev->resource[1].start; | |
1483 | ||
1ecc26bd RB |
1484 | tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, |
1485 | (unsigned long)port); | |
1486 | ||
1487 | memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); | |
1488 | ||
5fbe46b6 | 1489 | if (pdata && pdata->regs) { |
75d35213 | 1490 | /* Already mapped by setup code */ |
1acfc7ec | 1491 | port->membase = pdata->regs; |
588edbf3 | 1492 | } else { |
afefc415 AV |
1493 | port->flags |= UPF_IOREMAP; |
1494 | port->membase = NULL; | |
1495 | } | |
1e6c9c28 | 1496 | |
b843aa21 RB |
1497 | /* for console, the clock could already be configured */ |
1498 | if (!atmel_port->clk) { | |
7192f92c HS |
1499 | atmel_port->clk = clk_get(&pdev->dev, "usart"); |
1500 | clk_enable(atmel_port->clk); | |
1501 | port->uartclk = clk_get_rate(atmel_port->clk); | |
06a7f058 DB |
1502 | clk_disable(atmel_port->clk); |
1503 | /* only enable clock when USART is in use */ | |
afefc415 | 1504 | } |
a6670615 | 1505 | |
e8faff73 CS |
1506 | /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ |
1507 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) | |
1508 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; | |
1509 | else if (atmel_use_dma_tx(port)) { | |
a6670615 | 1510 | port->fifosize = PDC_BUFFER_SIZE; |
e8faff73 CS |
1511 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; |
1512 | } else { | |
1513 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
1514 | } | |
1e6c9c28 AV |
1515 | } |
1516 | ||
afefc415 AV |
1517 | /* |
1518 | * Register board-specific modem-control line handlers. | |
1519 | */ | |
71f2e2b8 | 1520 | void __init atmel_register_uart_fns(struct atmel_port_fns *fns) |
1e6c9c28 AV |
1521 | { |
1522 | if (fns->enable_ms) | |
7192f92c | 1523 | atmel_pops.enable_ms = fns->enable_ms; |
1e6c9c28 | 1524 | if (fns->get_mctrl) |
7192f92c | 1525 | atmel_pops.get_mctrl = fns->get_mctrl; |
1e6c9c28 | 1526 | if (fns->set_mctrl) |
7192f92c | 1527 | atmel_pops.set_mctrl = fns->set_mctrl; |
71f2e2b8 HS |
1528 | atmel_open_hook = fns->open; |
1529 | atmel_close_hook = fns->close; | |
7192f92c HS |
1530 | atmel_pops.pm = fns->pm; |
1531 | atmel_pops.set_wake = fns->set_wake; | |
1e6c9c28 AV |
1532 | } |
1533 | ||
69f6a27b JCPV |
1534 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
1535 | ||
749c4e60 | 1536 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 1537 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 1538 | { |
7192f92c | 1539 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) |
829dd811 | 1540 | cpu_relax(); |
d358788f RK |
1541 | UART_PUT_CHAR(port, ch); |
1542 | } | |
1e6c9c28 AV |
1543 | |
1544 | /* | |
1545 | * Interrupts are disabled on entering | |
1546 | */ | |
7192f92c | 1547 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 1548 | { |
7192f92c | 1549 | struct uart_port *port = &atmel_ports[co->index].uart; |
e8faff73 | 1550 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
d358788f | 1551 | unsigned int status, imr; |
39d4c922 | 1552 | unsigned int pdc_tx; |
1e6c9c28 AV |
1553 | |
1554 | /* | |
b843aa21 | 1555 | * First, save IMR and then disable interrupts |
1e6c9c28 | 1556 | */ |
b843aa21 | 1557 | imr = UART_GET_IMR(port); |
e8faff73 | 1558 | UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); |
1e6c9c28 | 1559 | |
39d4c922 MP |
1560 | /* Store PDC transmit status and disable it */ |
1561 | pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; | |
1562 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
1563 | ||
7192f92c | 1564 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
1565 | |
1566 | /* | |
b843aa21 RB |
1567 | * Finally, wait for transmitter to become empty |
1568 | * and restore IMR | |
1e6c9c28 AV |
1569 | */ |
1570 | do { | |
1571 | status = UART_GET_CSR(port); | |
7192f92c | 1572 | } while (!(status & ATMEL_US_TXRDY)); |
39d4c922 MP |
1573 | |
1574 | /* Restore PDC transmit status */ | |
1575 | if (pdc_tx) | |
1576 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
1577 | ||
b843aa21 RB |
1578 | /* set interrupts back the way they were */ |
1579 | UART_PUT_IER(port, imr); | |
1e6c9c28 AV |
1580 | } |
1581 | ||
1582 | /* | |
b843aa21 RB |
1583 | * If the port was already initialised (eg, by a boot loader), |
1584 | * try to determine the current setup. | |
1e6c9c28 | 1585 | */ |
b843aa21 RB |
1586 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, |
1587 | int *parity, int *bits) | |
1e6c9c28 AV |
1588 | { |
1589 | unsigned int mr, quot; | |
1590 | ||
1c0fd82f HS |
1591 | /* |
1592 | * If the baud rate generator isn't running, the port wasn't | |
1593 | * initialized by the boot loader. | |
1594 | */ | |
9c81c5c9 | 1595 | quot = UART_GET_BRGR(port) & ATMEL_US_CD; |
1c0fd82f HS |
1596 | if (!quot) |
1597 | return; | |
1e6c9c28 | 1598 | |
7192f92c HS |
1599 | mr = UART_GET_MR(port) & ATMEL_US_CHRL; |
1600 | if (mr == ATMEL_US_CHRL_8) | |
1e6c9c28 AV |
1601 | *bits = 8; |
1602 | else | |
1603 | *bits = 7; | |
1604 | ||
7192f92c HS |
1605 | mr = UART_GET_MR(port) & ATMEL_US_PAR; |
1606 | if (mr == ATMEL_US_PAR_EVEN) | |
1e6c9c28 | 1607 | *parity = 'e'; |
7192f92c | 1608 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
1609 | *parity = 'o'; |
1610 | ||
4d5e392c HS |
1611 | /* |
1612 | * The serial core only rounds down when matching this to a | |
1613 | * supported baud rate. Make sure we don't end up slightly | |
1614 | * lower than one of those, as it would make us fall through | |
1615 | * to a much lower baud rate than we really want. | |
1616 | */ | |
4d5e392c | 1617 | *baud = port->uartclk / (16 * (quot - 1)); |
1e6c9c28 AV |
1618 | } |
1619 | ||
7192f92c | 1620 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 1621 | { |
7192f92c | 1622 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
1623 | int baud = 115200; |
1624 | int bits = 8; | |
1625 | int parity = 'n'; | |
1626 | int flow = 'n'; | |
1627 | ||
b843aa21 RB |
1628 | if (port->membase == NULL) { |
1629 | /* Port not initialized yet - delay setup */ | |
afefc415 | 1630 | return -ENODEV; |
b843aa21 | 1631 | } |
1e6c9c28 | 1632 | |
06a7f058 DB |
1633 | clk_enable(atmel_ports[co->index].clk); |
1634 | ||
b843aa21 | 1635 | UART_PUT_IDR(port, -1); |
7192f92c HS |
1636 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
1637 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
1638 | |
1639 | if (options) | |
1640 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1641 | else | |
7192f92c | 1642 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
1643 | |
1644 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1645 | } | |
1646 | ||
7192f92c | 1647 | static struct uart_driver atmel_uart; |
1e6c9c28 | 1648 | |
7192f92c HS |
1649 | static struct console atmel_console = { |
1650 | .name = ATMEL_DEVICENAME, | |
1651 | .write = atmel_console_write, | |
1e6c9c28 | 1652 | .device = uart_console_device, |
7192f92c | 1653 | .setup = atmel_console_setup, |
1e6c9c28 AV |
1654 | .flags = CON_PRINTBUFFER, |
1655 | .index = -1, | |
7192f92c | 1656 | .data = &atmel_uart, |
1e6c9c28 AV |
1657 | }; |
1658 | ||
06a7f058 | 1659 | #define ATMEL_CONSOLE_DEVICE (&atmel_console) |
1e6c9c28 | 1660 | |
afefc415 AV |
1661 | /* |
1662 | * Early console initialization (before VM subsystem initialized). | |
1663 | */ | |
7192f92c | 1664 | static int __init atmel_console_init(void) |
1e6c9c28 | 1665 | { |
73e2798b | 1666 | if (atmel_default_console_device) { |
0d0a3cc1 VN |
1667 | struct atmel_uart_data *pdata = |
1668 | atmel_default_console_device->dev.platform_data; | |
efb8d21b | 1669 | int id = pdata->num; |
4cbf9f48 NF |
1670 | struct atmel_uart_port *port = &atmel_ports[id]; |
1671 | ||
4cbf9f48 NF |
1672 | port->backup_imr = 0; |
1673 | port->uart.line = id; | |
0d0a3cc1 | 1674 | |
4cbf9f48 NF |
1675 | add_preferred_console(ATMEL_DEVICENAME, id, NULL); |
1676 | atmel_init_port(port, atmel_default_console_device); | |
7192f92c | 1677 | register_console(&atmel_console); |
afefc415 | 1678 | } |
1e6c9c28 | 1679 | |
1e6c9c28 AV |
1680 | return 0; |
1681 | } | |
b843aa21 | 1682 | |
7192f92c | 1683 | console_initcall(atmel_console_init); |
1e6c9c28 | 1684 | |
afefc415 AV |
1685 | /* |
1686 | * Late console initialization. | |
1687 | */ | |
7192f92c | 1688 | static int __init atmel_late_console_init(void) |
afefc415 | 1689 | { |
b843aa21 RB |
1690 | if (atmel_default_console_device |
1691 | && !(atmel_console.flags & CON_ENABLED)) | |
7192f92c | 1692 | register_console(&atmel_console); |
afefc415 AV |
1693 | |
1694 | return 0; | |
1695 | } | |
b843aa21 | 1696 | |
7192f92c | 1697 | core_initcall(atmel_late_console_init); |
afefc415 | 1698 | |
dfa7f343 HS |
1699 | static inline bool atmel_is_console_port(struct uart_port *port) |
1700 | { | |
1701 | return port->cons && port->cons->index == port->line; | |
1702 | } | |
1703 | ||
1e6c9c28 | 1704 | #else |
7192f92c | 1705 | #define ATMEL_CONSOLE_DEVICE NULL |
dfa7f343 HS |
1706 | |
1707 | static inline bool atmel_is_console_port(struct uart_port *port) | |
1708 | { | |
1709 | return false; | |
1710 | } | |
1e6c9c28 AV |
1711 | #endif |
1712 | ||
7192f92c | 1713 | static struct uart_driver atmel_uart = { |
b843aa21 RB |
1714 | .owner = THIS_MODULE, |
1715 | .driver_name = "atmel_serial", | |
1716 | .dev_name = ATMEL_DEVICENAME, | |
1717 | .major = SERIAL_ATMEL_MAJOR, | |
1718 | .minor = MINOR_START, | |
1719 | .nr = ATMEL_MAX_UART, | |
1720 | .cons = ATMEL_CONSOLE_DEVICE, | |
1e6c9c28 AV |
1721 | }; |
1722 | ||
afefc415 | 1723 | #ifdef CONFIG_PM |
f826caa4 HS |
1724 | static bool atmel_serial_clk_will_stop(void) |
1725 | { | |
1726 | #ifdef CONFIG_ARCH_AT91 | |
1727 | return at91_suspend_entering_slow_clock(); | |
1728 | #else | |
1729 | return false; | |
1730 | #endif | |
1731 | } | |
1732 | ||
b843aa21 RB |
1733 | static int atmel_serial_suspend(struct platform_device *pdev, |
1734 | pm_message_t state) | |
1e6c9c28 | 1735 | { |
afefc415 | 1736 | struct uart_port *port = platform_get_drvdata(pdev); |
c811ab8c | 1737 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 1738 | |
e1c609ef HS |
1739 | if (atmel_is_console_port(port) && console_suspend_enabled) { |
1740 | /* Drain the TX shifter */ | |
1741 | while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) | |
1742 | cpu_relax(); | |
1743 | } | |
1744 | ||
f05596db AS |
1745 | /* we can not wake up if we're running on slow clock */ |
1746 | atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); | |
1747 | if (atmel_serial_clk_will_stop()) | |
1748 | device_set_wakeup_enable(&pdev->dev, 0); | |
1749 | ||
1750 | uart_suspend_port(&atmel_uart, port); | |
1e6c9c28 | 1751 | |
afefc415 AV |
1752 | return 0; |
1753 | } | |
1e6c9c28 | 1754 | |
7192f92c | 1755 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
1756 | { |
1757 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 1758 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 1759 | |
f05596db AS |
1760 | uart_resume_port(&atmel_uart, port); |
1761 | device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); | |
1e6c9c28 AV |
1762 | |
1763 | return 0; | |
1764 | } | |
afefc415 | 1765 | #else |
7192f92c HS |
1766 | #define atmel_serial_suspend NULL |
1767 | #define atmel_serial_resume NULL | |
afefc415 | 1768 | #endif |
1e6c9c28 | 1769 | |
7192f92c | 1770 | static int __devinit atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 1771 | { |
7192f92c | 1772 | struct atmel_uart_port *port; |
5fbe46b6 | 1773 | struct device_node *np = pdev->dev.of_node; |
deba1a0d | 1774 | struct atmel_uart_data *pdata = pdev->dev.platform_data; |
1ecc26bd | 1775 | void *data; |
4cbf9f48 | 1776 | int ret = -ENODEV; |
784557de | 1777 | struct pinctrl *pinctrl; |
1e6c9c28 | 1778 | |
9d09daf8 | 1779 | BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); |
1ecc26bd | 1780 | |
5fbe46b6 NF |
1781 | if (np) |
1782 | ret = of_alias_get_id(np, "serial"); | |
1783 | else | |
1784 | if (pdata) | |
1785 | ret = pdata->num; | |
4cbf9f48 NF |
1786 | |
1787 | if (ret < 0) | |
5fbe46b6 | 1788 | /* port id not found in platform data nor device-tree aliases: |
4cbf9f48 NF |
1789 | * auto-enumerate it */ |
1790 | ret = find_first_zero_bit(&atmel_ports_in_use, | |
1791 | sizeof(atmel_ports_in_use)); | |
1792 | ||
1793 | if (ret > ATMEL_MAX_UART) { | |
1794 | ret = -ENODEV; | |
1795 | goto err; | |
1796 | } | |
1797 | ||
1798 | if (test_and_set_bit(ret, &atmel_ports_in_use)) { | |
1799 | /* port already in use */ | |
1800 | ret = -EBUSY; | |
1801 | goto err; | |
1802 | } | |
1803 | ||
1804 | port = &atmel_ports[ret]; | |
f05596db | 1805 | port->backup_imr = 0; |
4cbf9f48 | 1806 | port->uart.line = ret; |
f05596db | 1807 | |
7192f92c | 1808 | atmel_init_port(port, pdev); |
1e6c9c28 | 1809 | |
784557de JCPV |
1810 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1811 | if (IS_ERR(pinctrl)) { | |
1812 | ret = PTR_ERR(pinctrl); | |
1813 | goto err; | |
1814 | } | |
1815 | ||
a6670615 CC |
1816 | if (!atmel_use_dma_rx(&port->uart)) { |
1817 | ret = -ENOMEM; | |
6433471d HS |
1818 | data = kmalloc(sizeof(struct atmel_uart_char) |
1819 | * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); | |
a6670615 CC |
1820 | if (!data) |
1821 | goto err_alloc_ring; | |
1822 | port->rx_ring.buf = data; | |
1823 | } | |
1ecc26bd | 1824 | |
7192f92c | 1825 | ret = uart_add_one_port(&atmel_uart, &port->uart); |
dfa7f343 HS |
1826 | if (ret) |
1827 | goto err_add_port; | |
1828 | ||
8da14b5f | 1829 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
06a7f058 DB |
1830 | if (atmel_is_console_port(&port->uart) |
1831 | && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { | |
1832 | /* | |
1833 | * The serial core enabled the clock for us, so undo | |
1834 | * the clk_enable() in atmel_console_setup() | |
1835 | */ | |
1836 | clk_disable(port->clk); | |
1837 | } | |
8da14b5f | 1838 | #endif |
06a7f058 | 1839 | |
dfa7f343 HS |
1840 | device_init_wakeup(&pdev->dev, 1); |
1841 | platform_set_drvdata(pdev, port); | |
1842 | ||
5dfbd1d7 CS |
1843 | if (port->rs485.flags & SER_RS485_ENABLED) { |
1844 | UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL); | |
1845 | UART_PUT_CR(&port->uart, ATMEL_US_RTSEN); | |
1846 | } | |
1847 | ||
dfa7f343 HS |
1848 | return 0; |
1849 | ||
1850 | err_add_port: | |
1ecc26bd RB |
1851 | kfree(port->rx_ring.buf); |
1852 | port->rx_ring.buf = NULL; | |
1853 | err_alloc_ring: | |
dfa7f343 | 1854 | if (!atmel_is_console_port(&port->uart)) { |
dfa7f343 HS |
1855 | clk_put(port->clk); |
1856 | port->clk = NULL; | |
afefc415 | 1857 | } |
4cbf9f48 | 1858 | err: |
afefc415 AV |
1859 | return ret; |
1860 | } | |
1861 | ||
7192f92c | 1862 | static int __devexit atmel_serial_remove(struct platform_device *pdev) |
afefc415 AV |
1863 | { |
1864 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 1865 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 AV |
1866 | int ret = 0; |
1867 | ||
afefc415 AV |
1868 | device_init_wakeup(&pdev->dev, 0); |
1869 | platform_set_drvdata(pdev, NULL); | |
1870 | ||
dfa7f343 HS |
1871 | ret = uart_remove_one_port(&atmel_uart, port); |
1872 | ||
1ecc26bd RB |
1873 | tasklet_kill(&atmel_port->tasklet); |
1874 | kfree(atmel_port->rx_ring.buf); | |
1875 | ||
dfa7f343 HS |
1876 | /* "port" is allocated statically, so we shouldn't free it */ |
1877 | ||
4cbf9f48 NF |
1878 | clear_bit(port->line, &atmel_ports_in_use); |
1879 | ||
dfa7f343 | 1880 | clk_put(atmel_port->clk); |
afefc415 AV |
1881 | |
1882 | return ret; | |
1883 | } | |
1884 | ||
7192f92c HS |
1885 | static struct platform_driver atmel_serial_driver = { |
1886 | .probe = atmel_serial_probe, | |
1887 | .remove = __devexit_p(atmel_serial_remove), | |
1888 | .suspend = atmel_serial_suspend, | |
1889 | .resume = atmel_serial_resume, | |
afefc415 | 1890 | .driver = { |
1e8ea802 | 1891 | .name = "atmel_usart", |
afefc415 | 1892 | .owner = THIS_MODULE, |
5fbe46b6 | 1893 | .of_match_table = of_match_ptr(atmel_serial_dt_ids), |
afefc415 AV |
1894 | }, |
1895 | }; | |
1896 | ||
7192f92c | 1897 | static int __init atmel_serial_init(void) |
afefc415 AV |
1898 | { |
1899 | int ret; | |
1900 | ||
7192f92c | 1901 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
1902 | if (ret) |
1903 | return ret; | |
1904 | ||
7192f92c | 1905 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 1906 | if (ret) |
7192f92c | 1907 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
1908 | |
1909 | return ret; | |
1910 | } | |
1911 | ||
7192f92c | 1912 | static void __exit atmel_serial_exit(void) |
afefc415 | 1913 | { |
7192f92c HS |
1914 | platform_driver_unregister(&atmel_serial_driver); |
1915 | uart_unregister_driver(&atmel_uart); | |
1e6c9c28 AV |
1916 | } |
1917 | ||
7192f92c HS |
1918 | module_init(atmel_serial_init); |
1919 | module_exit(atmel_serial_exit); | |
1e6c9c28 AV |
1920 | |
1921 | MODULE_AUTHOR("Rick Bronson"); | |
7192f92c | 1922 | MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); |
1e6c9c28 | 1923 | MODULE_LICENSE("GPL"); |
e169c139 | 1924 | MODULE_ALIAS("platform:atmel_usart"); |