[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / 8250 / 8250_dw.c

/*
 * Synopsys DesignWare 8250 driver.
 *
 * Copyright 2011 Picochip, Jamie Iles.
 * Copyright 2013 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
 * LCR is written whilst busy.  If it is, then a busy detect interrupt is
 * raised, the LCR needs to be rewritten and the uart status register read.
 */
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/serial_8250.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>

#include "8250.h"

/* Offsets for the DesignWare specific registers */
#define DW_UART_USR	0x1f /* UART Status Register */
#define DW_UART_CPR	0xf4 /* Component Parameter Register */
#define DW_UART_UCV	0xf8 /* UART Component Version */

/* Component Parameter Register bits */
#define DW_UART_CPR_ABP_DATA_WIDTH	(3 << 0)
#define DW_UART_CPR_AFCE_MODE		(1 << 4)
#define DW_UART_CPR_THRE_MODE		(1 << 5)
#define DW_UART_CPR_SIR_MODE		(1 << 6)
#define DW_UART_CPR_SIR_LP_MODE		(1 << 7)
#define DW_UART_CPR_ADDITIONAL_FEATURES	(1 << 8)
#define DW_UART_CPR_FIFO_ACCESS		(1 << 9)
#define DW_UART_CPR_FIFO_STAT		(1 << 10)
#define DW_UART_CPR_SHADOW		(1 << 11)
#define DW_UART_CPR_ENCODED_PARMS	(1 << 12)
#define DW_UART_CPR_DMA_EXTRA		(1 << 13)
#define DW_UART_CPR_FIFO_MODE		(0xff << 16)
/* Helper for fifo size calculation */
#define DW_UART_CPR_FIFO_SIZE(a)	(((a >> 16) & 0xff) * 16)


struct dw8250_data {
	int		last_mcr;
	int		line;
	struct clk	*clk;
};

static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
{
	struct dw8250_data *d = p->private_data;

	/* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
	if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
		value |= UART_MSR_CTS;
		value &= ~UART_MSR_DCTS;
	}

	return value;
}

static void dw8250_force_idle(struct uart_port *p)
{
	serial8250_clear_and_reinit_fifos(container_of
					  (p, struct uart_8250_port, port));
	(void)p->serial_in(p, UART_RX);
}

static void dw8250_serial_out(struct uart_port *p, int offset, int value)
{
	struct dw8250_data *d = p->private_data;

	if (offset == UART_MCR)
		d->last_mcr = value;

	writeb(value, p->membase + (offset << p->regshift));

	/* Make sure LCR write wasn't ignored */
	if (offset == UART_LCR) {
		int tries = 1000;
		while (tries--) {
			unsigned int lcr = p->serial_in(p, UART_LCR);
			if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
				return;
			dw8250_force_idle(p);
			writeb(value, p->membase + (UART_LCR << p->regshift));
		}
		/*
		 * FIXME: this deadlocks if port->lock is already held
		 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
		 */
	}
}

static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
{
	unsigned int value = readb(p->membase + (offset << p->regshift));

	return dw8250_modify_msr(p, offset, value);
}

static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
{
	struct dw8250_data *d = p->private_data;

	if (offset == UART_LCR)
		d->last_lcr = value;

	writel(value, p->membase + (offset << p->regshift));

	/* Make sure LCR write wasn't ignored */
	if (offset == UART_LCR) {
		int tries = 1000;
		while (tries--) {
			unsigned int lcr = p->serial_in(p, UART_LCR);
			if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
				return;
			dw8250_force_idle(p);
			writel(value, p->membase + (UART_LCR << p->regshift));
		}
		/*
		 * FIXME: this deadlocks if port->lock is already held
		 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
		 */
	}
}

static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
{
	offset <<= p->regshift;

	return readl(p->membase + offset);
}

static int dw8250_handle_irq(struct uart_port *p)
{
	struct dw8250_data *d = p->private_data;
	unsigned int iir = p->serial_in(p, UART_IIR);

	if (serial8250_handle_irq(p, iir)) {
		return 1;
	} else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
		/* Clear the USR and write the LCR again. */
		(void)p->serial_in(p, DW_UART_USR);
		p->serial_out(p, UART_LCR, d->last_lcr);

		return 1;
	}

	return 0;
}

static void
dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
{
	if (!state)
		pm_runtime_get_sync(port->dev);

	serial8250_do_pm(port, state, old);

	if (state)
		pm_runtime_put_sync_suspend(port->dev);
}

static int dw8250_probe_of(struct uart_port *p)
{
	struct device_node	*np = p->dev->of_node;
	u32			val;

	if (!of_property_read_u32(np, "reg-io-width", &val)) {
		switch (val) {
		case 1:
			break;
		case 4:
			p->iotype = UPIO_MEM32;
			p->serial_in = dw8250_serial_in32;
			p->serial_out = dw8250_serial_out32;
			break;
		default:
			dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
			return -EINVAL;
		}
	}

	if (!of_property_read_u32(np, "reg-shift", &val))
		p->regshift = val;

	/* clock got configured through clk api, all done */
	if (p->uartclk)
		return 0;

	/* try to find out clock frequency from DT as fallback */
	if (of_property_read_u32(np, "clock-frequency", &val)) {
		dev_err(p->dev, "clk or clock-frequency not defined\n");
		return -EINVAL;
	}
	p->uartclk = val;

	return 0;
}

#ifdef CONFIG_ACPI
static int dw8250_probe_acpi(struct uart_8250_port *up)
{
	const struct acpi_device_id *id;
	struct uart_port *p = &up->port;

	id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
	if (!id)
		return -ENODEV;

	p->iotype = UPIO_MEM32;
	p->serial_in = dw8250_serial_in32;
	p->serial_out = dw8250_serial_out32;
	p->regshift = 2;

	if (!p->uartclk)
		p->uartclk = (unsigned int)id->driver_data;

	up->dma = devm_kzalloc(p->dev, sizeof(*up->dma), GFP_KERNEL);
	if (!up->dma)
		return -ENOMEM;

	up->dma->rxconf.src_maxburst = p->fifosize / 4;
	up->dma->txconf.dst_maxburst = p->fifosize / 4;

	return 0;
}
#else
static inline int dw8250_probe_acpi(struct uart_8250_port *up)
{
	return -ENODEV;
}
#endif /* CONFIG_ACPI */

static void dw8250_setup_port(struct uart_8250_port *up)
{
	struct uart_port	*p = &up->port;
	u32			reg = readl(p->membase + DW_UART_UCV);

	/*
	 * If the Component Version Register returns zero, we know that
	 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
	 */
	if (!reg)
		return;

	dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
		(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);

	reg = readl(p->membase + DW_UART_CPR);
	if (!reg)
		return;

	/* Select the type based on fifo */
	if (reg & DW_UART_CPR_FIFO_MODE) {
		p->type = PORT_16550A;
		p->flags |= UPF_FIXED_TYPE;
		p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
		up->tx_loadsz = p->fifosize;
		up->capabilities = UART_CAP_FIFO;
	}

	if (reg & DW_UART_CPR_AFCE_MODE)
		up->capabilities |= UART_CAP_AFE;
}

static int dw8250_probe(struct platform_device *pdev)
{
	struct uart_8250_port uart = {};
	struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	struct dw8250_data *data;
	int err;

	if (!regs || !irq) {
		dev_err(&pdev->dev, "no registers/irq defined\n");
		return -EINVAL;
	}

	spin_lock_init(&uart.port.lock);
	uart.port.mapbase = regs->start;
	uart.port.irq = irq->start;
	uart.port.handle_irq = dw8250_handle_irq;
	uart.port.pm = dw8250_do_pm;
	uart.port.type = PORT_8250;
	uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
	uart.port.dev = &pdev->dev;

	uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
					 resource_size(regs));
	if (!uart.port.membase)
		return -ENOMEM;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->clk = devm_clk_get(&pdev->dev, NULL);
	if (!IS_ERR(data->clk)) {
		clk_prepare_enable(data->clk);
		uart.port.uartclk = clk_get_rate(data->clk);
	}

	uart.port.iotype = UPIO_MEM;
	uart.port.serial_in = dw8250_serial_in;
	uart.port.serial_out = dw8250_serial_out;
	uart.port.private_data = data;

	dw8250_setup_port(&uart);

	if (pdev->dev.of_node) {
		err = dw8250_probe_of(&uart.port);
		if (err)
			return err;
	} else if (ACPI_HANDLE(&pdev->dev)) {
		err = dw8250_probe_acpi(&uart);
		if (err)
			return err;
	} else {
		return -ENODEV;
	}

	data->line = serial8250_register_8250_port(&uart);
	if (data->line < 0)
		return data->line;

	platform_set_drvdata(pdev, data);

	pm_runtime_set_active(&pdev->dev);
	pm_runtime_enable(&pdev->dev);

	return 0;
}

static int dw8250_remove(struct platform_device *pdev)
{
	struct dw8250_data *data = platform_get_drvdata(pdev);

	pm_runtime_get_sync(&pdev->dev);

	serial8250_unregister_port(data->line);

	if (!IS_ERR(data->clk))
		clk_disable_unprepare(data->clk);

	pm_runtime_disable(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);

	return 0;
}

#ifdef CONFIG_PM
static int dw8250_suspend(struct device *dev)
{
	struct dw8250_data *data = dev_get_drvdata(dev);

	serial8250_suspend_port(data->line);

	return 0;
}

static int dw8250_resume(struct device *dev)
{
	struct dw8250_data *data = dev_get_drvdata(dev);

	serial8250_resume_port(data->line);

	return 0;
}
#endif /* CONFIG_PM */

#ifdef CONFIG_PM_RUNTIME
static int dw8250_runtime_suspend(struct device *dev)
{
	struct dw8250_data *data = dev_get_drvdata(dev);

	if (!IS_ERR(data->clk))
		clk_disable_unprepare(data->clk);

	return 0;
}

static int dw8250_runtime_resume(struct device *dev)
{
	struct dw8250_data *data = dev_get_drvdata(dev);

	if (!IS_ERR(data->clk))
		clk_prepare_enable(data->clk);

	return 0;
}
#endif

static const struct dev_pm_ops dw8250_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
	SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
};

static const struct of_device_id dw8250_of_match[] = {
	{ .compatible = "snps,dw-apb-uart" },
	{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dw8250_of_match);

static const struct acpi_device_id dw8250_acpi_match[] = {
	{ "INT33C4", 0 },
	{ "INT33C5", 0 },
	{ "INT3434", 0 },
	{ "INT3435", 0 },
	{ "80860F0A", 0 },
	{ },
};
MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);

static struct platform_driver dw8250_platform_driver = {
	.driver = {
		.name		= "dw-apb-uart",
		.owner		= THIS_MODULE,
		.pm		= &dw8250_pm_ops,
		.of_match_table	= dw8250_of_match,
		.acpi_match_table = ACPI_PTR(dw8250_acpi_match),
	},
	.probe			= dw8250_probe,
	.remove			= dw8250_remove,
};

module_platform_driver(dw8250_platform_driver);

MODULE_AUTHOR("Jamie Iles");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
Commit	Line	Data
7d4008eb JI	1	/*
	2	* Synopsys DesignWare 8250 driver.
	3	*
	4	* Copyright 2011 Picochip, Jamie Iles.
6a7320c4	5	* Copyright 2013 Intel Corporation
7d4008eb JI	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
	13	* LCR is written whilst busy. If it is, then a busy detect interrupt is
	14	* raised, the LCR needs to be rewritten and the uart status register read.
	15	*/
	16	#include <linux/device.h>
	17	#include <linux/init.h>
	18	#include <linux/io.h>
	19	#include <linux/module.h>
	20	#include <linux/serial_8250.h>
	21	#include <linux/serial_core.h>
	22	#include <linux/serial_reg.h>
	23	#include <linux/of.h>
	24	#include <linux/of_irq.h>
	25	#include <linux/of_platform.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/slab.h>
6a7320c4	28	#include <linux/acpi.h>
e302cd93	29	#include <linux/clk.h>
ffc3ae6d	30	#include <linux/pm_runtime.h>
7d4008eb	31
7277b2a1 HK	32	#include "8250.h"
7277b2a1 HK	33
30046df2 HK	34	/* Offsets for the DesignWare specific registers */
	35	#define DW_UART_USR 0x1f /* UART Status Register */
	36	#define DW_UART_CPR 0xf4 /* Component Parameter Register */
	37	#define DW_UART_UCV 0xf8 /* UART Component Version */
	38
	39	/* Component Parameter Register bits */
	40	#define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
	41	#define DW_UART_CPR_AFCE_MODE (1 << 4)
	42	#define DW_UART_CPR_THRE_MODE (1 << 5)
	43	#define DW_UART_CPR_SIR_MODE (1 << 6)
	44	#define DW_UART_CPR_SIR_LP_MODE (1 << 7)
	45	#define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
	46	#define DW_UART_CPR_FIFO_ACCESS (1 << 9)
	47	#define DW_UART_CPR_FIFO_STAT (1 << 10)
	48	#define DW_UART_CPR_SHADOW (1 << 11)
	49	#define DW_UART_CPR_ENCODED_PARMS (1 << 12)
	50	#define DW_UART_CPR_DMA_EXTRA (1 << 13)
	51	#define DW_UART_CPR_FIFO_MODE (0xff << 16)
	52	/* Helper for fifo size calculation */
	53	#define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
	54
	55
7d4008eb	56	struct dw8250_data {
b1338609	57	int last_mcr;
e302cd93 EL	58	int line;
e302cd93 EL	59	struct clk *clk;
7d4008eb JI	60	};
7d4008eb JI	61
b1338609 TK	62	static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
	63	{
	64	struct dw8250_data *d = p->private_data;
	65
	66	/* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
	67	if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
	68	value \|= UART_MSR_CTS;
	69	value &= ~UART_MSR_DCTS;
	70	}
	71
	72	return value;
	73	}
	74
6d5e7933 TK	75	static void dw8250_force_idle(struct uart_port *p)
	76	{
	77	serial8250_clear_and_reinit_fifos(container_of
	78	(p, struct uart_8250_port, port));
	79	(void)p->serial_in(p, UART_RX);
	80	}
	81
7d4008eb JI	82	static void dw8250_serial_out(struct uart_port *p, int offset, int value)
	83	{
	84	struct dw8250_data *d = p->private_data;
	85
b1338609 TK	86	if (offset == UART_MCR)
	87	d->last_mcr = value;
	88
	89	writeb(value, p->membase + (offset << p->regshift));
6d5e7933 TK	90
	91	/* Make sure LCR write wasn't ignored */
	92	if (offset == UART_LCR) {
	93	int tries = 1000;
	94	while (tries--) {
d791a3e3 JH	95	unsigned int lcr = p->serial_in(p, UART_LCR);
d791a3e3 JH	96	if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
6d5e7933 TK	97	return;
	98	dw8250_force_idle(p);
	99	writeb(value, p->membase + (UART_LCR << p->regshift));
	100	}
e3f5ff37 PH	101	/*
	102	* FIXME: this deadlocks if port->lock is already held
	103	* dev_err(p->dev, "Couldn't set LCR to %d\n", value);
	104	*/
6d5e7933	105	}
7d4008eb JI	106	}
	107
	108	static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
	109	{
b1338609	110	unsigned int value = readb(p->membase + (offset << p->regshift));
7d4008eb	111
b1338609	112	return dw8250_modify_msr(p, offset, value);
7d4008eb JI	113	}
	114
	115	static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
	116	{
	117	struct dw8250_data *d = p->private_data;
	118
6fa3eb70 S	119	if (offset == UART_LCR)
6fa3eb70 S	120	d->last_lcr = value;
b1338609 TK	121
b1338609 TK	122	writel(value, p->membase + (offset << p->regshift));
6d5e7933 TK	123
	124	/* Make sure LCR write wasn't ignored */
	125	if (offset == UART_LCR) {
	126	int tries = 1000;
	127	while (tries--) {
d791a3e3 JH	128	unsigned int lcr = p->serial_in(p, UART_LCR);
d791a3e3 JH	129	if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
6d5e7933 TK	130	return;
	131	dw8250_force_idle(p);
	132	writel(value, p->membase + (UART_LCR << p->regshift));
	133	}
e3f5ff37 PH	134	/*
	135	* FIXME: this deadlocks if port->lock is already held
	136	* dev_err(p->dev, "Couldn't set LCR to %d\n", value);
	137	*/
6d5e7933	138	}
7d4008eb JI	139	}
	140
	141	static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
	142	{
6fa3eb70	143	offset <<= p->regshift;
7d4008eb	144
6fa3eb70	145	return readl(p->membase + offset);
7d4008eb JI	146	}
7d4008eb JI	147
7d4008eb JI	148	static int dw8250_handle_irq(struct uart_port *p)
7d4008eb JI	149	{
6fa3eb70	150	struct dw8250_data *d = p->private_data;
7d4008eb JI	151	unsigned int iir = p->serial_in(p, UART_IIR);
	152
	153	if (serial8250_handle_irq(p, iir)) {
	154	return 1;
	155	} else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
6fa3eb70	156	/* Clear the USR and write the LCR again. */
30046df2	157	(void)p->serial_in(p, DW_UART_USR);
6fa3eb70	158	p->serial_out(p, UART_LCR, d->last_lcr);
7d4008eb JI	159
	160	return 1;
	161	}
	162
	163	return 0;
	164	}
	165
ffc3ae6d HK	166	static void
	167	dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
	168	{
	169	if (!state)
	170	pm_runtime_get_sync(port->dev);
	171
	172	serial8250_do_pm(port, state, old);
	173
	174	if (state)
	175	pm_runtime_put_sync_suspend(port->dev);
	176	}
	177
a7260c8c HK	178	static int dw8250_probe_of(struct uart_port *p)
	179	{
	180	struct device_node *np = p->dev->of_node;
	181	u32 val;
	182
	183	if (!of_property_read_u32(np, "reg-io-width", &val)) {
	184	switch (val) {
	185	case 1:
	186	break;
	187	case 4:
	188	p->iotype = UPIO_MEM32;
	189	p->serial_in = dw8250_serial_in32;
	190	p->serial_out = dw8250_serial_out32;
	191	break;
	192	default:
	193	dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
	194	return -EINVAL;
	195	}
	196	}
	197
	198	if (!of_property_read_u32(np, "reg-shift", &val))
	199	p->regshift = val;
	200
e302cd93 EL	201	/* clock got configured through clk api, all done */
	202	if (p->uartclk)
	203	return 0;
	204
	205	/* try to find out clock frequency from DT as fallback */
a7260c8c	206	if (of_property_read_u32(np, "clock-frequency", &val)) {
e302cd93	207	dev_err(p->dev, "clk or clock-frequency not defined\n");
a7260c8c HK	208	return -EINVAL;
	209	}
	210	p->uartclk = val;
	211
	212	return 0;
	213	}
	214
053fac36	215	#ifdef CONFIG_ACPI
94b2b47c	216	static int dw8250_probe_acpi(struct uart_8250_port *up)
6a7320c4 HK	217	{
6a7320c4 HK	218	const struct acpi_device_id *id;
94b2b47c	219	struct uart_port *p = &up->port;
6a7320c4 HK	220
	221	id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
	222	if (!id)
	223	return -ENODEV;
	224
	225	p->iotype = UPIO_MEM32;
	226	p->serial_in = dw8250_serial_in32;
	227	p->serial_out = dw8250_serial_out32;
	228	p->regshift = 2;
aea02e87 HK	229
	230	if (!p->uartclk)
	231	p->uartclk = (unsigned int)id->driver_data;
6a7320c4	232
94b2b47c HK	233	up->dma = devm_kzalloc(p->dev, sizeof(*up->dma), GFP_KERNEL);
	234	if (!up->dma)
	235	return -ENOMEM;
	236
	237	up->dma->rxconf.src_maxburst = p->fifosize / 4;
	238	up->dma->txconf.dst_maxburst = p->fifosize / 4;
7277b2a1	239
6a7320c4 HK	240	return 0;
6a7320c4 HK	241	}
053fac36	242	#else
3ec857ff	243	static inline int dw8250_probe_acpi(struct uart_8250_port *up)
053fac36 HK	244	{
	245	return -ENODEV;
	246	}
	247	#endif /* CONFIG_ACPI */
6a7320c4	248
30046df2 HK	249	static void dw8250_setup_port(struct uart_8250_port *up)
	250	{
	251	struct uart_port *p = &up->port;
	252	u32 reg = readl(p->membase + DW_UART_UCV);
	253
	254	/*
	255	* If the Component Version Register returns zero, we know that
	256	* ADDITIONAL_FEATURES are not enabled. No need to go any further.
	257	*/
	258	if (!reg)
	259	return;
	260
	261	dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
	262	(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
	263
	264	reg = readl(p->membase + DW_UART_CPR);
	265	if (!reg)
	266	return;
	267
	268	/* Select the type based on fifo */
	269	if (reg & DW_UART_CPR_FIFO_MODE) {
	270	p->type = PORT_16550A;
	271	p->flags \|= UPF_FIXED_TYPE;
	272	p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
	273	up->tx_loadsz = p->fifosize;
2920adb6	274	up->capabilities = UART_CAP_FIFO;
30046df2	275	}
2920adb6 HK	276
	277	if (reg & DW_UART_CPR_AFCE_MODE)
	278	up->capabilities \|= UART_CAP_AFE;
30046df2 HK	279	}
30046df2 HK	280
9671f099	281	static int dw8250_probe(struct platform_device *pdev)
7d4008eb	282	{
2655a2c7	283	struct uart_8250_port uart = {};
7d4008eb JI	284	struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7d4008eb JI	285	struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
7d4008eb	286	struct dw8250_data *data;
a7260c8c	287	int err;
7d4008eb JI	288
	289	if (!regs \|\| !irq) {
	290	dev_err(&pdev->dev, "no registers/irq defined\n");
	291	return -EINVAL;
	292	}
	293
2655a2c7 AC	294	spin_lock_init(&uart.port.lock);
	295	uart.port.mapbase = regs->start;
	296	uart.port.irq = irq->start;
	297	uart.port.handle_irq = dw8250_handle_irq;
ffc3ae6d	298	uart.port.pm = dw8250_do_pm;
2655a2c7	299	uart.port.type = PORT_8250;
f93366ff	300	uart.port.flags = UPF_SHARE_IRQ \| UPF_BOOT_AUTOCONF \| UPF_FIXED_PORT;
2655a2c7	301	uart.port.dev = &pdev->dev;
7d4008eb	302
b88d0826 HK	303	uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
b88d0826 HK	304	resource_size(regs));
f93366ff HK	305	if (!uart.port.membase)
	306	return -ENOMEM;
	307
e302cd93 EL	308	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	309	if (!data)
	310	return -ENOMEM;
	311
	312	data->clk = devm_clk_get(&pdev->dev, NULL);
	313	if (!IS_ERR(data->clk)) {
	314	clk_prepare_enable(data->clk);
	315	uart.port.uartclk = clk_get_rate(data->clk);
	316	}
	317
2655a2c7 AC	318	uart.port.iotype = UPIO_MEM;
	319	uart.port.serial_in = dw8250_serial_in;
	320	uart.port.serial_out = dw8250_serial_out;
e302cd93	321	uart.port.private_data = data;
a7260c8c	322
f5836a55 HK	323	dw8250_setup_port(&uart);
f5836a55 HK	324
a7260c8c HK	325	if (pdev->dev.of_node) {
	326	err = dw8250_probe_of(&uart.port);
	327	if (err)
	328	return err;
6a7320c4	329	} else if (ACPI_HANDLE(&pdev->dev)) {
94b2b47c	330	err = dw8250_probe_acpi(&uart);
6a7320c4 HK	331	if (err)
6a7320c4 HK	332	return err;
a7260c8c HK	333	} else {
a7260c8c HK	334	return -ENODEV;
7d4008eb JI	335	}
7d4008eb JI	336
2655a2c7	337	data->line = serial8250_register_8250_port(&uart);
7d4008eb JI	338	if (data->line < 0)
	339	return data->line;
	340
	341	platform_set_drvdata(pdev, data);
	342
ffc3ae6d HK	343	pm_runtime_set_active(&pdev->dev);
	344	pm_runtime_enable(&pdev->dev);
	345
7d4008eb JI	346	return 0;
	347	}
	348
ae8d8a14	349	static int dw8250_remove(struct platform_device *pdev)
7d4008eb JI	350	{
	351	struct dw8250_data *data = platform_get_drvdata(pdev);
	352
ffc3ae6d HK	353	pm_runtime_get_sync(&pdev->dev);
ffc3ae6d HK	354
7d4008eb JI	355	serial8250_unregister_port(data->line);
7d4008eb JI	356
e302cd93 EL	357	if (!IS_ERR(data->clk))
	358	clk_disable_unprepare(data->clk);
	359
ffc3ae6d HK	360	pm_runtime_disable(&pdev->dev);
	361	pm_runtime_put_noidle(&pdev->dev);
	362
7d4008eb JI	363	return 0;
	364	}
	365
b61c5ed5	366	#ifdef CONFIG_PM
ffc3ae6d	367	static int dw8250_suspend(struct device *dev)
b61c5ed5	368	{
ffc3ae6d	369	struct dw8250_data *data = dev_get_drvdata(dev);
b61c5ed5 JH	370
	371	serial8250_suspend_port(data->line);
	372
	373	return 0;
	374	}
	375
ffc3ae6d	376	static int dw8250_resume(struct device *dev)
b61c5ed5	377	{
ffc3ae6d	378	struct dw8250_data *data = dev_get_drvdata(dev);
b61c5ed5 JH	379
	380	serial8250_resume_port(data->line);
	381
	382	return 0;
	383	}
b61c5ed5 JH	384	#endif /* CONFIG_PM */
b61c5ed5 JH	385
ffc3ae6d HK	386	#ifdef CONFIG_PM_RUNTIME
	387	static int dw8250_runtime_suspend(struct device *dev)
	388	{
	389	struct dw8250_data *data = dev_get_drvdata(dev);
	390
dbd2df85 EG	391	if (!IS_ERR(data->clk))
dbd2df85 EG	392	clk_disable_unprepare(data->clk);
ffc3ae6d HK	393
	394	return 0;
	395	}
	396
	397	static int dw8250_runtime_resume(struct device *dev)
	398	{
	399	struct dw8250_data *data = dev_get_drvdata(dev);
	400
dbd2df85 EG	401	if (!IS_ERR(data->clk))
dbd2df85 EG	402	clk_prepare_enable(data->clk);
ffc3ae6d HK	403
	404	return 0;
	405	}
	406	#endif
	407
	408	static const struct dev_pm_ops dw8250_pm_ops = {
	409	SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
	410	SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
	411	};
	412
a7260c8c	413	static const struct of_device_id dw8250_of_match[] = {
7d4008eb JI	414	{ .compatible = "snps,dw-apb-uart" },
	415	{ /* Sentinel */ }
	416	};
a7260c8c	417	MODULE_DEVICE_TABLE(of, dw8250_of_match);
7d4008eb	418
6a7320c4	419	static const struct acpi_device_id dw8250_acpi_match[] = {
aea02e87 HK	420	{ "INT33C4", 0 },
aea02e87 HK	421	{ "INT33C5", 0 },
a718268a MW	422	{ "INT3434", 0 },
a718268a MW	423	{ "INT3435", 0 },
9d83e180	424	{ "80860F0A", 0 },
6a7320c4 HK	425	{ },
	426	};
	427	MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
	428
7d4008eb JI	429	static struct platform_driver dw8250_platform_driver = {
	430	.driver = {
	431	.name = "dw-apb-uart",
	432	.owner = THIS_MODULE,
ffc3ae6d	433	.pm = &dw8250_pm_ops,
a7260c8c	434	.of_match_table = dw8250_of_match,
6a7320c4	435	.acpi_match_table = ACPI_PTR(dw8250_acpi_match),
7d4008eb JI	436	},
7d4008eb JI	437	.probe = dw8250_probe,
2d47b716	438	.remove = dw8250_remove,
7d4008eb JI	439	};
7d4008eb JI	440
c8381c15	441	module_platform_driver(dw8250_platform_driver);
7d4008eb JI	442
	443	MODULE_AUTHOR("Jamie Iles");
	444	MODULE_LICENSE("GPL");
	445	MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");