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staging: iio: ad5933: avoid uninitialized variable in error case
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / iio / impedance-analyzer / ad5933.c
CommitLineData
f94aa354
MH		 1/*
2 * AD5933 AD5934 Impedance Converter, Network Analyzer
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9#include <linux/interrupt.h>
10#include <linux/device.h>
11#include <linux/kernel.h>
12#include <linux/sysfs.h>
13#include <linux/i2c.h>
14#include <linux/regulator/consumer.h>
15#include <linux/slab.h>
16#include <linux/types.h>
17#include <linux/err.h>
18#include <linux/delay.h>
748b636c 19#include <linux/module.h>
f94aa354
MH		 20#include <asm/div64.h>
21
06458e27
JC		 22#include <linux/iio/iio.h>
23#include <linux/iio/sysfs.h>
24#include <linux/iio/buffer.h>
032658a4 25#include <linux/iio/kfifo_buf.h>
f94aa354
MH		 26
27#include "ad5933.h"
28
29/* AD5933/AD5934 Registers */
30#define AD5933_REG_CONTROL_HB 0x80 /* R/W, 2 bytes */
31#define AD5933_REG_CONTROL_LB 0x81 /* R/W, 2 bytes */
32#define AD5933_REG_FREQ_START 0x82 /* R/W, 3 bytes */
33#define AD5933_REG_FREQ_INC 0x85 /* R/W, 3 bytes */
34#define AD5933_REG_INC_NUM 0x88 /* R/W, 2 bytes, 9 bit */
35#define AD5933_REG_SETTLING_CYCLES 0x8A /* R/W, 2 bytes */
36#define AD5933_REG_STATUS 0x8F /* R, 1 byte */
37#define AD5933_REG_TEMP_DATA 0x92 /* R, 2 bytes*/
38#define AD5933_REG_REAL_DATA 0x94 /* R, 2 bytes*/
39#define AD5933_REG_IMAG_DATA 0x96 /* R, 2 bytes*/
40
41/* AD5933_REG_CONTROL_HB Bits */
42#define AD5933_CTRL_INIT_START_FREQ (0x1 << 4)
43#define AD5933_CTRL_START_SWEEP (0x2 << 4)
44#define AD5933_CTRL_INC_FREQ (0x3 << 4)
45#define AD5933_CTRL_REPEAT_FREQ (0x4 << 4)
46#define AD5933_CTRL_MEASURE_TEMP (0x9 << 4)
47#define AD5933_CTRL_POWER_DOWN (0xA << 4)
48#define AD5933_CTRL_STANDBY (0xB << 4)
49
50#define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1)
51#define AD5933_CTRL_RANGE_200mVpp (0x1 << 1)
52#define AD5933_CTRL_RANGE_400mVpp (0x2 << 1)
53#define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1)
54#define AD5933_CTRL_RANGE(x) ((x) << 1)
55
56#define AD5933_CTRL_PGA_GAIN_1 (0x1 << 0)
57#define AD5933_CTRL_PGA_GAIN_5 (0x0 << 0)
58
59/* AD5933_REG_CONTROL_LB Bits */
60#define AD5933_CTRL_RESET (0x1 << 4)
61#define AD5933_CTRL_INT_SYSCLK (0x0 << 3)
62#define AD5933_CTRL_EXT_SYSCLK (0x1 << 3)
63
64/* AD5933_REG_STATUS Bits */
65#define AD5933_STAT_TEMP_VALID (0x1 << 0)
66#define AD5933_STAT_DATA_VALID (0x1 << 1)
67#define AD5933_STAT_SWEEP_DONE (0x1 << 2)
68
69/* I2C Block Commands */
70#define AD5933_I2C_BLOCK_WRITE 0xA0
71#define AD5933_I2C_BLOCK_READ 0xA1
72#define AD5933_I2C_ADDR_POINTER 0xB0
73
74/* Device Specs */
75#define AD5933_INT_OSC_FREQ_Hz 16776000
76#define AD5933_MAX_OUTPUT_FREQ_Hz 100000
77#define AD5933_MAX_RETRIES 100
78
79#define AD5933_OUT_RANGE 1
80#define AD5933_OUT_RANGE_AVAIL 2
81#define AD5933_OUT_SETTLING_CYCLES 3
82#define AD5933_IN_PGA_GAIN 4
83#define AD5933_IN_PGA_GAIN_AVAIL 5
84#define AD5933_FREQ_POINTS 6
85
86#define AD5933_POLL_TIME_ms 10
87#define AD5933_INIT_EXCITATION_TIME_ms 100
88
89struct ad5933_state {
90 struct i2c_client *client;
91 struct regulator *reg;
92 struct ad5933_platform_data *pdata;
93 struct delayed_work work;
94 unsigned long mclk_hz;
95 unsigned char ctrl_hb;
96 unsigned char ctrl_lb;
97 unsigned range_avail[4];
98 unsigned short vref_mv;
99 unsigned short settling_cycles;
100 unsigned short freq_points;
101 unsigned freq_start;
102 unsigned freq_inc;
103 unsigned state;
104 unsigned poll_time_jiffies;
105};
106
107static struct ad5933_platform_data ad5933_default_pdata = {
108 .vref_mv = 3300,
109};
110
f4e4b955 111static const struct iio_chan_spec ad5933_channels[] = {
cdacc05b
JC		 112 {
113 .type = IIO_TEMP,
114 .indexed = 1,
cdacc05b 115 .channel = 0,
da200c2b 116 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
cdacc05b 117 .address = AD5933_REG_TEMP_DATA,
81548735 118 .scan_index = -1,
cdacc05b
JC		 119 .scan_type = {
120 .sign = 's',
121 .realbits = 14,
122 .storagebits = 16,
123 },
124 }, { /* Ring Channels */
125 .type = IIO_VOLTAGE,
126 .indexed = 1,
127 .channel = 0,
af29aab0 128 .extend_name = "real",
cdacc05b
JC		 129 .address = AD5933_REG_REAL_DATA,
130 .scan_index = 0,
131 .scan_type = {
132 .sign = 's',
133 .realbits = 16,
134 .storagebits = 16,
135 },
136 }, {
137 .type = IIO_VOLTAGE,
138 .indexed = 1,
139 .channel = 0,
af29aab0 140 .extend_name = "imag",
cdacc05b
JC		 141 .address = AD5933_REG_IMAG_DATA,
142 .scan_index = 1,
143 .scan_type = {
144 .sign = 's',
145 .realbits = 16,
146 .storagebits = 16,
147 },
148 },
f94aa354
MH		 149};
150
151static int ad5933_i2c_write(struct i2c_client *client,
152 u8 reg, u8 len, u8 *data)
153{
154 int ret;
155
156 while (len--) {
157 ret = i2c_smbus_write_byte_data(client, reg++, *data++);
158 if (ret < 0) {
159 dev_err(&client->dev, "I2C write error\n");
160 return ret;
161 }
162 }
163 return 0;
164}
165
166static int ad5933_i2c_read(struct i2c_client *client,
167 u8 reg, u8 len, u8 *data)
168{
169 int ret;
170
171 while (len--) {
172 ret = i2c_smbus_read_byte_data(client, reg++);
173 if (ret < 0) {
174 dev_err(&client->dev, "I2C read error\n");
175 return ret;
176 }
177 *data++ = ret;
178 }
179 return 0;
180}
181
182static int ad5933_cmd(struct ad5933_state *st, unsigned char cmd)
183{
184 unsigned char dat = st->ctrl_hb | cmd;
185
186 return ad5933_i2c_write(st->client,
187 AD5933_REG_CONTROL_HB, 1, &dat);
188}
189
190static int ad5933_reset(struct ad5933_state *st)
191{
192 unsigned char dat = st->ctrl_lb | AD5933_CTRL_RESET;
193 return ad5933_i2c_write(st->client,
194 AD5933_REG_CONTROL_LB, 1, &dat);
195}
196
197static int ad5933_wait_busy(struct ad5933_state *st, unsigned char event)
198{
199 unsigned char val, timeout = AD5933_MAX_RETRIES;
200 int ret;
201
202 while (timeout--) {
203 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &val);
204 if (ret < 0)
205 return ret;
206 if (val & event)
207 return val;
208 cpu_relax();
209 mdelay(1);
210 }
211
212 return -EAGAIN;
213}
214
215static int ad5933_set_freq(struct ad5933_state *st,
216 unsigned reg, unsigned long freq)
217{
218 unsigned long long freqreg;
219 union {
220 u32 d32;
221 u8 d8[4];
222 } dat;
223
224 freqreg = (u64) freq * (u64) (1 << 27);
225 do_div(freqreg, st->mclk_hz / 4);
226
227 switch (reg) {
228 case AD5933_REG_FREQ_START:
229 st->freq_start = freq;
230 break;
231 case AD5933_REG_FREQ_INC:
232 st->freq_inc = freq;
233 break;
234 default:
235 return -EINVAL;
236 }
237
238 dat.d32 = cpu_to_be32(freqreg);
239 return ad5933_i2c_write(st->client, reg, 3, &dat.d8[1]);
240}
241
242static int ad5933_setup(struct ad5933_state *st)
243{
244 unsigned short dat;
245 int ret;
246
247 ret = ad5933_reset(st);
248 if (ret < 0)
249 return ret;
250
251 ret = ad5933_set_freq(st, AD5933_REG_FREQ_START, 10000);
252 if (ret < 0)
253 return ret;
254
255 ret = ad5933_set_freq(st, AD5933_REG_FREQ_INC, 200);
256 if (ret < 0)
257 return ret;
258
259 st->settling_cycles = 10;
260 dat = cpu_to_be16(st->settling_cycles);
261
262 ret = ad5933_i2c_write(st->client,
263 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
264 if (ret < 0)
265 return ret;
266
267 st->freq_points = 100;
268 dat = cpu_to_be16(st->freq_points);
269
270 return ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, (u8 *)&dat);
271}
272
273static void ad5933_calc_out_ranges(struct ad5933_state *st)
274{
275 int i;
276 unsigned normalized_3v3[4] = {1980, 198, 383, 970};
277
278 for (i = 0; i < 4; i++)
279 st->range_avail[i] = normalized_3v3[i] * st->vref_mv / 3300;
280
281}
282
283/*
284 * handles: AD5933_REG_FREQ_START and AD5933_REG_FREQ_INC
285 */
286
287static ssize_t ad5933_show_frequency(struct device *dev,
288 struct device_attribute *attr,
289 char *buf)
290{
ba86dc46 291 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
638e59fc 292 struct ad5933_state *st = iio_priv(indio_dev);
f94aa354
MH		 293 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
294 int ret;
295 unsigned long long freqreg;
296 union {
297 u32 d32;
298 u8 d8[4];
299 } dat;
300
638e59fc 301 mutex_lock(&indio_dev->mlock);
f94aa354 302 ret = ad5933_i2c_read(st->client, this_attr->address, 3, &dat.d8[1]);
638e59fc 303 mutex_unlock(&indio_dev->mlock);
f94aa354
MH		 304 if (ret < 0)
305 return ret;
306
307 freqreg = be32_to_cpu(dat.d32) & 0xFFFFFF;
308
309 freqreg = (u64) freqreg * (u64) (st->mclk_hz / 4);
310 do_div(freqreg, 1 << 27);
311
312 return sprintf(buf, "%d\n", (int) freqreg);
313}
314
315static ssize_t ad5933_store_frequency(struct device *dev,
316 struct device_attribute *attr,
317 const char *buf,
318 size_t len)
319{
ba86dc46 320 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
638e59fc 321 struct ad5933_state *st = iio_priv(indio_dev);
f94aa354
MH		 322 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
323 long val;
324 int ret;
325
326 ret = strict_strtoul(buf, 10, &val);
327 if (ret)
328 return ret;
329
330 if (val > AD5933_MAX_OUTPUT_FREQ_Hz)
331 return -EINVAL;
332
638e59fc 333 mutex_lock(&indio_dev->mlock);
f94aa354 334 ret = ad5933_set_freq(st, this_attr->address, val);
638e59fc 335 mutex_unlock(&indio_dev->mlock);
f94aa354
MH		 336
337 return ret ? ret : len;
338}
339
322c9563 340static IIO_DEVICE_ATTR(out_voltage0_freq_start, S_IRUGO | S_IWUSR,
f94aa354
MH		 341 ad5933_show_frequency,
342 ad5933_store_frequency,
343 AD5933_REG_FREQ_START);
344
322c9563 345static IIO_DEVICE_ATTR(out_voltage0_freq_increment, S_IRUGO | S_IWUSR,
f94aa354
MH		 346 ad5933_show_frequency,
347 ad5933_store_frequency,
348 AD5933_REG_FREQ_INC);
349
350static ssize_t ad5933_show(struct device *dev,
351 struct device_attribute *attr,
352 char *buf)
353{
ba86dc46 354 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
638e59fc 355 struct ad5933_state *st = iio_priv(indio_dev);
f94aa354
MH		 356 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
357 int ret = 0, len = 0;
358
638e59fc 359 mutex_lock(&indio_dev->mlock);
e15fbc91 360 switch ((u32) this_attr->address) {
f94aa354
MH		 361 case AD5933_OUT_RANGE:
362 len = sprintf(buf, "%d\n",
363 st->range_avail[(st->ctrl_hb >> 1) & 0x3]);
364 break;
365 case AD5933_OUT_RANGE_AVAIL:
366 len = sprintf(buf, "%d %d %d %d\n", st->range_avail[0],
367 st->range_avail[3], st->range_avail[2],
368 st->range_avail[1]);
369 break;
370 case AD5933_OUT_SETTLING_CYCLES:
371 len = sprintf(buf, "%d\n", st->settling_cycles);
372 break;
373 case AD5933_IN_PGA_GAIN:
374 len = sprintf(buf, "%s\n",
375 (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ?
376 "1" : "0.2");
377 break;
378 case AD5933_IN_PGA_GAIN_AVAIL:
379 len = sprintf(buf, "1 0.2\n");
380 break;
381 case AD5933_FREQ_POINTS:
382 len = sprintf(buf, "%d\n", st->freq_points);
383 break;
384 default:
385 ret = -EINVAL;
386 }
387
638e59fc 388 mutex_unlock(&indio_dev->mlock);
f94aa354
MH		 389 return ret ? ret : len;
390}
391
392static ssize_t ad5933_store(struct device *dev,
393 struct device_attribute *attr,
394 const char *buf,
395 size_t len)
396{
ba86dc46 397 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
638e59fc 398 struct ad5933_state *st = iio_priv(indio_dev);
f94aa354
MH		 399 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
400 long val;
401 int i, ret = 0;
402 unsigned short dat;
403
404 if (this_attr->address != AD5933_IN_PGA_GAIN) {
405 ret = strict_strtol(buf, 10, &val);
406 if (ret)
407 return ret;
408 }
409
638e59fc 410 mutex_lock(&indio_dev->mlock);
e15fbc91 411 switch ((u32) this_attr->address) {
f94aa354
MH		 412 case AD5933_OUT_RANGE:
413 for (i = 0; i < 4; i++)
414 if (val == st->range_avail[i]) {
415 st->ctrl_hb &= ~AD5933_CTRL_RANGE(0x3);
416 st->ctrl_hb |= AD5933_CTRL_RANGE(i);
417 ret = ad5933_cmd(st, 0);
418 break;
419 }
420 ret = -EINVAL;
421 break;
422 case AD5933_IN_PGA_GAIN:
423 if (sysfs_streq(buf, "1")) {
424 st->ctrl_hb |= AD5933_CTRL_PGA_GAIN_1;
425 } else if (sysfs_streq(buf, "0.2")) {
426 st->ctrl_hb &= ~AD5933_CTRL_PGA_GAIN_1;
427 } else {
428 ret = -EINVAL;
429 break;
430 }
431 ret = ad5933_cmd(st, 0);
432 break;
433 case AD5933_OUT_SETTLING_CYCLES:
434 val = clamp(val, 0L, 0x7FFL);
435 st->settling_cycles = val;
436
437 /* 2x, 4x handling, see datasheet */
438 if (val > 511)
439 val = (val >> 1) | (1 << 9);
440 else if (val > 1022)
441 val = (val >> 2) | (3 << 9);
442
443 dat = cpu_to_be16(val);
444 ret = ad5933_i2c_write(st->client,
445 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
446 break;
447 case AD5933_FREQ_POINTS:
448 val = clamp(val, 0L, 511L);
449 st->freq_points = val;
450
451 dat = cpu_to_be16(val);
452 ret = ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2,
453 (u8 *)&dat);
454 break;
455 default:
456 ret = -EINVAL;
457 }
458
638e59fc 459 mutex_unlock(&indio_dev->mlock);
f94aa354
MH		 460 return ret ? ret : len;
461}
462
322c9563 463static IIO_DEVICE_ATTR(out_voltage0_scale, S_IRUGO | S_IWUSR,
f94aa354
MH		 464 ad5933_show,
465 ad5933_store,
466 AD5933_OUT_RANGE);
467
322c9563 468static IIO_DEVICE_ATTR(out_voltage0_scale_available, S_IRUGO,
f94aa354
MH		 469 ad5933_show,
470 NULL,
471 AD5933_OUT_RANGE_AVAIL);
472
322c9563 473static IIO_DEVICE_ATTR(in_voltage0_scale, S_IRUGO | S_IWUSR,
f94aa354
MH		 474 ad5933_show,
475 ad5933_store,
476 AD5933_IN_PGA_GAIN);
477
322c9563 478static IIO_DEVICE_ATTR(in_voltage0_scale_available, S_IRUGO,
f94aa354
MH		 479 ad5933_show,
480 NULL,
481 AD5933_IN_PGA_GAIN_AVAIL);
482
322c9563 483static IIO_DEVICE_ATTR(out_voltage0_freq_points, S_IRUGO | S_IWUSR,
f94aa354
MH		 484 ad5933_show,
485 ad5933_store,
486 AD5933_FREQ_POINTS);
487
322c9563 488static IIO_DEVICE_ATTR(out_voltage0_settling_cycles, S_IRUGO | S_IWUSR,
f94aa354
MH		 489 ad5933_show,
490 ad5933_store,
491 AD5933_OUT_SETTLING_CYCLES);
492
493/* note:
494 * ideally we would handle the scale attributes via the iio_info
495 * (read|write)_raw methods, however this part is a untypical since we
496 * don't create dedicated sysfs channel attributes for out0 and in0.
497 */
498static struct attribute *ad5933_attributes[] = {
322c9563
JC		 499 &iio_dev_attr_out_voltage0_scale.dev_attr.attr,
500 &iio_dev_attr_out_voltage0_scale_available.dev_attr.attr,
501 &iio_dev_attr_out_voltage0_freq_start.dev_attr.attr,
502 &iio_dev_attr_out_voltage0_freq_increment.dev_attr.attr,
503 &iio_dev_attr_out_voltage0_freq_points.dev_attr.attr,
504 &iio_dev_attr_out_voltage0_settling_cycles.dev_attr.attr,
505 &iio_dev_attr_in_voltage0_scale.dev_attr.attr,
506 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
f94aa354
MH		 507 NULL
508};
509
510static const struct attribute_group ad5933_attribute_group = {
511 .attrs = ad5933_attributes,
512};
513
638e59fc 514static int ad5933_read_raw(struct iio_dev *indio_dev,
f94aa354
MH		 515 struct iio_chan_spec const *chan,
516 int *val,
517 int *val2,
518 long m)
519{
638e59fc 520 struct ad5933_state *st = iio_priv(indio_dev);
f94aa354
MH		 521 unsigned short dat;
522 int ret = -EINVAL;
523
638e59fc 524 mutex_lock(&indio_dev->mlock);
f94aa354 525 switch (m) {
967d3fe0
JC		 526 case IIO_CHAN_INFO_RAW:
527 case IIO_CHAN_INFO_PROCESSED:
638e59fc 528 if (iio_buffer_enabled(indio_dev)) {
f94aa354
MH		 529 ret = -EBUSY;
530 goto out;
531 }
532 ret = ad5933_cmd(st, AD5933_CTRL_MEASURE_TEMP);
533 if (ret < 0)
534 goto out;
535 ret = ad5933_wait_busy(st, AD5933_STAT_TEMP_VALID);
536 if (ret < 0)
537 goto out;
538
539 ret = ad5933_i2c_read(st->client,
540 AD5933_REG_TEMP_DATA, 2,
541 (u8 *)&dat);
542 if (ret < 0)
543 goto out;
638e59fc 544 mutex_unlock(&indio_dev->mlock);
f94aa354
MH		 545 ret = be16_to_cpu(dat);
546 /* Temp in Milli degrees Celsius */
547 if (ret < 8192)
548 *val = ret * 1000 / 32;
549 else
550 *val = (ret - 16384) * 1000 / 32;
551
552 return IIO_VAL_INT;
553 }
554
555out:
638e59fc 556 mutex_unlock(&indio_dev->mlock);
f94aa354
MH		 557 return ret;
558}
559
560static const struct iio_info ad5933_info = {
561 .read_raw = &ad5933_read_raw,
562 .attrs = &ad5933_attribute_group,
563 .driver_module = THIS_MODULE,
564};
565
566static int ad5933_ring_preenable(struct iio_dev *indio_dev)
567{
568 struct ad5933_state *st = iio_priv(indio_dev);
f94aa354
MH		 569 int ret;
570
550268ca 571 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
f94aa354
MH		 572 return -EINVAL;
573
f5ee7b80
JC		 574 ret = iio_sw_buffer_preenable(indio_dev);
575 if (ret < 0)
576 return ret;
f94aa354
MH		 577
578 ret = ad5933_reset(st);
579 if (ret < 0)
580 return ret;
581
582 ret = ad5933_cmd(st, AD5933_CTRL_STANDBY);
583 if (ret < 0)
584 return ret;
585
586 ret = ad5933_cmd(st, AD5933_CTRL_INIT_START_FREQ);
587 if (ret < 0)
588 return ret;
589
590 st->state = AD5933_CTRL_INIT_START_FREQ;
591
592 return 0;
593}
594
595static int ad5933_ring_postenable(struct iio_dev *indio_dev)
596{
597 struct ad5933_state *st = iio_priv(indio_dev);
598
599 /* AD5933_CTRL_INIT_START_FREQ:
600 * High Q complex circuits require a long time to reach steady state.
601 * To facilitate the measurement of such impedances, this mode allows
602 * the user full control of the settling time requirement before
603 * entering start frequency sweep mode where the impedance measurement
604 * takes place. In this mode the impedance is excited with the
605 * programmed start frequency (ad5933_ring_preenable),
606 * but no measurement takes place.
607 */
608
609 schedule_delayed_work(&st->work,
610 msecs_to_jiffies(AD5933_INIT_EXCITATION_TIME_ms));
611 return 0;
612}
613
614static int ad5933_ring_postdisable(struct iio_dev *indio_dev)
615{
616 struct ad5933_state *st = iio_priv(indio_dev);
617
618 cancel_delayed_work_sync(&st->work);
619 return ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
620}
621
14555b14 622static const struct iio_buffer_setup_ops ad5933_ring_setup_ops = {
f94aa354
MH		 623 .preenable = &ad5933_ring_preenable,
624 .postenable = &ad5933_ring_postenable,
625 .postdisable = &ad5933_ring_postdisable,
626};
627
628static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev)
629{
032658a4 630 indio_dev->buffer = iio_kfifo_allocate(indio_dev);
14555b14 631 if (!indio_dev->buffer)
f94aa354
MH		 632 return -ENOMEM;
633
f94aa354 634 /* Ring buffer functions - here trigger setup related */
1612244f 635 indio_dev->setup_ops = &ad5933_ring_setup_ops;
f94aa354 636
ec3afa40 637 indio_dev->modes |= INDIO_BUFFER_HARDWARE;
f94aa354
MH		 638
639 return 0;
640}
641
642static void ad5933_work(struct work_struct *work)
643{
644 struct ad5933_state *st = container_of(work,
645 struct ad5933_state, work.work);
646 struct iio_dev *indio_dev = i2c_get_clientdata(st->client);
f94aa354
MH		 647 signed short buf[2];
648 unsigned char status;
0b0d4fc3 649 int ret;
f94aa354
MH		 650
651 mutex_lock(&indio_dev->mlock);
652 if (st->state == AD5933_CTRL_INIT_START_FREQ) {
653 /* start sweep */
654 ad5933_cmd(st, AD5933_CTRL_START_SWEEP);
655 st->state = AD5933_CTRL_START_SWEEP;
656 schedule_delayed_work(&st->work, st->poll_time_jiffies);
0b0d4fc3 657 goto out;
f94aa354
MH		 658 }
659
0b0d4fc3
AB		 660 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status);
661 if (ret)
662 goto out;
f94aa354
MH		 663
664 if (status & AD5933_STAT_DATA_VALID) {
550268ca
JC		 665 int scan_count = bitmap_weight(indio_dev->active_scan_mask,
666 indio_dev->masklength);
0b0d4fc3 667 ret = ad5933_i2c_read(st->client,
550268ca 668 test_bit(1, indio_dev->active_scan_mask) ?
f94aa354 669 AD5933_REG_REAL_DATA : AD5933_REG_IMAG_DATA,
550268ca 670 scan_count * 2, (u8 *)buf);
0b0d4fc3
AB		 671 if (ret)
672 goto out;
f94aa354 673
550268ca 674 if (scan_count == 2) {
f94aa354
MH		 675 buf[0] = be16_to_cpu(buf[0]);
676 buf[1] = be16_to_cpu(buf[1]);
677 } else {
678 buf[0] = be16_to_cpu(buf[0]);
679 }
84b36ce5 680 iio_push_to_buffers(indio_dev, (u8 *)buf);
f94aa354
MH		 681 } else {
682 /* no data available - try again later */
683 schedule_delayed_work(&st->work, st->poll_time_jiffies);
0b0d4fc3 684 goto out;
f94aa354
MH		 685 }
686
687 if (status & AD5933_STAT_SWEEP_DONE) {
688 /* last sample received - power down do nothing until
689 * the ring enable is toggled */
690 ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
691 } else {
692 /* we just received a valid datum, move on to the next */
693 ad5933_cmd(st, AD5933_CTRL_INC_FREQ);
694 schedule_delayed_work(&st->work, st->poll_time_jiffies);
695 }
0b0d4fc3 696out:
f94aa354
MH		 697 mutex_unlock(&indio_dev->mlock);
698}
699
4ae1c61f 700static int ad5933_probe(struct i2c_client *client,
f94aa354
MH		 701 const struct i2c_device_id *id)
702{
26d25ae3 703 int ret, voltage_uv = 0;
f94aa354
MH		 704 struct ad5933_platform_data *pdata = client->dev.platform_data;
705 struct ad5933_state *st;
7cbb7537 706 struct iio_dev *indio_dev = iio_device_alloc(sizeof(*st));
f94aa354
MH		 707 if (indio_dev == NULL)
708 return -ENOMEM;
709
710 st = iio_priv(indio_dev);
711 i2c_set_clientdata(client, indio_dev);
712 st->client = client;
713
714 if (!pdata)
715 st->pdata = &ad5933_default_pdata;
716 else
717 st->pdata = pdata;
718
719 st->reg = regulator_get(&client->dev, "vcc");
720 if (!IS_ERR(st->reg)) {
721 ret = regulator_enable(st->reg);
722 if (ret)
723 goto error_put_reg;
724 voltage_uv = regulator_get_voltage(st->reg);
725 }
726
727 if (voltage_uv)
728 st->vref_mv = voltage_uv / 1000;
729 else
730 st->vref_mv = st->pdata->vref_mv;
731
732 if (st->pdata->ext_clk_Hz) {
733 st->mclk_hz = st->pdata->ext_clk_Hz;
734 st->ctrl_lb = AD5933_CTRL_EXT_SYSCLK;
735 } else {
736 st->mclk_hz = AD5933_INT_OSC_FREQ_Hz;
737 st->ctrl_lb = AD5933_CTRL_INT_SYSCLK;
738 }
739
740 ad5933_calc_out_ranges(st);
741 INIT_DELAYED_WORK(&st->work, ad5933_work);
742 st->poll_time_jiffies = msecs_to_jiffies(AD5933_POLL_TIME_ms);
743
744 indio_dev->dev.parent = &client->dev;
745 indio_dev->info = &ad5933_info;
746 indio_dev->name = id->name;
747 indio_dev->modes = INDIO_DIRECT_MODE;
748 indio_dev->channels = ad5933_channels;
81548735 749 indio_dev->num_channels = ARRAY_SIZE(ad5933_channels);
f94aa354
MH		 750
751 ret = ad5933_register_ring_funcs_and_init(indio_dev);
752 if (ret)
753 goto error_disable_reg;
754
81548735
LPC		 755 ret = iio_buffer_register(indio_dev, ad5933_channels,
756 ARRAY_SIZE(ad5933_channels));
f94aa354
MH		 757 if (ret)
758 goto error_unreg_ring;
759
760 /* enable both REAL and IMAG channels by default */
f79a9098
JC		 761 iio_scan_mask_set(indio_dev, indio_dev->buffer, 0);
762 iio_scan_mask_set(indio_dev, indio_dev->buffer, 1);
f94aa354
MH		 763
764 ret = ad5933_setup(st);
765 if (ret)
766 goto error_uninitialize_ring;
767
26d25ae3
JC		 768 ret = iio_device_register(indio_dev);
769 if (ret)
770 goto error_uninitialize_ring;
771
f94aa354
MH		 772 return 0;
773
774error_uninitialize_ring:
14555b14 775 iio_buffer_unregister(indio_dev);
f94aa354 776error_unreg_ring:
032658a4 777 iio_kfifo_free(indio_dev->buffer);
f94aa354
MH		 778error_disable_reg:
779 if (!IS_ERR(st->reg))
780 regulator_disable(st->reg);
781error_put_reg:
782 if (!IS_ERR(st->reg))
783 regulator_put(st->reg);
784
7cbb7537 785 iio_device_free(indio_dev);
f94aa354
MH		 786
787 return ret;
788}
789
447d4f29 790static int ad5933_remove(struct i2c_client *client)
f94aa354
MH		 791{
792 struct iio_dev *indio_dev = i2c_get_clientdata(client);
793 struct ad5933_state *st = iio_priv(indio_dev);
794
d2fffd6c 795 iio_device_unregister(indio_dev);
14555b14 796 iio_buffer_unregister(indio_dev);
032658a4 797 iio_kfifo_free(indio_dev->buffer);
f94aa354
MH		 798 if (!IS_ERR(st->reg)) {
799 regulator_disable(st->reg);
800 regulator_put(st->reg);
801 }
7cbb7537 802 iio_device_free(indio_dev);
f94aa354
MH		 803
804 return 0;
805}
806
807static const struct i2c_device_id ad5933_id[] = {
808 { "ad5933", 0 },
809 { "ad5934", 0 },
810 {}
811};
812
813MODULE_DEVICE_TABLE(i2c, ad5933_id);
814
815static struct i2c_driver ad5933_driver = {
816 .driver = {
817 .name = "ad5933",
818 },
819 .probe = ad5933_probe,
e543acf0 820 .remove = ad5933_remove,
f94aa354
MH		 821 .id_table = ad5933_id,
822};
6e5af184 823module_i2c_driver(ad5933_driver);
f94aa354
MH		 824
825MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
826MODULE_DESCRIPTION("Analog Devices AD5933 Impedance Conv. Network Analyzer");
827MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)