Commit | Line | Data |
---|---|---|
a9533e7e HP |
1 | /* |
2 | * Copyright (c) 2010 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
01d11441 | 17 | #include <linux/delay.h> |
3327989a BR |
18 | #include <linux/kernel.h> |
19 | #include <linux/string.h> | |
a1c16ed2 GKH |
20 | #include <bcmdefs.h> |
21 | #include <osl.h> | |
c6ac24e9 BR |
22 | #include <linux/module.h> |
23 | #include <linux/pci.h> | |
a9533e7e HP |
24 | #include <bcmutils.h> |
25 | #include <siutils.h> | |
26 | #include <bcmdevs.h> | |
27 | #include <hndsoc.h> | |
28 | #include <sbchipc.h> | |
29 | #include <pci_core.h> | |
30 | #include <pcie_core.h> | |
31 | #include <nicpci.h> | |
32 | #include <bcmnvram.h> | |
33 | #include <bcmsrom.h> | |
a9533e7e HP |
34 | #include <pcicfg.h> |
35 | #include <sbsocram.h> | |
36 | #ifdef BCMSDIO | |
37 | #include <bcmsdh.h> | |
38 | #include <sdio.h> | |
39 | #include <sbsdio.h> | |
40 | #include <sbhnddma.h> | |
41 | #include <sbsdpcmdev.h> | |
42 | #include <bcmsdpcm.h> | |
43 | #endif /* BCMSDIO */ | |
44 | #include <hndpmu.h> | |
45 | ||
46 | /* this file now contains only definitions for sb functions, only necessary | |
47 | *for devices using Sonics backplanes (bcm4329) | |
48 | */ | |
49 | ||
50 | /* if an amba SDIO device is supported, please further restrict the inclusion | |
51 | * of this file | |
52 | */ | |
53 | #ifdef BCMSDIO | |
54 | #include "siutils_priv.h" | |
55 | #endif | |
56 | ||
57 | /* local prototypes */ | |
e69284f2 | 58 | static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, |
a9533e7e | 59 | void *regs, uint bustype, void *sdh, char **vars, |
7cc4a4c0 JC |
60 | uint *varsz); |
61 | static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, | |
a9533e7e | 62 | void *sdh); |
7cc4a4c0 | 63 | static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, |
66cbd3ab | 64 | u32 savewin, uint *origidx, void *regs); |
7cc4a4c0 | 65 | static void si_nvram_process(si_info_t *sii, char *pvars); |
a9533e7e HP |
66 | |
67 | /* dev path concatenation util */ | |
7cc4a4c0 JC |
68 | static char *si_devpathvar(si_t *sih, char *var, int len, const char *name); |
69 | static bool _si_clkctl_cc(si_info_t *sii, uint mode); | |
70 | static bool si_ispcie(si_info_t *sii); | |
b4f790ee | 71 | static uint socram_banksize(si_info_t *sii, sbsocramregs_t *r, |
36ef9a1e | 72 | u8 idx, u8 mtype); |
a9533e7e HP |
73 | |
74 | /* global variable to indicate reservation/release of gpio's */ | |
66cbd3ab | 75 | static u32 si_gpioreservation; |
a9533e7e | 76 | |
a9533e7e HP |
77 | /* |
78 | * Allocate a si handle. | |
79 | * devid - pci device id (used to determine chip#) | |
80 | * osh - opaque OS handle | |
81 | * regs - virtual address of initial core registers | |
82 | * bustype - pci/sb/sdio/etc | |
83 | * vars - pointer to a pointer area for "environment" variables | |
84 | * varsz - pointer to int to return the size of the vars | |
85 | */ | |
e69284f2 BR |
86 | si_t *si_attach(uint devid, struct osl_info *osh, void *regs, uint bustype, |
87 | void *sdh, char **vars, uint *varsz) | |
0d2f0724 | 88 | { |
a9533e7e HP |
89 | si_info_t *sii; |
90 | ||
91 | /* alloc si_info_t */ | |
5fcc1fcb | 92 | sii = kmalloc(sizeof(si_info_t), GFP_ATOMIC); |
ca8c1e59 | 93 | if (sii == NULL) { |
97e17d0e | 94 | SI_ERROR(("si_attach: malloc failed!\n")); |
90ea2296 | 95 | return NULL; |
a9533e7e HP |
96 | } |
97 | ||
98 | if (si_doattach(sii, devid, osh, regs, bustype, sdh, vars, varsz) == | |
99 | NULL) { | |
182acb3c | 100 | kfree(sii); |
90ea2296 | 101 | return NULL; |
a9533e7e HP |
102 | } |
103 | sii->vars = vars ? *vars : NULL; | |
104 | sii->varsz = varsz ? *varsz : 0; | |
105 | ||
106 | return (si_t *) sii; | |
107 | } | |
108 | ||
109 | /* global kernel resource */ | |
110 | static si_info_t ksii; | |
111 | ||
0d2f0724 GKH |
112 | static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, |
113 | void *sdh) | |
114 | { | |
a9533e7e | 115 | |
cf2b4488 | 116 | #ifndef BRCM_FULLMAC |
a9533e7e | 117 | /* kludge to enable the clock on the 4306 which lacks a slowclock */ |
fa7a1db2 | 118 | if (bustype == PCI_BUS && !si_ispcie(sii)) |
a9533e7e | 119 | si_clkctl_xtal(&sii->pub, XTAL | PLL, ON); |
cf2b4488 | 120 | #endif |
a9533e7e HP |
121 | |
122 | #if defined(BCMSDIO) | |
fa7a1db2 | 123 | if (bustype == SDIO_BUS) { |
a9533e7e | 124 | int err; |
36ef9a1e | 125 | u8 clkset; |
a9533e7e HP |
126 | |
127 | /* Try forcing SDIO core to do ALPAvail request only */ | |
128 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; | |
129 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, | |
130 | clkset, &err); | |
131 | if (!err) { | |
36ef9a1e | 132 | u8 clkval; |
a9533e7e HP |
133 | |
134 | /* If register supported, wait for ALPAvail and then force ALP */ | |
135 | clkval = | |
136 | bcmsdh_cfg_read(sdh, SDIO_FUNC_1, | |
137 | SBSDIO_FUNC1_CHIPCLKCSR, NULL); | |
138 | if ((clkval & ~SBSDIO_AVBITS) == clkset) { | |
139 | SPINWAIT(((clkval = | |
140 | bcmsdh_cfg_read(sdh, SDIO_FUNC_1, | |
141 | SBSDIO_FUNC1_CHIPCLKCSR, | |
142 | NULL)), | |
143 | !SBSDIO_ALPAV(clkval)), | |
144 | PMU_MAX_TRANSITION_DLY); | |
145 | if (!SBSDIO_ALPAV(clkval)) { | |
146 | SI_ERROR(("timeout on ALPAV wait, clkval 0x%02x\n", clkval)); | |
0965ae88 | 147 | return false; |
a9533e7e HP |
148 | } |
149 | clkset = | |
150 | SBSDIO_FORCE_HW_CLKREQ_OFF | | |
151 | SBSDIO_FORCE_ALP; | |
152 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, | |
153 | SBSDIO_FUNC1_CHIPCLKCSR, | |
154 | clkset, &err); | |
7383141b | 155 | udelay(65); |
a9533e7e HP |
156 | } |
157 | } | |
158 | ||
159 | /* Also, disable the extra SDIO pull-ups */ | |
160 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0, | |
161 | NULL); | |
162 | } | |
163 | #endif /* defined(BCMSDIO) */ | |
164 | ||
0f0881b0 | 165 | return true; |
a9533e7e HP |
166 | } |
167 | ||
0d2f0724 GKH |
168 | static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, |
169 | u32 savewin, uint *origidx, void *regs) | |
170 | { | |
a9533e7e HP |
171 | bool pci, pcie; |
172 | uint i; | |
173 | uint pciidx, pcieidx, pcirev, pcierev; | |
174 | ||
175 | cc = si_setcoreidx(&sii->pub, SI_CC_IDX); | |
c03b63c1 | 176 | ASSERT(cc); |
a9533e7e HP |
177 | |
178 | /* get chipcommon rev */ | |
179 | sii->pub.ccrev = (int)si_corerev(&sii->pub); | |
180 | ||
181 | /* get chipcommon chipstatus */ | |
182 | if (sii->pub.ccrev >= 11) | |
183 | sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus); | |
184 | ||
185 | /* get chipcommon capabilites */ | |
186 | sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities); | |
187 | /* get chipcommon extended capabilities */ | |
188 | ||
cf2b4488 | 189 | #ifndef BRCM_FULLMAC |
a9533e7e HP |
190 | if (sii->pub.ccrev >= 35) |
191 | sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext); | |
cf2b4488 | 192 | #endif |
a9533e7e HP |
193 | /* get pmu rev and caps */ |
194 | if (sii->pub.cccaps & CC_CAP_PMU) { | |
195 | sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities); | |
196 | sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK; | |
197 | } | |
198 | ||
199 | /* | |
200 | SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n", | |
201 | sii->pub.ccrev, sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev, | |
202 | sii->pub.pmucaps)); | |
203 | */ | |
204 | ||
205 | /* figure out bus/orignal core idx */ | |
206 | sii->pub.buscoretype = NODEV_CORE_ID; | |
207 | sii->pub.buscorerev = NOREV; | |
208 | sii->pub.buscoreidx = BADIDX; | |
209 | ||
0965ae88 | 210 | pci = pcie = false; |
a9533e7e HP |
211 | pcirev = pcierev = NOREV; |
212 | pciidx = pcieidx = BADIDX; | |
213 | ||
214 | for (i = 0; i < sii->numcores; i++) { | |
215 | uint cid, crev; | |
216 | ||
217 | si_setcoreidx(&sii->pub, i); | |
218 | cid = si_coreid(&sii->pub); | |
219 | crev = si_corerev(&sii->pub); | |
220 | ||
221 | /* Display cores found */ | |
222 | SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n", | |
223 | i, cid, crev, sii->coresba[i], sii->regs[i])); | |
224 | ||
fa7a1db2 | 225 | if (bustype == PCI_BUS) { |
a9533e7e HP |
226 | if (cid == PCI_CORE_ID) { |
227 | pciidx = i; | |
228 | pcirev = crev; | |
0f0881b0 | 229 | pci = true; |
a9533e7e HP |
230 | } else if (cid == PCIE_CORE_ID) { |
231 | pcieidx = i; | |
232 | pcierev = crev; | |
0f0881b0 | 233 | pcie = true; |
a9533e7e HP |
234 | } |
235 | } | |
236 | #ifdef BCMSDIO | |
fa7a1db2 BR |
237 | else if (((bustype == SDIO_BUS) || |
238 | (bustype == SPI_BUS)) && | |
a9533e7e HP |
239 | ((cid == PCMCIA_CORE_ID) || (cid == SDIOD_CORE_ID))) { |
240 | sii->pub.buscorerev = crev; | |
241 | sii->pub.buscoretype = cid; | |
242 | sii->pub.buscoreidx = i; | |
243 | } | |
244 | #endif /* BCMSDIO */ | |
245 | ||
246 | /* find the core idx before entering this func. */ | |
247 | if ((savewin && (savewin == sii->coresba[i])) || | |
248 | (regs == sii->regs[i])) | |
249 | *origidx = i; | |
250 | } | |
251 | ||
cf2b4488 HP |
252 | #ifdef BRCM_FULLMAC |
253 | SI_MSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, | |
254 | sii->pub.buscoretype, sii->pub.buscorerev)); | |
255 | ||
256 | /* Make sure any on-chip ARM is off (in case strapping is wrong), | |
257 | * or downloaded code was | |
258 | * already running. | |
259 | */ | |
fa7a1db2 | 260 | if ((bustype == SDIO_BUS) || (bustype == SPI_BUS)) { |
cf2b4488 HP |
261 | if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) || |
262 | si_setcore(&sii->pub, ARMCM3_CORE_ID, 0)) | |
263 | si_core_disable(&sii->pub, 0); | |
264 | } | |
265 | #else | |
a9533e7e HP |
266 | if (pci && pcie) { |
267 | if (si_ispcie(sii)) | |
0965ae88 | 268 | pci = false; |
a9533e7e | 269 | else |
0965ae88 | 270 | pcie = false; |
a9533e7e HP |
271 | } |
272 | if (pci) { | |
273 | sii->pub.buscoretype = PCI_CORE_ID; | |
274 | sii->pub.buscorerev = pcirev; | |
275 | sii->pub.buscoreidx = pciidx; | |
276 | } else if (pcie) { | |
277 | sii->pub.buscoretype = PCIE_CORE_ID; | |
278 | sii->pub.buscorerev = pcierev; | |
279 | sii->pub.buscoreidx = pcieidx; | |
280 | } | |
281 | ||
282 | SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, | |
283 | sii->pub.buscoretype, sii->pub.buscorerev)); | |
284 | ||
285 | /* fixup necessary chip/core configurations */ | |
fa7a1db2 | 286 | if (sii->pub.bustype == PCI_BUS) { |
a9533e7e | 287 | if (SI_FAST(sii)) { |
ca8c1e59 | 288 | if (!sii->pch) { |
c03b63c1 | 289 | sii->pch = (void *)pcicore_init( |
ca8c1e59 JC |
290 | &sii->pub, sii->osh, |
291 | (void *)PCIEREGS(sii)); | |
292 | if (sii->pch == NULL) | |
0965ae88 | 293 | return false; |
ca8c1e59 | 294 | } |
a9533e7e HP |
295 | } |
296 | if (si_pci_fixcfg(&sii->pub)) { | |
297 | SI_ERROR(("si_doattach: sb_pci_fixcfg failed\n")); | |
0965ae88 | 298 | return false; |
a9533e7e HP |
299 | } |
300 | } | |
cf2b4488 | 301 | #endif |
a9533e7e HP |
302 | /* return to the original core */ |
303 | si_setcoreidx(&sii->pub, *origidx); | |
304 | ||
0f0881b0 | 305 | return true; |
a9533e7e HP |
306 | } |
307 | ||
0d2f0724 | 308 | static __used void si_nvram_process(si_info_t *sii, char *pvars) |
a2627bc0 | 309 | { |
a9533e7e HP |
310 | uint w = 0; |
311 | ||
312 | /* get boardtype and boardrev */ | |
fa7a1db2 | 313 | switch (sii->pub.bustype) { |
a9533e7e HP |
314 | case PCI_BUS: |
315 | /* do a pci config read to get subsystem id and subvendor id */ | |
57d8cd23 | 316 | pci_read_config_dword(sii->osh->pdev, PCI_CFG_SVID, &w); |
a9533e7e | 317 | /* Let nvram variables override subsystem Vend/ID */ |
7d4df48e | 318 | sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub, |
ca8c1e59 JC |
319 | "boardvendor"); |
320 | if (sii->pub.boardvendor == 0) | |
a9533e7e HP |
321 | sii->pub.boardvendor = w & 0xffff; |
322 | else | |
323 | SI_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", sii->pub.boardvendor, w & 0xffff)); | |
7d4df48e | 324 | sii->pub.boardtype = (u16)si_getdevpathintvar(&sii->pub, |
ca8c1e59 JC |
325 | "boardtype"); |
326 | if (sii->pub.boardtype == 0) | |
a9533e7e HP |
327 | sii->pub.boardtype = (w >> 16) & 0xffff; |
328 | else | |
329 | SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n", sii->pub.boardtype, (w >> 16) & 0xffff)); | |
330 | break; | |
331 | ||
332 | #ifdef BCMSDIO | |
333 | case SDIO_BUS: | |
334 | #endif | |
335 | sii->pub.boardvendor = getintvar(pvars, "manfid"); | |
336 | sii->pub.boardtype = getintvar(pvars, "prodid"); | |
337 | break; | |
338 | ||
339 | #ifdef BCMSDIO | |
340 | case SPI_BUS: | |
341 | sii->pub.boardvendor = VENDOR_BROADCOM; | |
342 | sii->pub.boardtype = SPI_BOARD; | |
343 | break; | |
344 | #endif | |
345 | ||
346 | case SI_BUS: | |
347 | case JTAG_BUS: | |
348 | sii->pub.boardvendor = VENDOR_BROADCOM; | |
ca8c1e59 JC |
349 | sii->pub.boardtype = getintvar(pvars, "prodid"); |
350 | if (pvars == NULL || (sii->pub.boardtype == 0)) { | |
351 | sii->pub.boardtype = getintvar(NULL, "boardtype"); | |
352 | if (sii->pub.boardtype == 0) | |
a9533e7e | 353 | sii->pub.boardtype = 0xffff; |
ca8c1e59 | 354 | } |
a9533e7e HP |
355 | break; |
356 | } | |
357 | ||
358 | if (sii->pub.boardtype == 0) { | |
359 | SI_ERROR(("si_doattach: unknown board type\n")); | |
360 | ASSERT(sii->pub.boardtype); | |
361 | } | |
362 | ||
363 | sii->pub.boardflags = getintvar(pvars, "boardflags"); | |
364 | } | |
365 | ||
366 | /* this is will make Sonics calls directly, since Sonics is no longer supported in the Si abstraction */ | |
367 | /* this has been customized for the bcm 4329 ONLY */ | |
368 | #ifdef BCMSDIO | |
e69284f2 | 369 | static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, |
0d2f0724 GKH |
370 | void *regs, uint bustype, void *sdh, |
371 | char **vars, uint *varsz) | |
372 | { | |
a9533e7e | 373 | struct si_pub *sih = &sii->pub; |
66cbd3ab | 374 | u32 w, savewin; |
a9533e7e HP |
375 | chipcregs_t *cc; |
376 | char *pvars = NULL; | |
377 | uint origidx; | |
378 | ||
379 | ASSERT(GOODREGS(regs)); | |
380 | ||
9249ede9 | 381 | memset((unsigned char *) sii, 0, sizeof(si_info_t)); |
a9533e7e HP |
382 | |
383 | savewin = 0; | |
384 | ||
385 | sih->buscoreidx = BADIDX; | |
386 | ||
387 | sii->curmap = regs; | |
388 | sii->sdh = sdh; | |
389 | sii->osh = osh; | |
390 | ||
391 | /* find Chipcommon address */ | |
392 | cc = (chipcregs_t *) sii->curmap; | |
393 | sih->bustype = bustype; | |
394 | ||
a9533e7e HP |
395 | /* bus/core/clk setup for register access */ |
396 | if (!si_buscore_prep(sii, bustype, devid, sdh)) { | |
397 | SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", | |
398 | bustype)); | |
399 | return NULL; | |
400 | } | |
401 | ||
402 | /* ChipID recognition. | |
403 | * We assume we can read chipid at offset 0 from the regs arg. | |
404 | * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon), | |
405 | * some way of recognizing them needs to be added here. | |
406 | */ | |
407 | w = R_REG(osh, &cc->chipid); | |
408 | sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT; | |
409 | /* Might as wll fill in chip id rev & pkg */ | |
410 | sih->chip = w & CID_ID_MASK; | |
411 | sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT; | |
412 | sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT; | |
413 | ||
dfa26436 | 414 | if ((sih->chip == BCM4329_CHIP_ID) && |
cf2b4488 HP |
415 | (sih->chippkg != BCM4329_289PIN_PKG_ID)) |
416 | sih->chippkg = BCM4329_182PIN_PKG_ID; | |
417 | ||
a9533e7e HP |
418 | sih->issim = IS_SIM(sih->chippkg); |
419 | ||
420 | /* scan for cores */ | |
421 | /* SI_MSG(("Found chip type SB (0x%08x)\n", w)); */ | |
422 | sb_scan(&sii->pub, regs, devid); | |
423 | ||
424 | /* no cores found, bail out */ | |
425 | if (sii->numcores == 0) { | |
426 | SI_ERROR(("si_doattach: could not find any cores\n")); | |
427 | return NULL; | |
428 | } | |
429 | /* bus/core/clk setup */ | |
430 | origidx = SI_CC_IDX; | |
431 | if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) { | |
432 | SI_ERROR(("si_doattach: si_buscore_setup failed\n")); | |
433 | goto exit; | |
434 | } | |
435 | ||
cf2b4488 HP |
436 | #ifdef BRCM_FULLMAC |
437 | pvars = NULL; | |
438 | #else | |
a9533e7e HP |
439 | /* Init nvram from flash if it exists */ |
440 | nvram_init((void *)&(sii->pub)); | |
441 | ||
442 | /* Init nvram from sprom/otp if they exist */ | |
443 | if (srom_var_init | |
fa7a1db2 | 444 | (&sii->pub, bustype, regs, sii->osh, vars, varsz)) { |
a9533e7e HP |
445 | SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n")); |
446 | goto exit; | |
447 | } | |
448 | pvars = vars ? *vars : NULL; | |
449 | si_nvram_process(sii, pvars); | |
cf2b4488 | 450 | #endif |
a9533e7e HP |
451 | |
452 | /* === NVRAM, clock is ready === */ | |
453 | ||
cf2b4488 HP |
454 | #ifdef BRCM_FULLMAC |
455 | if (sii->pub.ccrev >= 20) { | |
456 | #endif | |
a9533e7e HP |
457 | cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); |
458 | W_REG(osh, &cc->gpiopullup, 0); | |
459 | W_REG(osh, &cc->gpiopulldown, 0); | |
460 | sb_setcoreidx(sih, origidx); | |
cf2b4488 HP |
461 | #ifdef BRCM_FULLMAC |
462 | } | |
463 | #endif | |
a9533e7e | 464 | |
cf2b4488 | 465 | #ifndef BRCM_FULLMAC |
a9533e7e HP |
466 | /* PMU specific initializations */ |
467 | if (PMUCTL_ENAB(sih)) { | |
66cbd3ab | 468 | u32 xtalfreq; |
a9533e7e HP |
469 | si_pmu_init(sih, sii->osh); |
470 | si_pmu_chip_init(sih, sii->osh); | |
471 | xtalfreq = getintvar(pvars, "xtalfreq"); | |
472 | /* If xtalfreq var not available, try to measure it */ | |
473 | if (xtalfreq == 0) | |
474 | xtalfreq = si_pmu_measure_alpclk(sih, sii->osh); | |
475 | si_pmu_pll_init(sih, sii->osh, xtalfreq); | |
476 | si_pmu_res_init(sih, sii->osh); | |
477 | si_pmu_swreg_init(sih, sii->osh); | |
478 | } | |
479 | ||
480 | /* setup the GPIO based LED powersave register */ | |
ca8c1e59 JC |
481 | w = getintvar(pvars, "leddc"); |
482 | if (w == 0) | |
a9533e7e | 483 | w = DEFAULT_GPIOTIMERVAL; |
ce0f1b8c | 484 | sb_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w); |
a9533e7e HP |
485 | |
486 | #ifdef BCMDBG | |
487 | /* clear any previous epidiag-induced target abort */ | |
0965ae88 | 488 | sb_taclear(sih, false); |
a9533e7e | 489 | #endif /* BCMDBG */ |
cf2b4488 | 490 | #endif |
a9533e7e | 491 | |
90ea2296 | 492 | return sii; |
a9533e7e HP |
493 | |
494 | exit: | |
495 | return NULL; | |
496 | } | |
497 | ||
498 | #else /* BCMSDIO */ | |
e69284f2 | 499 | static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, |
0d2f0724 GKH |
500 | void *regs, uint bustype, void *sdh, |
501 | char **vars, uint *varsz) | |
502 | { | |
a9533e7e | 503 | struct si_pub *sih = &sii->pub; |
66cbd3ab | 504 | u32 w, savewin; |
a9533e7e HP |
505 | chipcregs_t *cc; |
506 | char *pvars = NULL; | |
507 | uint origidx; | |
508 | ||
509 | ASSERT(GOODREGS(regs)); | |
510 | ||
9249ede9 | 511 | memset((unsigned char *) sii, 0, sizeof(si_info_t)); |
a9533e7e HP |
512 | |
513 | savewin = 0; | |
514 | ||
515 | sih->buscoreidx = BADIDX; | |
516 | ||
517 | sii->curmap = regs; | |
518 | sii->sdh = sdh; | |
519 | sii->osh = osh; | |
520 | ||
521 | /* check to see if we are a si core mimic'ing a pci core */ | |
57d8cd23 BR |
522 | if (bustype == PCI_BUS) { |
523 | pci_read_config_dword(sii->osh->pdev, PCI_SPROM_CONTROL, &w); | |
524 | if (w == 0xffffffff) { | |
525 | SI_ERROR(("%s: incoming bus is PCI but it's a lie, " | |
526 | " switching to SI devid:0x%x\n", | |
527 | __func__, devid)); | |
528 | bustype = SI_BUS; | |
529 | } | |
a9533e7e HP |
530 | } |
531 | ||
532 | /* find Chipcommon address */ | |
533 | if (bustype == PCI_BUS) { | |
57d8cd23 | 534 | pci_read_config_dword(sii->osh->pdev, PCI_BAR0_WIN, &savewin); |
a9533e7e HP |
535 | if (!GOODCOREADDR(savewin, SI_ENUM_BASE)) |
536 | savewin = SI_ENUM_BASE; | |
57d8cd23 BR |
537 | pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN, |
538 | SI_ENUM_BASE); | |
a9533e7e HP |
539 | cc = (chipcregs_t *) regs; |
540 | } else { | |
541 | cc = (chipcregs_t *) REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE); | |
542 | } | |
543 | ||
544 | sih->bustype = bustype; | |
a9533e7e HP |
545 | |
546 | /* bus/core/clk setup for register access */ | |
547 | if (!si_buscore_prep(sii, bustype, devid, sdh)) { | |
548 | SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", | |
549 | bustype)); | |
550 | return NULL; | |
551 | } | |
552 | ||
553 | /* ChipID recognition. | |
554 | * We assume we can read chipid at offset 0 from the regs arg. | |
555 | * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon), | |
556 | * some way of recognizing them needs to be added here. | |
557 | */ | |
558 | w = R_REG(osh, &cc->chipid); | |
559 | sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT; | |
560 | /* Might as wll fill in chip id rev & pkg */ | |
561 | sih->chip = w & CID_ID_MASK; | |
562 | sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT; | |
563 | sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT; | |
564 | ||
565 | sih->issim = IS_SIM(sih->chippkg); | |
566 | ||
567 | /* scan for cores */ | |
92246bcb | 568 | if (sii->pub.socitype == SOCI_AI) { |
a9533e7e HP |
569 | SI_MSG(("Found chip type AI (0x%08x)\n", w)); |
570 | /* pass chipc address instead of original core base */ | |
c03b63c1 | 571 | ai_scan(&sii->pub, (void *)cc, devid); |
a9533e7e HP |
572 | } else { |
573 | SI_ERROR(("Found chip of unknown type (0x%08x)\n", w)); | |
574 | return NULL; | |
575 | } | |
576 | /* no cores found, bail out */ | |
577 | if (sii->numcores == 0) { | |
578 | SI_ERROR(("si_doattach: could not find any cores\n")); | |
579 | return NULL; | |
580 | } | |
581 | /* bus/core/clk setup */ | |
582 | origidx = SI_CC_IDX; | |
583 | if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) { | |
584 | SI_ERROR(("si_doattach: si_buscore_setup failed\n")); | |
585 | goto exit; | |
586 | } | |
587 | ||
588 | /* assume current core is CC */ | |
589 | if ((sii->pub.ccrev == 0x25) | |
590 | && | |
dfa26436 AS |
591 | ((sih->chip == BCM43236_CHIP_ID |
592 | || sih->chip == BCM43235_CHIP_ID | |
593 | || sih->chip == BCM43238_CHIP_ID) | |
ff29ee8f | 594 | && (sii->pub.chiprev <= 2))) { |
a9533e7e HP |
595 | |
596 | if ((cc->chipstatus & CST43236_BP_CLK) != 0) { | |
597 | uint clkdiv; | |
598 | clkdiv = R_REG(osh, &cc->clkdiv); | |
599 | /* otp_clk_div is even number, 120/14 < 9mhz */ | |
600 | clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT); | |
601 | W_REG(osh, &cc->clkdiv, clkdiv); | |
602 | SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv)); | |
603 | } | |
7383141b | 604 | udelay(10); |
a9533e7e HP |
605 | } |
606 | ||
607 | /* Init nvram from flash if it exists */ | |
608 | nvram_init((void *)&(sii->pub)); | |
609 | ||
610 | /* Init nvram from sprom/otp if they exist */ | |
611 | if (srom_var_init | |
fa7a1db2 | 612 | (&sii->pub, bustype, regs, sii->osh, vars, varsz)) { |
a9533e7e HP |
613 | SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n")); |
614 | goto exit; | |
615 | } | |
616 | pvars = vars ? *vars : NULL; | |
617 | si_nvram_process(sii, pvars); | |
618 | ||
619 | /* === NVRAM, clock is ready === */ | |
620 | cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); | |
621 | W_REG(osh, &cc->gpiopullup, 0); | |
622 | W_REG(osh, &cc->gpiopulldown, 0); | |
623 | si_setcoreidx(sih, origidx); | |
624 | ||
625 | /* PMU specific initializations */ | |
626 | if (PMUCTL_ENAB(sih)) { | |
66cbd3ab | 627 | u32 xtalfreq; |
a9533e7e HP |
628 | si_pmu_init(sih, sii->osh); |
629 | si_pmu_chip_init(sih, sii->osh); | |
630 | xtalfreq = getintvar(pvars, "xtalfreq"); | |
631 | /* If xtalfreq var not available, try to measure it */ | |
632 | if (xtalfreq == 0) | |
633 | xtalfreq = si_pmu_measure_alpclk(sih, sii->osh); | |
634 | si_pmu_pll_init(sih, sii->osh, xtalfreq); | |
635 | si_pmu_res_init(sih, sii->osh); | |
636 | si_pmu_swreg_init(sih, sii->osh); | |
637 | } | |
638 | ||
639 | /* setup the GPIO based LED powersave register */ | |
ca8c1e59 JC |
640 | w = getintvar(pvars, "leddc"); |
641 | if (w == 0) | |
a9533e7e | 642 | w = DEFAULT_GPIOTIMERVAL; |
ce0f1b8c | 643 | si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w); |
a9533e7e HP |
644 | |
645 | if (PCIE(sii)) { | |
646 | ASSERT(sii->pch != NULL); | |
647 | pcicore_attach(sii->pch, pvars, SI_DOATTACH); | |
648 | } | |
649 | ||
dfa26436 AS |
650 | if ((sih->chip == BCM43224_CHIP_ID) || |
651 | (sih->chip == BCM43421_CHIP_ID)) { | |
a9533e7e | 652 | /* enable 12 mA drive strenth for 43224 and set chipControl register bit 15 */ |
ff29ee8f | 653 | if (sih->chiprev == 0) { |
a9533e7e HP |
654 | SI_MSG(("Applying 43224A0 WARs\n")); |
655 | si_corereg(sih, SI_CC_IDX, | |
ce0f1b8c | 656 | offsetof(chipcregs_t, chipcontrol), |
a9533e7e HP |
657 | CCTRL43224_GPIO_TOGGLE, |
658 | CCTRL43224_GPIO_TOGGLE); | |
659 | si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE, | |
660 | CCTRL_43224A0_12MA_LED_DRIVE); | |
661 | } | |
ff29ee8f | 662 | if (sih->chiprev >= 1) { |
a9533e7e HP |
663 | SI_MSG(("Applying 43224B0+ WARs\n")); |
664 | si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE, | |
665 | CCTRL_43224B0_12MA_LED_DRIVE); | |
666 | } | |
667 | } | |
668 | ||
dfa26436 | 669 | if (sih->chip == BCM4313_CHIP_ID) { |
a9533e7e HP |
670 | /* enable 12 mA drive strenth for 4313 and set chipControl register bit 1 */ |
671 | SI_MSG(("Applying 4313 WARs\n")); | |
672 | si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE, | |
673 | CCTRL_4313_12MA_LED_DRIVE); | |
674 | } | |
675 | ||
dfa26436 | 676 | if (sih->chip == BCM4331_CHIP_ID) { |
a9533e7e | 677 | /* Enable Ext PA lines depending on chip package option */ |
0f0881b0 | 678 | si_chipcontrl_epa4331(sih, true); |
a9533e7e HP |
679 | } |
680 | ||
90ea2296 | 681 | return sii; |
a9533e7e | 682 | exit: |
fa7a1db2 | 683 | if (sih->bustype == PCI_BUS) { |
a9533e7e HP |
684 | if (sii->pch) |
685 | pcicore_deinit(sii->pch); | |
686 | sii->pch = NULL; | |
687 | } | |
688 | ||
689 | return NULL; | |
690 | } | |
691 | #endif /* BCMSDIO */ | |
692 | ||
693 | /* may be called with core in reset */ | |
0d2f0724 | 694 | void si_detach(si_t *sih) |
a2627bc0 | 695 | { |
a9533e7e HP |
696 | si_info_t *sii; |
697 | uint idx; | |
698 | ||
699 | struct si_pub *si_local = NULL; | |
02160695 | 700 | memcpy(&si_local, &sih, sizeof(si_t **)); |
a9533e7e HP |
701 | |
702 | sii = SI_INFO(sih); | |
703 | ||
704 | if (sii == NULL) | |
705 | return; | |
706 | ||
fa7a1db2 | 707 | if (sih->bustype == SI_BUS) |
a9533e7e HP |
708 | for (idx = 0; idx < SI_MAXCORES; idx++) |
709 | if (sii->regs[idx]) { | |
8968af14 | 710 | iounmap(sii->regs[idx]); |
a9533e7e HP |
711 | sii->regs[idx] = NULL; |
712 | } | |
713 | ||
cf2b4488 | 714 | #ifndef BRCM_FULLMAC |
a9533e7e HP |
715 | nvram_exit((void *)si_local); /* free up nvram buffers */ |
716 | ||
fa7a1db2 | 717 | if (sih->bustype == PCI_BUS) { |
a9533e7e HP |
718 | if (sii->pch) |
719 | pcicore_deinit(sii->pch); | |
720 | sii->pch = NULL; | |
721 | } | |
cf2b4488 | 722 | #endif |
a9533e7e HP |
723 | #if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS) |
724 | if (sii != &ksii) | |
725 | #endif /* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */ | |
182acb3c | 726 | kfree(sii); |
a9533e7e HP |
727 | } |
728 | ||
7a9b48b3 | 729 | struct osl_info *si_osh(si_t *sih) |
a9533e7e HP |
730 | { |
731 | si_info_t *sii; | |
732 | ||
733 | sii = SI_INFO(sih); | |
734 | return sii->osh; | |
735 | } | |
736 | ||
a9533e7e HP |
737 | /* register driver interrupt disabling and restoring callback functions */ |
738 | void | |
7cc4a4c0 | 739 | si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, |
a9533e7e HP |
740 | void *intrsenabled_fn, void *intr_arg) |
741 | { | |
742 | si_info_t *sii; | |
743 | ||
744 | sii = SI_INFO(sih); | |
745 | sii->intr_arg = intr_arg; | |
746 | sii->intrsoff_fn = (si_intrsoff_t) intrsoff_fn; | |
747 | sii->intrsrestore_fn = (si_intrsrestore_t) intrsrestore_fn; | |
748 | sii->intrsenabled_fn = (si_intrsenabled_t) intrsenabled_fn; | |
749 | /* save current core id. when this function called, the current core | |
750 | * must be the core which provides driver functions(il, et, wl, etc.) | |
751 | */ | |
752 | sii->dev_coreid = sii->coreid[sii->curidx]; | |
753 | } | |
754 | ||
7cc4a4c0 | 755 | void si_deregister_intr_callback(si_t *sih) |
a9533e7e HP |
756 | { |
757 | si_info_t *sii; | |
758 | ||
759 | sii = SI_INFO(sih); | |
760 | sii->intrsoff_fn = NULL; | |
761 | } | |
762 | ||
7cc4a4c0 | 763 | uint si_flag(si_t *sih) |
a9533e7e | 764 | { |
92246bcb | 765 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
766 | return ai_flag(sih); |
767 | else { | |
768 | ASSERT(0); | |
769 | return 0; | |
770 | } | |
771 | } | |
772 | ||
7cc4a4c0 | 773 | void si_setint(si_t *sih, int siflag) |
a9533e7e | 774 | { |
92246bcb | 775 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
776 | ai_setint(sih, siflag); |
777 | else | |
778 | ASSERT(0); | |
779 | } | |
780 | ||
781 | #ifndef BCMSDIO | |
7cc4a4c0 | 782 | uint si_coreid(si_t *sih) |
a9533e7e HP |
783 | { |
784 | si_info_t *sii; | |
785 | ||
786 | sii = SI_INFO(sih); | |
787 | return sii->coreid[sii->curidx]; | |
788 | } | |
789 | #endif | |
790 | ||
7cc4a4c0 | 791 | uint si_coreidx(si_t *sih) |
a9533e7e HP |
792 | { |
793 | si_info_t *sii; | |
794 | ||
795 | sii = SI_INFO(sih); | |
796 | return sii->curidx; | |
797 | } | |
798 | ||
7cc4a4c0 | 799 | bool si_backplane64(si_t *sih) |
a9533e7e | 800 | { |
90ea2296 | 801 | return (sih->cccaps & CC_CAP_BKPLN64) != 0; |
a9533e7e HP |
802 | } |
803 | ||
804 | #ifndef BCMSDIO | |
7cc4a4c0 | 805 | uint si_corerev(si_t *sih) |
a9533e7e | 806 | { |
92246bcb | 807 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
808 | return ai_corerev(sih); |
809 | else { | |
810 | ASSERT(0); | |
811 | return 0; | |
812 | } | |
813 | } | |
814 | #endif | |
815 | ||
816 | /* return index of coreid or BADIDX if not found */ | |
7cc4a4c0 | 817 | uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit) |
a9533e7e HP |
818 | { |
819 | si_info_t *sii; | |
820 | uint found; | |
821 | uint i; | |
822 | ||
823 | sii = SI_INFO(sih); | |
824 | ||
825 | found = 0; | |
826 | ||
827 | for (i = 0; i < sii->numcores; i++) | |
828 | if (sii->coreid[i] == coreid) { | |
829 | if (found == coreunit) | |
90ea2296 | 830 | return i; |
a9533e7e HP |
831 | found++; |
832 | } | |
833 | ||
90ea2296 | 834 | return BADIDX; |
a9533e7e HP |
835 | } |
836 | ||
a9533e7e HP |
837 | /* |
838 | * This function changes logical "focus" to the indicated core; | |
839 | * must be called with interrupts off. | |
840 | * Moreover, callers should keep interrupts off during switching out of and back to d11 core | |
841 | */ | |
7cc4a4c0 | 842 | void *si_setcore(si_t *sih, uint coreid, uint coreunit) |
a9533e7e HP |
843 | { |
844 | uint idx; | |
845 | ||
846 | idx = si_findcoreidx(sih, coreid, coreunit); | |
847 | if (!GOODIDX(idx)) | |
90ea2296 | 848 | return NULL; |
a9533e7e | 849 | |
92246bcb | 850 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
851 | return ai_setcoreidx(sih, idx); |
852 | else { | |
853 | #ifdef BCMSDIO | |
854 | return sb_setcoreidx(sih, idx); | |
855 | #else | |
856 | ASSERT(0); | |
857 | return NULL; | |
858 | #endif | |
859 | } | |
860 | } | |
861 | ||
862 | #ifndef BCMSDIO | |
7cc4a4c0 | 863 | void *si_setcoreidx(si_t *sih, uint coreidx) |
a9533e7e | 864 | { |
92246bcb | 865 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
866 | return ai_setcoreidx(sih, coreidx); |
867 | else { | |
868 | ASSERT(0); | |
869 | return NULL; | |
870 | } | |
871 | } | |
872 | #endif | |
873 | ||
874 | /* Turn off interrupt as required by sb_setcore, before switch core */ | |
7cc4a4c0 | 875 | void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val) |
a9533e7e HP |
876 | { |
877 | void *cc; | |
878 | si_info_t *sii; | |
879 | ||
880 | sii = SI_INFO(sih); | |
881 | ||
882 | if (SI_FAST(sii)) { | |
883 | /* Overloading the origidx variable to remember the coreid, | |
884 | * this works because the core ids cannot be confused with | |
885 | * core indices. | |
886 | */ | |
887 | *origidx = coreid; | |
888 | if (coreid == CC_CORE_ID) | |
889 | return (void *)CCREGS_FAST(sii); | |
890 | else if (coreid == sih->buscoretype) | |
891 | return (void *)PCIEREGS(sii); | |
892 | } | |
893 | INTR_OFF(sii, *intr_val); | |
894 | *origidx = sii->curidx; | |
895 | cc = si_setcore(sih, coreid, 0); | |
896 | ASSERT(cc != NULL); | |
897 | ||
898 | return cc; | |
899 | } | |
900 | ||
901 | /* restore coreidx and restore interrupt */ | |
7cc4a4c0 | 902 | void si_restore_core(si_t *sih, uint coreid, uint intr_val) |
a9533e7e HP |
903 | { |
904 | si_info_t *sii; | |
905 | ||
906 | sii = SI_INFO(sih); | |
907 | if (SI_FAST(sii) | |
908 | && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype))) | |
909 | return; | |
910 | ||
911 | si_setcoreidx(sih, coreid); | |
912 | INTR_RESTORE(sii, intr_val); | |
913 | } | |
914 | ||
66cbd3ab | 915 | u32 si_core_cflags(si_t *sih, u32 mask, u32 val) |
a9533e7e | 916 | { |
92246bcb | 917 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
918 | return ai_core_cflags(sih, mask, val); |
919 | else { | |
920 | ASSERT(0); | |
921 | return 0; | |
922 | } | |
923 | } | |
924 | ||
66cbd3ab | 925 | u32 si_core_sflags(si_t *sih, u32 mask, u32 val) |
a9533e7e | 926 | { |
92246bcb | 927 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
928 | return ai_core_sflags(sih, mask, val); |
929 | else { | |
930 | ASSERT(0); | |
931 | return 0; | |
932 | } | |
933 | } | |
934 | ||
7cc4a4c0 | 935 | bool si_iscoreup(si_t *sih) |
a9533e7e | 936 | { |
92246bcb | 937 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
938 | return ai_iscoreup(sih); |
939 | else { | |
940 | #ifdef BCMSDIO | |
941 | return sb_iscoreup(sih); | |
942 | #else | |
943 | ASSERT(0); | |
0965ae88 | 944 | return false; |
a9533e7e HP |
945 | #endif |
946 | } | |
947 | } | |
948 | ||
66cbd3ab | 949 | void si_write_wrapperreg(si_t *sih, u32 offset, u32 val) |
a9533e7e HP |
950 | { |
951 | /* only for 4319, no requirement for SOCI_SB */ | |
92246bcb | 952 | if (sih->socitype == SOCI_AI) { |
a9533e7e HP |
953 | ai_write_wrap_reg(sih, offset, val); |
954 | } | |
955 | } | |
956 | ||
7cc4a4c0 | 957 | uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) |
a9533e7e HP |
958 | { |
959 | ||
92246bcb | 960 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
961 | return ai_corereg(sih, coreidx, regoff, mask, val); |
962 | else { | |
963 | #ifdef BCMSDIO | |
964 | return sb_corereg(sih, coreidx, regoff, mask, val); | |
965 | #else | |
966 | ASSERT(0); | |
967 | return 0; | |
968 | #endif | |
969 | } | |
970 | } | |
971 | ||
66cbd3ab | 972 | void si_core_disable(si_t *sih, u32 bits) |
a9533e7e HP |
973 | { |
974 | ||
92246bcb | 975 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
976 | ai_core_disable(sih, bits); |
977 | #ifdef BCMSDIO | |
978 | else | |
979 | sb_core_disable(sih, bits); | |
980 | #endif | |
981 | } | |
982 | ||
66cbd3ab | 983 | void si_core_reset(si_t *sih, u32 bits, u32 resetbits) |
a9533e7e | 984 | { |
92246bcb | 985 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
986 | ai_core_reset(sih, bits, resetbits); |
987 | #ifdef BCMSDIO | |
988 | else | |
989 | sb_core_reset(sih, bits, resetbits); | |
990 | #endif | |
991 | } | |
992 | ||
b4f790ee | 993 | u32 si_alp_clock(si_t *sih) |
a2627bc0 | 994 | { |
a9533e7e HP |
995 | if (PMUCTL_ENAB(sih)) |
996 | return si_pmu_alp_clock(sih, si_osh(sih)); | |
997 | ||
998 | return ALP_CLOCK; | |
999 | } | |
1000 | ||
b4f790ee | 1001 | u32 si_ilp_clock(si_t *sih) |
a2627bc0 | 1002 | { |
a9533e7e HP |
1003 | if (PMUCTL_ENAB(sih)) |
1004 | return si_pmu_ilp_clock(sih, si_osh(sih)); | |
1005 | ||
1006 | return ILP_CLOCK; | |
1007 | } | |
1008 | ||
1009 | /* set chip watchdog reset timer to fire in 'ticks' */ | |
cf2b4488 HP |
1010 | #ifdef BRCM_FULLMAC |
1011 | void | |
1012 | si_watchdog(si_t *sih, uint ticks) | |
1013 | { | |
1014 | if (PMUCTL_ENAB(sih)) { | |
1015 | ||
1016 | if ((sih->chip == BCM4319_CHIP_ID) && (sih->chiprev == 0) && | |
1017 | (ticks != 0)) { | |
ce0f1b8c | 1018 | si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, |
cf2b4488 HP |
1019 | clk_ctl_st), ~0, 0x2); |
1020 | si_setcore(sih, USB20D_CORE_ID, 0); | |
1021 | si_core_disable(sih, 1); | |
1022 | si_setcore(sih, CC_CORE_ID, 0); | |
1023 | } | |
1024 | ||
1025 | if (ticks == 1) | |
1026 | ticks = 2; | |
ce0f1b8c | 1027 | si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog), |
cf2b4488 HP |
1028 | ~0, ticks); |
1029 | } else { | |
1030 | /* instant NMI */ | |
ce0f1b8c | 1031 | si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog), |
cf2b4488 HP |
1032 | ~0, ticks); |
1033 | } | |
1034 | } | |
1035 | #else | |
7cc4a4c0 | 1036 | void si_watchdog(si_t *sih, uint ticks) |
a9533e7e HP |
1037 | { |
1038 | uint nb, maxt; | |
1039 | ||
1040 | if (PMUCTL_ENAB(sih)) { | |
1041 | ||
dfa26436 | 1042 | if ((sih->chip == BCM4319_CHIP_ID) && |
ff29ee8f | 1043 | (sih->chiprev == 0) && (ticks != 0)) { |
a9533e7e | 1044 | si_corereg(sih, SI_CC_IDX, |
ce0f1b8c | 1045 | offsetof(chipcregs_t, clk_ctl_st), ~0, 0x2); |
a9533e7e HP |
1046 | si_setcore(sih, USB20D_CORE_ID, 0); |
1047 | si_core_disable(sih, 1); | |
1048 | si_setcore(sih, CC_CORE_ID, 0); | |
1049 | } | |
1050 | ||
1051 | nb = (sih->ccrev < 26) ? 16 : ((sih->ccrev >= 37) ? 32 : 24); | |
1052 | /* The mips compiler uses the sllv instruction, | |
1053 | * so we specially handle the 32-bit case. | |
1054 | */ | |
1055 | if (nb == 32) | |
1056 | maxt = 0xffffffff; | |
1057 | else | |
1058 | maxt = ((1 << nb) - 1); | |
1059 | ||
1060 | if (ticks == 1) | |
1061 | ticks = 2; | |
1062 | else if (ticks > maxt) | |
1063 | ticks = maxt; | |
1064 | ||
ce0f1b8c | 1065 | si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog), |
a9533e7e HP |
1066 | ~0, ticks); |
1067 | } else { | |
1068 | /* make sure we come up in fast clock mode; or if clearing, clear clock */ | |
1069 | si_clkctl_cc(sih, ticks ? CLK_FAST : CLK_DYNAMIC); | |
1070 | maxt = (1 << 28) - 1; | |
1071 | if (ticks > maxt) | |
1072 | ticks = maxt; | |
1073 | ||
ce0f1b8c | 1074 | si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog), ~0, |
a9533e7e HP |
1075 | ticks); |
1076 | } | |
1077 | } | |
cf2b4488 | 1078 | #endif |
a9533e7e | 1079 | |
a9533e7e | 1080 | /* return the slow clock source - LPO, XTAL, or PCI */ |
7cc4a4c0 | 1081 | static uint si_slowclk_src(si_info_t *sii) |
a9533e7e HP |
1082 | { |
1083 | chipcregs_t *cc; | |
57d8cd23 | 1084 | u32 val; |
a9533e7e HP |
1085 | |
1086 | ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID); | |
1087 | ||
1088 | if (sii->pub.ccrev < 6) { | |
fa7a1db2 | 1089 | if (sii->pub.bustype == PCI_BUS) { |
57d8cd23 BR |
1090 | pci_read_config_dword(sii->osh->pdev, PCI_GPIO_OUT, |
1091 | &val); | |
1092 | if (val & PCI_CFG_GPIO_SCS) | |
1093 | return SCC_SS_PCI; | |
1094 | } | |
1095 | return SCC_SS_XTAL; | |
a9533e7e HP |
1096 | } else if (sii->pub.ccrev < 10) { |
1097 | cc = (chipcregs_t *) si_setcoreidx(&sii->pub, sii->curidx); | |
90ea2296 | 1098 | return R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK; |
a9533e7e | 1099 | } else /* Insta-clock */ |
90ea2296 | 1100 | return SCC_SS_XTAL; |
a9533e7e HP |
1101 | } |
1102 | ||
1103 | /* return the ILP (slowclock) min or max frequency */ | |
7cc4a4c0 | 1104 | static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc) |
a9533e7e | 1105 | { |
66cbd3ab | 1106 | u32 slowclk; |
a9533e7e HP |
1107 | uint div; |
1108 | ||
1109 | ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID); | |
1110 | ||
1111 | /* shouldn't be here unless we've established the chip has dynamic clk control */ | |
1112 | ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL); | |
1113 | ||
1114 | slowclk = si_slowclk_src(sii); | |
1115 | if (sii->pub.ccrev < 6) { | |
1116 | if (slowclk == SCC_SS_PCI) | |
90ea2296 JC |
1117 | return max_freq ? (PCIMAXFREQ / 64) |
1118 | : (PCIMINFREQ / 64); | |
a9533e7e | 1119 | else |
90ea2296 JC |
1120 | return max_freq ? (XTALMAXFREQ / 32) |
1121 | : (XTALMINFREQ / 32); | |
a9533e7e HP |
1122 | } else if (sii->pub.ccrev < 10) { |
1123 | div = 4 * | |
1124 | (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> | |
1125 | SCC_CD_SHIFT) + 1); | |
1126 | if (slowclk == SCC_SS_LPO) | |
90ea2296 | 1127 | return max_freq ? LPOMAXFREQ : LPOMINFREQ; |
a9533e7e | 1128 | else if (slowclk == SCC_SS_XTAL) |
90ea2296 JC |
1129 | return max_freq ? (XTALMAXFREQ / div) |
1130 | : (XTALMINFREQ / div); | |
a9533e7e | 1131 | else if (slowclk == SCC_SS_PCI) |
90ea2296 JC |
1132 | return max_freq ? (PCIMAXFREQ / div) |
1133 | : (PCIMINFREQ / div); | |
a9533e7e HP |
1134 | else |
1135 | ASSERT(0); | |
1136 | } else { | |
1137 | /* Chipc rev 10 is InstaClock */ | |
1138 | div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT; | |
1139 | div = 4 * (div + 1); | |
90ea2296 | 1140 | return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div); |
a9533e7e | 1141 | } |
90ea2296 | 1142 | return 0; |
a9533e7e HP |
1143 | } |
1144 | ||
b4f790ee | 1145 | static void si_clkctl_setdelay(si_info_t *sii, void *chipcregs) |
a2627bc0 | 1146 | { |
a9533e7e HP |
1147 | chipcregs_t *cc = (chipcregs_t *) chipcregs; |
1148 | uint slowmaxfreq, pll_delay, slowclk; | |
1149 | uint pll_on_delay, fref_sel_delay; | |
1150 | ||
1151 | pll_delay = PLL_DELAY; | |
1152 | ||
1153 | /* If the slow clock is not sourced by the xtal then add the xtal_on_delay | |
1154 | * since the xtal will also be powered down by dynamic clk control logic. | |
1155 | */ | |
1156 | ||
1157 | slowclk = si_slowclk_src(sii); | |
1158 | if (slowclk != SCC_SS_XTAL) | |
1159 | pll_delay += XTAL_ON_DELAY; | |
1160 | ||
1161 | /* Starting with 4318 it is ILP that is used for the delays */ | |
1162 | slowmaxfreq = | |
0965ae88 | 1163 | si_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? false : true, cc); |
a9533e7e HP |
1164 | |
1165 | pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000; | |
1166 | fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000; | |
1167 | ||
1168 | W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay); | |
1169 | W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay); | |
1170 | } | |
1171 | ||
1172 | /* initialize power control delay registers */ | |
b4f790ee | 1173 | void si_clkctl_init(si_t *sih) |
a2627bc0 | 1174 | { |
a9533e7e HP |
1175 | si_info_t *sii; |
1176 | uint origidx = 0; | |
1177 | chipcregs_t *cc; | |
1178 | bool fast; | |
1179 | ||
1180 | if (!CCCTL_ENAB(sih)) | |
1181 | return; | |
1182 | ||
1183 | sii = SI_INFO(sih); | |
1184 | fast = SI_FAST(sii); | |
1185 | if (!fast) { | |
1186 | origidx = sii->curidx; | |
ca8c1e59 JC |
1187 | cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); |
1188 | if (cc == NULL) | |
a9533e7e | 1189 | return; |
ca8c1e59 JC |
1190 | } else { |
1191 | cc = (chipcregs_t *) CCREGS_FAST(sii); | |
1192 | if (cc == NULL) | |
1193 | return; | |
1194 | } | |
a9533e7e HP |
1195 | ASSERT(cc != NULL); |
1196 | ||
1197 | /* set all Instaclk chip ILP to 1 MHz */ | |
1198 | if (sih->ccrev >= 10) | |
1199 | SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK, | |
1200 | (ILP_DIV_1MHZ << SYCC_CD_SHIFT)); | |
1201 | ||
c03b63c1 | 1202 | si_clkctl_setdelay(sii, (void *)cc); |
a9533e7e HP |
1203 | |
1204 | if (!fast) | |
1205 | si_setcoreidx(sih, origidx); | |
1206 | } | |
1207 | ||
1208 | /* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */ | |
b4f790ee | 1209 | u16 si_clkctl_fast_pwrup_delay(si_t *sih) |
a2627bc0 | 1210 | { |
a9533e7e HP |
1211 | si_info_t *sii; |
1212 | uint origidx = 0; | |
1213 | chipcregs_t *cc; | |
1214 | uint slowminfreq; | |
7d4df48e | 1215 | u16 fpdelay; |
a9533e7e HP |
1216 | uint intr_val = 0; |
1217 | bool fast; | |
1218 | ||
1219 | sii = SI_INFO(sih); | |
1220 | if (PMUCTL_ENAB(sih)) { | |
1221 | INTR_OFF(sii, intr_val); | |
1222 | fpdelay = si_pmu_fast_pwrup_delay(sih, sii->osh); | |
1223 | INTR_RESTORE(sii, intr_val); | |
1224 | return fpdelay; | |
1225 | } | |
1226 | ||
1227 | if (!CCCTL_ENAB(sih)) | |
1228 | return 0; | |
1229 | ||
1230 | fast = SI_FAST(sii); | |
1231 | fpdelay = 0; | |
1232 | if (!fast) { | |
1233 | origidx = sii->curidx; | |
1234 | INTR_OFF(sii, intr_val); | |
ca8c1e59 JC |
1235 | cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); |
1236 | if (cc == NULL) | |
a9533e7e | 1237 | goto done; |
ca8c1e59 JC |
1238 | } else { |
1239 | cc = (chipcregs_t *) CCREGS_FAST(sii); | |
1240 | if (cc == NULL) | |
1241 | goto done; | |
1242 | } | |
a9533e7e HP |
1243 | ASSERT(cc != NULL); |
1244 | ||
0965ae88 | 1245 | slowminfreq = si_slowclk_freq(sii, false, cc); |
a9533e7e HP |
1246 | fpdelay = (((R_REG(sii->osh, &cc->pll_on_delay) + 2) * 1000000) + |
1247 | (slowminfreq - 1)) / slowminfreq; | |
1248 | ||
1249 | done: | |
1250 | if (!fast) { | |
1251 | si_setcoreidx(sih, origidx); | |
1252 | INTR_RESTORE(sii, intr_val); | |
1253 | } | |
1254 | return fpdelay; | |
1255 | } | |
1256 | ||
1257 | /* turn primary xtal and/or pll off/on */ | |
7cc4a4c0 | 1258 | int si_clkctl_xtal(si_t *sih, uint what, bool on) |
a9533e7e HP |
1259 | { |
1260 | si_info_t *sii; | |
66cbd3ab | 1261 | u32 in, out, outen; |
a9533e7e HP |
1262 | |
1263 | sii = SI_INFO(sih); | |
1264 | ||
fa7a1db2 | 1265 | switch (sih->bustype) { |
a9533e7e HP |
1266 | |
1267 | #ifdef BCMSDIO | |
1268 | case SDIO_BUS: | |
90ea2296 | 1269 | return -1; |
a9533e7e HP |
1270 | #endif /* BCMSDIO */ |
1271 | ||
1272 | case PCI_BUS: | |
1273 | /* pcie core doesn't have any mapping to control the xtal pu */ | |
1274 | if (PCIE(sii)) | |
1275 | return -1; | |
1276 | ||
57d8cd23 BR |
1277 | pci_read_config_dword(sii->osh->pdev, PCI_GPIO_IN, &in); |
1278 | pci_read_config_dword(sii->osh->pdev, PCI_GPIO_OUT, &out); | |
1279 | pci_read_config_dword(sii->osh->pdev, PCI_GPIO_OUTEN, &outen); | |
a9533e7e HP |
1280 | |
1281 | /* | |
1282 | * Avoid glitching the clock if GPRS is already using it. | |
1283 | * We can't actually read the state of the PLLPD so we infer it | |
1284 | * by the value of XTAL_PU which *is* readable via gpioin. | |
1285 | */ | |
1286 | if (on && (in & PCI_CFG_GPIO_XTAL)) | |
90ea2296 | 1287 | return 0; |
a9533e7e HP |
1288 | |
1289 | if (what & XTAL) | |
1290 | outen |= PCI_CFG_GPIO_XTAL; | |
1291 | if (what & PLL) | |
1292 | outen |= PCI_CFG_GPIO_PLL; | |
1293 | ||
1294 | if (on) { | |
1295 | /* turn primary xtal on */ | |
1296 | if (what & XTAL) { | |
1297 | out |= PCI_CFG_GPIO_XTAL; | |
1298 | if (what & PLL) | |
1299 | out |= PCI_CFG_GPIO_PLL; | |
57d8cd23 BR |
1300 | pci_write_config_dword(sii->osh->pdev, |
1301 | PCI_GPIO_OUT, out); | |
1302 | pci_write_config_dword(sii->osh->pdev, | |
1303 | PCI_GPIO_OUTEN, outen); | |
7383141b | 1304 | udelay(XTAL_ON_DELAY); |
a9533e7e HP |
1305 | } |
1306 | ||
1307 | /* turn pll on */ | |
1308 | if (what & PLL) { | |
1309 | out &= ~PCI_CFG_GPIO_PLL; | |
57d8cd23 BR |
1310 | pci_write_config_dword(sii->osh->pdev, |
1311 | PCI_GPIO_OUT, out); | |
7383141b | 1312 | mdelay(2); |
a9533e7e HP |
1313 | } |
1314 | } else { | |
1315 | if (what & XTAL) | |
1316 | out &= ~PCI_CFG_GPIO_XTAL; | |
1317 | if (what & PLL) | |
1318 | out |= PCI_CFG_GPIO_PLL; | |
57d8cd23 BR |
1319 | pci_write_config_dword(sii->osh->pdev, |
1320 | PCI_GPIO_OUT, out); | |
1321 | pci_write_config_dword(sii->osh->pdev, | |
1322 | PCI_GPIO_OUTEN, outen); | |
a9533e7e HP |
1323 | } |
1324 | ||
1325 | default: | |
90ea2296 | 1326 | return -1; |
a9533e7e HP |
1327 | } |
1328 | ||
90ea2296 | 1329 | return 0; |
a9533e7e HP |
1330 | } |
1331 | ||
1332 | /* | |
1333 | * clock control policy function throught chipcommon | |
1334 | * | |
1335 | * set dynamic clk control mode (forceslow, forcefast, dynamic) | |
1336 | * returns true if we are forcing fast clock | |
1337 | * this is a wrapper over the next internal function | |
1338 | * to allow flexible policy settings for outside caller | |
1339 | */ | |
7cc4a4c0 | 1340 | bool si_clkctl_cc(si_t *sih, uint mode) |
a9533e7e HP |
1341 | { |
1342 | si_info_t *sii; | |
1343 | ||
1344 | sii = SI_INFO(sih); | |
1345 | ||
1346 | /* chipcommon cores prior to rev6 don't support dynamic clock control */ | |
1347 | if (sih->ccrev < 6) | |
0965ae88 | 1348 | return false; |
a9533e7e HP |
1349 | |
1350 | if (PCI_FORCEHT(sii)) | |
90ea2296 | 1351 | return mode == CLK_FAST; |
a9533e7e HP |
1352 | |
1353 | return _si_clkctl_cc(sii, mode); | |
1354 | } | |
1355 | ||
1356 | /* clk control mechanism through chipcommon, no policy checking */ | |
7cc4a4c0 | 1357 | static bool _si_clkctl_cc(si_info_t *sii, uint mode) |
a9533e7e HP |
1358 | { |
1359 | uint origidx = 0; | |
1360 | chipcregs_t *cc; | |
66cbd3ab | 1361 | u32 scc; |
a9533e7e HP |
1362 | uint intr_val = 0; |
1363 | bool fast = SI_FAST(sii); | |
1364 | ||
1365 | /* chipcommon cores prior to rev6 don't support dynamic clock control */ | |
1366 | if (sii->pub.ccrev < 6) | |
0965ae88 | 1367 | return false; |
a9533e7e HP |
1368 | |
1369 | /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */ | |
1370 | ASSERT(sii->pub.ccrev != 10); | |
1371 | ||
1372 | if (!fast) { | |
1373 | INTR_OFF(sii, intr_val); | |
1374 | origidx = sii->curidx; | |
1375 | ||
fa7a1db2 | 1376 | if ((sii->pub.bustype == SI_BUS) && |
a9533e7e HP |
1377 | si_setcore(&sii->pub, MIPS33_CORE_ID, 0) && |
1378 | (si_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10)) | |
1379 | goto done; | |
1380 | ||
1381 | cc = (chipcregs_t *) si_setcore(&sii->pub, CC_CORE_ID, 0); | |
ca8c1e59 JC |
1382 | } else { |
1383 | cc = (chipcregs_t *) CCREGS_FAST(sii); | |
1384 | if (cc == NULL) | |
1385 | goto done; | |
1386 | } | |
a9533e7e HP |
1387 | ASSERT(cc != NULL); |
1388 | ||
1389 | if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20)) | |
1390 | goto done; | |
1391 | ||
1392 | switch (mode) { | |
1393 | case CLK_FAST: /* FORCEHT, fast (pll) clock */ | |
1394 | if (sii->pub.ccrev < 10) { | |
1395 | /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */ | |
1396 | si_clkctl_xtal(&sii->pub, XTAL, ON); | |
1397 | SET_REG(sii->osh, &cc->slow_clk_ctl, | |
1398 | (SCC_XC | SCC_FS | SCC_IP), SCC_IP); | |
1399 | } else if (sii->pub.ccrev < 20) { | |
1400 | OR_REG(sii->osh, &cc->system_clk_ctl, SYCC_HR); | |
1401 | } else { | |
1402 | OR_REG(sii->osh, &cc->clk_ctl_st, CCS_FORCEHT); | |
1403 | } | |
1404 | ||
1405 | /* wait for the PLL */ | |
1406 | if (PMUCTL_ENAB(&sii->pub)) { | |
66cbd3ab | 1407 | u32 htavail = CCS_HTAVAIL; |
a9533e7e HP |
1408 | SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) |
1409 | == 0), PMU_MAX_TRANSITION_DLY); | |
1410 | ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail); | |
1411 | } else { | |
7383141b | 1412 | udelay(PLL_DELAY); |
a9533e7e HP |
1413 | } |
1414 | break; | |
1415 | ||
1416 | case CLK_DYNAMIC: /* enable dynamic clock control */ | |
1417 | if (sii->pub.ccrev < 10) { | |
1418 | scc = R_REG(sii->osh, &cc->slow_clk_ctl); | |
1419 | scc &= ~(SCC_FS | SCC_IP | SCC_XC); | |
1420 | if ((scc & SCC_SS_MASK) != SCC_SS_XTAL) | |
1421 | scc |= SCC_XC; | |
1422 | W_REG(sii->osh, &cc->slow_clk_ctl, scc); | |
1423 | ||
1424 | /* for dynamic control, we have to release our xtal_pu "force on" */ | |
1425 | if (scc & SCC_XC) | |
1426 | si_clkctl_xtal(&sii->pub, XTAL, OFF); | |
1427 | } else if (sii->pub.ccrev < 20) { | |
1428 | /* Instaclock */ | |
1429 | AND_REG(sii->osh, &cc->system_clk_ctl, ~SYCC_HR); | |
1430 | } else { | |
1431 | AND_REG(sii->osh, &cc->clk_ctl_st, ~CCS_FORCEHT); | |
1432 | } | |
1433 | break; | |
1434 | ||
1435 | default: | |
1436 | ASSERT(0); | |
1437 | } | |
1438 | ||
1439 | done: | |
1440 | if (!fast) { | |
1441 | si_setcoreidx(&sii->pub, origidx); | |
1442 | INTR_RESTORE(sii, intr_val); | |
1443 | } | |
90ea2296 | 1444 | return mode == CLK_FAST; |
a9533e7e HP |
1445 | } |
1446 | ||
1447 | /* Build device path. Support SI, PCI, and JTAG for now. */ | |
0d2f0724 | 1448 | int si_devpath(si_t *sih, char *path, int size) |
a2627bc0 | 1449 | { |
a9533e7e HP |
1450 | int slen; |
1451 | ||
1452 | ASSERT(path != NULL); | |
1453 | ASSERT(size >= SI_DEVPATH_BUFSZ); | |
1454 | ||
1455 | if (!path || size <= 0) | |
1456 | return -1; | |
1457 | ||
fa7a1db2 | 1458 | switch (sih->bustype) { |
a9533e7e HP |
1459 | case SI_BUS: |
1460 | case JTAG_BUS: | |
1461 | slen = snprintf(path, (size_t) size, "sb/%u/", si_coreidx(sih)); | |
1462 | break; | |
1463 | case PCI_BUS: | |
1464 | ASSERT((SI_INFO(sih))->osh != NULL); | |
1465 | slen = snprintf(path, (size_t) size, "pci/%u/%u/", | |
1466 | OSL_PCI_BUS((SI_INFO(sih))->osh), | |
1467 | OSL_PCI_SLOT((SI_INFO(sih))->osh)); | |
1468 | break; | |
1469 | ||
1470 | #ifdef BCMSDIO | |
1471 | case SDIO_BUS: | |
1472 | SI_ERROR(("si_devpath: device 0 assumed\n")); | |
1473 | slen = snprintf(path, (size_t) size, "sd/%u/", si_coreidx(sih)); | |
1474 | break; | |
1475 | #endif | |
1476 | default: | |
1477 | slen = -1; | |
1478 | ASSERT(0); | |
1479 | break; | |
1480 | } | |
1481 | ||
1482 | if (slen < 0 || slen >= size) { | |
1483 | path[0] = '\0'; | |
1484 | return -1; | |
1485 | } | |
1486 | ||
1487 | return 0; | |
1488 | } | |
1489 | ||
1490 | /* Get a variable, but only if it has a devpath prefix */ | |
0d2f0724 | 1491 | char *si_getdevpathvar(si_t *sih, const char *name) |
a2627bc0 | 1492 | { |
a9533e7e HP |
1493 | char varname[SI_DEVPATH_BUFSZ + 32]; |
1494 | ||
1495 | si_devpathvar(sih, varname, sizeof(varname), name); | |
1496 | ||
90ea2296 | 1497 | return getvar(NULL, varname); |
a9533e7e HP |
1498 | } |
1499 | ||
1500 | /* Get a variable, but only if it has a devpath prefix */ | |
0d2f0724 | 1501 | int si_getdevpathintvar(si_t *sih, const char *name) |
a2627bc0 | 1502 | { |
a9533e7e | 1503 | #if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS) |
90ea2296 | 1504 | return getintvar(NULL, name); |
a9533e7e HP |
1505 | #else |
1506 | char varname[SI_DEVPATH_BUFSZ + 32]; | |
1507 | ||
1508 | si_devpathvar(sih, varname, sizeof(varname), name); | |
1509 | ||
90ea2296 | 1510 | return getintvar(NULL, varname); |
a9533e7e HP |
1511 | #endif |
1512 | } | |
1513 | ||
7cc4a4c0 | 1514 | char *si_getnvramflvar(si_t *sih, const char *name) |
a9533e7e | 1515 | { |
90ea2296 | 1516 | return getvar(NULL, name); |
a9533e7e HP |
1517 | } |
1518 | ||
1519 | /* Concatenate the dev path with a varname into the given 'var' buffer | |
1520 | * and return the 'var' pointer. | |
1521 | * Nothing is done to the arguments if len == 0 or var is NULL, var is still returned. | |
1522 | * On overflow, the first char will be set to '\0'. | |
1523 | */ | |
0d2f0724 GKH |
1524 | static char *si_devpathvar(si_t *sih, char *var, int len, const char *name) |
1525 | { | |
a9533e7e HP |
1526 | uint path_len; |
1527 | ||
1528 | if (!var || len <= 0) | |
1529 | return var; | |
1530 | ||
1531 | if (si_devpath(sih, var, len) == 0) { | |
1532 | path_len = strlen(var); | |
1533 | ||
1534 | if (strlen(name) + 1 > (uint) (len - path_len)) | |
1535 | var[0] = '\0'; | |
1536 | else | |
1537 | strncpy(var + path_len, name, len - path_len - 1); | |
1538 | } | |
1539 | ||
1540 | return var; | |
1541 | } | |
1542 | ||
0f0881b0 | 1543 | /* return true if PCIE capability exists in the pci config space */ |
84b9fac2 | 1544 | static __used bool si_ispcie(si_info_t *sii) |
a9533e7e | 1545 | { |
36ef9a1e | 1546 | u8 cap_ptr; |
a9533e7e | 1547 | |
fa7a1db2 | 1548 | if (sii->pub.bustype != PCI_BUS) |
0965ae88 | 1549 | return false; |
a9533e7e HP |
1550 | |
1551 | cap_ptr = | |
1552 | pcicore_find_pci_capability(sii->osh, PCI_CAP_PCIECAP_ID, NULL, | |
1553 | NULL); | |
1554 | if (!cap_ptr) | |
0965ae88 | 1555 | return false; |
a9533e7e | 1556 | |
0f0881b0 | 1557 | return true; |
a9533e7e HP |
1558 | } |
1559 | ||
a9533e7e HP |
1560 | #ifdef BCMSDIO |
1561 | /* initialize the sdio core */ | |
7cc4a4c0 | 1562 | void si_sdio_init(si_t *sih) |
a9533e7e HP |
1563 | { |
1564 | si_info_t *sii = SI_INFO(sih); | |
1565 | ||
1566 | if (((sih->buscoretype == PCMCIA_CORE_ID) && (sih->buscorerev >= 8)) || | |
1567 | (sih->buscoretype == SDIOD_CORE_ID)) { | |
1568 | uint idx; | |
1569 | sdpcmd_regs_t *sdpregs; | |
1570 | ||
1571 | /* get the current core index */ | |
1572 | idx = sii->curidx; | |
1573 | ASSERT(idx == si_findcoreidx(sih, D11_CORE_ID, 0)); | |
1574 | ||
1575 | /* switch to sdio core */ | |
ca8c1e59 JC |
1576 | sdpregs = (sdpcmd_regs_t *) si_setcore(sih, PCMCIA_CORE_ID, 0); |
1577 | if (!sdpregs) | |
a9533e7e HP |
1578 | sdpregs = |
1579 | (sdpcmd_regs_t *) si_setcore(sih, SDIOD_CORE_ID, 0); | |
1580 | ASSERT(sdpregs); | |
1581 | ||
1582 | SI_MSG(("si_sdio_init: For PCMCIA/SDIO Corerev %d, enable ints from core %d " "through SD core %d (%p)\n", sih->buscorerev, idx, sii->curidx, sdpregs)); | |
1583 | ||
1584 | /* enable backplane error and core interrupts */ | |
1585 | W_REG(sii->osh, &sdpregs->hostintmask, I_SBINT); | |
1586 | W_REG(sii->osh, &sdpregs->sbintmask, | |
1587 | (I_SB_SERR | I_SB_RESPERR | (1 << idx))); | |
1588 | ||
1589 | /* switch back to previous core */ | |
1590 | si_setcoreidx(sih, idx); | |
1591 | } | |
1592 | ||
1593 | /* enable interrupts */ | |
1594 | bcmsdh_intr_enable(sii->sdh); | |
1595 | ||
1596 | } | |
1597 | #endif /* BCMSDIO */ | |
1598 | ||
0d2f0724 | 1599 | bool si_pci_war16165(si_t *sih) |
a2627bc0 | 1600 | { |
a9533e7e HP |
1601 | si_info_t *sii; |
1602 | ||
1603 | sii = SI_INFO(sih); | |
1604 | ||
90ea2296 | 1605 | return PCI(sii) && (sih->buscorerev <= 10); |
a9533e7e HP |
1606 | } |
1607 | ||
b4f790ee | 1608 | void si_pci_up(si_t *sih) |
a2627bc0 | 1609 | { |
a9533e7e HP |
1610 | si_info_t *sii; |
1611 | ||
1612 | sii = SI_INFO(sih); | |
1613 | ||
1614 | /* if not pci bus, we're done */ | |
fa7a1db2 | 1615 | if (sih->bustype != PCI_BUS) |
a9533e7e HP |
1616 | return; |
1617 | ||
1618 | if (PCI_FORCEHT(sii)) | |
1619 | _si_clkctl_cc(sii, CLK_FAST); | |
1620 | ||
1621 | if (PCIE(sii)) | |
1622 | pcicore_up(sii->pch, SI_PCIUP); | |
1623 | ||
1624 | } | |
1625 | ||
1626 | /* Unconfigure and/or apply various WARs when system is going to sleep mode */ | |
9927fc2e | 1627 | void si_pci_sleep(si_t *sih) |
a2627bc0 | 1628 | { |
a9533e7e HP |
1629 | si_info_t *sii; |
1630 | ||
1631 | sii = SI_INFO(sih); | |
1632 | ||
1633 | pcicore_sleep(sii->pch); | |
1634 | } | |
1635 | ||
1636 | /* Unconfigure and/or apply various WARs when going down */ | |
b4f790ee | 1637 | void si_pci_down(si_t *sih) |
a2627bc0 | 1638 | { |
a9533e7e HP |
1639 | si_info_t *sii; |
1640 | ||
1641 | sii = SI_INFO(sih); | |
1642 | ||
1643 | /* if not pci bus, we're done */ | |
fa7a1db2 | 1644 | if (sih->bustype != PCI_BUS) |
a9533e7e HP |
1645 | return; |
1646 | ||
1647 | /* release FORCEHT since chip is going to "down" state */ | |
1648 | if (PCI_FORCEHT(sii)) | |
1649 | _si_clkctl_cc(sii, CLK_DYNAMIC); | |
1650 | ||
1651 | pcicore_down(sii->pch, SI_PCIDOWN); | |
1652 | } | |
1653 | ||
1654 | /* | |
1655 | * Configure the pci core for pci client (NIC) action | |
1656 | * coremask is the bitvec of cores by index to be enabled. | |
1657 | */ | |
0d2f0724 | 1658 | void si_pci_setup(si_t *sih, uint coremask) |
a2627bc0 | 1659 | { |
a9533e7e | 1660 | si_info_t *sii; |
c11b0ef8 | 1661 | struct sbpciregs *pciregs = NULL; |
66cbd3ab | 1662 | u32 siflag = 0, w; |
a9533e7e HP |
1663 | uint idx = 0; |
1664 | ||
1665 | sii = SI_INFO(sih); | |
1666 | ||
fa7a1db2 | 1667 | if (sii->pub.bustype != PCI_BUS) |
a9533e7e HP |
1668 | return; |
1669 | ||
1670 | ASSERT(PCI(sii) || PCIE(sii)); | |
1671 | ASSERT(sii->pub.buscoreidx != BADIDX); | |
1672 | ||
1673 | if (PCI(sii)) { | |
1674 | /* get current core index */ | |
1675 | idx = sii->curidx; | |
1676 | ||
1677 | /* we interrupt on this backplane flag number */ | |
1678 | siflag = si_flag(sih); | |
1679 | ||
1680 | /* switch over to pci core */ | |
c11b0ef8 | 1681 | pciregs = (struct sbpciregs *)si_setcoreidx(sih, sii->pub.buscoreidx); |
a9533e7e HP |
1682 | } |
1683 | ||
1684 | /* | |
1685 | * Enable sb->pci interrupts. Assume | |
1686 | * PCI rev 2.3 support was added in pci core rev 6 and things changed.. | |
1687 | */ | |
1688 | if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) { | |
1689 | /* pci config write to set this core bit in PCIIntMask */ | |
57d8cd23 | 1690 | pci_read_config_dword(sii->osh->pdev, PCI_INT_MASK, &w); |
a9533e7e | 1691 | w |= (coremask << PCI_SBIM_SHIFT); |
57d8cd23 | 1692 | pci_write_config_dword(sii->osh->pdev, PCI_INT_MASK, w); |
a9533e7e HP |
1693 | } else { |
1694 | /* set sbintvec bit for our flag number */ | |
1695 | si_setint(sih, siflag); | |
1696 | } | |
1697 | ||
1698 | if (PCI(sii)) { | |
1699 | OR_REG(sii->osh, &pciregs->sbtopci2, | |
1700 | (SBTOPCI_PREF | SBTOPCI_BURST)); | |
1701 | if (sii->pub.buscorerev >= 11) { | |
1702 | OR_REG(sii->osh, &pciregs->sbtopci2, | |
1703 | SBTOPCI_RC_READMULTI); | |
1704 | w = R_REG(sii->osh, &pciregs->clkrun); | |
1705 | W_REG(sii->osh, &pciregs->clkrun, | |
1706 | (w | PCI_CLKRUN_DSBL)); | |
1707 | w = R_REG(sii->osh, &pciregs->clkrun); | |
1708 | } | |
1709 | ||
1710 | /* switch back to previous core */ | |
1711 | si_setcoreidx(sih, idx); | |
1712 | } | |
1713 | } | |
1714 | ||
a9533e7e HP |
1715 | /* |
1716 | * Fixup SROMless PCI device's configuration. | |
1717 | * The current core may be changed upon return. | |
1718 | */ | |
7cc4a4c0 | 1719 | int si_pci_fixcfg(si_t *sih) |
a9533e7e HP |
1720 | { |
1721 | uint origidx, pciidx; | |
c11b0ef8 | 1722 | struct sbpciregs *pciregs = NULL; |
a9533e7e HP |
1723 | sbpcieregs_t *pcieregs = NULL; |
1724 | void *regs = NULL; | |
7d4df48e | 1725 | u16 val16, *reg16 = NULL; |
a9533e7e HP |
1726 | |
1727 | si_info_t *sii = SI_INFO(sih); | |
1728 | ||
fa7a1db2 | 1729 | ASSERT(sii->pub.bustype == PCI_BUS); |
a9533e7e HP |
1730 | |
1731 | /* Fixup PI in SROM shadow area to enable the correct PCI core access */ | |
1732 | /* save the current index */ | |
1733 | origidx = si_coreidx(&sii->pub); | |
1734 | ||
1735 | /* check 'pi' is correct and fix it if not */ | |
1736 | if (sii->pub.buscoretype == PCIE_CORE_ID) { | |
1737 | pcieregs = | |
1738 | (sbpcieregs_t *) si_setcore(&sii->pub, PCIE_CORE_ID, 0); | |
1739 | regs = pcieregs; | |
1740 | ASSERT(pcieregs != NULL); | |
1741 | reg16 = &pcieregs->sprom[SRSH_PI_OFFSET]; | |
1742 | } else if (sii->pub.buscoretype == PCI_CORE_ID) { | |
c11b0ef8 | 1743 | pciregs = (struct sbpciregs *)si_setcore(&sii->pub, PCI_CORE_ID, 0); |
a9533e7e HP |
1744 | regs = pciregs; |
1745 | ASSERT(pciregs != NULL); | |
1746 | reg16 = &pciregs->sprom[SRSH_PI_OFFSET]; | |
1747 | } | |
1748 | pciidx = si_coreidx(&sii->pub); | |
1749 | val16 = R_REG(sii->osh, reg16); | |
7d4df48e | 1750 | if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) { |
a9533e7e | 1751 | val16 = |
7d4df48e | 1752 | (u16) (pciidx << SRSH_PI_SHIFT) | (val16 & |
a9533e7e HP |
1753 | ~SRSH_PI_MASK); |
1754 | W_REG(sii->osh, reg16, val16); | |
1755 | } | |
1756 | ||
1757 | /* restore the original index */ | |
1758 | si_setcoreidx(&sii->pub, origidx); | |
1759 | ||
1760 | pcicore_hwup(sii->pch); | |
1761 | return 0; | |
1762 | } | |
1763 | ||
a9533e7e | 1764 | /* mask&set gpiocontrol bits */ |
66cbd3ab | 1765 | u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority) |
a9533e7e HP |
1766 | { |
1767 | uint regoff; | |
1768 | ||
1769 | regoff = 0; | |
1770 | ||
1771 | /* gpios could be shared on router platforms | |
1772 | * ignore reservation if it's high priority (e.g., test apps) | |
1773 | */ | |
1774 | if ((priority != GPIO_HI_PRIORITY) && | |
fa7a1db2 | 1775 | (sih->bustype == SI_BUS) && (val || mask)) { |
a9533e7e HP |
1776 | mask = priority ? (si_gpioreservation & mask) : |
1777 | ((si_gpioreservation | mask) & ~(si_gpioreservation)); | |
1778 | val &= mask; | |
1779 | } | |
1780 | ||
ce0f1b8c | 1781 | regoff = offsetof(chipcregs_t, gpiocontrol); |
90ea2296 | 1782 | return si_corereg(sih, SI_CC_IDX, regoff, mask, val); |
a9533e7e HP |
1783 | } |
1784 | ||
1e3950b8 HP |
1785 | /* Return the size of the specified SOCRAM bank */ |
1786 | static uint | |
1787 | socram_banksize(si_info_t *sii, sbsocramregs_t *regs, u8 index, | |
1788 | u8 mem_type) | |
a9533e7e | 1789 | { |
1e3950b8 HP |
1790 | uint banksize, bankinfo; |
1791 | uint bankidx = index | (mem_type << SOCRAM_BANKIDX_MEMTYPE_SHIFT); | |
a9533e7e | 1792 | |
1e3950b8 | 1793 | ASSERT(mem_type <= SOCRAM_MEMTYPE_DEVRAM); |
a9533e7e HP |
1794 | |
1795 | W_REG(sii->osh, ®s->bankidx, bankidx); | |
1796 | bankinfo = R_REG(sii->osh, ®s->bankinfo); | |
1797 | banksize = | |
1798 | SOCRAM_BANKINFO_SZBASE * ((bankinfo & SOCRAM_BANKINFO_SZMASK) + 1); | |
1799 | return banksize; | |
1800 | } | |
1801 | ||
a9533e7e | 1802 | /* Return the RAM size of the SOCRAM core */ |
66cbd3ab | 1803 | u32 si_socram_size(si_t *sih) |
a9533e7e HP |
1804 | { |
1805 | si_info_t *sii; | |
1806 | uint origidx; | |
1807 | uint intr_val = 0; | |
1808 | ||
1809 | sbsocramregs_t *regs; | |
1810 | bool wasup; | |
1811 | uint corerev; | |
66cbd3ab | 1812 | u32 coreinfo; |
a9533e7e HP |
1813 | uint memsize = 0; |
1814 | ||
1815 | sii = SI_INFO(sih); | |
1816 | ||
1817 | /* Block ints and save current core */ | |
1818 | INTR_OFF(sii, intr_val); | |
1819 | origidx = si_coreidx(sih); | |
1820 | ||
1821 | /* Switch to SOCRAM core */ | |
ca8c1e59 JC |
1822 | regs = si_setcore(sih, SOCRAM_CORE_ID, 0); |
1823 | if (!regs) | |
a9533e7e HP |
1824 | goto done; |
1825 | ||
1826 | /* Get info for determining size */ | |
ca8c1e59 JC |
1827 | wasup = si_iscoreup(sih); |
1828 | if (!wasup) | |
a9533e7e HP |
1829 | si_core_reset(sih, 0, 0); |
1830 | corerev = si_corerev(sih); | |
1831 | coreinfo = R_REG(sii->osh, ®s->coreinfo); | |
1832 | ||
1833 | /* Calculate size from coreinfo based on rev */ | |
1834 | if (corerev == 0) | |
1835 | memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK)); | |
1836 | else if (corerev < 3) { | |
1837 | memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK)); | |
1838 | memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; | |
1839 | } else if ((corerev <= 7) || (corerev == 12)) { | |
1840 | uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; | |
1841 | uint bsz = (coreinfo & SRCI_SRBSZ_MASK); | |
1842 | uint lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT; | |
1843 | if (lss != 0) | |
1844 | nb--; | |
1845 | memsize = nb * (1 << (bsz + SR_BSZ_BASE)); | |
1846 | if (lss != 0) | |
1847 | memsize += (1 << ((lss - 1) + SR_BSZ_BASE)); | |
1848 | } else { | |
36ef9a1e | 1849 | u8 i; |
a9533e7e HP |
1850 | uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; |
1851 | for (i = 0; i < nb; i++) | |
1852 | memsize += | |
1853 | socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM); | |
1854 | } | |
1855 | ||
1856 | /* Return to previous state and core */ | |
1857 | if (!wasup) | |
1858 | si_core_disable(sih, 0); | |
1859 | si_setcoreidx(sih, origidx); | |
1860 | ||
1861 | done: | |
1862 | INTR_RESTORE(sii, intr_val); | |
1863 | ||
1864 | return memsize; | |
1865 | } | |
1866 | ||
7cc4a4c0 | 1867 | void si_chipcontrl_epa4331(si_t *sih, bool on) |
a9533e7e HP |
1868 | { |
1869 | si_info_t *sii; | |
1870 | chipcregs_t *cc; | |
1871 | uint origidx; | |
66cbd3ab | 1872 | u32 val; |
a9533e7e HP |
1873 | |
1874 | sii = SI_INFO(sih); | |
1875 | origidx = si_coreidx(sih); | |
1876 | ||
1877 | cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); | |
1878 | ||
1879 | val = R_REG(sii->osh, &cc->chipcontrol); | |
1880 | ||
1881 | if (on) { | |
1882 | if (sih->chippkg == 9 || sih->chippkg == 0xb) { | |
1883 | /* Ext PA Controls for 4331 12x9 Package */ | |
1884 | W_REG(sii->osh, &cc->chipcontrol, val | | |
1885 | (CCTRL4331_EXTPA_EN | | |
1886 | CCTRL4331_EXTPA_ON_GPIO2_5)); | |
1887 | } else { | |
1888 | /* Ext PA Controls for 4331 12x12 Package */ | |
1889 | W_REG(sii->osh, &cc->chipcontrol, | |
1890 | val | (CCTRL4331_EXTPA_EN)); | |
1891 | } | |
1892 | } else { | |
1893 | val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5); | |
1894 | W_REG(sii->osh, &cc->chipcontrol, val); | |
1895 | } | |
1896 | ||
1897 | si_setcoreidx(sih, origidx); | |
1898 | } | |
1899 | ||
1900 | /* Enable BT-COEX & Ex-PA for 4313 */ | |
7cc4a4c0 | 1901 | void si_epa_4313war(si_t *sih) |
a9533e7e HP |
1902 | { |
1903 | si_info_t *sii; | |
1904 | chipcregs_t *cc; | |
1905 | uint origidx; | |
1906 | ||
1907 | sii = SI_INFO(sih); | |
1908 | origidx = si_coreidx(sih); | |
1909 | ||
1910 | cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); | |
1911 | ||
1912 | /* EPA Fix */ | |
1913 | W_REG(sii->osh, &cc->gpiocontrol, | |
1914 | R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK); | |
1915 | ||
1916 | si_setcoreidx(sih, origidx); | |
1917 | } | |
1918 | ||
1919 | /* check if the device is removed */ | |
7cc4a4c0 | 1920 | bool si_deviceremoved(si_t *sih) |
a9533e7e | 1921 | { |
66cbd3ab | 1922 | u32 w; |
a9533e7e HP |
1923 | si_info_t *sii; |
1924 | ||
1925 | sii = SI_INFO(sih); | |
1926 | ||
fa7a1db2 | 1927 | switch (sih->bustype) { |
a9533e7e HP |
1928 | case PCI_BUS: |
1929 | ASSERT(sii->osh != NULL); | |
57d8cd23 | 1930 | pci_read_config_dword(sii->osh->pdev, PCI_CFG_VID, &w); |
a9533e7e | 1931 | if ((w & 0xFFFF) != VENDOR_BROADCOM) |
0f0881b0 | 1932 | return true; |
a9533e7e HP |
1933 | break; |
1934 | } | |
0965ae88 | 1935 | return false; |
a9533e7e HP |
1936 | } |
1937 | ||
7cc4a4c0 | 1938 | bool si_is_sprom_available(si_t *sih) |
a9533e7e HP |
1939 | { |
1940 | if (sih->ccrev >= 31) { | |
1941 | si_info_t *sii; | |
1942 | uint origidx; | |
1943 | chipcregs_t *cc; | |
66cbd3ab | 1944 | u32 sromctrl; |
a9533e7e HP |
1945 | |
1946 | if ((sih->cccaps & CC_CAP_SROM) == 0) | |
0965ae88 | 1947 | return false; |
a9533e7e HP |
1948 | |
1949 | sii = SI_INFO(sih); | |
1950 | origidx = sii->curidx; | |
1951 | cc = si_setcoreidx(sih, SI_CC_IDX); | |
1952 | sromctrl = R_REG(sii->osh, &cc->sromcontrol); | |
1953 | si_setcoreidx(sih, origidx); | |
90ea2296 | 1954 | return sromctrl & SRC_PRESENT; |
a9533e7e HP |
1955 | } |
1956 | ||
dfa26436 | 1957 | switch (sih->chip) { |
a9533e7e HP |
1958 | case BCM4329_CHIP_ID: |
1959 | return (sih->chipst & CST4329_SPROM_SEL) != 0; | |
1960 | case BCM4319_CHIP_ID: | |
1961 | return (sih->chipst & CST4319_SPROM_SEL) != 0; | |
1962 | case BCM4336_CHIP_ID: | |
1963 | return (sih->chipst & CST4336_SPROM_PRESENT) != 0; | |
1964 | case BCM4330_CHIP_ID: | |
1965 | return (sih->chipst & CST4330_SPROM_PRESENT) != 0; | |
1966 | case BCM4313_CHIP_ID: | |
1967 | return (sih->chipst & CST4313_SPROM_PRESENT) != 0; | |
1968 | case BCM4331_CHIP_ID: | |
1969 | return (sih->chipst & CST4331_SPROM_PRESENT) != 0; | |
1970 | default: | |
0f0881b0 | 1971 | return true; |
a9533e7e HP |
1972 | } |
1973 | } | |
1974 | ||
7cc4a4c0 | 1975 | bool si_is_otp_disabled(si_t *sih) |
a9533e7e | 1976 | { |
dfa26436 | 1977 | switch (sih->chip) { |
a9533e7e HP |
1978 | case BCM4329_CHIP_ID: |
1979 | return (sih->chipst & CST4329_SPROM_OTP_SEL_MASK) == | |
1980 | CST4329_OTP_PWRDN; | |
1981 | case BCM4319_CHIP_ID: | |
1982 | return (sih->chipst & CST4319_SPROM_OTP_SEL_MASK) == | |
1983 | CST4319_OTP_PWRDN; | |
1984 | case BCM4336_CHIP_ID: | |
90ea2296 | 1985 | return (sih->chipst & CST4336_OTP_PRESENT) == 0; |
a9533e7e | 1986 | case BCM4330_CHIP_ID: |
90ea2296 | 1987 | return (sih->chipst & CST4330_OTP_PRESENT) == 0; |
a9533e7e HP |
1988 | case BCM4313_CHIP_ID: |
1989 | return (sih->chipst & CST4313_OTP_PRESENT) == 0; | |
1990 | /* These chips always have their OTP on */ | |
1991 | case BCM43224_CHIP_ID: | |
1992 | case BCM43225_CHIP_ID: | |
1993 | case BCM43421_CHIP_ID: | |
1994 | case BCM43235_CHIP_ID: | |
1995 | case BCM43236_CHIP_ID: | |
1996 | case BCM43238_CHIP_ID: | |
1997 | case BCM4331_CHIP_ID: | |
1998 | default: | |
0965ae88 | 1999 | return false; |
a9533e7e HP |
2000 | } |
2001 | } | |
2002 | ||
7cc4a4c0 | 2003 | bool si_is_otp_powered(si_t *sih) |
a9533e7e HP |
2004 | { |
2005 | if (PMUCTL_ENAB(sih)) | |
2006 | return si_pmu_is_otp_powered(sih, si_osh(sih)); | |
0f0881b0 | 2007 | return true; |
a9533e7e HP |
2008 | } |
2009 | ||
7cc4a4c0 | 2010 | void si_otp_power(si_t *sih, bool on) |
a9533e7e HP |
2011 | { |
2012 | if (PMUCTL_ENAB(sih)) | |
2013 | si_pmu_otp_power(sih, si_osh(sih), on); | |
7383141b | 2014 | udelay(1000); |
a9533e7e HP |
2015 | } |
2016 |