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ssb: pci: separate workarounds
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ssb / driver_pcicore.c
CommitLineData
61e115a5
MB		 1/*
2 * Sonics Silicon Backplane
3 * Broadcom PCI-core driver
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include <linux/ssb/ssb.h>
12#include <linux/pci.h>
13#include <linux/delay.h>
7cb44615 14#include <linux/ssb/ssb_embedded.h>
61e115a5
MB		 15
16#include "ssb_private.h"
17
ccc7c28a
RM		 18static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
19static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
20static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
21static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
22 u8 address, u16 data);
61e115a5 23
6e914101
RM		 24static void ssb_commit_settings(struct ssb_bus *bus);
25
61e115a5
MB		 26static inline
27u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
28{
29 return ssb_read32(pc->dev, offset);
30}
31
32static inline
33void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
34{
35 ssb_write32(pc->dev, offset, value);
36}
37
7cb44615
MB		 38static inline
39u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
40{
41 return ssb_read16(pc->dev, offset);
42}
43
44static inline
45void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
46{
47 ssb_write16(pc->dev, offset, value);
48}
49
61e115a5
MB		 50/**************************************************
51 * Code for hostmode operation.
52 **************************************************/
53
54#ifdef CONFIG_SSB_PCICORE_HOSTMODE
55
56#include <asm/paccess.h>
57/* Probe a 32bit value on the bus and catch bus exceptions.
58 * Returns nonzero on a bus exception.
59 * This is MIPS specific */
60#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
61
62/* Assume one-hot slot wiring */
63#define SSB_PCI_SLOT_MAX 16
64
65/* Global lock is OK, as we won't have more than one extpci anyway. */
66static DEFINE_SPINLOCK(cfgspace_lock);
67/* Core to access the external PCI config space. Can only have one. */
68static struct ssb_pcicore *extpci_core;
69
61e115a5
MB		 70
71static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
72 unsigned int bus, unsigned int dev,
73 unsigned int func, unsigned int off)
74{
75 u32 addr = 0;
76 u32 tmp;
77
7cb44615
MB		 78 /* We do only have one cardbus device behind the bridge. */
79 if (pc->cardbusmode && (dev >= 1))
61e115a5 80 goto out;
7cb44615 81
61e115a5
MB		 82 if (bus == 0) {
83 /* Type 0 transaction */
84 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
85 goto out;
86 /* Slide the window */
87 tmp = SSB_PCICORE_SBTOPCI_CFG0;
88 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
89 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
90 /* Calculate the address */
91 addr = SSB_PCI_CFG;
92 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
93 addr |= (func << 8);
94 addr |= (off & ~3);
95 } else {
96 /* Type 1 transaction */
97 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
98 SSB_PCICORE_SBTOPCI_CFG1);
99 /* Calculate the address */
100 addr = SSB_PCI_CFG;
101 addr |= (bus << 16);
102 addr |= (dev << 11);
103 addr |= (func << 8);
104 addr |= (off & ~3);
105 }
106out:
107 return addr;
108}
109
110static int ssb_extpci_read_config(struct ssb_pcicore *pc,
111 unsigned int bus, unsigned int dev,
112 unsigned int func, unsigned int off,
113 void *buf, int len)
114{
115 int err = -EINVAL;
116 u32 addr, val;
117 void __iomem *mmio;
118
119 SSB_WARN_ON(!pc->hostmode);
120 if (unlikely(len != 1 && len != 2 && len != 4))
121 goto out;
122 addr = get_cfgspace_addr(pc, bus, dev, func, off);
123 if (unlikely(!addr))
124 goto out;
125 err = -ENOMEM;
126 mmio = ioremap_nocache(addr, len);
127 if (!mmio)
128 goto out;
129
130 if (mips_busprobe32(val, mmio)) {
131 val = 0xffffffff;
132 goto unmap;
133 }
134
135 val = readl(mmio);
136 val >>= (8 * (off & 3));
137
138 switch (len) {
139 case 1:
140 *((u8 *)buf) = (u8)val;
141 break;
142 case 2:
143 *((u16 *)buf) = (u16)val;
144 break;
145 case 4:
146 *((u32 *)buf) = (u32)val;
147 break;
148 }
149 err = 0;
150unmap:
151 iounmap(mmio);
152out:
153 return err;
154}
155
156static int ssb_extpci_write_config(struct ssb_pcicore *pc,
157 unsigned int bus, unsigned int dev,
158 unsigned int func, unsigned int off,
159 const void *buf, int len)
160{
161 int err = -EINVAL;
162 u32 addr, val = 0;
163 void __iomem *mmio;
164
165 SSB_WARN_ON(!pc->hostmode);
166 if (unlikely(len != 1 && len != 2 && len != 4))
167 goto out;
168 addr = get_cfgspace_addr(pc, bus, dev, func, off);
169 if (unlikely(!addr))
170 goto out;
171 err = -ENOMEM;
172 mmio = ioremap_nocache(addr, len);
173 if (!mmio)
174 goto out;
175
176 if (mips_busprobe32(val, mmio)) {
177 val = 0xffffffff;
178 goto unmap;
179 }
180
181 switch (len) {
182 case 1:
183 val = readl(mmio);
184 val &= ~(0xFF << (8 * (off & 3)));
185 val |= *((const u8 *)buf) << (8 * (off & 3));
186 break;
187 case 2:
188 val = readl(mmio);
189 val &= ~(0xFFFF << (8 * (off & 3)));
190 val |= *((const u16 *)buf) << (8 * (off & 3));
191 break;
192 case 4:
193 val = *((const u32 *)buf);
194 break;
195 }
196 writel(val, mmio);
197
198 err = 0;
199unmap:
200 iounmap(mmio);
201out:
202 return err;
203}
204
205static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
206 int reg, int size, u32 *val)
207{
208 unsigned long flags;
209 int err;
210
211 spin_lock_irqsave(&cfgspace_lock, flags);
212 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
213 PCI_FUNC(devfn), reg, val, size);
214 spin_unlock_irqrestore(&cfgspace_lock, flags);
215
216 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
217}
218
219static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
220 int reg, int size, u32 val)
221{
222 unsigned long flags;
223 int err;
224
225 spin_lock_irqsave(&cfgspace_lock, flags);
226 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
227 PCI_FUNC(devfn), reg, &val, size);
228 spin_unlock_irqrestore(&cfgspace_lock, flags);
229
230 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
231}
232
233static struct pci_ops ssb_pcicore_pciops = {
234 .read = ssb_pcicore_read_config,
235 .write = ssb_pcicore_write_config,
236};
237
238static struct resource ssb_pcicore_mem_resource = {
239 .name = "SSB PCIcore external memory",
240 .start = SSB_PCI_DMA,
241 .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
fc71acc8 242 .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
61e115a5
MB		 243};
244
245static struct resource ssb_pcicore_io_resource = {
246 .name = "SSB PCIcore external I/O",
247 .start = 0x100,
248 .end = 0x7FF,
fc71acc8 249 .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
61e115a5
MB		 250};
251
252static struct pci_controller ssb_pcicore_controller = {
253 .pci_ops = &ssb_pcicore_pciops,
254 .io_resource = &ssb_pcicore_io_resource,
255 .mem_resource = &ssb_pcicore_mem_resource,
61e115a5
MB		 256};
257
aab547ce
MB		 258/* This function is called when doing a pci_enable_device().
259 * We must first check if the device is a device on the PCI-core bridge. */
260int ssb_pcicore_plat_dev_init(struct pci_dev *d)
261{
aab547ce
MB		 262 if (d->bus->ops != &ssb_pcicore_pciops) {
263 /* This is not a device on the PCI-core bridge. */
264 return -ENODEV;
265 }
266
267 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
268 pci_name(d));
269
aab547ce
MB		 270 /* Fix up interrupt lines */
271 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
272 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
273
274 return 0;
275}
276
277/* Early PCI fixup for a device on the PCI-core bridge. */
278static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
279{
280 u8 lat;
281
282 if (dev->bus->ops != &ssb_pcicore_pciops) {
283 /* This is not a device on the PCI-core bridge. */
284 return;
285 }
286 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
287 return;
288
289 ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
290
291 /* Enable PCI bridge bus mastering and memory space */
292 pci_set_master(dev);
293 if (pcibios_enable_device(dev, ~0) < 0) {
294 ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
295 return;
296 }
297
298 /* Enable PCI bridge BAR1 prefetch and burst */
299 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
300
301 /* Make sure our latency is high enough to handle the devices behind us */
302 lat = 168;
303 ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
304 pci_name(dev), lat);
305 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
306}
307DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
308
309/* PCI device IRQ mapping. */
310int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
311{
312 if (dev->bus->ops != &ssb_pcicore_pciops) {
313 /* This is not a device on the PCI-core bridge. */
314 return -ENODEV;
315 }
316 return ssb_mips_irq(extpci_core->dev) + 2;
317}
318
61e115a5
MB		 319static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
320{
321 u32 val;
322
323 if (WARN_ON(extpci_core))
324 return;
325 extpci_core = pc;
326
327 ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
328 /* Reset devices on the external PCI bus */
329 val = SSB_PCICORE_CTL_RST_OE;
330 val |= SSB_PCICORE_CTL_CLK_OE;
331 pcicore_write32(pc, SSB_PCICORE_CTL, val);
332 val |= SSB_PCICORE_CTL_CLK; /* Clock on */
333 pcicore_write32(pc, SSB_PCICORE_CTL, val);
334 udelay(150); /* Assertion time demanded by the PCI standard */
335 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
336 pcicore_write32(pc, SSB_PCICORE_CTL, val);
337 val = SSB_PCICORE_ARBCTL_INTERN;
338 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
339 udelay(1); /* Assertion time demanded by the PCI standard */
340
7cb44615
MB		 341 if (pc->dev->bus->has_cardbus_slot) {
342 ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
343 pc->cardbusmode = 1;
344 /* GPIO 1 resets the bridge */
345 ssb_gpio_out(pc->dev->bus, 1, 1);
346 ssb_gpio_outen(pc->dev->bus, 1, 1);
347 pcicore_write16(pc, SSB_PCICORE_SPROM(0),
348 pcicore_read16(pc, SSB_PCICORE_SPROM(0))
349 | 0x0400);
350 }
61e115a5
MB		 351
352 /* 64MB I/O window */
353 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
354 SSB_PCICORE_SBTOPCI_IO);
355 /* 64MB config space */
356 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
357 SSB_PCICORE_SBTOPCI_CFG0);
358 /* 1GB memory window */
359 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
360 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
361
362 /* Enable PCI bridge BAR0 prefetch and burst */
363 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
364 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
365 /* Clear error conditions */
366 val = 0;
367 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
368
369 /* Enable PCI interrupts */
370 pcicore_write32(pc, SSB_PCICORE_IMASK,
371 SSB_PCICORE_IMASK_INTA);
372
373 /* Ok, ready to run, register it to the system.
374 * The following needs change, if we want to port hostmode
375 * to non-MIPS platform. */
fc71acc8
MB		 376 ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
377 set_io_port_base(ssb_pcicore_controller.io_map_base);
61e115a5
MB		 378 /* Give some time to the PCI controller to configure itself with the new
379 * values. Not waiting at this point causes crashes of the machine. */
380 mdelay(10);
381 register_pci_controller(&ssb_pcicore_controller);
382}
383
384static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
385{
386 struct ssb_bus *bus = pc->dev->bus;
387 u16 chipid_top;
388 u32 tmp;
389
390 chipid_top = (bus->chip_id & 0xFF00);
391 if (chipid_top != 0x4700 &&
392 chipid_top != 0x5300)
393 return 0;
394
2d8d4fdf 395 if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
61e115a5
MB		 396 return 0;
397
398 /* The 200-pin BCM4712 package does not bond out PCI. Even when
399 * PCI is bonded out, some boards may leave the pins floating. */
400 if (bus->chip_id == 0x4712) {
401 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
402 return 0;
403 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
404 return 0;
405 }
406 if (bus->chip_id == 0x5350)
407 return 0;
408
409 return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
410}
411#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
412
ccc7c28a
RM		 413/**************************************************
414 * Workarounds.
415 **************************************************/
416
417static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
418{
419 return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
420}
421
422static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
423{
424 const u8 serdes_pll_device = 0x1D;
425 const u8 serdes_rx_device = 0x1F;
426 u16 tmp;
427
428 ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
429 ssb_pcicore_polarity_workaround(pc));
430 tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
431 if (tmp & 0x4000)
432 ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
433}
61e115a5 434
6e914101
RM		 435static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
436{
437 struct ssb_device *pdev = pc->dev;
438 struct ssb_bus *bus = pdev->bus;
439 u32 tmp;
440
441 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
442 tmp |= SSB_PCICORE_SBTOPCI_PREF;
443 tmp |= SSB_PCICORE_SBTOPCI_BURST;
444 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
445
446 if (pdev->id.revision < 5) {
447 tmp = ssb_read32(pdev, SSB_IMCFGLO);
448 tmp &= ~SSB_IMCFGLO_SERTO;
449 tmp |= 2;
450 tmp &= ~SSB_IMCFGLO_REQTO;
451 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
452 ssb_write32(pdev, SSB_IMCFGLO, tmp);
453 ssb_commit_settings(bus);
454 } else if (pdev->id.revision >= 11) {
455 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
456 tmp |= SSB_PCICORE_SBTOPCI_MRM;
457 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
458 }
459}
460
461static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
462{
463 struct ssb_device *pdev = pc->dev;
464 u32 tmp;
465
466 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
467 /* TLP Workaround register. */
468 tmp = ssb_pcie_read(pc, 0x4);
469 tmp |= 0x8;
470 ssb_pcie_write(pc, 0x4, tmp);
471 }
472 if (pdev->id.revision == 0) {
473 const u8 serdes_rx_device = 0x1F;
474
475 ssb_pcie_mdio_write(pc, serdes_rx_device,
476 2 /* Timer */, 0x8128);
477 ssb_pcie_mdio_write(pc, serdes_rx_device,
478 6 /* CDR */, 0x0100);
479 ssb_pcie_mdio_write(pc, serdes_rx_device,
480 7 /* CDR BW */, 0x1466);
481 } else if (pdev->id.revision == 1) {
482 /* DLLP Link Control register. */
483 tmp = ssb_pcie_read(pc, 0x100);
484 tmp |= 0x40;
485 ssb_pcie_write(pc, 0x100, tmp);
486 }
487}
488
61e115a5
MB		 489/**************************************************
490 * Generic and Clientmode operation code.
491 **************************************************/
492
493static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
494{
495 /* Disable PCI interrupts. */
496 ssb_write32(pc->dev, SSB_INTVEC, 0);
497}
498
499void ssb_pcicore_init(struct ssb_pcicore *pc)
500{
501 struct ssb_device *dev = pc->dev;
61e115a5
MB		 502
503 if (!dev)
504 return;
61e115a5
MB		 505 if (!ssb_device_is_enabled(dev))
506 ssb_device_enable(dev, 0);
507
508#ifdef CONFIG_SSB_PCICORE_HOSTMODE
509 pc->hostmode = pcicore_is_in_hostmode(pc);
510 if (pc->hostmode)
511 ssb_pcicore_init_hostmode(pc);
512#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
513 if (!pc->hostmode)
514 ssb_pcicore_init_clientmode(pc);
ccc7c28a
RM		 515
516 ssb_pcicore_serdes_workaround(pc);
61e115a5
MB		 517}
518
519static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
520{
521 pcicore_write32(pc, 0x130, address);
522 return pcicore_read32(pc, 0x134);
523}
524
525static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
526{
527 pcicore_write32(pc, 0x130, address);
528 pcicore_write32(pc, 0x134, data);
529}
530
1b1c7acd
RM		 531static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
532{
533 const u16 mdio_control = 0x128;
534 const u16 mdio_data = 0x12C;
535 u32 v;
536 int i;
537
538 v = (1 << 30); /* Start of Transaction */
539 v |= (1 << 28); /* Write Transaction */
540 v |= (1 << 17); /* Turnaround */
541 v |= (0x1F << 18);
542 v |= (phy << 4);
543 pcicore_write32(pc, mdio_data, v);
544
545 udelay(10);
546 for (i = 0; i < 200; i++) {
547 v = pcicore_read32(pc, mdio_control);
548 if (v & 0x100 /* Trans complete */)
549 break;
550 msleep(1);
551 }
552}
553
ba91d1a1
RM		 554static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
555{
556 const u16 mdio_control = 0x128;
557 const u16 mdio_data = 0x12C;
558 int max_retries = 10;
559 u16 ret = 0;
560 u32 v;
561 int i;
562
563 v = 0x80; /* Enable Preamble Sequence */
564 v |= 0x2; /* MDIO Clock Divisor */
565 pcicore_write32(pc, mdio_control, v);
566
567 if (pc->dev->id.revision >= 10) {
568 max_retries = 200;
569 ssb_pcie_mdio_set_phy(pc, device);
570 }
571
572 v = (1 << 30); /* Start of Transaction */
573 v |= (1 << 29); /* Read Transaction */
574 v |= (1 << 17); /* Turnaround */
575 if (pc->dev->id.revision < 10)
576 v |= (u32)device << 22;
577 v |= (u32)address << 18;
578 pcicore_write32(pc, mdio_data, v);
579 /* Wait for the device to complete the transaction */
580 udelay(10);
9be1cb39 581 for (i = 0; i < max_retries; i++) {
ba91d1a1
RM		 582 v = pcicore_read32(pc, mdio_control);
583 if (v & 0x100 /* Trans complete */) {
584 udelay(10);
585 ret = pcicore_read32(pc, mdio_data);
586 break;
587 }
588 msleep(1);
589 }
590 pcicore_write32(pc, mdio_control, 0);
591 return ret;
592}
ba91d1a1 593
61e115a5
MB		 594static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
595 u8 address, u16 data)
596{
597 const u16 mdio_control = 0x128;
598 const u16 mdio_data = 0x12C;
1b1c7acd 599 int max_retries = 10;
61e115a5
MB		 600 u32 v;
601 int i;
602
603 v = 0x80; /* Enable Preamble Sequence */
604 v |= 0x2; /* MDIO Clock Divisor */
605 pcicore_write32(pc, mdio_control, v);
606
1b1c7acd
RM		 607 if (pc->dev->id.revision >= 10) {
608 max_retries = 200;
609 ssb_pcie_mdio_set_phy(pc, device);
610 }
611
61e115a5
MB		 612 v = (1 << 30); /* Start of Transaction */
613 v |= (1 << 28); /* Write Transaction */
614 v |= (1 << 17); /* Turnaround */
1b1c7acd
RM		 615 if (pc->dev->id.revision < 10)
616 v |= (u32)device << 22;
61e115a5
MB		 617 v |= (u32)address << 18;
618 v |= data;
619 pcicore_write32(pc, mdio_data, v);
620 /* Wait for the device to complete the transaction */
621 udelay(10);
1b1c7acd 622 for (i = 0; i < max_retries; i++) {
61e115a5
MB		 623 v = pcicore_read32(pc, mdio_control);
624 if (v & 0x100 /* Trans complete */)
625 break;
626 msleep(1);
627 }
628 pcicore_write32(pc, mdio_control, 0);
629}
630
631static void ssb_broadcast_value(struct ssb_device *dev,
632 u32 address, u32 data)
633{
634 /* This is used for both, PCI and ChipCommon core, so be careful. */
635 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
636 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
637
638 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
639 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
640 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
641 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
642}
643
644static void ssb_commit_settings(struct ssb_bus *bus)
645{
646 struct ssb_device *dev;
647
648 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
649 if (WARN_ON(!dev))
650 return;
651 /* This forces an update of the cached registers. */
652 ssb_broadcast_value(dev, 0xFD8, 0);
653}
654
655int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
656 struct ssb_device *dev)
657{
658 struct ssb_device *pdev = pc->dev;
659 struct ssb_bus *bus;
660 int err = 0;
661 u32 tmp;
662
9e095a68
MB		 663 if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
664 /* This SSB device is not on a PCI host-bus. So the IRQs are
665 * not routed through the PCI core.
666 * So we must not enable routing through the PCI core. */
667 goto out;
668 }
669
61e115a5
MB		 670 if (!pdev)
671 goto out;
672 bus = pdev->bus;
673
a3bafeed
MB		 674 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
675
61e115a5 676 /* Enable interrupts for this device. */
8b45499c 677 if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
61e115a5
MB		 678 u32 coremask;
679
680 /* Calculate the "coremask" for the device. */
681 coremask = (1 << dev->core_index);
682
8b45499c 683 SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
61e115a5
MB		 684 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
685 if (err)
686 goto out;
687 tmp |= coremask << 8;
688 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
689 if (err)
690 goto out;
691 } else {
692 u32 intvec;
693
694 intvec = ssb_read32(pdev, SSB_INTVEC);
51e8b885
MB		 695 tmp = ssb_read32(dev, SSB_TPSFLAG);
696 tmp &= SSB_TPSFLAG_BPFLAG;
697 intvec |= (1 << tmp);
61e115a5
MB		 698 ssb_write32(pdev, SSB_INTVEC, intvec);
699 }
700
701 /* Setup PCIcore operation. */
702 if (pc->setup_done)
703 goto out;
704 if (pdev->id.coreid == SSB_DEV_PCI) {
6e914101 705 ssb_pcicore_pci_setup_workarounds(pc);
61e115a5
MB		 706 } else {
707 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
6e914101 708 ssb_pcicore_pcie_setup_workarounds(pc);
61e115a5
MB		 709 }
710 pc->setup_done = 1;
711out:
712 return err;
713}
714EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
kernel source for telekom puls (alcatel/mediatek)