[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ssb / driver_mipscore.c

/*
 * Sonics Silicon Backplane
 * Broadcom MIPS core driver
 *
 * Copyright 2005, Broadcom Corporation
 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include <linux/ssb/ssb.h>

#include <linux/mtd/physmap.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/time.h>

#include "ssb_private.h"

static const char * const part_probes[] = { "bcm47xxpart", NULL };

static struct physmap_flash_data ssb_pflash_data = {
	.part_probe_types	= part_probes,
};

static struct resource ssb_pflash_resource = {
	.name	= "ssb_pflash",
	.flags  = IORESOURCE_MEM,
};

struct platform_device ssb_pflash_dev = {
	.name		= "physmap-flash",
	.dev		= {
		.platform_data  = &ssb_pflash_data,
	},
	.resource	= &ssb_pflash_resource,
	.num_resources	= 1,
};

static inline u32 mips_read32(struct ssb_mipscore *mcore,
			      u16 offset)
{
	return ssb_read32(mcore->dev, offset);
}

static inline void mips_write32(struct ssb_mipscore *mcore,
				u16 offset,
				u32 value)
{
	ssb_write32(mcore->dev, offset, value);
}

static const u32 ipsflag_irq_mask[] = {
	0,
	SSB_IPSFLAG_IRQ1,
	SSB_IPSFLAG_IRQ2,
	SSB_IPSFLAG_IRQ3,
	SSB_IPSFLAG_IRQ4,
};

static const u32 ipsflag_irq_shift[] = {
	0,
	SSB_IPSFLAG_IRQ1_SHIFT,
	SSB_IPSFLAG_IRQ2_SHIFT,
	SSB_IPSFLAG_IRQ3_SHIFT,
	SSB_IPSFLAG_IRQ4_SHIFT,
};

static inline u32 ssb_irqflag(struct ssb_device *dev)
{
	u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
	if (tpsflag)
		return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
	else
		/* not irq supported */
		return 0x3f;
}

static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
{
	struct ssb_bus *bus = rdev->bus;
	int i;
	for (i = 0; i < bus->nr_devices; i++) {
		struct ssb_device *dev;
		dev = &(bus->devices[i]);
		if (ssb_irqflag(dev) == irqflag)
			return dev;
	}
	return NULL;
}

/* Get the MIPS IRQ assignment for a specified device.
 * If unassigned, 0 is returned.
 * If disabled, 5 is returned.
 * If not supported, 6 is returned.
 */
unsigned int ssb_mips_irq(struct ssb_device *dev)
{
	struct ssb_bus *bus = dev->bus;
	struct ssb_device *mdev = bus->mipscore.dev;
	u32 irqflag;
	u32 ipsflag;
	u32 tmp;
	unsigned int irq;

	irqflag = ssb_irqflag(dev);
	if (irqflag == 0x3f)
		return 6;
	ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
	for (irq = 1; irq <= 4; irq++) {
		tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
		if (tmp == irqflag)
			break;
	}
	if (irq	== 5) {
		if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
			irq = 0;
	}

	return irq;
}

static void clear_irq(struct ssb_bus *bus, unsigned int irq)
{
	struct ssb_device *dev = bus->mipscore.dev;

	/* Clear the IRQ in the MIPScore backplane registers */
	if (irq == 0) {
		ssb_write32(dev, SSB_INTVEC, 0);
	} else {
		ssb_write32(dev, SSB_IPSFLAG,
			    ssb_read32(dev, SSB_IPSFLAG) |
			    ipsflag_irq_mask[irq]);
	}
}

static void set_irq(struct ssb_device *dev, unsigned int irq)
{
	unsigned int oldirq = ssb_mips_irq(dev);
	struct ssb_bus *bus = dev->bus;
	struct ssb_device *mdev = bus->mipscore.dev;
	u32 irqflag = ssb_irqflag(dev);

	BUG_ON(oldirq == 6);

	dev->irq = irq + 2;

	/* clear the old irq */
	if (oldirq == 0)
		ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
	else if (oldirq != 5)
		clear_irq(bus, oldirq);

	/* assign the new one */
	if (irq == 0) {
		ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
	} else {
		u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
		if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
			u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
			struct ssb_device *olddev = find_device(dev, oldipsflag);
			if (olddev)
				set_irq(olddev, 0);
		}
		irqflag <<= ipsflag_irq_shift[irq];
		irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
		ssb_write32(mdev, SSB_IPSFLAG, irqflag);
	}
	ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
		dev->id.coreid, oldirq+2, irq+2);
}

static void print_irq(struct ssb_device *dev, unsigned int irq)
{
	static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
	ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
		dev->id.coreid,
		irq_name[0], irq == 0 ? "*" : " ",
		irq_name[1], irq == 1 ? "*" : " ",
		irq_name[2], irq == 2 ? "*" : " ",
		irq_name[3], irq == 3 ? "*" : " ",
		irq_name[4], irq == 4 ? "*" : " ",
		irq_name[5], irq == 5 ? "*" : " ",
		irq_name[6], irq == 6 ? "*" : " ");
}

static void dump_irq(struct ssb_bus *bus)
{
	int i;
	for (i = 0; i < bus->nr_devices; i++) {
		struct ssb_device *dev;
		dev = &(bus->devices[i]);
		print_irq(dev, ssb_mips_irq(dev));
	}
}

static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus = mcore->dev->bus;

	if (ssb_extif_available(&bus->extif))
		mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
	else if (ssb_chipco_available(&bus->chipco))
		mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
	else
		mcore->nr_serial_ports = 0;
}

static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus = mcore->dev->bus;
	struct ssb_pflash *pflash = &mcore->pflash;

	/* When there is no chipcommon on the bus there is 4MB flash */
	if (!ssb_chipco_available(&bus->chipco)) {
		pflash->present = true;
		pflash->buswidth = 2;
		pflash->window = SSB_FLASH1;
		pflash->window_size = SSB_FLASH1_SZ;
		goto ssb_pflash;
	}

	/* There is ChipCommon, so use it to read info about flash */
	switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
	case SSB_CHIPCO_FLASHT_STSER:
	case SSB_CHIPCO_FLASHT_ATSER:
		pr_debug("Found serial flash\n");
		ssb_sflash_init(&bus->chipco);
		break;
	case SSB_CHIPCO_FLASHT_PARA:
		pr_debug("Found parallel flash\n");
		pflash->present = true;
		pflash->window = SSB_FLASH2;
		pflash->window_size = SSB_FLASH2_SZ;
		if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
		               & SSB_CHIPCO_CFG_DS16) == 0)
			pflash->buswidth = 1;
		else
			pflash->buswidth = 2;
		break;
	}

ssb_pflash:
	if (pflash->present) {
		ssb_pflash_data.width = pflash->buswidth;
		ssb_pflash_resource.start = pflash->window;
		ssb_pflash_resource.end = pflash->window + pflash->window_size;
	}
}

u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus = mcore->dev->bus;
	u32 pll_type, n, m, rate = 0;

	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
		return ssb_pmu_get_cpu_clock(&bus->chipco);

	if (ssb_extif_available(&bus->extif)) {
		ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
	} else if (ssb_chipco_available(&bus->chipco)) {
		ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
	} else
		return 0;

	if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
		rate = 200000000;
	} else {
		rate = ssb_calc_clock_rate(pll_type, n, m);
	}

	if (pll_type == SSB_PLLTYPE_6) {
		rate *= 2;
	}

	return rate;
}

void ssb_mipscore_init(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus;
	struct ssb_device *dev;
	unsigned long hz, ns;
	unsigned int irq, i;

	if (!mcore->dev)
		return; /* We don't have a MIPS core */

	ssb_dbg("Initializing MIPS core...\n");

	bus = mcore->dev->bus;
	hz = ssb_clockspeed(bus);
	if (!hz)
		hz = 100000000;
	ns = 1000000000 / hz;

	if (ssb_extif_available(&bus->extif))
		ssb_extif_timing_init(&bus->extif, ns);
	else if (ssb_chipco_available(&bus->chipco))
		ssb_chipco_timing_init(&bus->chipco, ns);

	/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
	for (irq = 2, i = 0; i < bus->nr_devices; i++) {
		int mips_irq;
		dev = &(bus->devices[i]);
		mips_irq = ssb_mips_irq(dev);
		if (mips_irq > 4)
			dev->irq = 0;
		else
			dev->irq = mips_irq + 2;
		if (dev->irq > 5)
			continue;
		switch (dev->id.coreid) {
		case SSB_DEV_USB11_HOST:
			/* shouldn't need a separate irq line for non-4710, most of them have a proper
			 * external usb controller on the pci */
			if ((bus->chip_id == 0x4710) && (irq <= 4)) {
				set_irq(dev, irq++);
			}
			break;
		case SSB_DEV_PCI:
		case SSB_DEV_ETHERNET:
		case SSB_DEV_ETHERNET_GBIT:
		case SSB_DEV_80211:
		case SSB_DEV_USB20_HOST:
			/* These devices get their own IRQ line if available, the rest goes on IRQ0 */
			if (irq <= 4) {
				set_irq(dev, irq++);
				break;
			}
			/* fallthrough */
		case SSB_DEV_EXTIF:
			set_irq(dev, 0);
			break;
		}
	}
	ssb_dbg("after irq reconfiguration\n");
	dump_irq(bus);

	ssb_mips_serial_init(mcore);
	ssb_mips_flash_detect(mcore);
}
Commit	Line	Data
61e115a5 MB	1	/*
	2	* Sonics Silicon Backplane
	3	* Broadcom MIPS core driver
	4	*
	5	* Copyright 2005, Broadcom Corporation
eb032b98	6	* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
61e115a5 MB	7	*
	8	* Licensed under the GNU/GPL. See COPYING for details.
	9	*/
	10
	11	#include <linux/ssb/ssb.h>
	12
c7a4a9e3	13	#include <linux/mtd/physmap.h>
61e115a5 MB	14	#include <linux/serial.h>
	15	#include <linux/serial_core.h>
	16	#include <linux/serial_reg.h>
	17	#include <linux/time.h>
	18
	19	#include "ssb_private.h"
	20
255e9fd4	21	static const char * const part_probes[] = { "bcm47xxpart", NULL };
c7a4a9e3 RM	22
	23	static struct physmap_flash_data ssb_pflash_data = {
	24	.part_probe_types = part_probes,
	25	};
	26
	27	static struct resource ssb_pflash_resource = {
	28	.name = "ssb_pflash",
	29	.flags = IORESOURCE_MEM,
	30	};
	31
	32	struct platform_device ssb_pflash_dev = {
	33	.name = "physmap-flash",
	34	.dev = {
	35	.platform_data = &ssb_pflash_data,
	36	},
	37	.resource = &ssb_pflash_resource,
	38	.num_resources = 1,
	39	};
61e115a5 MB	40
	41	static inline u32 mips_read32(struct ssb_mipscore *mcore,
	42	u16 offset)
	43	{
	44	return ssb_read32(mcore->dev, offset);
	45	}
	46
	47	static inline void mips_write32(struct ssb_mipscore *mcore,
	48	u16 offset,
	49	u32 value)
	50	{
	51	ssb_write32(mcore->dev, offset, value);
	52	}
	53
	54	static const u32 ipsflag_irq_mask[] = {
	55	0,
	56	SSB_IPSFLAG_IRQ1,
	57	SSB_IPSFLAG_IRQ2,
	58	SSB_IPSFLAG_IRQ3,
	59	SSB_IPSFLAG_IRQ4,
	60	};
	61
	62	static const u32 ipsflag_irq_shift[] = {
	63	0,
	64	SSB_IPSFLAG_IRQ1_SHIFT,
	65	SSB_IPSFLAG_IRQ2_SHIFT,
	66	SSB_IPSFLAG_IRQ3_SHIFT,
	67	SSB_IPSFLAG_IRQ4_SHIFT,
	68	};
	69
	70	static inline u32 ssb_irqflag(struct ssb_device *dev)
	71	{
ea4bbfd0 MC	72	u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
	73	if (tpsflag)
	74	return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
	75	else
	76	/* not irq supported */
	77	return 0x3f;
	78	}
	79
	80	static struct ssb_device find_device(struct ssb_device rdev, int irqflag)
	81	{
	82	struct ssb_bus *bus = rdev->bus;
	83	int i;
	84	for (i = 0; i < bus->nr_devices; i++) {
	85	struct ssb_device *dev;
	86	dev = &(bus->devices[i]);
	87	if (ssb_irqflag(dev) == irqflag)
	88	return dev;
	89	}
	90	return NULL;
61e115a5 MB	91	}
	92
	93	/* Get the MIPS IRQ assignment for a specified device.
	94	* If unassigned, 0 is returned.
ea4bbfd0 MC	95	* If disabled, 5 is returned.
ea4bbfd0 MC	96	* If not supported, 6 is returned.
61e115a5 MB	97	*/
	98	unsigned int ssb_mips_irq(struct ssb_device *dev)
	99	{
	100	struct ssb_bus *bus = dev->bus;
ea4bbfd0	101	struct ssb_device *mdev = bus->mipscore.dev;
61e115a5 MB	102	u32 irqflag;
	103	u32 ipsflag;
	104	u32 tmp;
	105	unsigned int irq;
	106
	107	irqflag = ssb_irqflag(dev);
ea4bbfd0 MC	108	if (irqflag == 0x3f)
ea4bbfd0 MC	109	return 6;
61e115a5 MB	110	ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
	111	for (irq = 1; irq <= 4; irq++) {
	112	tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
	113	if (tmp == irqflag)
	114	break;
	115	}
ea4bbfd0 MC	116	if (irq == 5) {
	117	if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
	118	irq = 0;
	119	}
61e115a5 MB	120
	121	return irq;
	122	}
	123
	124	static void clear_irq(struct ssb_bus *bus, unsigned int irq)
	125	{
	126	struct ssb_device *dev = bus->mipscore.dev;
	127
	128	/* Clear the IRQ in the MIPScore backplane registers */
	129	if (irq == 0) {
	130	ssb_write32(dev, SSB_INTVEC, 0);
	131	} else {
	132	ssb_write32(dev, SSB_IPSFLAG,
	133	ssb_read32(dev, SSB_IPSFLAG) \|
	134	ipsflag_irq_mask[irq]);
	135	}
	136	}
	137
	138	static void set_irq(struct ssb_device *dev, unsigned int irq)
	139	{
	140	unsigned int oldirq = ssb_mips_irq(dev);
	141	struct ssb_bus *bus = dev->bus;
	142	struct ssb_device *mdev = bus->mipscore.dev;
	143	u32 irqflag = ssb_irqflag(dev);
	144
ea4bbfd0 MC	145	BUG_ON(oldirq == 6);
ea4bbfd0 MC	146
61e115a5 MB	147	dev->irq = irq + 2;
61e115a5 MB	148
61e115a5 MB	149	/* clear the old irq */
	150	if (oldirq == 0)
	151	ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
ea4bbfd0	152	else if (oldirq != 5)
61e115a5 MB	153	clear_irq(bus, oldirq);
	154
	155	/* assign the new one */
2633da23 MB	156	if (irq == 0) {
	157	ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) \| ssb_read32(mdev, SSB_INTVEC)));
	158	} else {
ea4bbfd0 MC	159	u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
	160	if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
	161	u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
	162	struct ssb_device *olddev = find_device(dev, oldipsflag);
	163	if (olddev)
	164	set_irq(olddev, 0);
	165	}
2633da23	166	irqflag <<= ipsflag_irq_shift[irq];
ea4bbfd0	167	irqflag \|= (ipsflag & ~ipsflag_irq_mask[irq]);
2633da23 MB	168	ssb_write32(mdev, SSB_IPSFLAG, irqflag);
2633da23 MB	169	}
33a606ac JP	170	ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
33a606ac JP	171	dev->id.coreid, oldirq+2, irq+2);
ea4bbfd0 MC	172	}
	173
	174	static void print_irq(struct ssb_device *dev, unsigned int irq)
	175	{
ea4bbfd0	176	static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
33a606ac JP	177	ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
	178	dev->id.coreid,
	179	irq_name[0], irq == 0 ? "*" : " ",
	180	irq_name[1], irq == 1 ? "*" : " ",
	181	irq_name[2], irq == 2 ? "*" : " ",
	182	irq_name[3], irq == 3 ? "*" : " ",
	183	irq_name[4], irq == 4 ? "*" : " ",
	184	irq_name[5], irq == 5 ? "*" : " ",
	185	irq_name[6], irq == 6 ? "*" : " ");
ea4bbfd0 MC	186	}
	187
	188	static void dump_irq(struct ssb_bus *bus)
	189	{
	190	int i;
	191	for (i = 0; i < bus->nr_devices; i++) {
	192	struct ssb_device *dev;
	193	dev = &(bus->devices[i]);
	194	print_irq(dev, ssb_mips_irq(dev));
	195	}
61e115a5 MB	196	}
	197
	198	static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
	199	{
	200	struct ssb_bus *bus = mcore->dev->bus;
	201
0362063b	202	if (ssb_extif_available(&bus->extif))
61e115a5	203	mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
0362063b	204	else if (ssb_chipco_available(&bus->chipco))
61e115a5 MB	205	mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
	206	else
	207	mcore->nr_serial_ports = 0;
	208	}
	209
	210	static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
	211	{
	212	struct ssb_bus *bus = mcore->dev->bus;
f1ab57e3	213	struct ssb_pflash *pflash = &mcore->pflash;
61e115a5	214
902d9e0f	215	/* When there is no chipcommon on the bus there is 4MB flash */
0362063b	216	if (!ssb_chipco_available(&bus->chipco)) {
f1ab57e3 RM	217	pflash->present = true;
	218	pflash->buswidth = 2;
	219	pflash->window = SSB_FLASH1;
	220	pflash->window_size = SSB_FLASH1_SZ;
c7a4a9e3	221	goto ssb_pflash;
902d9e0f RM	222	}
	223
	224	/* There is ChipCommon, so use it to read info about flash */
	225	switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
	226	case SSB_CHIPCO_FLASHT_STSER:
	227	case SSB_CHIPCO_FLASHT_ATSER:
72a525cb RM	228	pr_debug("Found serial flash\n");
72a525cb RM	229	ssb_sflash_init(&bus->chipco);
902d9e0f RM	230	break;
	231	case SSB_CHIPCO_FLASHT_PARA:
	232	pr_debug("Found parallel flash\n");
f1ab57e3 RM	233	pflash->present = true;
	234	pflash->window = SSB_FLASH2;
	235	pflash->window_size = SSB_FLASH2_SZ;
61e115a5 MB	236	if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
61e115a5 MB	237	& SSB_CHIPCO_CFG_DS16) == 0)
f1ab57e3	238	pflash->buswidth = 1;
902d9e0f	239	else
f1ab57e3	240	pflash->buswidth = 2;
902d9e0f	241	break;
61e115a5	242	}
c7a4a9e3 RM	243
	244	ssb_pflash:
	245	if (pflash->present) {
	246	ssb_pflash_data.width = pflash->buswidth;
	247	ssb_pflash_resource.start = pflash->window;
	248	ssb_pflash_resource.end = pflash->window + pflash->window_size;
	249	}
61e115a5 MB	250	}
	251
	252	u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
	253	{
	254	struct ssb_bus *bus = mcore->dev->bus;
	255	u32 pll_type, n, m, rate = 0;
	256
d486a5b4 HM	257	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
	258	return ssb_pmu_get_cpu_clock(&bus->chipco);
	259
0362063b	260	if (ssb_extif_available(&bus->extif)) {
61e115a5	261	ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
0362063b	262	} else if (ssb_chipco_available(&bus->chipco)) {
61e115a5 MB	263	ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
	264	} else
	265	return 0;
	266
	267	if ((pll_type == SSB_PLLTYPE_5) \|\| (bus->chip_id == 0x5365)) {
	268	rate = 200000000;
	269	} else {
	270	rate = ssb_calc_clock_rate(pll_type, n, m);
	271	}
	272
	273	if (pll_type == SSB_PLLTYPE_6) {
	274	rate *= 2;
	275	}
	276
	277	return rate;
	278	}
	279
	280	void ssb_mipscore_init(struct ssb_mipscore *mcore)
	281	{
7007d00c	282	struct ssb_bus *bus;
61e115a5 MB	283	struct ssb_device *dev;
	284	unsigned long hz, ns;
	285	unsigned int irq, i;
	286
	287	if (!mcore->dev)
	288	return; /* We don't have a MIPS core */
	289
33a606ac	290	ssb_dbg("Initializing MIPS core...\n");
61e115a5	291
7007d00c	292	bus = mcore->dev->bus;
61e115a5 MB	293	hz = ssb_clockspeed(bus);
	294	if (!hz)
	295	hz = 100000000;
	296	ns = 1000000000 / hz;
	297
0362063b	298	if (ssb_extif_available(&bus->extif))
61e115a5	299	ssb_extif_timing_init(&bus->extif, ns);
0362063b	300	else if (ssb_chipco_available(&bus->chipco))
61e115a5 MB	301	ssb_chipco_timing_init(&bus->chipco, ns);
	302
	303	/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
	304	for (irq = 2, i = 0; i < bus->nr_devices; i++) {
ea4bbfd0	305	int mips_irq;
61e115a5	306	dev = &(bus->devices[i]);
ea4bbfd0 MC	307	mips_irq = ssb_mips_irq(dev);
	308	if (mips_irq > 4)
	309	dev->irq = 0;
	310	else
	311	dev->irq = mips_irq + 2;
	312	if (dev->irq > 5)
	313	continue;
61e115a5 MB	314	switch (dev->id.coreid) {
	315	case SSB_DEV_USB11_HOST:
	316	/* shouldn't need a separate irq line for non-4710, most of them have a proper
	317	* external usb controller on the pci */
	318	if ((bus->chip_id == 0x4710) && (irq <= 4)) {
	319	set_irq(dev, irq++);
61e115a5	320	}
ea4bbfd0	321	break;
61e115a5 MB	322	case SSB_DEV_PCI:
61e115a5 MB	323	case SSB_DEV_ETHERNET:
aab547ce	324	case SSB_DEV_ETHERNET_GBIT:
61e115a5 MB	325	case SSB_DEV_80211:
	326	case SSB_DEV_USB20_HOST:
	327	/* These devices get their own IRQ line if available, the rest goes on IRQ0 */
	328	if (irq <= 4) {
	329	set_irq(dev, irq++);
	330	break;
	331	}
83e34f03 JF	332	/* fallthrough */
	333	case SSB_DEV_EXTIF:
	334	set_irq(dev, 0);
	335	break;
61e115a5 MB	336	}
61e115a5 MB	337	}
33a606ac	338	ssb_dbg("after irq reconfiguration\n");
ea4bbfd0	339	dump_irq(bus);
61e115a5 MB	340
	341	ssb_mips_serial_init(mcore);
	342	ssb_mips_flash_detect(mcore);
	343	}