[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / orion_spi.c

/*
 * orion_spi.c -- Marvell Orion SPI controller driver
 *
 * Author: Shadi Ammouri <shadi@marvell.com>
 * Copyright (C) 2007-2008 Marvell Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/spi/orion_spi.h>
#include <asm/unaligned.h>

#define DRIVER_NAME			"orion_spi"

#define ORION_NUM_CHIPSELECTS		1 /* only one slave is supported*/
#define ORION_SPI_WAIT_RDY_MAX_LOOP	2000 /* in usec */

#define ORION_SPI_IF_CTRL_REG		0x00
#define ORION_SPI_IF_CONFIG_REG		0x04
#define ORION_SPI_DATA_OUT_REG		0x08
#define ORION_SPI_DATA_IN_REG		0x0c
#define ORION_SPI_INT_CAUSE_REG		0x10

#define ORION_SPI_IF_8_16_BIT_MODE	(1 << 5)
#define ORION_SPI_CLK_PRESCALE_MASK	0x1F

struct orion_spi {
	struct work_struct	work;

	/* Lock access to transfer list.	*/
	spinlock_t		lock;

	struct list_head	msg_queue;
	struct spi_master	*master;
	void __iomem		*base;
	unsigned int		max_speed;
	unsigned int		min_speed;
	struct orion_spi_info	*spi_info;
};

static struct workqueue_struct *orion_spi_wq;

static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
{
	return orion_spi->base + reg;
}

static inline void
orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
{
	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	u32 val;

	val = readl(reg_addr);
	val |= mask;
	writel(val, reg_addr);
}

static inline void
orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
{
	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	u32 val;

	val = readl(reg_addr);
	val &= ~mask;
	writel(val, reg_addr);
}

static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
{
	if (size == 16) {
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  ORION_SPI_IF_8_16_BIT_MODE);
	} else if (size == 8) {
		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  ORION_SPI_IF_8_16_BIT_MODE);
	} else {
		pr_debug("Bad bits per word value %d (only 8 or 16 are "
			 "allowed).\n", size);
		return -EINVAL;
	}

	return 0;
}

static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
{
	u32 tclk_hz;
	u32 rate;
	u32 prescale;
	u32 reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	tclk_hz = orion_spi->spi_info->tclk;

	/*
	 * the supported rates are: 4,6,8...30
	 * round up as we look for equal or less speed
	 */
	rate = DIV_ROUND_UP(tclk_hz, speed);
	rate = roundup(rate, 2);

	/* check if requested speed is too small */
	if (rate > 30)
		return -EINVAL;

	if (rate < 4)
		rate = 4;

	/* Convert the rate to SPI clock divisor value.	*/
	prescale = 0x10 + rate/2;

	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale);
	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));

	return 0;
}

/*
 * called only when no transfer is active on the bus
 */
static int
orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct orion_spi *orion_spi;
	unsigned int speed = spi->max_speed_hz;
	unsigned int bits_per_word = spi->bits_per_word;
	int	rc;

	orion_spi = spi_master_get_devdata(spi->master);

	if ((t != NULL) && t->speed_hz)
		speed = t->speed_hz;

	if ((t != NULL) && t->bits_per_word)
		bits_per_word = t->bits_per_word;

	rc = orion_spi_baudrate_set(spi, speed);
	if (rc)
		return rc;

	return orion_spi_set_transfer_size(orion_spi, bits_per_word);
}

static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
{
	if (enable)
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	else
		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
}

static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
{
	int i;

	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
		if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
			return 1;
		else
			udelay(1);
	}

	return -1;
}

static inline int
orion_spi_write_read_8bit(struct spi_device *spi,
			  const u8 **tx_buf, u8 **rx_buf)
{
	void __iomem *tx_reg, *rx_reg, *int_reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);
	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);

	/* clear the interrupt cause register */
	writel(0x0, int_reg);

	if (tx_buf && *tx_buf)
		writel(*(*tx_buf)++, tx_reg);
	else
		writel(0, tx_reg);

	if (orion_spi_wait_till_ready(orion_spi) < 0) {
		dev_err(&spi->dev, "TXS timed out\n");
		return -1;
	}

	if (rx_buf && *rx_buf)
		*(*rx_buf)++ = readl(rx_reg);

	return 1;
}

static inline int
orion_spi_write_read_16bit(struct spi_device *spi,
			   const u16 **tx_buf, u16 **rx_buf)
{
	void __iomem *tx_reg, *rx_reg, *int_reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);
	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);

	/* clear the interrupt cause register */
	writel(0x0, int_reg);

	if (tx_buf && *tx_buf)
		writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
	else
		writel(0, tx_reg);

	if (orion_spi_wait_till_ready(orion_spi) < 0) {
		dev_err(&spi->dev, "TXS timed out\n");
		return -1;
	}

	if (rx_buf && *rx_buf)
		put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);

	return 1;
}

static unsigned int
orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
{
	struct orion_spi *orion_spi;
	unsigned int count;
	int word_len;

	orion_spi = spi_master_get_devdata(spi->master);
	word_len = spi->bits_per_word;
	count = xfer->len;

	if (word_len == 8) {
		const u8 *tx = xfer->tx_buf;
		u8 *rx = xfer->rx_buf;

		do {
			if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
				goto out;
			count--;
		} while (count);
	} else if (word_len == 16) {
		const u16 *tx = xfer->tx_buf;
		u16 *rx = xfer->rx_buf;

		do {
			if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
				goto out;
			count -= 2;
		} while (count);
	}

out:
	return xfer->len - count;
}


static void orion_spi_work(struct work_struct *work)
{
	struct orion_spi *orion_spi =
		container_of(work, struct orion_spi, work);

	spin_lock_irq(&orion_spi->lock);
	while (!list_empty(&orion_spi->msg_queue)) {
		struct spi_message *m;
		struct spi_device *spi;
		struct spi_transfer *t = NULL;
		int par_override = 0;
		int status = 0;
		int cs_active = 0;

		m = container_of(orion_spi->msg_queue.next, struct spi_message,
				 queue);

		list_del_init(&m->queue);
		spin_unlock_irq(&orion_spi->lock);

		spi = m->spi;

		/* Load defaults */
		status = orion_spi_setup_transfer(spi, NULL);

		if (status < 0)
			goto msg_done;

		list_for_each_entry(t, &m->transfers, transfer_list) {
			if (par_override || t->speed_hz || t->bits_per_word) {
				par_override = 1;
				status = orion_spi_setup_transfer(spi, t);
				if (status < 0)
					break;
				if (!t->speed_hz && !t->bits_per_word)
					par_override = 0;
			}

			if (!cs_active) {
				orion_spi_set_cs(orion_spi, 1);
				cs_active = 1;
			}

			if (t->len)
				m->actual_length +=
					orion_spi_write_read(spi, t);

			if (t->delay_usecs)
				udelay(t->delay_usecs);

			if (t->cs_change) {
				orion_spi_set_cs(orion_spi, 0);
				cs_active = 0;
			}
		}

msg_done:
		if (cs_active)
			orion_spi_set_cs(orion_spi, 0);

		m->status = status;
		m->complete(m->context);

		spin_lock_irq(&orion_spi->lock);
	}

	spin_unlock_irq(&orion_spi->lock);
}

static int __init orion_spi_reset(struct orion_spi *orion_spi)
{
	/* Verify that the CS is deasserted */
	orion_spi_set_cs(orion_spi, 0);

	return 0;
}

static int orion_spi_setup(struct spi_device *spi)
{
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	if (spi->mode) {
		dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
			spi->mode);
		return -EINVAL;
	}

	/* Fix ac timing if required.   */
	if (orion_spi->spi_info->enable_clock_fix)
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  (1 << 14));

	if ((spi->max_speed_hz == 0)
			|| (spi->max_speed_hz > orion_spi->max_speed))
		spi->max_speed_hz = orion_spi->max_speed;

	if (spi->max_speed_hz < orion_spi->min_speed) {
		dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
			spi->max_speed_hz);
		return -EINVAL;
	}

	/*
	 * baudrate & width will be set orion_spi_setup_transfer
	 */
	return 0;
}

static int orion_spi_transfer(struct spi_device *spi, struct spi_message *m)
{
	struct orion_spi *orion_spi;
	struct spi_transfer *t = NULL;
	unsigned long flags;

	m->actual_length = 0;
	m->status = 0;

	/* reject invalid messages and transfers */
	if (list_empty(&m->transfers) || !m->complete)
		return -EINVAL;

	orion_spi = spi_master_get_devdata(spi->master);

	list_for_each_entry(t, &m->transfers, transfer_list) {
		unsigned int bits_per_word = spi->bits_per_word;

		if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
			dev_err(&spi->dev,
				"message rejected : "
				"invalid transfer data buffers\n");
			goto msg_rejected;
		}

		if ((t != NULL) && t->bits_per_word)
			bits_per_word = t->bits_per_word;

		if ((bits_per_word != 8) && (bits_per_word != 16)) {
			dev_err(&spi->dev,
				"message rejected : "
				"invalid transfer bits_per_word (%d bits)\n",
				bits_per_word);
			goto msg_rejected;
		}
		/*make sure buffer length is even when working in 16 bit mode*/
		if ((t != NULL) && (t->bits_per_word == 16) && (t->len & 1)) {
			dev_err(&spi->dev,
				"message rejected : "
				"odd data length (%d) while in 16 bit mode\n",
				t->len);
			goto msg_rejected;
		}

		if (t->speed_hz && t->speed_hz < orion_spi->min_speed) {
			dev_err(&spi->dev,
				"message rejected : "
				"device min speed (%d Hz) exceeds "
				"required transfer speed (%d Hz)\n",
				orion_spi->min_speed, t->speed_hz);
			goto msg_rejected;
		}
	}


	spin_lock_irqsave(&orion_spi->lock, flags);
	list_add_tail(&m->queue, &orion_spi->msg_queue);
	queue_work(orion_spi_wq, &orion_spi->work);
	spin_unlock_irqrestore(&orion_spi->lock, flags);

	return 0;
msg_rejected:
	/* Message rejected and not queued */
	m->status = -EINVAL;
	if (m->complete)
		m->complete(m->context);
	return -EINVAL;
}

static int __init orion_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct orion_spi *spi;
	struct resource *r;
	struct orion_spi_info *spi_info;
	int status = 0;

	spi_info = pdev->dev.platform_data;

	master = spi_alloc_master(&pdev->dev, sizeof *spi);
	if (master == NULL) {
		dev_dbg(&pdev->dev, "master allocation failed\n");
		return -ENOMEM;
	}

	if (pdev->id != -1)
		master->bus_num = pdev->id;

	master->setup = orion_spi_setup;
	master->transfer = orion_spi_transfer;
	master->num_chipselect = ORION_NUM_CHIPSELECTS;

	dev_set_drvdata(&pdev->dev, master);

	spi = spi_master_get_devdata(master);
	spi->master = master;
	spi->spi_info = spi_info;

	spi->max_speed = DIV_ROUND_UP(spi_info->tclk, 4);
	spi->min_speed = DIV_ROUND_UP(spi_info->tclk, 30);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		status = -ENODEV;
		goto out;
	}

	if (!request_mem_region(r->start, (r->end - r->start) + 1,
				dev_name(&pdev->dev))) {
		status = -EBUSY;
		goto out;
	}
	spi->base = ioremap(r->start, SZ_1K);

	INIT_WORK(&spi->work, orion_spi_work);

	spin_lock_init(&spi->lock);
	INIT_LIST_HEAD(&spi->msg_queue);

	if (orion_spi_reset(spi) < 0)
		goto out_rel_mem;

	status = spi_register_master(master);
	if (status < 0)
		goto out_rel_mem;

	return status;

out_rel_mem:
	release_mem_region(r->start, (r->end - r->start) + 1);

out:
	spi_master_put(master);
	return status;
}


static int __exit orion_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct orion_spi *spi;
	struct resource *r;

	master = dev_get_drvdata(&pdev->dev);
	spi = spi_master_get_devdata(master);

	cancel_work_sync(&spi->work);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(r->start, (r->end - r->start) + 1);

	spi_unregister_master(master);

	return 0;
}

MODULE_ALIAS("platform:" DRIVER_NAME);

static struct platform_driver orion_spi_driver = {
	.driver = {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
	},
	.remove		= __exit_p(orion_spi_remove),
};

static int __init orion_spi_init(void)
{
	orion_spi_wq = create_singlethread_workqueue(
				orion_spi_driver.driver.name);
	if (orion_spi_wq == NULL)
		return -ENOMEM;

	return platform_driver_probe(&orion_spi_driver, orion_spi_probe);
}
module_init(orion_spi_init);

static void __exit orion_spi_exit(void)
{
	flush_workqueue(orion_spi_wq);
	platform_driver_unregister(&orion_spi_driver);

	destroy_workqueue(orion_spi_wq);
}
module_exit(orion_spi_exit);

MODULE_DESCRIPTION("Orion SPI driver");
MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
60cadec9 SA	1	/*
	2	* orion_spi.c -- Marvell Orion SPI controller driver
	3	*
	4	* Author: Shadi Ammouri <shadi@marvell.com>
	5	* Copyright (C) 2007-2008 Marvell Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/delay.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18	#include <linux/spi/spi.h>
	19	#include <linux/spi/orion_spi.h>
	20	#include <asm/unaligned.h>
	21
	22	#define DRIVER_NAME "orion_spi"
	23
	24	#define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
	25	#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
	26
	27	#define ORION_SPI_IF_CTRL_REG 0x00
	28	#define ORION_SPI_IF_CONFIG_REG 0x04
	29	#define ORION_SPI_DATA_OUT_REG 0x08
	30	#define ORION_SPI_DATA_IN_REG 0x0c
	31	#define ORION_SPI_INT_CAUSE_REG 0x10
	32
	33	#define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
	34	#define ORION_SPI_CLK_PRESCALE_MASK 0x1F
	35
	36	struct orion_spi {
	37	struct work_struct work;
	38
	39	/* Lock access to transfer list. */
	40	spinlock_t lock;
	41
	42	struct list_head msg_queue;
	43	struct spi_master *master;
	44	void __iomem *base;
	45	unsigned int max_speed;
	46	unsigned int min_speed;
	47	struct orion_spi_info *spi_info;
	48	};
	49
	50	static struct workqueue_struct *orion_spi_wq;
	51
	52	static inline void __iomem spi_reg(struct orion_spi orion_spi, u32 reg)
	53	{
	54	return orion_spi->base + reg;
	55	}
	56
	57	static inline void
	58	orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
	59	{
	60	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	61	u32 val;
	62
	63	val = readl(reg_addr);
	64	val \|= mask;
65	writel(val, reg_addr);
66	}
67
68	static inline void
69	orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
70	{
71	void __iomem *reg_addr = spi_reg(orion_spi, reg);
72	u32 val;
73
74	val = readl(reg_addr);
75	val &= ~mask;
76	writel(val, reg_addr);
77	}
78
79	static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
80	{
81	if (size == 16) {
82	orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
83	ORION_SPI_IF_8_16_BIT_MODE);
84	} else if (size == 8) {
85	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
86	ORION_SPI_IF_8_16_BIT_MODE);
87	} else {
88	pr_debug("Bad bits per word value %d (only 8 or 16 are "
89	"allowed).\n", size);
90	return -EINVAL;
91	}
92
93	return 0;
94	}
95
96	static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
97	{
98	u32 tclk_hz;
99	u32 rate;
100	u32 prescale;
101	u32 reg;
102	struct orion_spi *orion_spi;
103
104	orion_spi = spi_master_get_devdata(spi->master);
105
106	tclk_hz = orion_spi->spi_info->tclk;
107
108	/*
109	* the supported rates are: 4,6,8...30
110	* round up as we look for equal or less speed
111	*/
112	rate = DIV_ROUND_UP(tclk_hz, speed);
113	rate = roundup(rate, 2);
114
115	/* check if requested speed is too small */
116	if (rate > 30)
117	return -EINVAL;
118
119	if (rate < 4)
120	rate = 4;
121
122	/* Convert the rate to SPI clock divisor value. */
123	prescale = 0x10 + rate/2;
124
125	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
126	reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) \| prescale);
127	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
128
129	return 0;
130	}
131
132	/*
133	* called only when no transfer is active on the bus
134	*/
135	static int
136	orion_spi_setup_transfer(struct spi_device spi, struct spi_transfer t)
137	{
138	struct orion_spi *orion_spi;
139	unsigned int speed = spi->max_speed_hz;
140	unsigned int bits_per_word = spi->bits_per_word;
141	int rc;
142
143	orion_spi = spi_master_get_devdata(spi->master);
144
145	if ((t != NULL) && t->speed_hz)
146	speed = t->speed_hz;
147
148	if ((t != NULL) && t->bits_per_word)
149	bits_per_word = t->bits_per_word;
150
151	rc = orion_spi_baudrate_set(spi, speed);
152	if (rc)
153	return rc;
154
155	return orion_spi_set_transfer_size(orion_spi, bits_per_word);
156	}
157
158	static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
159	{
160	if (enable)
161	orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
162	else
163	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
164	}
165
166	static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
167	{
168	int i;
169
170	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
171	if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
172	return 1;
173	else
174	udelay(1);
175	}
176
177	return -1;
178	}
179
180	static inline int
181	orion_spi_write_read_8bit(struct spi_device *spi,
182	const u8 tx_buf, u8 rx_buf)
183	{
184	void __iomem tx_reg, rx_reg, *int_reg;
185	struct orion_spi *orion_spi;
186
187	orion_spi = spi_master_get_devdata(spi->master);
188	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
189	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
190	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
191
192	/* clear the interrupt cause register */
193	writel(0x0, int_reg);
194
195	if (tx_buf && *tx_buf)
196	writel((tx_buf)++, tx_reg);
197	else
198	writel(0, tx_reg);
199
200	if (orion_spi_wait_till_ready(orion_spi) < 0) {
201	dev_err(&spi->dev, "TXS timed out\n");
202	return -1;
203	}
204
205	if (rx_buf && *rx_buf)
206	(rx_buf)++ = readl(rx_reg);
207
208	return 1;
209	}
210
211	static inline int
212	orion_spi_write_read_16bit(struct spi_device *spi,
213	const u16 tx_buf, u16 rx_buf)
214	{
215	void __iomem tx_reg, rx_reg, *int_reg;
216	struct orion_spi *orion_spi;
217
218	orion_spi = spi_master_get_devdata(spi->master);
219	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
220	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
221	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
222
223	/* clear the interrupt cause register */
224	writel(0x0, int_reg);
225
226	if (tx_buf && *tx_buf)
227	writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
228	else
229	writel(0, tx_reg);
230
231	if (orion_spi_wait_till_ready(orion_spi) < 0) {
232	dev_err(&spi->dev, "TXS timed out\n");
233	return -1;
234	}
235
236	if (rx_buf && *rx_buf)
237	put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
238
239	return 1;
240	}
241
242	static unsigned int
243	orion_spi_write_read(struct spi_device spi, struct spi_transfer xfer)
244	{
245	struct orion_spi *orion_spi;
246	unsigned int count;
247	int word_len;
248
249	orion_spi = spi_master_get_devdata(spi->master);
250	word_len = spi->bits_per_word;
251	count = xfer->len;
252
253	if (word_len == 8) {
254	const u8 *tx = xfer->tx_buf;
255	u8 *rx = xfer->rx_buf;
256
257	do {
258	if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
259	goto out;
260	count--;
261	} while (count);
262	} else if (word_len == 16) {
263	const u16 *tx = xfer->tx_buf;
264	u16 *rx = xfer->rx_buf;
265
266	do {
267	if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
268	goto out;
269	count -= 2;
270	} while (count);
271	}
272
273	out:
274	return xfer->len - count;
275	}
276
277
278	static void orion_spi_work(struct work_struct *work)
279	{
280	struct orion_spi *orion_spi =
281	container_of(work, struct orion_spi, work);
282
283	spin_lock_irq(&orion_spi->lock);
284	while (!list_empty(&orion_spi->msg_queue)) {
285	struct spi_message *m;
286	struct spi_device *spi;
287	struct spi_transfer *t = NULL;
288	int par_override = 0;
289	int status = 0;
290	int cs_active = 0;
291
292	m = container_of(orion_spi->msg_queue.next, struct spi_message,
293	queue);
294
295	list_del_init(&m->queue);
296	spin_unlock_irq(&orion_spi->lock);
297
298	spi = m->spi;
299
300	/* Load defaults */
301	status = orion_spi_setup_transfer(spi, NULL);
302
303	if (status < 0)
304	goto msg_done;
305
306	list_for_each_entry(t, &m->transfers, transfer_list) {
307	if (par_override \|\| t->speed_hz \|\| t->bits_per_word) {
308	par_override = 1;
309	status = orion_spi_setup_transfer(spi, t);
310	if (status < 0)
311	break;
312	if (!t->speed_hz && !t->bits_per_word)
313	par_override = 0;
314	}
315
316	if (!cs_active) {
317	orion_spi_set_cs(orion_spi, 1);
318	cs_active = 1;
319	}
320
321	if (t->len)
322	m->actual_length +=
323	orion_spi_write_read(spi, t);
324
325	if (t->delay_usecs)
326	udelay(t->delay_usecs);
327
328	if (t->cs_change) {
329	orion_spi_set_cs(orion_spi, 0);
330	cs_active = 0;
331	}
332	}
333
334	msg_done:
335	if (cs_active)
336	orion_spi_set_cs(orion_spi, 0);
337
338	m->status = status;
339	m->complete(m->context);
340
341	spin_lock_irq(&orion_spi->lock);
342	}
343
344	spin_unlock_irq(&orion_spi->lock);
345	}
346
347	static int __init orion_spi_reset(struct orion_spi *orion_spi)
348	{
349	/* Verify that the CS is deasserted */
350	orion_spi_set_cs(orion_spi, 0);
351
352	return 0;
353	}
354
355	static int orion_spi_setup(struct spi_device *spi)
356	{
357	struct orion_spi *orion_spi;
358
359	orion_spi = spi_master_get_devdata(spi->master);
360
361	if (spi->mode) {
362	dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
363	spi->mode);
364	return -EINVAL;
365	}
366
2bec19fe LB	367	/* Fix ac timing if required. */
	368	if (orion_spi->spi_info->enable_clock_fix)
	369	orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
	370	(1 << 14));
	371
60cadec9 SA	372	if ((spi->max_speed_hz == 0)
	373	\|\| (spi->max_speed_hz > orion_spi->max_speed))
	374	spi->max_speed_hz = orion_spi->max_speed;
	375
	376	if (spi->max_speed_hz < orion_spi->min_speed) {
	377	dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
	378	spi->max_speed_hz);
	379	return -EINVAL;
	380	}
	381
	382	/*
	383	* baudrate & width will be set orion_spi_setup_transfer
	384	*/
	385	return 0;
	386	}
	387
	388	static int orion_spi_transfer(struct spi_device spi, struct spi_message m)
	389	{
	390	struct orion_spi *orion_spi;
	391	struct spi_transfer *t = NULL;
	392	unsigned long flags;
	393
	394	m->actual_length = 0;
	395	m->status = 0;
	396
	397	/* reject invalid messages and transfers */
	398	if (list_empty(&m->transfers) \|\| !m->complete)
	399	return -EINVAL;
	400
	401	orion_spi = spi_master_get_devdata(spi->master);
	402
	403	list_for_each_entry(t, &m->transfers, transfer_list) {
	404	unsigned int bits_per_word = spi->bits_per_word;
	405
	406	if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
	407	dev_err(&spi->dev,
	408	"message rejected : "
	409	"invalid transfer data buffers\n");
	410	goto msg_rejected;
	411	}
	412
	413	if ((t != NULL) && t->bits_per_word)
	414	bits_per_word = t->bits_per_word;
	415
	416	if ((bits_per_word != 8) && (bits_per_word != 16)) {
	417	dev_err(&spi->dev,
	418	"message rejected : "
	419	"invalid transfer bits_per_word (%d bits)\n",
	420	bits_per_word);
	421	goto msg_rejected;
	422	}
	423	/make sure buffer length is even when working in 16 bit mode/
	424	if ((t != NULL) && (t->bits_per_word == 16) && (t->len & 1)) {
	425	dev_err(&spi->dev,
	426	"message rejected : "
	427	"odd data length (%d) while in 16 bit mode\n",
	428	t->len);
	429	goto msg_rejected;
	430	}
	431
f2fe1638	432	if (t->speed_hz && t->speed_hz < orion_spi->min_speed) {
60cadec9 SA	433	dev_err(&spi->dev,
	434	"message rejected : "
	435	"device min speed (%d Hz) exceeds "
	436	"required transfer speed (%d Hz)\n",
	437	orion_spi->min_speed, t->speed_hz);
	438	goto msg_rejected;
	439	}
	440	}
	441
	442
	443	spin_lock_irqsave(&orion_spi->lock, flags);
	444	list_add_tail(&m->queue, &orion_spi->msg_queue);
	445	queue_work(orion_spi_wq, &orion_spi->work);
	446	spin_unlock_irqrestore(&orion_spi->lock, flags);
	447
	448	return 0;
	449	msg_rejected:
	450	/* Message rejected and not queued */
	451	m->status = -EINVAL;
	452	if (m->complete)
	453	m->complete(m->context);
	454	return -EINVAL;
	455	}
	456
	457	static int __init orion_spi_probe(struct platform_device *pdev)
	458	{
	459	struct spi_master *master;
	460	struct orion_spi *spi;
	461	struct resource *r;
	462	struct orion_spi_info *spi_info;
	463	int status = 0;
	464
	465	spi_info = pdev->dev.platform_data;
	466
	467	master = spi_alloc_master(&pdev->dev, sizeof *spi);
	468	if (master == NULL) {
	469	dev_dbg(&pdev->dev, "master allocation failed\n");
	470	return -ENOMEM;
	471	}
	472
	473	if (pdev->id != -1)
	474	master->bus_num = pdev->id;
	475
	476	master->setup = orion_spi_setup;
	477	master->transfer = orion_spi_transfer;
	478	master->num_chipselect = ORION_NUM_CHIPSELECTS;
	479
	480	dev_set_drvdata(&pdev->dev, master);
	481
	482	spi = spi_master_get_devdata(master);
	483	spi->master = master;
	484	spi->spi_info = spi_info;
	485
	486	spi->max_speed = DIV_ROUND_UP(spi_info->tclk, 4);
	487	spi->min_speed = DIV_ROUND_UP(spi_info->tclk, 30);
	488
	489	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	490	if (r == NULL) {
	491	status = -ENODEV;
	492	goto out;
	493	}
	494
	495	if (!request_mem_region(r->start, (r->end - r->start) + 1,
6c7377ab	496	dev_name(&pdev->dev))) {
60cadec9 SA	497	status = -EBUSY;
	498	goto out;
	499	}
	500	spi->base = ioremap(r->start, SZ_1K);
	501
	502	INIT_WORK(&spi->work, orion_spi_work);
	503
	504	spin_lock_init(&spi->lock);
	505	INIT_LIST_HEAD(&spi->msg_queue);
	506
	507	if (orion_spi_reset(spi) < 0)
	508	goto out_rel_mem;
	509
	510	status = spi_register_master(master);
	511	if (status < 0)
	512	goto out_rel_mem;
	513
	514	return status;
	515
	516	out_rel_mem:
	517	release_mem_region(r->start, (r->end - r->start) + 1);
	518
	519	out:
	520	spi_master_put(master);
	521	return status;
	522	}
	523
	524
	525	static int __exit orion_spi_remove(struct platform_device *pdev)
	526	{
	527	struct spi_master *master;
	528	struct orion_spi *spi;
	529	struct resource *r;
	530
	531	master = dev_get_drvdata(&pdev->dev);
	532	spi = spi_master_get_devdata(master);
	533
	534	cancel_work_sync(&spi->work);
	535
	536	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	537	release_mem_region(r->start, (r->end - r->start) + 1);
	538
	539	spi_unregister_master(master);
	540
	541	return 0;
	542	}
	543
	544	MODULE_ALIAS("platform:" DRIVER_NAME);
	545
	546	static struct platform_driver orion_spi_driver = {
	547	.driver = {
	548	.name = DRIVER_NAME,
	549	.owner = THIS_MODULE,
	550	},
	551	.remove = __exit_p(orion_spi_remove),
	552	};
	553
	554	static int __init orion_spi_init(void)
	555	{
	556	orion_spi_wq = create_singlethread_workqueue(
	557	orion_spi_driver.driver.name);
	558	if (orion_spi_wq == NULL)
	559	return -ENOMEM;
	560
561	return platform_driver_probe(&orion_spi_driver, orion_spi_probe);
562	}
563	module_init(orion_spi_init);
564
565	static void __exit orion_spi_exit(void)
566	{
567	flush_workqueue(orion_spi_wq);
568	platform_driver_unregister(&orion_spi_driver);
569
570	destroy_workqueue(orion_spi_wq);
571	}
572	module_exit(orion_spi_exit);
573
574	MODULE_DESCRIPTION("Orion SPI driver");
575	MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
576	MODULE_LICENSE("GPL");