[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / sh / pfc / pinctrl.c

/*
 * SuperH Pin Function Controller pinmux support.
 *
 * Copyright (C) 2012  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/init.h>
#include <linux/module.h>
#include <linux/sh_pfc.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf-generic.h>

struct sh_pfc_pinctrl {
	struct pinctrl_dev *pctl;
	struct sh_pfc *pfc;

	struct pinmux_gpio **functions;
	unsigned int nr_functions;

	struct pinctrl_pin_desc *pads;
	unsigned int nr_pads;

	spinlock_t lock;
};

static struct sh_pfc_pinctrl *sh_pfc_pmx;

/*
 * No group support yet
 */
static int sh_pfc_get_noop_count(struct pinctrl_dev *pctldev)
{
	return 0;
}

static const char *sh_pfc_get_noop_name(struct pinctrl_dev *pctldev,
					 unsigned selector)
{
	return NULL;
}

static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
				 const unsigned **pins, unsigned *num_pins)
{
	return -ENOTSUPP;
}

static struct pinctrl_ops sh_pfc_pinctrl_ops = {
	.get_groups_count	= sh_pfc_get_noop_count,
	.get_group_name		= sh_pfc_get_noop_name,
	.get_group_pins		= sh_pfc_get_group_pins,
};

static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->nr_functions;
}

static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
					    unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->functions[selector]->name;
}

static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
				      const char * const **groups,
				      unsigned * const num_groups)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*groups = &pmx->functions[func]->name;
	*num_groups = 1;

	return 0;
}

static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
			      unsigned group)
{
	return 0;
}

static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
				unsigned group)
{
}

static inline int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset)
{
	if (sh_pfc_config_gpio(pfc, offset,
			       PINMUX_TYPE_FUNCTION,
			       GPIO_CFG_DRYRUN) != 0)
		return -EINVAL;

	if (sh_pfc_config_gpio(pfc, offset,
			       PINMUX_TYPE_FUNCTION,
			       GPIO_CFG_REQ) != 0)
		return -EINVAL;

	return 0;
}

static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
				      struct pinctrl_gpio_range *range,
				      unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	unsigned long flags;
	int ret, pinmux_type;

	spin_lock_irqsave(&pfc->lock, flags);

	pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;

	switch (pinmux_type) {
	case PINMUX_TYPE_FUNCTION:
		pr_notice_once("Use of GPIO API for function requests is "
			       "deprecated, convert to pinctrl\n");
		/* handle for now */
		ret = sh_pfc_config_function(pfc, offset);
		if (unlikely(ret < 0))
			goto err;

		break;
	case PINMUX_TYPE_GPIO:
		break;
	default:
		pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
		return -ENOTSUPP;
	}

	ret = 0;

err:
	spin_unlock_irqrestore(&pfc->lock, flags);

	return ret;
}

static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	unsigned long flags;
	int pinmux_type;

	spin_lock_irqsave(&pfc->lock, flags);

	pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;

	sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);

	spin_unlock_irqrestore(&pfc->lock, flags);
}

static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset, bool input)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	unsigned long flags;
	int pinmux_type, new_pinmux_type;
	int ret = -EINVAL;

	new_pinmux_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;

	spin_lock_irqsave(&pfc->lock, flags);

	pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;

	switch (pinmux_type) {
	case PINMUX_TYPE_GPIO:
		break;
	case PINMUX_TYPE_OUTPUT:
	case PINMUX_TYPE_INPUT:
	case PINMUX_TYPE_INPUT_PULLUP:
	case PINMUX_TYPE_INPUT_PULLDOWN:
		sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
		break;
	default:
		goto err;
	}

	if (sh_pfc_config_gpio(pfc, offset,
			       new_pinmux_type,
			       GPIO_CFG_DRYRUN) != 0)
		goto err;

	if (sh_pfc_config_gpio(pfc, offset,
			       new_pinmux_type,
			       GPIO_CFG_REQ) != 0)
		BUG();

	pfc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
	pfc->gpios[offset].flags |= new_pinmux_type;

	ret = 0;

err:
	spin_unlock_irqrestore(&pfc->lock, flags);

	return ret;
}

static struct pinmux_ops sh_pfc_pinmux_ops = {
	.get_functions_count	= sh_pfc_get_functions_count,
	.get_function_name	= sh_pfc_get_function_name,
	.get_function_groups	= sh_pfc_get_function_groups,
	.enable			= sh_pfc_noop_enable,
	.disable		= sh_pfc_noop_disable,
	.gpio_request_enable	= sh_pfc_gpio_request_enable,
	.gpio_disable_free	= sh_pfc_gpio_disable_free,
	.gpio_set_direction	= sh_pfc_gpio_set_direction,
};

static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
			      unsigned long *config)
{
	enum pin_config_param param = (enum pin_config_param)(*config);

	switch (param) {
	default:
		break;
	}

	return -ENOTSUPP;
}

static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
			      unsigned long config)
{
	return -EINVAL;
}

static struct pinconf_ops sh_pfc_pinconf_ops = {
	.is_generic		= true,
	.pin_config_get		= sh_pfc_pinconf_get,
	.pin_config_set		= sh_pfc_pinconf_set,
};

static struct pinctrl_gpio_range sh_pfc_gpio_range = {
	.name		= KBUILD_MODNAME,
	.id		= 0,
};

static struct pinctrl_desc sh_pfc_pinctrl_desc = {
	.name		= KBUILD_MODNAME,
	.owner		= THIS_MODULE,
	.pctlops	= &sh_pfc_pinctrl_ops,
	.pmxops		= &sh_pfc_pinmux_ops,
	.confops	= &sh_pfc_pinconf_ops,
};

int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
{
	sh_pfc_pmx = kzalloc(sizeof(struct sh_pfc_pinctrl), GFP_KERNEL);
	if (unlikely(!sh_pfc_pmx))
		return -ENOMEM;

	spin_lock_init(&sh_pfc_pmx->lock);

	sh_pfc_pmx->pfc = pfc;

	return 0;
}

static inline void __devinit sh_pfc_map_one_gpio(struct sh_pfc *pfc,
						 struct sh_pfc_pinctrl *pmx,
						 struct pinmux_gpio *gpio,
						 unsigned offset)
{
	struct pinmux_data_reg *dummy;
	unsigned long flags;
	int bit;

	gpio->flags &= ~PINMUX_FLAG_TYPE;

	if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0)
		gpio->flags |= PINMUX_TYPE_GPIO;
	else {
		gpio->flags |= PINMUX_TYPE_FUNCTION;

		spin_lock_irqsave(&pmx->lock, flags);
		pmx->nr_functions++;
		spin_unlock_irqrestore(&pmx->lock, flags);
	}
}

/* pinmux ranges -> pinctrl pin descs */
static int __devinit sh_pfc_map_gpios(struct sh_pfc *pfc,
				      struct sh_pfc_pinctrl *pmx)
{
	unsigned long flags;
	int i;

	pmx->nr_pads = pfc->last_gpio - pfc->first_gpio + 1;

	pmx->pads = kmalloc(sizeof(struct pinctrl_pin_desc) * pmx->nr_pads,
			    GFP_KERNEL);
	if (unlikely(!pmx->pads)) {
		pmx->nr_pads = 0;
		return -ENOMEM;
	}

	spin_lock_irqsave(&pfc->lock, flags);

	/*
	 * We don't necessarily have a 1:1 mapping between pin and linux
	 * GPIO number, as the latter maps to the associated enum_id.
	 * Care needs to be taken to translate back to pin space when
	 * dealing with any pin configurations.
	 */
	for (i = 0; i < pmx->nr_pads; i++) {
		struct pinctrl_pin_desc *pin = pmx->pads + i;
		struct pinmux_gpio *gpio = pfc->gpios + i;

		pin->number = pfc->first_gpio + i;
		pin->name = gpio->name;

		sh_pfc_map_one_gpio(pfc, pmx, gpio, i);
	}

	spin_unlock_irqrestore(&pfc->lock, flags);

	sh_pfc_pinctrl_desc.pins = pmx->pads;
	sh_pfc_pinctrl_desc.npins = pmx->nr_pads;

	return 0;
}

static int __devinit sh_pfc_map_functions(struct sh_pfc *pfc,
					  struct sh_pfc_pinctrl *pmx)
{
	unsigned long flags;
	int i, fn;

	pmx->functions = kzalloc(pmx->nr_functions * sizeof(void *),
				 GFP_KERNEL);
	if (unlikely(!pmx->functions))
		return -ENOMEM;

	spin_lock_irqsave(&pmx->lock, flags);

	for (i = fn = 0; i < pmx->nr_pads; i++) {
		struct pinmux_gpio *gpio = pfc->gpios + i;

		if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
			pmx->functions[fn++] = gpio;
	}

	spin_unlock_irqrestore(&pmx->lock, flags);

	return 0;
}

static int __devinit sh_pfc_pinctrl_probe(struct platform_device *pdev)
{
	struct sh_pfc *pfc;
	int ret;

	if (unlikely(!sh_pfc_pmx))
		return -ENODEV;

	pfc = sh_pfc_pmx->pfc;

	ret = sh_pfc_map_gpios(pfc, sh_pfc_pmx);
	if (unlikely(ret != 0))
		return ret;

	ret = sh_pfc_map_functions(pfc, sh_pfc_pmx);
	if (unlikely(ret != 0))
		goto free_pads;

	sh_pfc_pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, &pdev->dev,
					    sh_pfc_pmx);
	if (IS_ERR(sh_pfc_pmx->pctl)) {
		ret = PTR_ERR(sh_pfc_pmx->pctl);
		goto free_functions;
	}

	sh_pfc_gpio_range.npins = pfc->last_gpio - pfc->first_gpio + 1;
	sh_pfc_gpio_range.base = pfc->first_gpio;
	sh_pfc_gpio_range.pin_base = pfc->first_gpio;

	pinctrl_add_gpio_range(sh_pfc_pmx->pctl, &sh_pfc_gpio_range);

	platform_set_drvdata(pdev, sh_pfc_pmx);

	return 0;

free_functions:
	kfree(sh_pfc_pmx->functions);
free_pads:
	kfree(sh_pfc_pmx->pads);
	kfree(sh_pfc_pmx);

	return ret;
}

static int __devexit sh_pfc_pinctrl_remove(struct platform_device *pdev)
{
	struct sh_pfc_pinctrl *pmx = platform_get_drvdata(pdev);

	pinctrl_remove_gpio_range(pmx->pctl, &sh_pfc_gpio_range);
	pinctrl_unregister(pmx->pctl);

	platform_set_drvdata(pdev, NULL);

	kfree(sh_pfc_pmx->functions);
	kfree(sh_pfc_pmx->pads);
	kfree(sh_pfc_pmx);

	return 0;
}

static struct platform_driver sh_pfc_pinctrl_driver = {
	.probe		= sh_pfc_pinctrl_probe,
	.remove		= __devexit_p(sh_pfc_pinctrl_remove),
	.driver		= {
		.name	= KBUILD_MODNAME,
		.owner	= THIS_MODULE,
	},
};

static struct platform_device sh_pfc_pinctrl_device = {
	.name		= KBUILD_MODNAME,
	.id		= -1,
};

static int __init sh_pfc_pinctrl_init(void)
{
	int rc;

	rc = platform_driver_register(&sh_pfc_pinctrl_driver);
	if (likely(!rc)) {
		rc = platform_device_register(&sh_pfc_pinctrl_device);
		if (unlikely(rc))
			platform_driver_unregister(&sh_pfc_pinctrl_driver);
	}

	return rc;
}

static void __exit sh_pfc_pinctrl_exit(void)
{
	platform_driver_unregister(&sh_pfc_pinctrl_driver);
}

subsys_initcall(sh_pfc_pinctrl_init);
module_exit(sh_pfc_pinctrl_exit);
Commit	Line	Data
ca5481c6 PM	1	/*
	2	* SuperH Pin Function Controller pinmux support.
	3	*
	4	* Copyright (C) 2012 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	11
	12	#include <linux/init.h>
	13	#include <linux/module.h>
	14	#include <linux/sh_pfc.h>
	15	#include <linux/err.h>
	16	#include <linux/slab.h>
d93a891f	17	#include <linux/spinlock.h>
ca5481c6 PM	18	#include <linux/platform_device.h>
	19	#include <linux/pinctrl/consumer.h>
	20	#include <linux/pinctrl/pinctrl.h>
	21	#include <linux/pinctrl/pinconf.h>
	22	#include <linux/pinctrl/pinmux.h>
	23	#include <linux/pinctrl/pinconf-generic.h>
	24
	25	struct sh_pfc_pinctrl {
	26	struct pinctrl_dev *pctl;
	27	struct sh_pfc *pfc;
	28
d93a891f PM	29	struct pinmux_gpio **functions;
	30	unsigned int nr_functions;
	31
ca5481c6 PM	32	struct pinctrl_pin_desc *pads;
ca5481c6 PM	33	unsigned int nr_pads;
d93a891f PM	34
d93a891f PM	35	spinlock_t lock;
ca5481c6 PM	36	};
	37
	38	static struct sh_pfc_pinctrl *sh_pfc_pmx;
	39
	40	/*
	41	* No group support yet
	42	*/
	43	static int sh_pfc_get_noop_count(struct pinctrl_dev *pctldev)
	44	{
	45	return 0;
	46	}
	47
	48	static const char sh_pfc_get_noop_name(struct pinctrl_dev pctldev,
	49	unsigned selector)
	50	{
	51	return NULL;
	52	}
	53
	54	static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
	55	const unsigned *pins, unsigned num_pins)
	56	{
	57	return -ENOTSUPP;
	58	}
	59
	60	static struct pinctrl_ops sh_pfc_pinctrl_ops = {
	61	.get_groups_count = sh_pfc_get_noop_count,
	62	.get_group_name = sh_pfc_get_noop_name,
	63	.get_group_pins = sh_pfc_get_group_pins,
	64	};
	65
d93a891f PM	66	static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
	67	{
	68	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	69
	70	return pmx->nr_functions;
	71	}
	72
	73	static const char sh_pfc_get_function_name(struct pinctrl_dev pctldev,
	74	unsigned selector)
	75	{
	76	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	77
	78	return pmx->functions[selector]->name;
	79	}
ca5481c6	80
ca5481c6 PM	81	static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
	82	const char * const **groups,
	83	unsigned * const num_groups)
	84	{
d93a891f PM	85	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	86
	87	*groups = &pmx->functions[func]->name;
	88	*num_groups = 1;
	89
ca5481c6 PM	90	return 0;
	91	}
	92
	93	static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
	94	unsigned group)
	95	{
	96	return 0;
	97	}
	98
	99	static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
	100	unsigned group)
	101	{
	102	}
	103
d93a891f PM	104	static inline int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset)
	105	{
	106	if (sh_pfc_config_gpio(pfc, offset,
	107	PINMUX_TYPE_FUNCTION,
	108	GPIO_CFG_DRYRUN) != 0)
	109	return -EINVAL;
	110
	111	if (sh_pfc_config_gpio(pfc, offset,
	112	PINMUX_TYPE_FUNCTION,
	113	GPIO_CFG_REQ) != 0)
	114	return -EINVAL;
	115
	116	return 0;
	117	}
	118
ca5481c6 PM	119	static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
	120	struct pinctrl_gpio_range *range,
	121	unsigned offset)
	122	{
	123	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	124	struct sh_pfc *pfc = pmx->pfc;
ca5481c6	125	unsigned long flags;
d93a891f	126	int ret, pinmux_type;
ca5481c6 PM	127
	128	spin_lock_irqsave(&pfc->lock, flags);
	129
d93a891f	130	pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
ca5481c6	131
d93a891f PM	132	switch (pinmux_type) {
	133	case PINMUX_TYPE_FUNCTION:
	134	pr_notice_once("Use of GPIO API for function requests is "
	135	"deprecated, convert to pinctrl\n");
	136	/* handle for now */
	137	ret = sh_pfc_config_function(pfc, offset);
	138	if (unlikely(ret < 0))
ca5481c6	139	goto err;
ca5481c6	140
d93a891f PM	141	break;
	142	case PINMUX_TYPE_GPIO:
	143	break;
	144	default:
	145	pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
	146	return -ENOTSUPP;
	147	}
ca5481c6 PM	148
	149	ret = 0;
	150
	151	err:
	152	spin_unlock_irqrestore(&pfc->lock, flags);
	153
	154	return ret;
	155	}
	156
	157	static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
	158	struct pinctrl_gpio_range *range,
	159	unsigned offset)
	160	{
	161	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	162	struct sh_pfc *pfc = pmx->pfc;
	163	unsigned long flags;
	164	int pinmux_type;
	165
	166	spin_lock_irqsave(&pfc->lock, flags);
	167
	168	pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
	169
	170	sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
	171
ca5481c6 PM	172	spin_unlock_irqrestore(&pfc->lock, flags);
	173	}
	174
	175	static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
	176	struct pinctrl_gpio_range *range,
	177	unsigned offset, bool input)
	178	{
	179	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	180	struct sh_pfc *pfc = pmx->pfc;
	181	unsigned long flags;
	182	int pinmux_type, new_pinmux_type;
	183	int ret = -EINVAL;
	184
	185	new_pinmux_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
	186
	187	spin_lock_irqsave(&pfc->lock, flags);
	188
	189	pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
	190
	191	switch (pinmux_type) {
	192	case PINMUX_TYPE_GPIO:
	193	break;
	194	case PINMUX_TYPE_OUTPUT:
	195	case PINMUX_TYPE_INPUT:
	196	case PINMUX_TYPE_INPUT_PULLUP:
	197	case PINMUX_TYPE_INPUT_PULLDOWN:
	198	sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
	199	break;
	200	default:
	201	goto err;
	202	}
	203
	204	if (sh_pfc_config_gpio(pfc, offset,
	205	new_pinmux_type,
	206	GPIO_CFG_DRYRUN) != 0)
	207	goto err;
	208
	209	if (sh_pfc_config_gpio(pfc, offset,
	210	new_pinmux_type,
	211	GPIO_CFG_REQ) != 0)
	212	BUG();
	213
	214	pfc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
	215	pfc->gpios[offset].flags \|= new_pinmux_type;
	216
	217	ret = 0;
	218
	219	err:
	220	spin_unlock_irqrestore(&pfc->lock, flags);
	221
	222	return ret;
	223	}
	224
	225	static struct pinmux_ops sh_pfc_pinmux_ops = {
d93a891f PM	226	.get_functions_count = sh_pfc_get_functions_count,
d93a891f PM	227	.get_function_name = sh_pfc_get_function_name,
ca5481c6 PM	228	.get_function_groups = sh_pfc_get_function_groups,
	229	.enable = sh_pfc_noop_enable,
	230	.disable = sh_pfc_noop_disable,
	231	.gpio_request_enable = sh_pfc_gpio_request_enable,
	232	.gpio_disable_free = sh_pfc_gpio_disable_free,
	233	.gpio_set_direction = sh_pfc_gpio_set_direction,
	234	};
	235
	236	static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
	237	unsigned long *config)
	238	{
d93a891f PM	239	enum pin_config_param param = (enum pin_config_param)(*config);
	240
	241	switch (param) {
	242	default:
	243	break;
	244	}
	245
ca5481c6 PM	246	return -ENOTSUPP;
	247	}
	248
	249	static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
	250	unsigned long config)
	251	{
	252	return -EINVAL;
	253	}
	254
	255	static struct pinconf_ops sh_pfc_pinconf_ops = {
	256	.is_generic = true,
	257	.pin_config_get = sh_pfc_pinconf_get,
	258	.pin_config_set = sh_pfc_pinconf_set,
	259	};
	260
	261	static struct pinctrl_gpio_range sh_pfc_gpio_range = {
	262	.name = KBUILD_MODNAME,
	263	.id = 0,
	264	};
	265
	266	static struct pinctrl_desc sh_pfc_pinctrl_desc = {
	267	.name = KBUILD_MODNAME,
	268	.owner = THIS_MODULE,
	269	.pctlops = &sh_pfc_pinctrl_ops,
	270	.pmxops = &sh_pfc_pinmux_ops,
	271	.confops = &sh_pfc_pinconf_ops,
	272	};
	273
	274	int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
	275	{
d93a891f	276	sh_pfc_pmx = kzalloc(sizeof(struct sh_pfc_pinctrl), GFP_KERNEL);
ca5481c6 PM	277	if (unlikely(!sh_pfc_pmx))
	278	return -ENOMEM;
	279
d93a891f PM	280	spin_lock_init(&sh_pfc_pmx->lock);
d93a891f PM	281
ca5481c6 PM	282	sh_pfc_pmx->pfc = pfc;
	283
	284	return 0;
	285	}
	286
d93a891f PM	287	static inline void __devinit sh_pfc_map_one_gpio(struct sh_pfc *pfc,
	288	struct sh_pfc_pinctrl *pmx,
	289	struct pinmux_gpio *gpio,
	290	unsigned offset)
	291	{
	292	struct pinmux_data_reg *dummy;
	293	unsigned long flags;
	294	int bit;
	295
	296	gpio->flags &= ~PINMUX_FLAG_TYPE;
	297
	298	if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0)
	299	gpio->flags \|= PINMUX_TYPE_GPIO;
	300	else {
	301	gpio->flags \|= PINMUX_TYPE_FUNCTION;
	302
	303	spin_lock_irqsave(&pmx->lock, flags);
	304	pmx->nr_functions++;
	305	spin_unlock_irqrestore(&pmx->lock, flags);
	306	}
	307	}
	308
ca5481c6 PM	309	/* pinmux ranges -> pinctrl pin descs */
	310	static int __devinit sh_pfc_map_gpios(struct sh_pfc *pfc,
	311	struct sh_pfc_pinctrl *pmx)
	312	{
d93a891f	313	unsigned long flags;
ca5481c6 PM	314	int i;
	315
	316	pmx->nr_pads = pfc->last_gpio - pfc->first_gpio + 1;
	317
	318	pmx->pads = kmalloc(sizeof(struct pinctrl_pin_desc) * pmx->nr_pads,
	319	GFP_KERNEL);
	320	if (unlikely(!pmx->pads)) {
	321	pmx->nr_pads = 0;
	322	return -ENOMEM;
	323	}
	324
d93a891f PM	325	spin_lock_irqsave(&pfc->lock, flags);
d93a891f PM	326
ca5481c6 PM	327	/*
	328	* We don't necessarily have a 1:1 mapping between pin and linux
	329	* GPIO number, as the latter maps to the associated enum_id.
	330	* Care needs to be taken to translate back to pin space when
	331	* dealing with any pin configurations.
	332	*/
	333	for (i = 0; i < pmx->nr_pads; i++) {
	334	struct pinctrl_pin_desc *pin = pmx->pads + i;
	335	struct pinmux_gpio *gpio = pfc->gpios + i;
	336
	337	pin->number = pfc->first_gpio + i;
	338	pin->name = gpio->name;
d93a891f PM	339
d93a891f PM	340	sh_pfc_map_one_gpio(pfc, pmx, gpio, i);
ca5481c6 PM	341	}
ca5481c6 PM	342
d93a891f PM	343	spin_unlock_irqrestore(&pfc->lock, flags);
d93a891f PM	344
ca5481c6 PM	345	sh_pfc_pinctrl_desc.pins = pmx->pads;
	346	sh_pfc_pinctrl_desc.npins = pmx->nr_pads;
	347
	348	return 0;
	349	}
	350
d93a891f PM	351	static int __devinit sh_pfc_map_functions(struct sh_pfc *pfc,
	352	struct sh_pfc_pinctrl *pmx)
	353	{
	354	unsigned long flags;
	355	int i, fn;
	356
	357	pmx->functions = kzalloc(pmx->nr_functions * sizeof(void *),
	358	GFP_KERNEL);
	359	if (unlikely(!pmx->functions))
	360	return -ENOMEM;
	361
	362	spin_lock_irqsave(&pmx->lock, flags);
	363
	364	for (i = fn = 0; i < pmx->nr_pads; i++) {
	365	struct pinmux_gpio *gpio = pfc->gpios + i;
	366
	367	if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
	368	pmx->functions[fn++] = gpio;
	369	}
	370
	371	spin_unlock_irqrestore(&pmx->lock, flags);
	372
	373	return 0;
	374	}
	375
ca5481c6 PM	376	static int __devinit sh_pfc_pinctrl_probe(struct platform_device *pdev)
	377	{
	378	struct sh_pfc *pfc;
	379	int ret;
	380
	381	if (unlikely(!sh_pfc_pmx))
	382	return -ENODEV;
	383
	384	pfc = sh_pfc_pmx->pfc;
	385
	386	ret = sh_pfc_map_gpios(pfc, sh_pfc_pmx);
	387	if (unlikely(ret != 0))
	388	return ret;
	389
d93a891f PM	390	ret = sh_pfc_map_functions(pfc, sh_pfc_pmx);
	391	if (unlikely(ret != 0))
	392	goto free_pads;
	393
ca5481c6 PM	394	sh_pfc_pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, &pdev->dev,
	395	sh_pfc_pmx);
	396	if (IS_ERR(sh_pfc_pmx->pctl)) {
	397	ret = PTR_ERR(sh_pfc_pmx->pctl);
d93a891f	398	goto free_functions;
ca5481c6 PM	399	}
	400
	401	sh_pfc_gpio_range.npins = pfc->last_gpio - pfc->first_gpio + 1;
	402	sh_pfc_gpio_range.base = pfc->first_gpio;
	403	sh_pfc_gpio_range.pin_base = pfc->first_gpio;
	404
	405	pinctrl_add_gpio_range(sh_pfc_pmx->pctl, &sh_pfc_gpio_range);
	406
	407	platform_set_drvdata(pdev, sh_pfc_pmx);
	408
	409	return 0;
	410
d93a891f PM	411	free_functions:
	412	kfree(sh_pfc_pmx->functions);
	413	free_pads:
ca5481c6 PM	414	kfree(sh_pfc_pmx->pads);
ca5481c6 PM	415	kfree(sh_pfc_pmx);
d93a891f	416
ca5481c6 PM	417	return ret;
	418	}
	419
	420	static int __devexit sh_pfc_pinctrl_remove(struct platform_device *pdev)
	421	{
	422	struct sh_pfc_pinctrl *pmx = platform_get_drvdata(pdev);
	423
	424	pinctrl_remove_gpio_range(pmx->pctl, &sh_pfc_gpio_range);
	425	pinctrl_unregister(pmx->pctl);
	426
	427	platform_set_drvdata(pdev, NULL);
	428
d93a891f	429	kfree(sh_pfc_pmx->functions);
ca5481c6 PM	430	kfree(sh_pfc_pmx->pads);
	431	kfree(sh_pfc_pmx);
	432
	433	return 0;
	434	}
	435
	436	static struct platform_driver sh_pfc_pinctrl_driver = {
	437	.probe = sh_pfc_pinctrl_probe,
	438	.remove = __devexit_p(sh_pfc_pinctrl_remove),
	439	.driver = {
	440	.name = KBUILD_MODNAME,
	441	.owner = THIS_MODULE,
	442	},
	443	};
	444
	445	static struct platform_device sh_pfc_pinctrl_device = {
	446	.name = KBUILD_MODNAME,
	447	.id = -1,
	448	};
	449
	450	static int __init sh_pfc_pinctrl_init(void)
	451	{
	452	int rc;
	453
	454	rc = platform_driver_register(&sh_pfc_pinctrl_driver);
	455	if (likely(!rc)) {
	456	rc = platform_device_register(&sh_pfc_pinctrl_device);
	457	if (unlikely(rc))
	458	platform_driver_unregister(&sh_pfc_pinctrl_driver);
	459	}
	460
	461	return rc;
	462	}
	463
	464	static void __exit sh_pfc_pinctrl_exit(void)
	465	{
	466	platform_driver_unregister(&sh_pfc_pinctrl_driver);
	467	}
	468
	469	subsys_initcall(sh_pfc_pinctrl_init);
	470	module_exit(sh_pfc_pinctrl_exit);