projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | #include <linux/serial_core.h> |
| e108b2ca | 2 | #include <asm/io.h> |
| 69edbba0 | 3 | #include <linux/gpio.h> |
| 3ea6bc3d | 4 | |
| 1da177e4 LT |
5 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) |
| 6 | #include <asm/regs306x.h> | |
| 7 | #endif | |
| 8 | #if defined(CONFIG_H8S2678) | |
| 9 | #include <asm/regs267x.h> | |
| 10 | #endif | |
| 1da177e4 | 11 | |
| 0fbde950 MD |
12 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
| 13 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | |
| 14 | defined(CONFIG_CPU_SUBTYPE_SH7708) || \ | |
| 15 | defined(CONFIG_CPU_SUBTYPE_SH7709) | |
| 1da177e4 LT |
16 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ |
| 17 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ | |
| 1da177e4 LT |
18 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) |
| 19 | # define SCIF0 0xA4400000 | |
| 20 | # define SCIF2 0xA4410000 | |
| 1da177e4 LT |
21 | # define SCPCR 0xA4000116 |
| 22 | # define SCPDR 0xA4000136 | |
| 31a49c4b YS |
23 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 24 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| fd88cac9 PM |
25 | # define PORT_PTCR 0xA405011EUL |
| 26 | # define PORT_PVCR 0xA4050122UL | |
| 27 | # define SCIF_ORER 0x0200 /* overrun error bit */ | |
| 1da177e4 | 28 | #elif defined(CONFIG_SH_RTS7751R2D) |
| 7abc404a | 29 | # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ |
| 1da177e4 LT |
30 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
| 31 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 05627486 PM |
32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
| 33 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
| 34 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | |
| 35 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | |
| 36 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
| 37 | defined(CONFIG_CPU_SUBTYPE_SH7751R) | |
| 1da177e4 LT |
38 | # define SCSPTR1 0xffe0001c /* 8 bit SCI */ |
| 39 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | |
| 40 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 1da177e4 | 41 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
| b7a76e4b PM |
42 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ |
| 43 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ | |
| 44 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ | |
| 1da177e4 | 45 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 2b1bd1ac | 46 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
| e108b2ca | 47 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ |
| 9465a54f NI |
48 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 49 | # define PACR 0xa4050100 | |
| 50 | # define PBCR 0xa4050102 | |
| e108b2ca PM |
51 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
| 52 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ | |
| 53 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ | |
| 54 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ | |
| 55 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ | |
| 41504c39 | 56 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
| 346b7463 MD |
57 | # define PADR 0xA4050120 |
| 58 | # define PSDR 0xA405013e | |
| 59 | # define PWDR 0xA4050166 | |
| 60 | # define PSCR 0xA405011E | |
| 41504c39 | 61 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 9109a30e MD |
62 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
| 63 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | |
| 64 | # define SCSPTR0 SCPDR0 | |
| 65 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 178dd0cd PM |
66 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
| 67 | # define SCSPTR0 0xa4050160 | |
| 68 | # define SCSPTR1 0xa405013e | |
| 69 | # define SCSPTR2 0xa4050160 | |
| 70 | # define SCSPTR3 0xa405013e | |
| 71 | # define SCSPTR4 0xa4050128 | |
| 72 | # define SCSPTR5 0xa4050128 | |
| 73 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 47948d2b KM |
74 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) |
| 75 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 1da177e4 | 76 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
| 1da177e4 LT |
77 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
| 78 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 1da177e4 | 79 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
| 1da177e4 | 80 | # define SCIF_PTR2_OFFS 0x0000020 |
| 1da177e4 | 81 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
| 1da177e4 | 82 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) |
| 1da177e4 LT |
83 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
| 84 | #elif defined(CONFIG_H8S2678) | |
| 1da177e4 | 85 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
| 7d740a06 YS |
86 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 87 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
| 88 | # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ | |
| c63847a3 | 89 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ |
| 7d740a06 | 90 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| b7a76e4b PM |
91 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
| 92 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ | |
| 93 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ | |
| 94 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ | |
| 95 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| b7a76e4b PM |
96 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
| 97 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
| 98 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ | |
| e108b2ca | 99 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
| 55ba99eb KM |
100 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
| 101 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
| 32351a28 PM |
102 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ |
| 103 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ | |
| 104 | # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ | |
| 105 | # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ | |
| 106 | # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ | |
| 107 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ | |
| 34aeb43e | 108 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
| 2825999e PG |
109 | #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ |
| 110 | defined(CONFIG_CPU_SUBTYPE_SH7203) || \ | |
| a8f67f4b PM |
111 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ |
| 112 | defined(CONFIG_CPU_SUBTYPE_SH7263) | |
| 9d4436a6 YS |
113 | # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ |
| 114 | # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ | |
| 115 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ | |
| 116 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ | |
| 2825999e PG |
117 | # if defined(CONFIG_CPU_SUBTYPE_SH7201) |
| 118 | # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ | |
| 119 | # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ | |
| 120 | # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ | |
| 121 | # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ | |
| 122 | # endif | |
| 9d4436a6 YS |
123 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) |
| 124 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ | |
| 125 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ | |
| 126 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ | |
| 127 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 2b1bd1ac PM |
128 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
| 129 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ | |
| 130 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ | |
| 131 | # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ | |
| 132 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ | |
| 133 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | |
| 1da177e4 LT |
134 | #else |
| 135 | # error CPU subtype not defined | |
| 136 | #endif | |
| 137 | ||
| 1da177e4 LT |
138 | /* SCxSR SCI */ |
| 139 | #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 140 | #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 141 | #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 142 | #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 143 | #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 144 | #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 145 | /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 146 | /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 147 | ||
| 148 | #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) | |
| 149 | ||
| 150 | /* SCxSR SCIF */ | |
| 151 | #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 152 | #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 153 | #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 154 | #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 155 | #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 156 | #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 157 | #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 158 | #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 159 | ||
| 3ea6bc3d | 160 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
161 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 162 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| c63847a3 NI |
163 | # define SCIF_ORER 0x0200 |
| 164 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) | |
| 165 | # define SCIF_RFDC_MASK 0x007f | |
| 166 | # define SCIF_TXROOM_MAX 64 | |
| 167 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | |
| 168 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK ) | |
| 169 | # define SCIF_RFDC_MASK 0x007f | |
| 170 | # define SCIF_TXROOM_MAX 64 | |
| 171 | /* SH7763 SCIF2 support */ | |
| 172 | # define SCIF2_RFDC_MASK 0x001f | |
| 173 | # define SCIF2_TXROOM_MAX 16 | |
| 1da177e4 | 174 | #else |
| c63847a3 NI |
175 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) |
| 176 | # define SCIF_RFDC_MASK 0x001f | |
| 177 | # define SCIF_TXROOM_MAX 16 | |
| 1da177e4 LT |
178 | #endif |
| 179 | ||
| d830fa45 PM |
180 | #ifndef SCIF_ORER |
| 181 | #define SCIF_ORER 0x0000 | |
| 182 | #endif | |
| 183 | ||
| 15c73aaa PM |
184 | #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) |
| 185 | #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) | |
| 186 | #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) | |
| 187 | #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) | |
| 188 | #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) | |
| 189 | #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | |
| 190 | #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | |
| d830fa45 | 191 | #define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) |
| 15c73aaa | 192 | |
| 3ea6bc3d | 193 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
194 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 195 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 15c73aaa PM |
196 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) |
| 197 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) | |
| 198 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) | |
| 199 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) | |
| 1da177e4 | 200 | #else |
| 1da177e4 LT |
201 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) |
| 202 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) | |
| 203 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) | |
| 204 | # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) | |
| 205 | #endif | |
| 206 | ||
| 207 | /* SCFCR */ | |
| 208 | #define SCFCR_RFRST 0x0002 | |
| 209 | #define SCFCR_TFRST 0x0004 | |
| 1da177e4 LT |
210 | #define SCFCR_MCE 0x0008 |
| 211 | ||
| 212 | #define SCI_MAJOR 204 | |
| 213 | #define SCI_MINOR_START 8 | |
| 214 | ||
| 1da177e4 | 215 | #define SCI_IN(size, offset) \ |
| b7a76e4b | 216 | if ((size) == 8) { \ |
| 7ff731ae | 217 | return ioread8(port->membase + (offset)); \ |
| b7a76e4b | 218 | } else { \ |
| 7ff731ae | 219 | return ioread16(port->membase + (offset)); \ |
| 1da177e4 LT |
220 | } |
| 221 | #define SCI_OUT(size, offset, value) \ | |
| b7a76e4b | 222 | if ((size) == 8) { \ |
| 7ff731ae | 223 | iowrite8(value, port->membase + (offset)); \ |
| 3d2c2f3e | 224 | } else if ((size) == 16) { \ |
| 7ff731ae | 225 | iowrite16(value, port->membase + (offset)); \ |
| 1da177e4 LT |
226 | } |
| 227 | ||
| 228 | #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ | |
| 229 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
| 230 | { \ | |
| 1a22f08d YS |
231 | if (port->type == PORT_SCIF) { \ |
| 232 | SCI_IN(scif_size, scif_offset) \ | |
| 233 | } else { /* PORT_SCI or PORT_SCIFA */ \ | |
| 234 | SCI_IN(sci_size, sci_offset); \ | |
| 1da177e4 LT |
235 | } \ |
| 236 | } \ | |
| 237 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
| 238 | { \ | |
| 1a22f08d YS |
239 | if (port->type == PORT_SCIF) { \ |
| 240 | SCI_OUT(scif_size, scif_offset, value) \ | |
| 241 | } else { /* PORT_SCI or PORT_SCIFA */ \ | |
| 242 | SCI_OUT(sci_size, sci_offset, value); \ | |
| 1da177e4 LT |
243 | } \ |
| 244 | } | |
| 245 | ||
| 168f3623 YS |
246 | #ifdef CONFIG_H8300 |
| 247 | /* h8300 don't have SCIF */ | |
| 248 | #define CPU_SCIF_FNS(name) \ | |
| 249 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
| 250 | { \ | |
| 251 | return 0; \ | |
| 252 | } \ | |
| 253 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
| 254 | { \ | |
| 255 | } | |
| 256 | #else | |
| 257 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ | |
| 1da177e4 LT |
258 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ |
| 259 | { \ | |
| b7a76e4b | 260 | SCI_IN(scif_size, scif_offset); \ |
| 1da177e4 LT |
261 | } \ |
| 262 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
| 263 | { \ | |
| 264 | SCI_OUT(scif_size, scif_offset, value); \ | |
| 265 | } | |
| 168f3623 | 266 | #endif |
| 1da177e4 LT |
267 | |
| 268 | #define CPU_SCI_FNS(name, sci_offset, sci_size) \ | |
| 269 | static inline unsigned int sci_##name##_in(struct uart_port* port) \ | |
| 270 | { \ | |
| b7a76e4b | 271 | SCI_IN(sci_size, sci_offset); \ |
| 1da177e4 LT |
272 | } \ |
| 273 | static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \ | |
| 274 | { \ | |
| 275 | SCI_OUT(sci_size, sci_offset, value); \ | |
| 276 | } | |
| 277 | ||
| 278 | #ifdef CONFIG_CPU_SH3 | |
| 9465a54f NI |
279 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
| 280 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 281 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 282 | h8_sci_offset, h8_sci_size) \ | |
| 283 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | |
| 284 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
| 285 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
| 3ea6bc3d | 286 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
287 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 288 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 1da177e4 LT |
289 | #define SCIF_FNS(name, scif_offset, scif_size) \ |
| 290 | CPU_SCIF_FNS(name, scif_offset, scif_size) | |
| 291 | #else | |
| 292 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 293 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 294 | h8_sci_offset, h8_sci_size) \ | |
| 295 | CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size) | |
| 296 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
| 297 | CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) | |
| 298 | #endif | |
| 299 | #elif defined(__H8300H__) || defined(__H8300S__) | |
| 300 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 301 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 302 | h8_sci_offset, h8_sci_size) \ | |
| 303 | CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) | |
| 168f3623 YS |
304 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ |
| 305 | CPU_SCIF_FNS(name) | |
| 47948d2b KM |
306 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ |
| 307 | defined(CONFIG_CPU_SUBTYPE_SH7724) | |
| 178dd0cd PM |
308 | #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \ |
| 309 | CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) | |
| 310 | #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ | |
| 311 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
| 1da177e4 LT |
312 | #else |
| 313 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 314 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 315 | h8_sci_offset, h8_sci_size) \ | |
| 316 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | |
| 317 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
| 318 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
| 319 | #endif | |
| 320 | ||
| 3ea6bc3d | 321 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
322 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 323 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 9465a54f | 324 | |
| 1da177e4 LT |
325 | SCIF_FNS(SCSMR, 0x00, 16) |
| 326 | SCIF_FNS(SCBRR, 0x04, 8) | |
| 327 | SCIF_FNS(SCSCR, 0x08, 16) | |
| 1da177e4 LT |
328 | SCIF_FNS(SCxSR, 0x14, 16) |
| 329 | SCIF_FNS(SCFCR, 0x18, 16) | |
| 330 | SCIF_FNS(SCFDR, 0x1c, 16) | |
| 331 | SCIF_FNS(SCxTDR, 0x20, 8) | |
| 332 | SCIF_FNS(SCxRDR, 0x24, 8) | |
| 333 | SCIF_FNS(SCLSR, 0x24, 16) | |
| 47948d2b KM |
334 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ |
| 335 | defined(CONFIG_CPU_SUBTYPE_SH7724) | |
| 178dd0cd PM |
336 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) |
| 337 | SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) | |
| 338 | SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) | |
| 339 | SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) | |
| 340 | SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) | |
| 341 | SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) | |
| f686359e | 342 | SCIx_FNS(SCSPTR, 0, 0, 0, 0) |
| 178dd0cd PM |
343 | SCIF_FNS(SCFCR, 0x18, 16) |
| 344 | SCIF_FNS(SCFDR, 0x1c, 16) | |
| 345 | SCIF_FNS(SCLSR, 0x24, 16) | |
| 1da177e4 LT |
346 | #else |
| 347 | /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ | |
| 348 | /* name off sz off sz off sz off sz off sz*/ | |
| 349 | SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) | |
| 350 | SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) | |
| 351 | SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) | |
| 352 | SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) | |
| 353 | SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) | |
| 354 | SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) | |
| 355 | SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) | |
| 32351a28 PM |
356 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
| 357 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
| 55ba99eb KM |
358 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
| 359 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
| c2697968 | 360 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
| b7a76e4b PM |
361 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) |
| 362 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
| 363 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
| 364 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
| c2697968 | 365 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
| c63847a3 NI |
366 | SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) |
| 367 | SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) | |
| c2697968 PM |
368 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) |
| 369 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
| 370 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
| 371 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
| b7a76e4b | 372 | #else |
| 1da177e4 | 373 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
| 9b4e466f MD |
374 | #if defined(CONFIG_CPU_SUBTYPE_SH7722) |
| 375 | SCIF_FNS(SCSPTR, 0, 0, 0, 0) | |
| 376 | #else | |
| 1da177e4 | 377 | SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) |
| 9b4e466f | 378 | #endif |
| 1da177e4 LT |
379 | SCIF_FNS(SCLSR, 0, 0, 0x24, 16) |
| 380 | #endif | |
| b7a76e4b | 381 | #endif |
| 1da177e4 LT |
382 | #define sci_in(port, reg) sci_##reg##_in(port) |
| 383 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | |
| 384 | ||
| 385 | /* H8/300 series SCI pins assignment */ | |
| 386 | #if defined(__H8300H__) || defined(__H8300S__) | |
| 387 | static const struct __attribute__((packed)) { | |
| 388 | int port; /* GPIO port no */ | |
| 389 | unsigned short rx,tx; /* GPIO bit no */ | |
| 390 | } h8300_sci_pins[] = { | |
| 391 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
| 392 | { /* SCI0 */ | |
| 393 | .port = H8300_GPIO_P9, | |
| 394 | .rx = H8300_GPIO_B2, | |
| 395 | .tx = H8300_GPIO_B0, | |
| 396 | }, | |
| 397 | { /* SCI1 */ | |
| 398 | .port = H8300_GPIO_P9, | |
| 399 | .rx = H8300_GPIO_B3, | |
| 400 | .tx = H8300_GPIO_B1, | |
| 401 | }, | |
| 402 | { /* SCI2 */ | |
| 403 | .port = H8300_GPIO_PB, | |
| 404 | .rx = H8300_GPIO_B7, | |
| 405 | .tx = H8300_GPIO_B6, | |
| 406 | } | |
| 407 | #elif defined(CONFIG_H8S2678) | |
| 408 | { /* SCI0 */ | |
| 409 | .port = H8300_GPIO_P3, | |
| 410 | .rx = H8300_GPIO_B2, | |
| 411 | .tx = H8300_GPIO_B0, | |
| 412 | }, | |
| 413 | { /* SCI1 */ | |
| 414 | .port = H8300_GPIO_P3, | |
| 415 | .rx = H8300_GPIO_B3, | |
| 416 | .tx = H8300_GPIO_B1, | |
| 417 | }, | |
| 418 | { /* SCI2 */ | |
| 419 | .port = H8300_GPIO_P5, | |
| 420 | .rx = H8300_GPIO_B1, | |
| 421 | .tx = H8300_GPIO_B0, | |
| 422 | } | |
| 423 | #endif | |
| 424 | }; | |
| 425 | #endif | |
| 426 | ||
| 0fbde950 MD |
427 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
| 428 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | |
| 429 | defined(CONFIG_CPU_SUBTYPE_SH7708) || \ | |
| 430 | defined(CONFIG_CPU_SUBTYPE_SH7709) | |
| 1da177e4 LT |
431 | static inline int sci_rxd_in(struct uart_port *port) |
| 432 | { | |
| 433 | if (port->mapbase == 0xfffffe80) | |
| 434 | return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | |
| 435 | if (port->mapbase == 0xa4000150) | |
| 436 | return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
| 437 | if (port->mapbase == 0xa4000140) | |
| 438 | return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
| 439 | return 1; | |
| 440 | } | |
| 441 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | |
| 442 | static inline int sci_rxd_in(struct uart_port *port) | |
| 443 | { | |
| 444 | if (port->mapbase == SCIF0) | |
| 445 | return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
| 446 | if (port->mapbase == SCIF2) | |
| 447 | return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
| 448 | return 1; | |
| 449 | } | |
| 9465a54f | 450 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
| e108b2ca PM |
451 | static inline int sci_rxd_in(struct uart_port *port) |
| 452 | { | |
| 9465a54f NI |
453 | return sci_in(port,SCxSR)&0x0010 ? 1 : 0; |
| 454 | } | |
| 31a49c4b YS |
455 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 456 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 3ea6bc3d MB |
457 | static inline int sci_rxd_in(struct uart_port *port) |
| 458 | { | |
| 459 | if (port->mapbase == 0xa4430000) | |
| 460 | return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; | |
| 461 | else if (port->mapbase == 0xa4438000) | |
| 462 | return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; | |
| 463 | return 1; | |
| 464 | } | |
| 05627486 PM |
465 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
| 466 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
| 467 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | |
| 468 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
| 469 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | |
| 961e9ff9 | 470 | defined(CONFIG_CPU_SUBTYPE_SH7091) |
| 1da177e4 LT |
471 | static inline int sci_rxd_in(struct uart_port *port) |
| 472 | { | |
| 1da177e4 LT |
473 | if (port->mapbase == 0xffe00000) |
| 474 | return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | |
| 1da177e4 LT |
475 | if (port->mapbase == 0xffe80000) |
| 476 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
| 1da177e4 LT |
477 | return 1; |
| 478 | } | |
| 961e9ff9 NI |
479 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
| 480 | static inline int sci_rxd_in(struct uart_port *port) | |
| 481 | { | |
| 482 | if (port->mapbase == 0xffe80000) | |
| 483 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
| 484 | return 1; | |
| 485 | } | |
| 1da177e4 LT |
486 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
| 487 | static inline int sci_rxd_in(struct uart_port *port) | |
| 488 | { | |
| 489 | if (port->mapbase == 0xfe600000) | |
| 490 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 491 | if (port->mapbase == 0xfe610000) | |
| 492 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 493 | if (port->mapbase == 0xfe620000) | |
| 494 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 495 | return 1; |
| 1da177e4 | 496 | } |
| e108b2ca PM |
497 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
| 498 | static inline int sci_rxd_in(struct uart_port *port) | |
| 499 | { | |
| 500 | if (port->mapbase == 0xffe00000) | |
| 501 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 502 | if (port->mapbase == 0xffe10000) | |
| 503 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 504 | if (port->mapbase == 0xffe20000) | |
| 505 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 506 | if (port->mapbase == 0xffe30000) | |
| 507 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 508 | return 1; | |
| 509 | } | |
| 346b7463 | 510 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
| 41504c39 PM |
511 | static inline int sci_rxd_in(struct uart_port *port) |
| 512 | { | |
| 513 | if (port->mapbase == 0xffe00000) | |
| 514 | return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ | |
| 515 | return 1; | |
| 516 | } | |
| 346b7463 MD |
517 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
| 518 | static inline int sci_rxd_in(struct uart_port *port) | |
| 519 | { | |
| 520 | if (port->mapbase == 0xffe00000) | |
| 521 | return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */ | |
| 522 | if (port->mapbase == 0xffe10000) | |
| 523 | return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */ | |
| 524 | if (port->mapbase == 0xffe20000) | |
| 525 | return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */ | |
| 526 | ||
| 527 | return 1; | |
| 528 | } | |
| 178dd0cd PM |
529 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
| 530 | static inline int sci_rxd_in(struct uart_port *port) | |
| 531 | { | |
| 532 | if (port->mapbase == 0xffe00000) | |
| 533 | return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */ | |
| 534 | if (port->mapbase == 0xffe10000) | |
| 535 | return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */ | |
| 536 | if (port->mapbase == 0xffe20000) | |
| 537 | return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */ | |
| 538 | if (port->mapbase == 0xa4e30000) | |
| 539 | return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */ | |
| 540 | if (port->mapbase == 0xa4e40000) | |
| 541 | return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */ | |
| 542 | if (port->mapbase == 0xa4e50000) | |
| 543 | return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ | |
| 544 | return 1; | |
| 545 | } | |
| 47948d2b KM |
546 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) |
| 547 | # define SCFSR 0x0010 | |
| 548 | # define SCASSR 0x0014 | |
| 549 | static inline int sci_rxd_in(struct uart_port *port) | |
| 550 | { | |
| 551 | if (port->type == PORT_SCIF) | |
| 552 | return ctrl_inw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0; | |
| 553 | if (port->type == PORT_SCIFA) | |
| 554 | return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0; | |
| 555 | return 1; | |
| 556 | } | |
| 1da177e4 LT |
557 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
| 558 | static inline int sci_rxd_in(struct uart_port *port) | |
| 559 | { | |
| e9e8b1fb | 560 | return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ |
| 1da177e4 LT |
561 | } |
| 562 | #elif defined(__H8300H__) || defined(__H8300S__) | |
| 563 | static inline int sci_rxd_in(struct uart_port *port) | |
| 564 | { | |
| 565 | int ch = (port->mapbase - SMR0) >> 3; | |
| 566 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; | |
| 567 | } | |
| 7d740a06 YS |
568 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 569 | static inline int sci_rxd_in(struct uart_port *port) | |
| 570 | { | |
| 571 | if (port->mapbase == 0xffe00000) | |
| 572 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 573 | if (port->mapbase == 0xffe08000) | |
| 574 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| c63847a3 NI |
575 | if (port->mapbase == 0xffe10000) |
| 576 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */ | |
| 577 | ||
| 7d740a06 YS |
578 | return 1; |
| 579 | } | |
| b7a76e4b PM |
580 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
| 581 | static inline int sci_rxd_in(struct uart_port *port) | |
| 582 | { | |
| 583 | if (port->mapbase == 0xff923000) | |
| 584 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 585 | if (port->mapbase == 0xff924000) | |
| 586 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 587 | if (port->mapbase == 0xff925000) | |
| 588 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 589 | return 1; |
| b7a76e4b PM |
590 | } |
| 591 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | |
| 592 | static inline int sci_rxd_in(struct uart_port *port) | |
| 593 | { | |
| 594 | if (port->mapbase == 0xffe00000) | |
| 595 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 596 | if (port->mapbase == 0xffe10000) | |
| 597 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 598 | return 1; |
| b7a76e4b | 599 | } |
| 55ba99eb KM |
600 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
| 601 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
| 32351a28 PM |
602 | static inline int sci_rxd_in(struct uart_port *port) |
| 603 | { | |
| 604 | if (port->mapbase == 0xffea0000) | |
| 605 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 606 | if (port->mapbase == 0xffeb0000) | |
| 607 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 608 | if (port->mapbase == 0xffec0000) | |
| 609 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 610 | if (port->mapbase == 0xffed0000) | |
| 611 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 612 | if (port->mapbase == 0xffee0000) | |
| 613 | return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 614 | if (port->mapbase == 0xffef0000) | |
| 615 | return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 616 | return 1; | |
| 617 | } | |
| 2825999e PG |
618 | #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ |
| 619 | defined(CONFIG_CPU_SUBTYPE_SH7203) || \ | |
| a8f67f4b PM |
620 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ |
| 621 | defined(CONFIG_CPU_SUBTYPE_SH7263) | |
| 9d4436a6 YS |
622 | static inline int sci_rxd_in(struct uart_port *port) |
| 623 | { | |
| 624 | if (port->mapbase == 0xfffe8000) | |
| 625 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 626 | if (port->mapbase == 0xfffe8800) | |
| 627 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 628 | if (port->mapbase == 0xfffe9000) | |
| 629 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 630 | if (port->mapbase == 0xfffe9800) | |
| 631 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 2825999e PG |
632 | #if defined(CONFIG_CPU_SUBTYPE_SH7201) |
| 633 | if (port->mapbase == 0xfffeA000) | |
| 634 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 635 | if (port->mapbase == 0xfffeA800) | |
| 636 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 637 | if (port->mapbase == 0xfffeB000) | |
| 638 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 639 | if (port->mapbase == 0xfffeB800) | |
| 640 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 641 | #endif | |
| 31388750 | 642 | return 1; |
| 9d4436a6 YS |
643 | } |
| 644 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | |
| 645 | static inline int sci_rxd_in(struct uart_port *port) | |
| 646 | { | |
| 647 | if (port->mapbase == 0xf8400000) | |
| 648 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 649 | if (port->mapbase == 0xf8410000) | |
| 650 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 651 | if (port->mapbase == 0xf8420000) | |
| 652 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 653 | return 1; |
| 9d4436a6 | 654 | } |
| 2b1bd1ac PM |
655 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
| 656 | static inline int sci_rxd_in(struct uart_port *port) | |
| 657 | { | |
| 658 | if (port->mapbase == 0xffc30000) | |
| 659 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 660 | if (port->mapbase == 0xffc40000) | |
| 661 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 662 | if (port->mapbase == 0xffc50000) | |
| 663 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 664 | if (port->mapbase == 0xffc60000) | |
| 665 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 1760b7d7 | 666 | return 1; |
| 2b1bd1ac | 667 | } |
| 1da177e4 | 668 | #endif |