[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / bfa / bfa_ioc.h

/*
 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
 * All rights reserved
 * www.brocade.com
 *
 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License (GPL) Version 2 as
 * published by the Free Software Foundation
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */

#ifndef __BFA_IOC_H__
#define __BFA_IOC_H__

#include "bfad_drv.h"
#include "bfa_cs.h"
#include "bfi.h"

#define BFA_DBG_FWTRC_ENTS	(BFI_IOC_TRC_ENTS)
#define BFA_DBG_FWTRC_LEN					\
	(BFA_DBG_FWTRC_ENTS * sizeof(struct bfa_trc_s) +	\
	(sizeof(struct bfa_trc_mod_s) -				\
	BFA_TRC_MAX * sizeof(struct bfa_trc_s)))
/*
 * BFA timer declarations
 */
typedef void (*bfa_timer_cbfn_t)(void *);

/*
 * BFA timer data structure
 */
struct bfa_timer_s {
	struct list_head	qe;
	bfa_timer_cbfn_t timercb;
	void		*arg;
	int		timeout;	/* in millisecs */
};

/*
 * Timer module structure
 */
struct bfa_timer_mod_s {
	struct list_head timer_q;
};

#define BFA_TIMER_FREQ 200 /* specified in millisecs */

void bfa_timer_beat(struct bfa_timer_mod_s *mod);
void bfa_timer_begin(struct bfa_timer_mod_s *mod, struct bfa_timer_s *timer,
			bfa_timer_cbfn_t timercb, void *arg,
			unsigned int timeout);
void bfa_timer_stop(struct bfa_timer_s *timer);

/*
 * Generic Scatter Gather Element used by driver
 */
struct bfa_sge_s {
	u32	sg_len;
	void		*sg_addr;
};

#define bfa_sge_word_swap(__sge) do {					     \
	((u32 *)(__sge))[0] = swab32(((u32 *)(__sge))[0]);      \
	((u32 *)(__sge))[1] = swab32(((u32 *)(__sge))[1]);      \
	((u32 *)(__sge))[2] = swab32(((u32 *)(__sge))[2]);      \
} while (0)

#define bfa_swap_words(_x)  (	\
	((_x) << 32) | ((_x) >> 32))

#ifdef __BIG_ENDIAN
#define bfa_sge_to_be(_x)
#define bfa_sge_to_le(_x)	bfa_sge_word_swap(_x)
#define bfa_sgaddr_le(_x)	bfa_swap_words(_x)
#else
#define	bfa_sge_to_be(_x)	bfa_sge_word_swap(_x)
#define bfa_sge_to_le(_x)
#define bfa_sgaddr_le(_x)	(_x)
#endif

/*
 * PCI device information required by IOC
 */
struct bfa_pcidev_s {
	int		pci_slot;
	u8		pci_func;
	u16		device_id;
	void __iomem	*pci_bar_kva;
};

/*
 * Structure used to remember the DMA-able memory block's KVA and Physical
 * Address
 */
struct bfa_dma_s {
	void		*kva;	/* ! Kernel virtual address	*/
	u64	pa;	/* ! Physical address		*/
};

#define BFA_DMA_ALIGN_SZ	256
#define BFA_ROUNDUP(_l, _s)	(((_l) + ((_s) - 1)) & ~((_s) - 1))

/*
 * smem size for Crossbow and Catapult
 */
#define BFI_SMEM_CB_SIZE	0x200000U	/* ! 2MB for crossbow	*/
#define BFI_SMEM_CT_SIZE	0x280000U	/* ! 2.5MB for catapult	*/

#define bfa_dma_be_addr_set(dma_addr, pa)	\
		__bfa_dma_be_addr_set(&dma_addr, (u64)pa)
static inline void
__bfa_dma_be_addr_set(union bfi_addr_u *dma_addr, u64 pa)
{
	dma_addr->a32.addr_lo = cpu_to_be32(pa);
	dma_addr->a32.addr_hi = cpu_to_be32(pa >> 32);
}

#define bfa_alen_set(__alen, __len, __pa)	\
	__bfa_alen_set(__alen, __len, (u64)__pa)

static inline void
__bfa_alen_set(struct bfi_alen_s *alen, u32 len, u64 pa)
{
	alen->al_len = cpu_to_be32(len);
	bfa_dma_be_addr_set(alen->al_addr, pa);
}

struct bfa_ioc_regs_s {
	void __iomem *hfn_mbox_cmd;
	void __iomem *hfn_mbox;
	void __iomem *lpu_mbox_cmd;
	void __iomem *lpu_mbox;
	void __iomem *pss_ctl_reg;
	void __iomem *pss_err_status_reg;
	void __iomem *app_pll_fast_ctl_reg;
	void __iomem *app_pll_slow_ctl_reg;
	void __iomem *ioc_sem_reg;
	void __iomem *ioc_usage_sem_reg;
	void __iomem *ioc_init_sem_reg;
	void __iomem *ioc_usage_reg;
	void __iomem *host_page_num_fn;
	void __iomem *heartbeat;
	void __iomem *ioc_fwstate;
	void __iomem *alt_ioc_fwstate;
	void __iomem *ll_halt;
	void __iomem *alt_ll_halt;
	void __iomem *err_set;
	void __iomem *ioc_fail_sync;
	void __iomem *shirq_isr_next;
	void __iomem *shirq_msk_next;
	void __iomem *smem_page_start;
	u32	smem_pg0;
};

#define bfa_mem_read(_raddr, _off)	swab32(readl(((_raddr) + (_off))))
#define bfa_mem_write(_raddr, _off, _val)	\
			writel(swab32((_val)), ((_raddr) + (_off)))
/*
 * IOC Mailbox structures
 */
struct bfa_mbox_cmd_s {
	struct list_head	qe;
	u32	msg[BFI_IOC_MSGSZ];
};

/*
 * IOC mailbox module
 */
typedef void (*bfa_ioc_mbox_mcfunc_t)(void *cbarg, struct bfi_mbmsg_s *m);
struct bfa_ioc_mbox_mod_s {
	struct list_head		cmd_q;	/*  pending mbox queue	*/
	int			nmclass;	/*  number of handlers */
	struct {
		bfa_ioc_mbox_mcfunc_t	cbfn;	/*  message handlers	*/
		void			*cbarg;
	} mbhdlr[BFI_MC_MAX];
};

/*
 * IOC callback function interfaces
 */
typedef void (*bfa_ioc_enable_cbfn_t)(void *bfa, enum bfa_status status);
typedef void (*bfa_ioc_disable_cbfn_t)(void *bfa);
typedef void (*bfa_ioc_hbfail_cbfn_t)(void *bfa);
typedef void (*bfa_ioc_reset_cbfn_t)(void *bfa);
struct bfa_ioc_cbfn_s {
	bfa_ioc_enable_cbfn_t	enable_cbfn;
	bfa_ioc_disable_cbfn_t	disable_cbfn;
	bfa_ioc_hbfail_cbfn_t	hbfail_cbfn;
	bfa_ioc_reset_cbfn_t	reset_cbfn;
};

/*
 * Heartbeat failure notification queue element.
 */
struct bfa_ioc_hbfail_notify_s {
	struct list_head		qe;
	bfa_ioc_hbfail_cbfn_t	cbfn;
	void			*cbarg;
};

/*
 * Initialize a heartbeat failure notification structure
 */
#define bfa_ioc_hbfail_init(__notify, __cbfn, __cbarg) do {	\
	(__notify)->cbfn = (__cbfn);      \
	(__notify)->cbarg = (__cbarg);      \
} while (0)

struct bfa_iocpf_s {
	bfa_fsm_t		fsm;
	struct bfa_ioc_s	*ioc;
	u32		retry_count;
	bfa_boolean_t		auto_recover;
};

struct bfa_ioc_s {
	bfa_fsm_t		fsm;
	struct bfa_s		*bfa;
	struct bfa_pcidev_s	pcidev;
	struct bfa_timer_mod_s	*timer_mod;
	struct bfa_timer_s	ioc_timer;
	struct bfa_timer_s	sem_timer;
	struct bfa_timer_s	hb_timer;
	u32		hb_count;
	struct list_head		hb_notify_q;
	void			*dbg_fwsave;
	int			dbg_fwsave_len;
	bfa_boolean_t		dbg_fwsave_once;
	enum bfi_mclass		ioc_mc;
	struct bfa_ioc_regs_s	ioc_regs;
	struct bfa_trc_mod_s	*trcmod;
	struct bfa_ioc_drv_stats_s	stats;
	bfa_boolean_t		fcmode;
	bfa_boolean_t		ctdev;
	bfa_boolean_t		cna;
	bfa_boolean_t		pllinit;
	bfa_boolean_t		stats_busy;	/*  outstanding stats */
	u8			port_id;
	struct bfa_dma_s	attr_dma;
	struct bfi_ioc_attr_s	*attr;
	struct bfa_ioc_cbfn_s	*cbfn;
	struct bfa_ioc_mbox_mod_s mbox_mod;
	struct bfa_ioc_hwif_s	*ioc_hwif;
	struct bfa_iocpf_s	iocpf;
};

struct bfa_ioc_hwif_s {
	bfa_status_t (*ioc_pll_init) (void __iomem *rb, bfa_boolean_t fcmode);
	bfa_boolean_t	(*ioc_firmware_lock)	(struct bfa_ioc_s *ioc);
	void		(*ioc_firmware_unlock)	(struct bfa_ioc_s *ioc);
	void		(*ioc_reg_init)	(struct bfa_ioc_s *ioc);
	void		(*ioc_map_port)	(struct bfa_ioc_s *ioc);
	void		(*ioc_isr_mode_set)	(struct bfa_ioc_s *ioc,
					bfa_boolean_t msix);
	void		(*ioc_notify_fail)	(struct bfa_ioc_s *ioc);
	void		(*ioc_ownership_reset)	(struct bfa_ioc_s *ioc);
	bfa_boolean_t   (*ioc_sync_start)       (struct bfa_ioc_s *ioc);
	void		(*ioc_sync_join)	(struct bfa_ioc_s *ioc);
	void		(*ioc_sync_leave)	(struct bfa_ioc_s *ioc);
	void		(*ioc_sync_ack)		(struct bfa_ioc_s *ioc);
	bfa_boolean_t	(*ioc_sync_complete)	(struct bfa_ioc_s *ioc);
};

#define bfa_ioc_pcifn(__ioc)		((__ioc)->pcidev.pci_func)
#define bfa_ioc_devid(__ioc)		((__ioc)->pcidev.device_id)
#define bfa_ioc_bar0(__ioc)		((__ioc)->pcidev.pci_bar_kva)
#define bfa_ioc_portid(__ioc)		((__ioc)->port_id)
#define bfa_ioc_fetch_stats(__ioc, __stats) \
		(((__stats)->drv_stats) = (__ioc)->stats)
#define bfa_ioc_clr_stats(__ioc)	\
		memset(&(__ioc)->stats, 0, sizeof((__ioc)->stats))
#define bfa_ioc_maxfrsize(__ioc)	((__ioc)->attr->maxfrsize)
#define bfa_ioc_rx_bbcredit(__ioc)	((__ioc)->attr->rx_bbcredit)
#define bfa_ioc_speed_sup(__ioc)	\
	BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop)
#define bfa_ioc_get_nports(__ioc)	\
	BFI_ADAPTER_GETP(NPORTS, (__ioc)->attr->adapter_prop)

#define bfa_ioc_stats(_ioc, _stats)	((_ioc)->stats._stats++)
#define BFA_IOC_FWIMG_MINSZ	(16 * 1024)
#define BFA_IOC_FWIMG_TYPE(__ioc)					\
	(((__ioc)->ctdev) ?						\
	 (((__ioc)->fcmode) ? BFI_IMAGE_CT_FC : BFI_IMAGE_CT_CNA) :	\
	 BFI_IMAGE_CB_FC)
#define BFA_IOC_FW_SMEM_SIZE(__ioc)					\
	(((__ioc)->ctdev) ? BFI_SMEM_CT_SIZE : BFI_SMEM_CB_SIZE)
#define BFA_IOC_FLASH_CHUNK_NO(off)		(off / BFI_FLASH_CHUNK_SZ_WORDS)
#define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off)	(off % BFI_FLASH_CHUNK_SZ_WORDS)
#define BFA_IOC_FLASH_CHUNK_ADDR(chunkno)  (chunkno * BFI_FLASH_CHUNK_SZ_WORDS)

/*
 * IOC mailbox interface
 */
void bfa_ioc_mbox_queue(struct bfa_ioc_s *ioc, struct bfa_mbox_cmd_s *cmd);
void bfa_ioc_mbox_register(struct bfa_ioc_s *ioc,
		bfa_ioc_mbox_mcfunc_t *mcfuncs);
void bfa_ioc_mbox_isr(struct bfa_ioc_s *ioc);
void bfa_ioc_mbox_send(struct bfa_ioc_s *ioc, void *ioc_msg, int len);
void bfa_ioc_msgget(struct bfa_ioc_s *ioc, void *mbmsg);
void bfa_ioc_mbox_regisr(struct bfa_ioc_s *ioc, enum bfi_mclass mc,
		bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg);

/*
 * IOC interfaces
 */

#define bfa_ioc_pll_init_asic(__ioc) \
	((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \
			   (__ioc)->fcmode))

bfa_status_t bfa_ioc_pll_init(struct bfa_ioc_s *ioc);
bfa_status_t bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode);
bfa_boolean_t bfa_ioc_ct_pll_init_complete(void __iomem *rb);
bfa_status_t bfa_ioc_ct_pll_init(void __iomem *rb, bfa_boolean_t fcmode);

#define	bfa_ioc_isr_mode_set(__ioc, __msix)			\
			((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix))
#define	bfa_ioc_ownership_reset(__ioc)				\
			((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc))


void bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc);
void bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc);

void bfa_ioc_attach(struct bfa_ioc_s *ioc, void *bfa,
		struct bfa_ioc_cbfn_s *cbfn, struct bfa_timer_mod_s *timer_mod);
void bfa_ioc_auto_recover(bfa_boolean_t auto_recover);
void bfa_ioc_detach(struct bfa_ioc_s *ioc);
void bfa_ioc_pci_init(struct bfa_ioc_s *ioc, struct bfa_pcidev_s *pcidev,
		enum bfi_mclass mc);
void bfa_ioc_mem_claim(struct bfa_ioc_s *ioc,  u8 *dm_kva, u64 dm_pa);
void bfa_ioc_enable(struct bfa_ioc_s *ioc);
void bfa_ioc_disable(struct bfa_ioc_s *ioc);
bfa_boolean_t bfa_ioc_intx_claim(struct bfa_ioc_s *ioc);

void bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type,
		u32 boot_param);
void bfa_ioc_isr(struct bfa_ioc_s *ioc, struct bfi_mbmsg_s *msg);
void bfa_ioc_error_isr(struct bfa_ioc_s *ioc);
bfa_boolean_t bfa_ioc_is_operational(struct bfa_ioc_s *ioc);
bfa_boolean_t bfa_ioc_is_initialized(struct bfa_ioc_s *ioc);
bfa_boolean_t bfa_ioc_is_disabled(struct bfa_ioc_s *ioc);
bfa_boolean_t bfa_ioc_fw_mismatch(struct bfa_ioc_s *ioc);
bfa_boolean_t bfa_ioc_adapter_is_disabled(struct bfa_ioc_s *ioc);
void bfa_ioc_reset_fwstate(struct bfa_ioc_s *ioc);
enum bfa_ioc_type_e bfa_ioc_get_type(struct bfa_ioc_s *ioc);
void bfa_ioc_get_adapter_serial_num(struct bfa_ioc_s *ioc, char *serial_num);
void bfa_ioc_get_adapter_fw_ver(struct bfa_ioc_s *ioc, char *fw_ver);
void bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc_s *ioc, char *optrom_ver);
void bfa_ioc_get_adapter_model(struct bfa_ioc_s *ioc, char *model);
void bfa_ioc_get_adapter_manufacturer(struct bfa_ioc_s *ioc,
		char *manufacturer);
void bfa_ioc_get_pci_chip_rev(struct bfa_ioc_s *ioc, char *chip_rev);
enum bfa_ioc_state bfa_ioc_get_state(struct bfa_ioc_s *ioc);

void bfa_ioc_get_attr(struct bfa_ioc_s *ioc, struct bfa_ioc_attr_s *ioc_attr);
void bfa_ioc_get_adapter_attr(struct bfa_ioc_s *ioc,
		struct bfa_adapter_attr_s *ad_attr);
void bfa_ioc_debug_memclaim(struct bfa_ioc_s *ioc, void *dbg_fwsave);
bfa_status_t bfa_ioc_debug_fwsave(struct bfa_ioc_s *ioc, void *trcdata,
		int *trclen);
bfa_status_t bfa_ioc_debug_fwtrc(struct bfa_ioc_s *ioc, void *trcdata,
				 int *trclen);
bfa_status_t bfa_ioc_debug_fwcore(struct bfa_ioc_s *ioc, void *buf,
	u32 *offset, int *buflen);
void bfa_ioc_set_fcmode(struct bfa_ioc_s *ioc);
bfa_boolean_t bfa_ioc_get_fcmode(struct bfa_ioc_s *ioc);
bfa_boolean_t bfa_ioc_sem_get(void __iomem *sem_reg);
void bfa_ioc_fwver_get(struct bfa_ioc_s *ioc,
			struct bfi_ioc_image_hdr_s *fwhdr);
bfa_boolean_t bfa_ioc_fwver_cmp(struct bfa_ioc_s *ioc,
			struct bfi_ioc_image_hdr_s *fwhdr);
bfa_status_t bfa_ioc_fw_stats_get(struct bfa_ioc_s *ioc, void *stats);
bfa_status_t bfa_ioc_fw_stats_clear(struct bfa_ioc_s *ioc);

/*
 * bfa mfg wwn API functions
 */
mac_t bfa_ioc_get_mac(struct bfa_ioc_s *ioc);
mac_t bfa_ioc_get_mfg_mac(struct bfa_ioc_s *ioc);

/*
 * F/W Image Size & Chunk
 */
extern u32 bfi_image_ct_fc_size;
extern u32 bfi_image_ct_cna_size;
extern u32 bfi_image_cb_fc_size;
extern u32 *bfi_image_ct_fc;
extern u32 *bfi_image_ct_cna;
extern u32 *bfi_image_cb_fc;

static inline u32 *
bfi_image_ct_fc_get_chunk(u32 off)
{	return (u32 *)(bfi_image_ct_fc + off); }

static inline u32 *
bfi_image_ct_cna_get_chunk(u32 off)
{	return (u32 *)(bfi_image_ct_cna + off); }

static inline u32 *
bfi_image_cb_fc_get_chunk(u32 off)
{	return (u32 *)(bfi_image_cb_fc + off); }

static inline u32*
bfa_cb_image_get_chunk(int type, u32 off)
{
	switch (type) {
	case BFI_IMAGE_CT_FC:
		return bfi_image_ct_fc_get_chunk(off);	break;
	case BFI_IMAGE_CT_CNA:
		return bfi_image_ct_cna_get_chunk(off);	break;
	case BFI_IMAGE_CB_FC:
		return bfi_image_cb_fc_get_chunk(off);	break;
	default: return NULL;
	}
}

static inline u32
bfa_cb_image_get_size(int type)
{
	switch (type) {
	case BFI_IMAGE_CT_FC:
		return bfi_image_ct_fc_size;	break;
	case BFI_IMAGE_CT_CNA:
		return bfi_image_ct_cna_size;	break;
	case BFI_IMAGE_CB_FC:
		return bfi_image_cb_fc_size;	break;
	default: return 0;
	}
}

/*
 * CNA TRCMOD declaration
 */
/*
 * !!! Only append to the enums defined here to avoid any versioning
 * !!! needed between trace utility and driver version
 */
enum {
	BFA_TRC_CNA_PORT	= 1,
	BFA_TRC_CNA_IOC		= 2,
	BFA_TRC_CNA_IOC_CB	= 3,
	BFA_TRC_CNA_IOC_CT	= 4,
};

#endif /* __BFA_IOC_H__ */
Commit	Line	Data
7725ccfd	1	/*
a36c61f9	2	* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
7725ccfd JH	3	* All rights reserved
	4	* www.brocade.com
	5	*
	6	* Linux driver for Brocade Fibre Channel Host Bus Adapter.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License (GPL) Version 2 as
	10	* published by the Free Software Foundation
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*/
	17
	18	#ifndef __BFA_IOC_H__
	19	#define __BFA_IOC_H__
	20
f16a1750	21	#include "bfad_drv.h"
a36c61f9 KG	22	#include "bfa_cs.h"
	23	#include "bfi.h"
	24
f7f73812 MZ	25	#define BFA_DBG_FWTRC_ENTS (BFI_IOC_TRC_ENTS)
	26	#define BFA_DBG_FWTRC_LEN \
	27	(BFA_DBG_FWTRC_ENTS * sizeof(struct bfa_trc_s) + \
	28	(sizeof(struct bfa_trc_mod_s) - \
	29	BFA_TRC_MAX * sizeof(struct bfa_trc_s)))
acdc79a6	30	/*
a36c61f9 KG	31	* BFA timer declarations
	32	*/
	33	typedef void (bfa_timer_cbfn_t)(void );
	34
acdc79a6	35	/*
a36c61f9 KG	36	* BFA timer data structure
	37	*/
	38	struct bfa_timer_s {
	39	struct list_head qe;
	40	bfa_timer_cbfn_t timercb;
	41	void *arg;
acdc79a6	42	int timeout; /* in millisecs */
a36c61f9 KG	43	};
a36c61f9 KG	44
acdc79a6	45	/*
a36c61f9 KG	46	* Timer module structure
	47	*/
	48	struct bfa_timer_mod_s {
	49	struct list_head timer_q;
	50	};
	51
acdc79a6	52	#define BFA_TIMER_FREQ 200 /* specified in millisecs */
a36c61f9 KG	53
a36c61f9 KG	54	void bfa_timer_beat(struct bfa_timer_mod_s *mod);
a36c61f9 KG	55	void bfa_timer_begin(struct bfa_timer_mod_s mod, struct bfa_timer_s timer,
	56	bfa_timer_cbfn_t timercb, void *arg,
	57	unsigned int timeout);
	58	void bfa_timer_stop(struct bfa_timer_s *timer);
	59
acdc79a6	60	/*
a36c61f9 KG	61	* Generic Scatter Gather Element used by driver
	62	*/
	63	struct bfa_sge_s {
	64	u32 sg_len;
	65	void *sg_addr;
	66	};
	67
	68	#define bfa_sge_word_swap(__sge) do { \
53440260 JH	69	((u32 )(__sge))[0] = swab32(((u32 )(__sge))[0]); \
	70	((u32 )(__sge))[1] = swab32(((u32 )(__sge))[1]); \
	71	((u32 )(__sge))[2] = swab32(((u32 )(__sge))[2]); \
a36c61f9 KG	72	} while (0)
	73
	74	#define bfa_swap_words(_x) ( \
	75	((_x) << 32) \| ((_x) >> 32))
	76
f16a1750	77	#ifdef __BIG_ENDIAN
a36c61f9 KG	78	#define bfa_sge_to_be(_x)
	79	#define bfa_sge_to_le(_x) bfa_sge_word_swap(_x)
	80	#define bfa_sgaddr_le(_x) bfa_swap_words(_x)
	81	#else
	82	#define bfa_sge_to_be(_x) bfa_sge_word_swap(_x)
	83	#define bfa_sge_to_le(_x)
	84	#define bfa_sgaddr_le(_x) (_x)
	85	#endif
7725ccfd	86
acdc79a6	87	/*
7725ccfd JH	88	* PCI device information required by IOC
	89	*/
	90	struct bfa_pcidev_s {
a36c61f9 KG	91	int pci_slot;
a36c61f9 KG	92	u8 pci_func;
acdc79a6 JH	93	u16 device_id;
acdc79a6 JH	94	void __iomem *pci_bar_kva;
7725ccfd JH	95	};
7725ccfd JH	96
acdc79a6	97	/*
7725ccfd JH	98	* Structure used to remember the DMA-able memory block's KVA and Physical
	99	* Address
	100	*/
	101	struct bfa_dma_s {
a36c61f9 KG	102	void kva; / ! Kernel virtual address */
a36c61f9 KG	103	u64 pa; /* ! Physical address */
7725ccfd JH	104	};
	105
	106	#define BFA_DMA_ALIGN_SZ 256
	107	#define BFA_ROUNDUP(_l, _s) (((_l) + ((_s) - 1)) & ~((_s) - 1))
	108
acdc79a6	109	/*
a36c61f9 KG	110	* smem size for Crossbow and Catapult
	111	*/
	112	#define BFI_SMEM_CB_SIZE 0x200000U /* ! 2MB for crossbow */
	113	#define BFI_SMEM_CT_SIZE 0x280000U /* ! 2.5MB for catapult */
7725ccfd	114
7725ccfd JH	115	#define bfa_dma_be_addr_set(dma_addr, pa) \
	116	__bfa_dma_be_addr_set(&dma_addr, (u64)pa)
	117	static inline void
	118	__bfa_dma_be_addr_set(union bfi_addr_u *dma_addr, u64 pa)
	119	{
50444a34	120	dma_addr->a32.addr_lo = cpu_to_be32(pa);
f16a1750	121	dma_addr->a32.addr_hi = cpu_to_be32(pa >> 32);
7725ccfd JH	122	}
7725ccfd JH	123
85ce928d KG	124	#define bfa_alen_set(__alen, __len, __pa) \
	125	__bfa_alen_set(__alen, __len, (u64)__pa)
	126
	127	static inline void
	128	__bfa_alen_set(struct bfi_alen_s *alen, u32 len, u64 pa)
	129	{
	130	alen->al_len = cpu_to_be32(len);
	131	bfa_dma_be_addr_set(alen->al_addr, pa);
	132	}
	133
7725ccfd	134	struct bfa_ioc_regs_s {
53440260 JH	135	void __iomem *hfn_mbox_cmd;
	136	void __iomem *hfn_mbox;
	137	void __iomem *lpu_mbox_cmd;
	138	void __iomem *lpu_mbox;
	139	void __iomem *pss_ctl_reg;
	140	void __iomem *pss_err_status_reg;
	141	void __iomem *app_pll_fast_ctl_reg;
	142	void __iomem *app_pll_slow_ctl_reg;
	143	void __iomem *ioc_sem_reg;
	144	void __iomem *ioc_usage_sem_reg;
	145	void __iomem *ioc_init_sem_reg;
	146	void __iomem *ioc_usage_reg;
	147	void __iomem *host_page_num_fn;
	148	void __iomem *heartbeat;
	149	void __iomem *ioc_fwstate;
f1d584d7	150	void __iomem *alt_ioc_fwstate;
53440260	151	void __iomem *ll_halt;
f1d584d7	152	void __iomem *alt_ll_halt;
53440260	153	void __iomem *err_set;
f1d584d7	154	void __iomem *ioc_fail_sync;
53440260 JH	155	void __iomem *shirq_isr_next;
	156	void __iomem *shirq_msk_next;
	157	void __iomem *smem_page_start;
7725ccfd JH	158	u32 smem_pg0;
	159	};
	160
53440260	161	#define bfa_mem_read(_raddr, _off) swab32(readl(((_raddr) + (_off))))
7725ccfd	162	#define bfa_mem_write(_raddr, _off, _val) \
53440260	163	writel(swab32((_val)), ((_raddr) + (_off)))
acdc79a6	164	/*
7725ccfd JH	165	* IOC Mailbox structures
	166	*/
	167	struct bfa_mbox_cmd_s {
a36c61f9	168	struct list_head qe;
7725ccfd JH	169	u32 msg[BFI_IOC_MSGSZ];
	170	};
	171
acdc79a6	172	/*
7725ccfd JH	173	* IOC mailbox module
	174	*/
	175	typedef void (bfa_ioc_mbox_mcfunc_t)(void cbarg, struct bfi_mbmsg_s *m);
	176	struct bfa_ioc_mbox_mod_s {
a36c61f9 KG	177	struct list_head cmd_q; /* pending mbox queue */
a36c61f9 KG	178	int nmclass; /* number of handlers */
7725ccfd JH	179	struct {
	180	bfa_ioc_mbox_mcfunc_t cbfn; /* message handlers */
	181	void *cbarg;
	182	} mbhdlr[BFI_MC_MAX];
	183	};
	184
acdc79a6	185	/*
7725ccfd JH	186	* IOC callback function interfaces
	187	*/
	188	typedef void (bfa_ioc_enable_cbfn_t)(void bfa, enum bfa_status status);
	189	typedef void (bfa_ioc_disable_cbfn_t)(void bfa);
	190	typedef void (bfa_ioc_hbfail_cbfn_t)(void bfa);
	191	typedef void (bfa_ioc_reset_cbfn_t)(void bfa);
	192	struct bfa_ioc_cbfn_s {
	193	bfa_ioc_enable_cbfn_t enable_cbfn;
	194	bfa_ioc_disable_cbfn_t disable_cbfn;
	195	bfa_ioc_hbfail_cbfn_t hbfail_cbfn;
	196	bfa_ioc_reset_cbfn_t reset_cbfn;
	197	};
	198
acdc79a6	199	/*
7725ccfd JH	200	* Heartbeat failure notification queue element.
	201	*/
	202	struct bfa_ioc_hbfail_notify_s {
	203	struct list_head qe;
	204	bfa_ioc_hbfail_cbfn_t cbfn;
	205	void *cbarg;
	206	};
	207
acdc79a6	208	/*
7725ccfd JH	209	* Initialize a heartbeat failure notification structure
	210	*/
	211	#define bfa_ioc_hbfail_init(__notify, __cbfn, __cbarg) do { \
	212	(__notify)->cbfn = (__cbfn); \
	213	(__notify)->cbarg = (__cbarg); \
	214	} while (0)
	215
a36c61f9 KG	216	struct bfa_iocpf_s {
	217	bfa_fsm_t fsm;
	218	struct bfa_ioc_s *ioc;
	219	u32 retry_count;
	220	bfa_boolean_t auto_recover;
	221	};
	222
7725ccfd JH	223	struct bfa_ioc_s {
	224	bfa_fsm_t fsm;
	225	struct bfa_s *bfa;
	226	struct bfa_pcidev_s pcidev;
a36c61f9 KG	227	struct bfa_timer_mod_s *timer_mod;
	228	struct bfa_timer_s ioc_timer;
	229	struct bfa_timer_s sem_timer;
	230	struct bfa_timer_s hb_timer;
7725ccfd	231	u32 hb_count;
7725ccfd JH	232	struct list_head hb_notify_q;
	233	void *dbg_fwsave;
	234	int dbg_fwsave_len;
	235	bfa_boolean_t dbg_fwsave_once;
	236	enum bfi_mclass ioc_mc;
a36c61f9	237	struct bfa_ioc_regs_s ioc_regs;
7725ccfd	238	struct bfa_trc_mod_s *trcmod;
7725ccfd	239	struct bfa_ioc_drv_stats_s stats;
7725ccfd JH	240	bfa_boolean_t fcmode;
	241	bfa_boolean_t ctdev;
	242	bfa_boolean_t cna;
	243	bfa_boolean_t pllinit;
a36c61f9	244	bfa_boolean_t stats_busy; /* outstanding stats */
7725ccfd	245	u8 port_id;
7725ccfd JH	246	struct bfa_dma_s attr_dma;
	247	struct bfi_ioc_attr_s *attr;
	248	struct bfa_ioc_cbfn_s *cbfn;
	249	struct bfa_ioc_mbox_mod_s mbox_mod;
a36c61f9 KG	250	struct bfa_ioc_hwif_s *ioc_hwif;
a36c61f9 KG	251	struct bfa_iocpf_s iocpf;
0a20de44 KG	252	};
	253
	254	struct bfa_ioc_hwif_s {
53440260	255	bfa_status_t (ioc_pll_init) (void __iomem rb, bfa_boolean_t fcmode);
a36c61f9 KG	256	bfa_boolean_t (ioc_firmware_lock) (struct bfa_ioc_s ioc);
	257	void (ioc_firmware_unlock) (struct bfa_ioc_s ioc);
	258	void (ioc_reg_init) (struct bfa_ioc_s ioc);
	259	void (ioc_map_port) (struct bfa_ioc_s ioc);
	260	void (ioc_isr_mode_set) (struct bfa_ioc_s ioc,
	261	bfa_boolean_t msix);
f1d584d7	262	void (ioc_notify_fail) (struct bfa_ioc_s ioc);
a36c61f9	263	void (ioc_ownership_reset) (struct bfa_ioc_s ioc);
45d7f0cc	264	bfa_boolean_t (ioc_sync_start) (struct bfa_ioc_s ioc);
f1d584d7 KG	265	void (ioc_sync_join) (struct bfa_ioc_s ioc);
	266	void (ioc_sync_leave) (struct bfa_ioc_s ioc);
	267	void (ioc_sync_ack) (struct bfa_ioc_s ioc);
	268	bfa_boolean_t (ioc_sync_complete) (struct bfa_ioc_s ioc);
7725ccfd JH	269	};
7725ccfd JH	270
f8ceafde JH	271	#define bfa_ioc_pcifn(__ioc) ((__ioc)->pcidev.pci_func)
	272	#define bfa_ioc_devid(__ioc) ((__ioc)->pcidev.device_id)
	273	#define bfa_ioc_bar0(__ioc) ((__ioc)->pcidev.pci_bar_kva)
7725ccfd JH	274	#define bfa_ioc_portid(__ioc) ((__ioc)->port_id)
7725ccfd JH	275	#define bfa_ioc_fetch_stats(__ioc, __stats) \
f8ceafde	276	(((__stats)->drv_stats) = (__ioc)->stats)
7725ccfd	277	#define bfa_ioc_clr_stats(__ioc) \
6a18b167	278	memset(&(__ioc)->stats, 0, sizeof((__ioc)->stats))
f8ceafde JH	279	#define bfa_ioc_maxfrsize(__ioc) ((__ioc)->attr->maxfrsize)
f8ceafde JH	280	#define bfa_ioc_rx_bbcredit(__ioc) ((__ioc)->attr->rx_bbcredit)
7725ccfd JH	281	#define bfa_ioc_speed_sup(__ioc) \
7725ccfd JH	282	BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop)
a36c61f9	283	#define bfa_ioc_get_nports(__ioc) \
0a20de44 KG	284	BFI_ADAPTER_GETP(NPORTS, (__ioc)->attr->adapter_prop)
0a20de44 KG	285
a36c61f9 KG	286	#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++)
	287	#define BFA_IOC_FWIMG_MINSZ (16 * 1024)
	288	#define BFA_IOC_FWIMG_TYPE(__ioc) \
	289	(((__ioc)->ctdev) ? \
	290	(((__ioc)->fcmode) ? BFI_IMAGE_CT_FC : BFI_IMAGE_CT_CNA) : \
293f82d5	291	BFI_IMAGE_CB_FC)
a36c61f9 KG	292	#define BFA_IOC_FW_SMEM_SIZE(__ioc) \
	293	(((__ioc)->ctdev) ? BFI_SMEM_CT_SIZE : BFI_SMEM_CB_SIZE)
	294	#define BFA_IOC_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS)
	295	#define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS)
0a20de44	296	#define BFA_IOC_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS)
7725ccfd	297
acdc79a6	298	/*
7725ccfd JH	299	* IOC mailbox interface
	300	*/
	301	void bfa_ioc_mbox_queue(struct bfa_ioc_s ioc, struct bfa_mbox_cmd_s cmd);
	302	void bfa_ioc_mbox_register(struct bfa_ioc_s *ioc,
	303	bfa_ioc_mbox_mcfunc_t *mcfuncs);
	304	void bfa_ioc_mbox_isr(struct bfa_ioc_s *ioc);
	305	void bfa_ioc_mbox_send(struct bfa_ioc_s ioc, void ioc_msg, int len);
	306	void bfa_ioc_msgget(struct bfa_ioc_s ioc, void mbmsg);
	307	void bfa_ioc_mbox_regisr(struct bfa_ioc_s *ioc, enum bfi_mclass mc,
	308	bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg);
	309
acdc79a6	310	/*
7725ccfd JH	311	* IOC interfaces
7725ccfd JH	312	*/
a36c61f9 KG	313
	314	#define bfa_ioc_pll_init_asic(__ioc) \
	315	((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \
	316	(__ioc)->fcmode))
	317
	318	bfa_status_t bfa_ioc_pll_init(struct bfa_ioc_s *ioc);
53440260 JH	319	bfa_status_t bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode);
	320	bfa_boolean_t bfa_ioc_ct_pll_init_complete(void __iomem *rb);
	321	bfa_status_t bfa_ioc_ct_pll_init(void __iomem *rb, bfa_boolean_t fcmode);
a36c61f9 KG	322
a36c61f9 KG	323	#define bfa_ioc_isr_mode_set(__ioc, __msix) \
0a20de44	324	((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix))
a36c61f9	325	#define bfa_ioc_ownership_reset(__ioc) \
0a20de44 KG	326	((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc))
0a20de44 KG	327
a36c61f9	328
0a20de44 KG	329	void bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc);
0a20de44 KG	330	void bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc);
a36c61f9	331
7725ccfd	332	void bfa_ioc_attach(struct bfa_ioc_s ioc, void bfa,
a36c61f9 KG	333	struct bfa_ioc_cbfn_s cbfn, struct bfa_timer_mod_s timer_mod);
a36c61f9 KG	334	void bfa_ioc_auto_recover(bfa_boolean_t auto_recover);
7725ccfd JH	335	void bfa_ioc_detach(struct bfa_ioc_s *ioc);
	336	void bfa_ioc_pci_init(struct bfa_ioc_s ioc, struct bfa_pcidev_s pcidev,
	337	enum bfi_mclass mc);
7725ccfd JH	338	void bfa_ioc_mem_claim(struct bfa_ioc_s ioc, u8 dm_kva, u64 dm_pa);
	339	void bfa_ioc_enable(struct bfa_ioc_s *ioc);
	340	void bfa_ioc_disable(struct bfa_ioc_s *ioc);
	341	bfa_boolean_t bfa_ioc_intx_claim(struct bfa_ioc_s *ioc);
	342
a36c61f9 KG	343	void bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type,
a36c61f9 KG	344	u32 boot_param);
7725ccfd JH	345	void bfa_ioc_isr(struct bfa_ioc_s ioc, struct bfi_mbmsg_s msg);
7725ccfd JH	346	void bfa_ioc_error_isr(struct bfa_ioc_s *ioc);
7725ccfd	347	bfa_boolean_t bfa_ioc_is_operational(struct bfa_ioc_s *ioc);
a36c61f9	348	bfa_boolean_t bfa_ioc_is_initialized(struct bfa_ioc_s *ioc);
7725ccfd JH	349	bfa_boolean_t bfa_ioc_is_disabled(struct bfa_ioc_s *ioc);
	350	bfa_boolean_t bfa_ioc_fw_mismatch(struct bfa_ioc_s *ioc);
	351	bfa_boolean_t bfa_ioc_adapter_is_disabled(struct bfa_ioc_s *ioc);
f1d584d7	352	void bfa_ioc_reset_fwstate(struct bfa_ioc_s *ioc);
0a4b1fc0 KG	353	enum bfa_ioc_type_e bfa_ioc_get_type(struct bfa_ioc_s *ioc);
	354	void bfa_ioc_get_adapter_serial_num(struct bfa_ioc_s ioc, char serial_num);
	355	void bfa_ioc_get_adapter_fw_ver(struct bfa_ioc_s ioc, char fw_ver);
	356	void bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc_s ioc, char optrom_ver);
	357	void bfa_ioc_get_adapter_model(struct bfa_ioc_s ioc, char model);
	358	void bfa_ioc_get_adapter_manufacturer(struct bfa_ioc_s *ioc,
a36c61f9	359	char *manufacturer);
0a4b1fc0 KG	360	void bfa_ioc_get_pci_chip_rev(struct bfa_ioc_s ioc, char chip_rev);
	361	enum bfa_ioc_state bfa_ioc_get_state(struct bfa_ioc_s *ioc);
	362
7725ccfd JH	363	void bfa_ioc_get_attr(struct bfa_ioc_s ioc, struct bfa_ioc_attr_s ioc_attr);
	364	void bfa_ioc_get_adapter_attr(struct bfa_ioc_s *ioc,
	365	struct bfa_adapter_attr_s *ad_attr);
7725ccfd JH	366	void bfa_ioc_debug_memclaim(struct bfa_ioc_s ioc, void dbg_fwsave);
	367	bfa_status_t bfa_ioc_debug_fwsave(struct bfa_ioc_s ioc, void trcdata,
	368	int *trclen);
	369	bfa_status_t bfa_ioc_debug_fwtrc(struct bfa_ioc_s ioc, void trcdata,
	370	int *trclen);
a36c61f9 KG	371	bfa_status_t bfa_ioc_debug_fwcore(struct bfa_ioc_s ioc, void buf,
a36c61f9 KG	372	u32 offset, int buflen);
7725ccfd JH	373	void bfa_ioc_set_fcmode(struct bfa_ioc_s *ioc);
7725ccfd JH	374	bfa_boolean_t bfa_ioc_get_fcmode(struct bfa_ioc_s *ioc);
53440260	375	bfa_boolean_t bfa_ioc_sem_get(void __iomem *sem_reg);
0a20de44 KG	376	void bfa_ioc_fwver_get(struct bfa_ioc_s *ioc,
	377	struct bfi_ioc_image_hdr_s *fwhdr);
	378	bfa_boolean_t bfa_ioc_fwver_cmp(struct bfa_ioc_s *ioc,
	379	struct bfi_ioc_image_hdr_s *fwhdr);
a36c61f9 KG	380	bfa_status_t bfa_ioc_fw_stats_get(struct bfa_ioc_s ioc, void stats);
a36c61f9 KG	381	bfa_status_t bfa_ioc_fw_stats_clear(struct bfa_ioc_s *ioc);
7725ccfd JH	382
	383	/*
	384	* bfa mfg wwn API functions
	385	*/
7725ccfd	386	mac_t bfa_ioc_get_mac(struct bfa_ioc_s *ioc);
15b64a83	387	mac_t bfa_ioc_get_mfg_mac(struct bfa_ioc_s *ioc);
7725ccfd	388
a36c61f9 KG	389	/*
	390	* F/W Image Size & Chunk
	391	*/
	392	extern u32 bfi_image_ct_fc_size;
	393	extern u32 bfi_image_ct_cna_size;
	394	extern u32 bfi_image_cb_fc_size;
	395	extern u32 *bfi_image_ct_fc;
	396	extern u32 *bfi_image_ct_cna;
	397	extern u32 *bfi_image_cb_fc;
	398
	399	static inline u32 *
	400	bfi_image_ct_fc_get_chunk(u32 off)
	401	{ return (u32 *)(bfi_image_ct_fc + off); }
	402
	403	static inline u32 *
	404	bfi_image_ct_cna_get_chunk(u32 off)
	405	{ return (u32 *)(bfi_image_ct_cna + off); }
7725ccfd	406
a36c61f9 KG	407	static inline u32 *
	408	bfi_image_cb_fc_get_chunk(u32 off)
	409	{ return (u32 *)(bfi_image_cb_fc + off); }
	410
	411	static inline u32*
	412	bfa_cb_image_get_chunk(int type, u32 off)
	413	{
	414	switch (type) {
	415	case BFI_IMAGE_CT_FC:
	416	return bfi_image_ct_fc_get_chunk(off); break;
	417	case BFI_IMAGE_CT_CNA:
	418	return bfi_image_ct_cna_get_chunk(off); break;
	419	case BFI_IMAGE_CB_FC:
	420	return bfi_image_cb_fc_get_chunk(off); break;
52f94b6f	421	default: return NULL;
a36c61f9 KG	422	}
	423	}
	424
	425	static inline u32
	426	bfa_cb_image_get_size(int type)
	427	{
	428	switch (type) {
	429	case BFI_IMAGE_CT_FC:
	430	return bfi_image_ct_fc_size; break;
	431	case BFI_IMAGE_CT_CNA:
	432	return bfi_image_ct_cna_size; break;
	433	case BFI_IMAGE_CB_FC:
	434	return bfi_image_cb_fc_size; break;
	435	default: return 0;
	436	}
	437	}
	438
acdc79a6	439	/*
a36c61f9 KG	440	* CNA TRCMOD declaration
	441	*/
	442	/*
	443	* !!! Only append to the enums defined here to avoid any versioning
	444	* !!! needed between trace utility and driver version
	445	*/
	446	enum {
	447	BFA_TRC_CNA_PORT = 1,
	448	BFA_TRC_CNA_IOC = 2,
	449	BFA_TRC_CNA_IOC_CB = 3,
	450	BFA_TRC_CNA_IOC_CT = 4,
	451	};
	452
	453	#endif /* __BFA_IOC_H__ */