[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / a2091.h

#ifndef A2091_H
#define A2091_H

/* $Id: a2091.h,v 1.4 1997/01/19 23:07:09 davem Exp $
 *
 * Header file for the Commodore A2091 Zorro II SCSI controller for Linux
 *
 * Written and (C) 1993, Hamish Macdonald, see a2091.c for more info
 *
 */

#include <linux/types.h>

#ifndef CMD_PER_LUN
#define CMD_PER_LUN		2
#endif

#ifndef CAN_QUEUE
#define CAN_QUEUE		16
#endif

/*
 * if the transfer address ANDed with this results in a non-zero
 * result, then we can't use DMA.
 */
#define A2091_XFER_MASK		(0xff000001)

struct a2091_scsiregs {
		 unsigned char	pad1[64];
	volatile unsigned short	ISTR;
	volatile unsigned short	CNTR;
		 unsigned char	pad2[60];
	volatile unsigned int	WTC;
	volatile unsigned long	ACR;
		 unsigned char	pad3[6];
	volatile unsigned short	DAWR;
		 unsigned char	pad4;
	volatile unsigned char	SASR;
		 unsigned char	pad5;
	volatile unsigned char	SCMD;
		 unsigned char	pad6[76];
	volatile unsigned short	ST_DMA;
	volatile unsigned short	SP_DMA;
	volatile unsigned short	CINT;
		 unsigned char	pad7[2];
	volatile unsigned short	FLUSH;
};

#define DAWR_A2091		(3)

/* CNTR bits. */
#define CNTR_TCEN		(1<<7)
#define CNTR_PREST		(1<<6)
#define CNTR_PDMD		(1<<5)
#define CNTR_INTEN		(1<<4)
#define CNTR_DDIR		(1<<3)

/* ISTR bits. */
#define ISTR_INTX		(1<<8)
#define ISTR_INT_F		(1<<7)
#define ISTR_INTS		(1<<6)
#define ISTR_E_INT		(1<<5)
#define ISTR_INT_P		(1<<4)
#define ISTR_UE_INT		(1<<3)
#define ISTR_OE_INT		(1<<2)
#define ISTR_FF_FLG		(1<<1)
#define ISTR_FE_FLG		(1<<0)

#endif /* A2091_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef A2091_H
	2	#define A2091_H
	3
	4	/* $Id: a2091.h,v 1.4 1997/01/19 23:07:09 davem Exp $
	5	*
	6	* Header file for the Commodore A2091 Zorro II SCSI controller for Linux
	7	*
	8	* Written and (C) 1993, Hamish Macdonald, see a2091.c for more info
	9	*
	10	*/
	11
	12	#include <linux/types.h>
	13
1da177e4	14	#ifndef CMD_PER_LUN
09bc85b0	15	#define CMD_PER_LUN 2
1da177e4 LT	16	#endif
	17
	18	#ifndef CAN_QUEUE
09bc85b0	19	#define CAN_QUEUE 16
1da177e4 LT	20	#endif
	21
	22	/*
	23	* if the transfer address ANDed with this results in a non-zero
	24	* result, then we can't use DMA.
	25	*/
09bc85b0	26	#define A2091_XFER_MASK (0xff000001)
1da177e4	27
56522e39	28	struct a2091_scsiregs {
09bc85b0 GU	29	unsigned char pad1[64];
	30	volatile unsigned short ISTR;
	31	volatile unsigned short CNTR;
	32	unsigned char pad2[60];
	33	volatile unsigned int WTC;
	34	volatile unsigned long ACR;
	35	unsigned char pad3[6];
	36	volatile unsigned short DAWR;
	37	unsigned char pad4;
	38	volatile unsigned char SASR;
	39	unsigned char pad5;
	40	volatile unsigned char SCMD;
	41	unsigned char pad6[76];
	42	volatile unsigned short ST_DMA;
	43	volatile unsigned short SP_DMA;
	44	volatile unsigned short CINT;
	45	unsigned char pad7[2];
	46	volatile unsigned short FLUSH;
56522e39	47	};
1da177e4 LT	48
	49	#define DAWR_A2091 (3)
	50
	51	/* CNTR bits. */
	52	#define CNTR_TCEN (1<<7)
	53	#define CNTR_PREST (1<<6)
	54	#define CNTR_PDMD (1<<5)
	55	#define CNTR_INTEN (1<<4)
	56	#define CNTR_DDIR (1<<3)
	57
	58	/* ISTR bits. */
	59	#define ISTR_INTX (1<<8)
	60	#define ISTR_INT_F (1<<7)
	61	#define ISTR_INTS (1<<6)
	62	#define ISTR_E_INT (1<<5)
	63	#define ISTR_INT_P (1<<4)
	64	#define ISTR_UE_INT (1<<3)
	65	#define ISTR_OE_INT (1<<2)
	66	#define ISTR_FF_FLG (1<<1)
	67	#define ISTR_FE_FLG (1<<0)
	68
	69	#endif /* A2091_H */