[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / rtc / rtc-sa1100.c

/*
 * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
 *
 * Copyright (c) 2000 Nils Faerber
 *
 * Based on rtc.c by Paul Gortmaker
 *
 * Original Driver by Nils Faerber <nils@kernelconcepts.de>
 *
 * Modifications from:
 *   CIH <cih@coventive.com>
 *   Nicolas Pitre <nico@cam.org>
 *   Andrew Christian <andrew.christian@hp.com>
 *
 * Converted to the RTC subsystem and Driver Model
 *   by Richard Purdie <rpurdie@rpsys.net>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/string.h>
#include <linux/pm.h>
#include <linux/bitops.h>

#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/rtc.h>

#ifdef CONFIG_ARCH_PXA
#include <asm/arch/pxa-regs.h>
#endif

#define TIMER_FREQ		CLOCK_TICK_RATE
#define RTC_DEF_DIVIDER		32768 - 1
#define RTC_DEF_TRIM		0

static unsigned long rtc_freq = 1024;
static struct rtc_time rtc_alarm;
static DEFINE_SPINLOCK(sa1100_rtc_lock);

static int rtc_update_alarm(struct rtc_time *alrm)
{
	struct rtc_time alarm_tm, now_tm;
	unsigned long now, time;
	int ret;

	do {
		now = RCNR;
		rtc_time_to_tm(now, &now_tm);
		rtc_next_alarm_time(&alarm_tm, &now_tm, alrm);
		ret = rtc_tm_to_time(&alarm_tm, &time);
		if (ret != 0)
			break;

		RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL);
		RTAR = time;
	} while (now != RCNR);

	return ret;
}

static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = to_platform_device(dev_id);
	struct rtc_device *rtc = platform_get_drvdata(pdev);
	unsigned int rtsr;
	unsigned long events = 0;

	spin_lock(&sa1100_rtc_lock);

	rtsr = RTSR;
	/* clear interrupt sources */
	RTSR = 0;
	RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2);

	/* clear alarm interrupt if it has occurred */
	if (rtsr & RTSR_AL)
		rtsr &= ~RTSR_ALE;
	RTSR = rtsr & (RTSR_ALE | RTSR_HZE);

	/* update irq data & counter */
	if (rtsr & RTSR_AL)
		events |= RTC_AF | RTC_IRQF;
	if (rtsr & RTSR_HZ)
		events |= RTC_UF | RTC_IRQF;

	rtc_update_irq(rtc, 1, events);

	if (rtsr & RTSR_AL && rtc_periodic_alarm(&rtc_alarm))
		rtc_update_alarm(&rtc_alarm);

	spin_unlock(&sa1100_rtc_lock);

	return IRQ_HANDLED;
}

static int rtc_timer1_count;

static irqreturn_t timer1_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = to_platform_device(dev_id);
	struct rtc_device *rtc = platform_get_drvdata(pdev);

	/*
	 * If we match for the first time, rtc_timer1_count will be 1.
	 * Otherwise, we wrapped around (very unlikely but
	 * still possible) so compute the amount of missed periods.
	 * The match reg is updated only when the data is actually retrieved
	 * to avoid unnecessary interrupts.
	 */
	OSSR = OSSR_M1;	/* clear match on timer1 */

	rtc_update_irq(rtc, rtc_timer1_count, RTC_PF | RTC_IRQF);

	if (rtc_timer1_count == 1)
		rtc_timer1_count = (rtc_freq * ((1<<30)/(TIMER_FREQ>>2)));

	return IRQ_HANDLED;
}

static int sa1100_rtc_read_callback(struct device *dev, int data)
{
	if (data & RTC_PF) {
		/* interpolate missed periods and set match for the next */
		unsigned long period = TIMER_FREQ/rtc_freq;
		unsigned long oscr = OSCR;
		unsigned long osmr1 = OSMR1;
		unsigned long missed = (oscr - osmr1)/period;
		data += missed << 8;
		OSSR = OSSR_M1;	/* clear match on timer 1 */
		OSMR1 = osmr1 + (missed + 1)*period;
		/* Ensure we didn't miss another match in the mean time.
		 * Here we compare (match - OSCR) 8 instead of 0 --
		 * see comment in pxa_timer_interrupt() for explanation.
		 */
		while( (signed long)((osmr1 = OSMR1) - OSCR) <= 8 ) {
			data += 0x100;
			OSSR = OSSR_M1;	/* clear match on timer 1 */
			OSMR1 = osmr1 + period;
		}
	}
	return data;
}

static int sa1100_rtc_open(struct device *dev)
{
	int ret;

	ret = request_irq(IRQ_RTC1Hz, sa1100_rtc_interrupt, IRQF_DISABLED,
				"rtc 1Hz", dev);
	if (ret) {
		dev_err(dev, "IRQ %d already in use.\n", IRQ_RTC1Hz);
		goto fail_ui;
	}
	ret = request_irq(IRQ_RTCAlrm, sa1100_rtc_interrupt, IRQF_DISABLED,
				"rtc Alrm", dev);
	if (ret) {
		dev_err(dev, "IRQ %d already in use.\n", IRQ_RTCAlrm);
		goto fail_ai;
	}
	ret = request_irq(IRQ_OST1, timer1_interrupt, IRQF_DISABLED,
				"rtc timer", dev);
	if (ret) {
		dev_err(dev, "IRQ %d already in use.\n", IRQ_OST1);
		goto fail_pi;
	}
	return 0;

 fail_pi:
	free_irq(IRQ_RTCAlrm, dev);
 fail_ai:
	free_irq(IRQ_RTC1Hz, dev);
 fail_ui:
	return ret;
}

static void sa1100_rtc_release(struct device *dev)
{
	spin_lock_irq(&sa1100_rtc_lock);
	RTSR = 0;
	OIER &= ~OIER_E1;
	OSSR = OSSR_M1;
	spin_unlock_irq(&sa1100_rtc_lock);

	free_irq(IRQ_OST1, dev);
	free_irq(IRQ_RTCAlrm, dev);
	free_irq(IRQ_RTC1Hz, dev);
}


static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd,
		unsigned long arg)
{
	switch(cmd) {
	case RTC_AIE_OFF:
		spin_lock_irq(&sa1100_rtc_lock);
		RTSR &= ~RTSR_ALE;
		spin_unlock_irq(&sa1100_rtc_lock);
		return 0;
	case RTC_AIE_ON:
		spin_lock_irq(&sa1100_rtc_lock);
		RTSR |= RTSR_ALE;
		spin_unlock_irq(&sa1100_rtc_lock);
		return 0;
	case RTC_UIE_OFF:
		spin_lock_irq(&sa1100_rtc_lock);
		RTSR &= ~RTSR_HZE;
		spin_unlock_irq(&sa1100_rtc_lock);
		return 0;
	case RTC_UIE_ON:
		spin_lock_irq(&sa1100_rtc_lock);
		RTSR |= RTSR_HZE;
		spin_unlock_irq(&sa1100_rtc_lock);
		return 0;
	case RTC_PIE_OFF:
		spin_lock_irq(&sa1100_rtc_lock);
		OIER &= ~OIER_E1;
		spin_unlock_irq(&sa1100_rtc_lock);
		return 0;
	case RTC_PIE_ON:
		spin_lock_irq(&sa1100_rtc_lock);
		OSMR1 = TIMER_FREQ/rtc_freq + OSCR;
		OIER |= OIER_E1;
		rtc_timer1_count = 1;
		spin_unlock_irq(&sa1100_rtc_lock);
		return 0;
	case RTC_IRQP_READ:
		return put_user(rtc_freq, (unsigned long *)arg);
	case RTC_IRQP_SET:
		if (arg < 1 || arg > TIMER_FREQ)
			return -EINVAL;
		rtc_freq = arg;
		return 0;
	}
	return -ENOIOCTLCMD;
}

static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	rtc_time_to_tm(RCNR, tm);
	return 0;
}

static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	unsigned long time;
	int ret;

	ret = rtc_tm_to_time(tm, &time);
	if (ret == 0)
		RCNR = time;
	return ret;
}

static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	u32	rtsr;

	memcpy(&alrm->time, &rtc_alarm, sizeof(struct rtc_time));
	rtsr = RTSR;
	alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
	alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
	return 0;
}

static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	int ret;

	spin_lock_irq(&sa1100_rtc_lock);
	ret = rtc_update_alarm(&alrm->time);
	if (ret == 0) {
		if (alrm->enabled)
			RTSR |= RTSR_ALE;
		else
			RTSR &= ~RTSR_ALE;
	}
	spin_unlock_irq(&sa1100_rtc_lock);

	return ret;
}

static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
{
	seq_printf(seq, "trim/divider\t: 0x%08x\n", (u32) RTTR);
	seq_printf(seq, "update_IRQ\t: %s\n",
			(RTSR & RTSR_HZE) ? "yes" : "no");
	seq_printf(seq, "periodic_IRQ\t: %s\n",
			(OIER & OIER_E1) ? "yes" : "no");
	seq_printf(seq, "periodic_freq\t: %ld\n", rtc_freq);

	return 0;
}

static const struct rtc_class_ops sa1100_rtc_ops = {
	.open = sa1100_rtc_open,
	.read_callback = sa1100_rtc_read_callback,
	.release = sa1100_rtc_release,
	.ioctl = sa1100_rtc_ioctl,
	.read_time = sa1100_rtc_read_time,
	.set_time = sa1100_rtc_set_time,
	.read_alarm = sa1100_rtc_read_alarm,
	.set_alarm = sa1100_rtc_set_alarm,
	.proc = sa1100_rtc_proc,
};

static int sa1100_rtc_probe(struct platform_device *pdev)
{
	struct rtc_device *rtc;

	/*
	 * According to the manual we should be able to let RTTR be zero
	 * and then a default diviser for a 32.768KHz clock is used.
	 * Apparently this doesn't work, at least for my SA1110 rev 5.
	 * If the clock divider is uninitialized then reset it to the
	 * default value to get the 1Hz clock.
	 */
	if (RTTR == 0) {
		RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
		dev_warn(&pdev->dev, "warning: initializing default clock divider/trim value\n");
		/* The current RTC value probably doesn't make sense either */
		RCNR = 0;
	}

	rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops,
				THIS_MODULE);

	if (IS_ERR(rtc))
		return PTR_ERR(rtc);

	platform_set_drvdata(pdev, rtc);

	return 0;
}

static int sa1100_rtc_remove(struct platform_device *pdev)
{
	struct rtc_device *rtc = platform_get_drvdata(pdev);

 	if (rtc)
		rtc_device_unregister(rtc);

	return 0;
}

static struct platform_driver sa1100_rtc_driver = {
	.probe		= sa1100_rtc_probe,
	.remove		= sa1100_rtc_remove,
	.driver		= {
		.name		= "sa1100-rtc",
	},
};

static int __init sa1100_rtc_init(void)
{
	return platform_driver_register(&sa1100_rtc_driver);
}

static void __exit sa1100_rtc_exit(void)
{
	platform_driver_unregister(&sa1100_rtc_driver);
}

module_init(sa1100_rtc_init);
module_exit(sa1100_rtc_exit);

MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL");
Commit	Line	Data
e842f1c8 RP	1	/*
	2	* Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
	3	*
	4	* Copyright (c) 2000 Nils Faerber
	5	*
	6	* Based on rtc.c by Paul Gortmaker
	7	*
	8	* Original Driver by Nils Faerber <nils@kernelconcepts.de>
	9	*
	10	* Modifications from:
	11	* CIH <cih@coventive.com>
	12	* Nicolas Pitre <nico@cam.org>
	13	* Andrew Christian <andrew.christian@hp.com>
	14	*
	15	* Converted to the RTC subsystem and Driver Model
	16	* by Richard Purdie <rpurdie@rpsys.net>
	17	*
	18	* This program is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License
	20	* as published by the Free Software Foundation; either version
	21	* 2 of the License, or (at your option) any later version.
	22	*/
	23
	24	#include <linux/platform_device.h>
	25	#include <linux/module.h>
	26	#include <linux/rtc.h>
	27	#include <linux/init.h>
	28	#include <linux/fs.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/string.h>
	31	#include <linux/pm.h>
1977f032	32	#include <linux/bitops.h>
e842f1c8	33
e842f1c8 RP	34	#include <asm/hardware.h>
	35	#include <asm/irq.h>
	36	#include <asm/rtc.h>
	37
	38	#ifdef CONFIG_ARCH_PXA
	39	#include <asm/arch/pxa-regs.h>
	40	#endif
	41
	42	#define TIMER_FREQ CLOCK_TICK_RATE
	43	#define RTC_DEF_DIVIDER 32768 - 1
	44	#define RTC_DEF_TRIM 0
	45
	46	static unsigned long rtc_freq = 1024;
	47	static struct rtc_time rtc_alarm;
34af946a	48	static DEFINE_SPINLOCK(sa1100_rtc_lock);
e842f1c8 RP	49
	50	static int rtc_update_alarm(struct rtc_time *alrm)
	51	{
	52	struct rtc_time alarm_tm, now_tm;
	53	unsigned long now, time;
	54	int ret;
	55
	56	do {
	57	now = RCNR;
	58	rtc_time_to_tm(now, &now_tm);
	59	rtc_next_alarm_time(&alarm_tm, &now_tm, alrm);
	60	ret = rtc_tm_to_time(&alarm_tm, &time);
	61	if (ret != 0)
	62	break;
	63
	64	RTSR = RTSR & (RTSR_HZE\|RTSR_ALE\|RTSR_AL);
	65	RTAR = time;
	66	} while (now != RCNR);
	67
	68	return ret;
	69	}
	70
7d12e780	71	static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
e842f1c8 RP	72	{
	73	struct platform_device *pdev = to_platform_device(dev_id);
	74	struct rtc_device *rtc = platform_get_drvdata(pdev);
	75	unsigned int rtsr;
	76	unsigned long events = 0;
	77
	78	spin_lock(&sa1100_rtc_lock);
	79
	80	rtsr = RTSR;
	81	/* clear interrupt sources */
	82	RTSR = 0;
	83	RTSR = (RTSR_AL \| RTSR_HZ) & (rtsr >> 2);
	84
	85	/* clear alarm interrupt if it has occurred */
	86	if (rtsr & RTSR_AL)
	87	rtsr &= ~RTSR_ALE;
	88	RTSR = rtsr & (RTSR_ALE \| RTSR_HZE);
	89
	90	/* update irq data & counter */
	91	if (rtsr & RTSR_AL)
	92	events \|= RTC_AF \| RTC_IRQF;
	93	if (rtsr & RTSR_HZ)
	94	events \|= RTC_UF \| RTC_IRQF;
	95
ab6a2d70	96	rtc_update_irq(rtc, 1, events);
e842f1c8 RP	97
	98	if (rtsr & RTSR_AL && rtc_periodic_alarm(&rtc_alarm))
	99	rtc_update_alarm(&rtc_alarm);
	100
	101	spin_unlock(&sa1100_rtc_lock);
	102
	103	return IRQ_HANDLED;
	104	}
	105
	106	static int rtc_timer1_count;
	107
7d12e780	108	static irqreturn_t timer1_interrupt(int irq, void *dev_id)
e842f1c8 RP	109	{
	110	struct platform_device *pdev = to_platform_device(dev_id);
	111	struct rtc_device *rtc = platform_get_drvdata(pdev);
	112
	113	/*
	114	* If we match for the first time, rtc_timer1_count will be 1.
	115	* Otherwise, we wrapped around (very unlikely but
	116	* still possible) so compute the amount of missed periods.
	117	* The match reg is updated only when the data is actually retrieved
	118	* to avoid unnecessary interrupts.
	119	*/
	120	OSSR = OSSR_M1; /* clear match on timer1 */
	121
ab6a2d70	122	rtc_update_irq(rtc, rtc_timer1_count, RTC_PF \| RTC_IRQF);
e842f1c8 RP	123
	124	if (rtc_timer1_count == 1)
	125	rtc_timer1_count = (rtc_freq * ((1<<30)/(TIMER_FREQ>>2)));
	126
	127	return IRQ_HANDLED;
	128	}
	129
	130	static int sa1100_rtc_read_callback(struct device *dev, int data)
	131	{
	132	if (data & RTC_PF) {
	133	/* interpolate missed periods and set match for the next */
	134	unsigned long period = TIMER_FREQ/rtc_freq;
	135	unsigned long oscr = OSCR;
	136	unsigned long osmr1 = OSMR1;
	137	unsigned long missed = (oscr - osmr1)/period;
	138	data += missed << 8;
	139	OSSR = OSSR_M1; /* clear match on timer 1 */
	140	OSMR1 = osmr1 + (missed + 1)*period;
	141	/* Ensure we didn't miss another match in the mean time.
	142	* Here we compare (match - OSCR) 8 instead of 0 --
	143	* see comment in pxa_timer_interrupt() for explanation.
	144	*/
	145	while( (signed long)((osmr1 = OSMR1) - OSCR) <= 8 ) {
	146	data += 0x100;
	147	OSSR = OSSR_M1; /* clear match on timer 1 */
	148	OSMR1 = osmr1 + period;
	149	}
	150	}
	151	return data;
	152	}
	153
	154	static int sa1100_rtc_open(struct device *dev)
	155	{
	156	int ret;
	157
dace1453	158	ret = request_irq(IRQ_RTC1Hz, sa1100_rtc_interrupt, IRQF_DISABLED,
e842f1c8 RP	159	"rtc 1Hz", dev);
e842f1c8 RP	160	if (ret) {
2260a25c	161	dev_err(dev, "IRQ %d already in use.\n", IRQ_RTC1Hz);
e842f1c8 RP	162	goto fail_ui;
e842f1c8 RP	163	}
dace1453	164	ret = request_irq(IRQ_RTCAlrm, sa1100_rtc_interrupt, IRQF_DISABLED,
e842f1c8 RP	165	"rtc Alrm", dev);
e842f1c8 RP	166	if (ret) {
2260a25c	167	dev_err(dev, "IRQ %d already in use.\n", IRQ_RTCAlrm);
e842f1c8 RP	168	goto fail_ai;
e842f1c8 RP	169	}
dace1453	170	ret = request_irq(IRQ_OST1, timer1_interrupt, IRQF_DISABLED,
e842f1c8 RP	171	"rtc timer", dev);
e842f1c8 RP	172	if (ret) {
2260a25c	173	dev_err(dev, "IRQ %d already in use.\n", IRQ_OST1);
e842f1c8 RP	174	goto fail_pi;
	175	}
	176	return 0;
	177
	178	fail_pi:
f1226701	179	free_irq(IRQ_RTCAlrm, dev);
e842f1c8	180	fail_ai:
f1226701	181	free_irq(IRQ_RTC1Hz, dev);
e842f1c8 RP	182	fail_ui:
	183	return ret;
	184	}
	185
	186	static void sa1100_rtc_release(struct device *dev)
	187	{
	188	spin_lock_irq(&sa1100_rtc_lock);
	189	RTSR = 0;
	190	OIER &= ~OIER_E1;
	191	OSSR = OSSR_M1;
	192	spin_unlock_irq(&sa1100_rtc_lock);
	193
	194	free_irq(IRQ_OST1, dev);
	195	free_irq(IRQ_RTCAlrm, dev);
	196	free_irq(IRQ_RTC1Hz, dev);
	197	}
	198
	199
	200	static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd,
	201	unsigned long arg)
	202	{
	203	switch(cmd) {
	204	case RTC_AIE_OFF:
	205	spin_lock_irq(&sa1100_rtc_lock);
	206	RTSR &= ~RTSR_ALE;
	207	spin_unlock_irq(&sa1100_rtc_lock);
	208	return 0;
	209	case RTC_AIE_ON:
	210	spin_lock_irq(&sa1100_rtc_lock);
	211	RTSR \|= RTSR_ALE;
	212	spin_unlock_irq(&sa1100_rtc_lock);
	213	return 0;
	214	case RTC_UIE_OFF:
	215	spin_lock_irq(&sa1100_rtc_lock);
	216	RTSR &= ~RTSR_HZE;
	217	spin_unlock_irq(&sa1100_rtc_lock);
	218	return 0;
	219	case RTC_UIE_ON:
	220	spin_lock_irq(&sa1100_rtc_lock);
	221	RTSR \|= RTSR_HZE;
	222	spin_unlock_irq(&sa1100_rtc_lock);
	223	return 0;
	224	case RTC_PIE_OFF:
	225	spin_lock_irq(&sa1100_rtc_lock);
	226	OIER &= ~OIER_E1;
	227	spin_unlock_irq(&sa1100_rtc_lock);
	228	return 0;
	229	case RTC_PIE_ON:
e842f1c8 RP	230	spin_lock_irq(&sa1100_rtc_lock);
	231	OSMR1 = TIMER_FREQ/rtc_freq + OSCR;
	232	OIER \|= OIER_E1;
	233	rtc_timer1_count = 1;
	234	spin_unlock_irq(&sa1100_rtc_lock);
	235	return 0;
	236	case RTC_IRQP_READ:
	237	return put_user(rtc_freq, (unsigned long *)arg);
	238	case RTC_IRQP_SET:
	239	if (arg < 1 \|\| arg > TIMER_FREQ)
	240	return -EINVAL;
e842f1c8 RP	241	rtc_freq = arg;
	242	return 0;
	243	}
b3969e58	244	return -ENOIOCTLCMD;
e842f1c8 RP	245	}
	246
	247	static int sa1100_rtc_read_time(struct device dev, struct rtc_time tm)
	248	{
	249	rtc_time_to_tm(RCNR, tm);
	250	return 0;
	251	}
	252
	253	static int sa1100_rtc_set_time(struct device dev, struct rtc_time tm)
	254	{
	255	unsigned long time;
	256	int ret;
	257
	258	ret = rtc_tm_to_time(tm, &time);
	259	if (ret == 0)
	260	RCNR = time;
	261	return ret;
	262	}
	263
	264	static int sa1100_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	265	{
32b49da4 DB	266	u32 rtsr;
32b49da4 DB	267
e842f1c8	268	memcpy(&alrm->time, &rtc_alarm, sizeof(struct rtc_time));
32b49da4 DB	269	rtsr = RTSR;
	270	alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
	271	alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
e842f1c8 RP	272	return 0;
	273	}
	274
	275	static int sa1100_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	276	{
	277	int ret;
	278
	279	spin_lock_irq(&sa1100_rtc_lock);
	280	ret = rtc_update_alarm(&alrm->time);
	281	if (ret == 0) {
e842f1c8	282	if (alrm->enabled)
32b49da4	283	RTSR \|= RTSR_ALE;
e842f1c8	284	else
32b49da4	285	RTSR &= ~RTSR_ALE;
e842f1c8 RP	286	}
	287	spin_unlock_irq(&sa1100_rtc_lock);
	288
	289	return ret;
	290	}
	291
	292	static int sa1100_rtc_proc(struct device dev, struct seq_file seq)
	293	{
a2db8dfc	294	seq_printf(seq, "trim/divider\t: 0x%08x\n", (u32) RTTR);
e842f1c8 RP	295	seq_printf(seq, "update_IRQ\t: %s\n",
	296	(RTSR & RTSR_HZE) ? "yes" : "no");
	297	seq_printf(seq, "periodic_IRQ\t: %s\n",
	298	(OIER & OIER_E1) ? "yes" : "no");
	299	seq_printf(seq, "periodic_freq\t: %ld\n", rtc_freq);
	300
	301	return 0;
	302	}
	303
ff8371ac	304	static const struct rtc_class_ops sa1100_rtc_ops = {
e842f1c8 RP	305	.open = sa1100_rtc_open,
	306	.read_callback = sa1100_rtc_read_callback,
	307	.release = sa1100_rtc_release,
	308	.ioctl = sa1100_rtc_ioctl,
	309	.read_time = sa1100_rtc_read_time,
	310	.set_time = sa1100_rtc_set_time,
	311	.read_alarm = sa1100_rtc_read_alarm,
	312	.set_alarm = sa1100_rtc_set_alarm,
	313	.proc = sa1100_rtc_proc,
	314	};
	315
	316	static int sa1100_rtc_probe(struct platform_device *pdev)
	317	{
	318	struct rtc_device *rtc;
	319
	320	/*
	321	* According to the manual we should be able to let RTTR be zero
	322	* and then a default diviser for a 32.768KHz clock is used.
	323	* Apparently this doesn't work, at least for my SA1110 rev 5.
	324	* If the clock divider is uninitialized then reset it to the
	325	* default value to get the 1Hz clock.
	326	*/
	327	if (RTTR == 0) {
	328	RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
2260a25c	329	dev_warn(&pdev->dev, "warning: initializing default clock divider/trim value\n");
e842f1c8 RP	330	/* The current RTC value probably doesn't make sense either */
	331	RCNR = 0;
	332	}
	333
	334	rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops,
	335	THIS_MODULE);
	336
2260a25c	337	if (IS_ERR(rtc))
e842f1c8	338	return PTR_ERR(rtc);
e842f1c8 RP	339
	340	platform_set_drvdata(pdev, rtc);
	341
e842f1c8 RP	342	return 0;
	343	}
	344
	345	static int sa1100_rtc_remove(struct platform_device *pdev)
	346	{
	347	struct rtc_device *rtc = platform_get_drvdata(pdev);
	348
	349	if (rtc)
	350	rtc_device_unregister(rtc);
	351
	352	return 0;
	353	}
	354
	355	static struct platform_driver sa1100_rtc_driver = {
	356	.probe = sa1100_rtc_probe,
	357	.remove = sa1100_rtc_remove,
	358	.driver = {
	359	.name = "sa1100-rtc",
	360	},
	361	};
	362
	363	static int __init sa1100_rtc_init(void)
	364	{
	365	return platform_driver_register(&sa1100_rtc_driver);
	366	}
	367
	368	static void __exit sa1100_rtc_exit(void)
	369	{
	370	platform_driver_unregister(&sa1100_rtc_driver);
	371	}
	372
	373	module_init(sa1100_rtc_init);
	374	module_exit(sa1100_rtc_exit);
	375
	376	MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
	377	MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
	378	MODULE_LICENSE("GPL");