fix mali API_VERSION grep
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / rtc / rtc-s3c.c
CommitLineData
1add6781 1/* drivers/rtc/rtc-s3c.c
e48add8c
AD
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
1add6781
BD
5 *
6 * Copyright (c) 2004,2006 Simtec Electronics
7 * Ben Dooks, <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * S3C2410/S3C2440/S3C24XX Internal RTC Driver
15*/
16
17#include <linux/module.h>
18#include <linux/fs.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/interrupt.h>
23#include <linux/rtc.h>
24#include <linux/bcd.h>
25#include <linux/clk.h>
9974b6ea 26#include <linux/log2.h>
5a0e3ad6 27#include <linux/slab.h>
39ce4084 28#include <linux/of.h>
dbd9acbe
SK
29#include <linux/uaccess.h>
30#include <linux/io.h>
1add6781 31
1add6781 32#include <asm/irq.h>
b9d7c5d3 33#include "rtc-s3c.h"
1add6781 34
9f4123b7
MC
35enum s3c_cpu_type {
36 TYPE_S3C2410,
25c1a246
HS
37 TYPE_S3C2416,
38 TYPE_S3C2443,
9f4123b7
MC
39 TYPE_S3C64XX,
40};
41
c3cba928
TB
42struct s3c_rtc_drv_data {
43 int cpu_type;
44};
45
1add6781
BD
46/* I have yet to find an S3C implementation with more than one
47 * of these rtc blocks in */
48
e48add8c 49static struct clk *rtc_clk;
1add6781
BD
50static void __iomem *s3c_rtc_base;
51static int s3c_rtc_alarmno = NO_IRQ;
52static int s3c_rtc_tickno = NO_IRQ;
9f4123b7 53static enum s3c_cpu_type s3c_rtc_cpu_type;
1add6781
BD
54
55static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
1add6781 56
88cee8fd
DK
57static void s3c_rtc_alarm_clk_enable(bool enable)
58{
59 static DEFINE_SPINLOCK(s3c_rtc_alarm_clk_lock);
60 static bool alarm_clk_enabled;
61 unsigned long irq_flags;
62
63 spin_lock_irqsave(&s3c_rtc_alarm_clk_lock, irq_flags);
64 if (enable) {
65 if (!alarm_clk_enabled) {
66 clk_enable(rtc_clk);
67 alarm_clk_enabled = true;
68 }
69 } else {
70 if (alarm_clk_enabled) {
71 clk_disable(rtc_clk);
72 alarm_clk_enabled = false;
73 }
74 }
75 spin_unlock_irqrestore(&s3c_rtc_alarm_clk_lock, irq_flags);
76}
77
1add6781
BD
78/* IRQ Handlers */
79
7d12e780 80static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
1add6781
BD
81{
82 struct rtc_device *rdev = id;
83
cefe4fbb 84 clk_enable(rtc_clk);
ab6a2d70 85 rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
2f3478f6
AD
86
87 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
88 writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP);
89
cefe4fbb 90 clk_disable(rtc_clk);
88cee8fd
DK
91
92 s3c_rtc_alarm_clk_enable(false);
93
1add6781
BD
94 return IRQ_HANDLED;
95}
96
7d12e780 97static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
1add6781
BD
98{
99 struct rtc_device *rdev = id;
100
cefe4fbb 101 clk_enable(rtc_clk);
773be7ee 102 rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
2f3478f6
AD
103
104 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
105 writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP);
106
cefe4fbb 107 clk_disable(rtc_clk);
1add6781
BD
108 return IRQ_HANDLED;
109}
110
111/* Update control registers */
2ec38a03 112static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
1add6781
BD
113{
114 unsigned int tmp;
115
d4a48c2a 116 dev_dbg(dev, "%s: aie=%d\n", __func__, enabled);
1add6781 117
cefe4fbb 118 clk_enable(rtc_clk);
9a654518 119 tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
1add6781 120
2ec38a03 121 if (enabled)
1add6781
BD
122 tmp |= S3C2410_RTCALM_ALMEN;
123
9a654518 124 writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
cefe4fbb 125 clk_disable(rtc_clk);
2ec38a03 126
88cee8fd
DK
127 s3c_rtc_alarm_clk_enable(enabled);
128
2ec38a03 129 return 0;
1add6781
BD
130}
131
773be7ee 132static int s3c_rtc_setfreq(struct device *dev, int freq)
1add6781 133{
9f4123b7
MC
134 struct platform_device *pdev = to_platform_device(dev);
135 struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
136 unsigned int tmp = 0;
25c1a246 137 int val;
1add6781 138
5d2a5037
JC
139 if (!is_power_of_2(freq))
140 return -EINVAL;
141
cefe4fbb 142 clk_enable(rtc_clk);
1add6781 143 spin_lock_irq(&s3c_rtc_pie_lock);
1add6781 144
25c1a246 145 if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
9f4123b7
MC
146 tmp = readb(s3c_rtc_base + S3C2410_TICNT);
147 tmp &= S3C2410_TICNT_ENABLE;
148 }
149
25c1a246
HS
150 val = (rtc_dev->max_user_freq / freq) - 1;
151
152 if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
153 tmp |= S3C2443_TICNT_PART(val);
154 writel(S3C2443_TICNT1_PART(val), s3c_rtc_base + S3C2443_TICNT1);
155
156 if (s3c_rtc_cpu_type == TYPE_S3C2416)
157 writel(S3C2416_TICNT2_PART(val), s3c_rtc_base + S3C2416_TICNT2);
158 } else {
159 tmp |= val;
160 }
1add6781 161
2f3478f6 162 writel(tmp, s3c_rtc_base + S3C2410_TICNT);
1add6781 163 spin_unlock_irq(&s3c_rtc_pie_lock);
cefe4fbb 164 clk_disable(rtc_clk);
773be7ee
BD
165
166 return 0;
1add6781
BD
167}
168
169/* Time read/write */
170
171static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
172{
173 unsigned int have_retried = 0;
9a654518 174 void __iomem *base = s3c_rtc_base;
1add6781 175
cefe4fbb 176 clk_enable(rtc_clk);
1add6781 177 retry_get_time:
9a654518
BD
178 rtc_tm->tm_min = readb(base + S3C2410_RTCMIN);
179 rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR);
180 rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE);
181 rtc_tm->tm_mon = readb(base + S3C2410_RTCMON);
182 rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR);
183 rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC);
1add6781 184
48fc7f7e 185 /* the only way to work out whether the system was mid-update
1add6781
BD
186 * when we read it is to check the second counter, and if it
187 * is zero, then we re-try the entire read
188 */
189
190 if (rtc_tm->tm_sec == 0 && !have_retried) {
191 have_retried = 1;
192 goto retry_get_time;
193 }
194
fe20ba70
AB
195 rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
196 rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
197 rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
198 rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
199 rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
200 rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
1add6781
BD
201
202 rtc_tm->tm_year += 100;
4e8896cd 203
d4a48c2a 204 dev_dbg(dev, "read time %04d.%02d.%02d %02d:%02d:%02d\n",
4e8896cd
MH
205 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
206 rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
207
1add6781
BD
208 rtc_tm->tm_mon -= 1;
209
cefe4fbb 210 clk_disable(rtc_clk);
5b3ffddd 211 return rtc_valid_tm(rtc_tm);
1add6781
BD
212}
213
214static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
215{
9a654518 216 void __iomem *base = s3c_rtc_base;
641741e0 217 int year = tm->tm_year - 100;
9a654518 218
d4a48c2a 219 dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n",
30ffc40c 220 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
641741e0
BD
221 tm->tm_hour, tm->tm_min, tm->tm_sec);
222
223 /* we get around y2k by simply not supporting it */
1add6781 224
641741e0 225 if (year < 0 || year >= 100) {
9a654518 226 dev_err(dev, "rtc only supports 100 years\n");
1add6781 227 return -EINVAL;
9a654518
BD
228 }
229
2dbcd05f 230 clk_enable(rtc_clk);
fe20ba70
AB
231 writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC);
232 writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN);
233 writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR);
234 writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE);
235 writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON);
236 writeb(bin2bcd(year), base + S3C2410_RTCYEAR);
cefe4fbb 237 clk_disable(rtc_clk);
1add6781
BD
238
239 return 0;
240}
241
242static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
243{
244 struct rtc_time *alm_tm = &alrm->time;
9a654518 245 void __iomem *base = s3c_rtc_base;
1add6781
BD
246 unsigned int alm_en;
247
cefe4fbb 248 clk_enable(rtc_clk);
9a654518
BD
249 alm_tm->tm_sec = readb(base + S3C2410_ALMSEC);
250 alm_tm->tm_min = readb(base + S3C2410_ALMMIN);
251 alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR);
252 alm_tm->tm_mon = readb(base + S3C2410_ALMMON);
253 alm_tm->tm_mday = readb(base + S3C2410_ALMDATE);
254 alm_tm->tm_year = readb(base + S3C2410_ALMYEAR);
1add6781 255
9a654518 256 alm_en = readb(base + S3C2410_RTCALM);
1add6781 257
a2db8dfc
DB
258 alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
259
d4a48c2a 260 dev_dbg(dev, "read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n",
1add6781 261 alm_en,
30ffc40c 262 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
1add6781
BD
263 alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
264
265
266 /* decode the alarm enable field */
267
268 if (alm_en & S3C2410_RTCALM_SECEN)
fe20ba70 269 alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
1add6781 270 else
dd061d1a 271 alm_tm->tm_sec = -1;
1add6781
BD
272
273 if (alm_en & S3C2410_RTCALM_MINEN)
fe20ba70 274 alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
1add6781 275 else
dd061d1a 276 alm_tm->tm_min = -1;
1add6781
BD
277
278 if (alm_en & S3C2410_RTCALM_HOUREN)
fe20ba70 279 alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
1add6781 280 else
dd061d1a 281 alm_tm->tm_hour = -1;
1add6781
BD
282
283 if (alm_en & S3C2410_RTCALM_DAYEN)
fe20ba70 284 alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
1add6781 285 else
dd061d1a 286 alm_tm->tm_mday = -1;
1add6781
BD
287
288 if (alm_en & S3C2410_RTCALM_MONEN) {
fe20ba70 289 alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
1add6781
BD
290 alm_tm->tm_mon -= 1;
291 } else {
dd061d1a 292 alm_tm->tm_mon = -1;
1add6781
BD
293 }
294
295 if (alm_en & S3C2410_RTCALM_YEAREN)
fe20ba70 296 alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
1add6781 297 else
dd061d1a 298 alm_tm->tm_year = -1;
1add6781 299
cefe4fbb 300 clk_disable(rtc_clk);
1add6781
BD
301 return 0;
302}
303
304static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
305{
306 struct rtc_time *tm = &alrm->time;
9a654518 307 void __iomem *base = s3c_rtc_base;
1add6781
BD
308 unsigned int alrm_en;
309
cefe4fbb 310 clk_enable(rtc_clk);
d4a48c2a 311 dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n",
1add6781 312 alrm->enabled,
4e8896cd 313 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
30ffc40c 314 tm->tm_hour, tm->tm_min, tm->tm_sec);
1add6781 315
9a654518
BD
316 alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
317 writeb(0x00, base + S3C2410_RTCALM);
1add6781
BD
318
319 if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
320 alrm_en |= S3C2410_RTCALM_SECEN;
fe20ba70 321 writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC);
1add6781
BD
322 }
323
324 if (tm->tm_min < 60 && tm->tm_min >= 0) {
325 alrm_en |= S3C2410_RTCALM_MINEN;
fe20ba70 326 writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN);
1add6781
BD
327 }
328
329 if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
330 alrm_en |= S3C2410_RTCALM_HOUREN;
fe20ba70 331 writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR);
1add6781
BD
332 }
333
d4a48c2a 334 dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en);
1add6781 335
9a654518 336 writeb(alrm_en, base + S3C2410_RTCALM);
1add6781 337
2ec38a03 338 s3c_rtc_setaie(dev, alrm->enabled);
1add6781 339
cefe4fbb 340 clk_disable(rtc_clk);
1add6781
BD
341 return 0;
342}
343
1add6781
BD
344static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
345{
9f4123b7 346 unsigned int ticnt;
1add6781 347
cefe4fbb 348 clk_enable(rtc_clk);
9f4123b7 349 if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
f61ae671 350 ticnt = readw(s3c_rtc_base + S3C2410_RTCCON);
9f4123b7
MC
351 ticnt &= S3C64XX_RTCCON_TICEN;
352 } else {
353 ticnt = readb(s3c_rtc_base + S3C2410_TICNT);
354 ticnt &= S3C2410_TICNT_ENABLE;
355 }
356
357 seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
cefe4fbb 358 clk_disable(rtc_clk);
1add6781
BD
359 return 0;
360}
361
ff8371ac 362static const struct rtc_class_ops s3c_rtcops = {
1add6781
BD
363 .read_time = s3c_rtc_gettime,
364 .set_time = s3c_rtc_settime,
365 .read_alarm = s3c_rtc_getalarm,
366 .set_alarm = s3c_rtc_setalarm,
e6eb524e
CY
367 .proc = s3c_rtc_proc,
368 .alarm_irq_enable = s3c_rtc_setaie,
1add6781
BD
369};
370
371static void s3c_rtc_enable(struct platform_device *pdev, int en)
372{
9a654518 373 void __iomem *base = s3c_rtc_base;
1add6781
BD
374 unsigned int tmp;
375
376 if (s3c_rtc_base == NULL)
377 return;
378
cefe4fbb 379 clk_enable(rtc_clk);
1add6781 380 if (!en) {
f61ae671 381 tmp = readw(base + S3C2410_RTCCON);
9f4123b7
MC
382 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
383 tmp &= ~S3C64XX_RTCCON_TICEN;
384 tmp &= ~S3C2410_RTCCON_RTCEN;
f61ae671 385 writew(tmp, base + S3C2410_RTCCON);
9f4123b7 386
25c1a246 387 if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
9f4123b7
MC
388 tmp = readb(base + S3C2410_TICNT);
389 tmp &= ~S3C2410_TICNT_ENABLE;
390 writeb(tmp, base + S3C2410_TICNT);
391 }
1add6781
BD
392 } else {
393 /* re-enable the device, and check it is ok */
394
f61ae671 395 if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) {
1add6781
BD
396 dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
397
f61ae671
CY
398 tmp = readw(base + S3C2410_RTCCON);
399 writew(tmp | S3C2410_RTCCON_RTCEN,
400 base + S3C2410_RTCCON);
1add6781
BD
401 }
402
f61ae671 403 if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) {
1add6781
BD
404 dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
405
f61ae671
CY
406 tmp = readw(base + S3C2410_RTCCON);
407 writew(tmp & ~S3C2410_RTCCON_CNTSEL,
408 base + S3C2410_RTCCON);
1add6781
BD
409 }
410
f61ae671 411 if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) {
1add6781
BD
412 dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
413
f61ae671
CY
414 tmp = readw(base + S3C2410_RTCCON);
415 writew(tmp & ~S3C2410_RTCCON_CLKRST,
416 base + S3C2410_RTCCON);
1add6781
BD
417 }
418 }
cefe4fbb 419 clk_disable(rtc_clk);
1add6781
BD
420}
421
5a167f45 422static int s3c_rtc_remove(struct platform_device *dev)
1add6781 423{
1add6781 424 platform_set_drvdata(dev, NULL);
1add6781 425
2ec38a03 426 s3c_rtc_setaie(&dev->dev, 0);
1add6781 427
1a3224f1 428 clk_unprepare(rtc_clk);
e48add8c
AD
429 rtc_clk = NULL;
430
1add6781
BD
431 return 0;
432}
433
d2524caa
HS
434static const struct of_device_id s3c_rtc_dt_match[];
435
436static inline int s3c_rtc_get_driver_data(struct platform_device *pdev)
437{
438#ifdef CONFIG_OF
c3cba928 439 struct s3c_rtc_drv_data *data;
d2524caa
HS
440 if (pdev->dev.of_node) {
441 const struct of_device_id *match;
442 match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
c3cba928
TB
443 data = (struct s3c_rtc_drv_data *) match->data;
444 return data->cpu_type;
d2524caa
HS
445 }
446#endif
447 return platform_get_device_id(pdev)->driver_data;
448}
449
5a167f45 450static int s3c_rtc_probe(struct platform_device *pdev)
1add6781
BD
451{
452 struct rtc_device *rtc;
e1df962e 453 struct rtc_time rtc_tm;
1add6781
BD
454 struct resource *res;
455 int ret;
25c1a246 456 int tmp;
1add6781 457
d4a48c2a 458 dev_dbg(&pdev->dev, "%s: probe=%p\n", __func__, pdev);
1add6781
BD
459
460 /* find the IRQs */
461
462 s3c_rtc_tickno = platform_get_irq(pdev, 1);
463 if (s3c_rtc_tickno < 0) {
464 dev_err(&pdev->dev, "no irq for rtc tick\n");
1ee8c0ca 465 return s3c_rtc_tickno;
1add6781
BD
466 }
467
468 s3c_rtc_alarmno = platform_get_irq(pdev, 0);
469 if (s3c_rtc_alarmno < 0) {
470 dev_err(&pdev->dev, "no irq for alarm\n");
1ee8c0ca 471 return s3c_rtc_alarmno;
1add6781
BD
472 }
473
d4a48c2a 474 dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n",
1add6781
BD
475 s3c_rtc_tickno, s3c_rtc_alarmno);
476
477 /* get the memory region */
478
479 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8cbce1e5
TR
480 s3c_rtc_base = devm_ioremap_resource(&pdev->dev, res);
481 if (IS_ERR(s3c_rtc_base))
482 return PTR_ERR(s3c_rtc_base);
1add6781 483
1b997329 484 rtc_clk = devm_clk_get(&pdev->dev, "rtc");
e48add8c
AD
485 if (IS_ERR(rtc_clk)) {
486 dev_err(&pdev->dev, "failed to find rtc clock source\n");
487 ret = PTR_ERR(rtc_clk);
488 rtc_clk = NULL;
1b997329 489 return ret;
e48add8c
AD
490 }
491
1a3224f1 492 clk_prepare_enable(rtc_clk);
e48add8c 493
1add6781
BD
494 /* check to see if everything is setup correctly */
495
496 s3c_rtc_enable(pdev, 1);
497
d4a48c2a 498 dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n",
f61ae671 499 readw(s3c_rtc_base + S3C2410_RTCCON));
1add6781 500
51b7616e
YK
501 device_init_wakeup(&pdev->dev, 1);
502
1add6781
BD
503 /* register RTC and exit */
504
4c99c13a 505 rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops,
1add6781
BD
506 THIS_MODULE);
507
508 if (IS_ERR(rtc)) {
509 dev_err(&pdev->dev, "cannot attach rtc\n");
510 ret = PTR_ERR(rtc);
511 goto err_nortc;
512 }
513
d2524caa 514 s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev);
eaa6e4dd 515
051fe54e
TK
516 /* Check RTC Time */
517
e1df962e 518 s3c_rtc_gettime(NULL, &rtc_tm);
051fe54e 519
e1df962e
CY
520 if (rtc_valid_tm(&rtc_tm)) {
521 rtc_tm.tm_year = 100;
522 rtc_tm.tm_mon = 0;
523 rtc_tm.tm_mday = 1;
524 rtc_tm.tm_hour = 0;
525 rtc_tm.tm_min = 0;
526 rtc_tm.tm_sec = 0;
527
528 s3c_rtc_settime(NULL, &rtc_tm);
529
530 dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
051fe54e
TK
531 }
532
25c1a246 533 if (s3c_rtc_cpu_type != TYPE_S3C2410)
9f4123b7
MC
534 rtc->max_user_freq = 32768;
535 else
536 rtc->max_user_freq = 128;
537
25c1a246
HS
538 if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
539 tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
540 tmp |= S3C2443_RTCCON_TICSEL;
541 writew(tmp, s3c_rtc_base + S3C2410_RTCCON);
542 }
543
1add6781 544 platform_set_drvdata(pdev, rtc);
e893de59
MC
545
546 s3c_rtc_setfreq(&pdev->dev, 1);
547
1b997329 548 ret = devm_request_irq(&pdev->dev, s3c_rtc_alarmno, s3c_rtc_alarmirq,
2f6e5f94 549 0, "s3c2410-rtc alarm", rtc);
62d17601
MH
550 if (ret) {
551 dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret);
552 goto err_alarm_irq;
553 }
554
1b997329 555 ret = devm_request_irq(&pdev->dev, s3c_rtc_tickno, s3c_rtc_tickirq,
2f6e5f94 556 0, "s3c2410-rtc tick", rtc);
62d17601
MH
557 if (ret) {
558 dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret);
1b997329 559 goto err_alarm_irq;
62d17601
MH
560 }
561
cefe4fbb
DK
562 clk_disable(rtc_clk);
563
1add6781
BD
564 return 0;
565
62d17601
MH
566 err_alarm_irq:
567 platform_set_drvdata(pdev, NULL);
62d17601 568
1add6781
BD
569 err_nortc:
570 s3c_rtc_enable(pdev, 0);
1a3224f1 571 clk_disable_unprepare(rtc_clk);
1add6781 572
1add6781
BD
573 return ret;
574}
575
32e445aa 576#ifdef CONFIG_PM_SLEEP
1add6781
BD
577/* RTC Power management control */
578
9f4123b7 579static int ticnt_save, ticnt_en_save;
32e445aa 580static bool wake_en;
1add6781 581
32e445aa 582static int s3c_rtc_suspend(struct device *dev)
1add6781 583{
32e445aa
JH
584 struct platform_device *pdev = to_platform_device(dev);
585
cefe4fbb 586 clk_enable(rtc_clk);
1add6781 587 /* save TICNT for anyone using periodic interrupts */
9a654518 588 ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
9f4123b7 589 if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
f61ae671 590 ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON);
9f4123b7
MC
591 ticnt_en_save &= S3C64XX_RTCCON_TICEN;
592 }
1add6781 593 s3c_rtc_enable(pdev, 0);
f501ed52 594
32e445aa 595 if (device_may_wakeup(dev) && !wake_en) {
52cd4e5c
BD
596 if (enable_irq_wake(s3c_rtc_alarmno) == 0)
597 wake_en = true;
598 else
32e445aa 599 dev_err(dev, "enable_irq_wake failed\n");
52cd4e5c 600 }
cefe4fbb 601 clk_disable(rtc_clk);
f501ed52 602
1add6781
BD
603 return 0;
604}
605
32e445aa 606static int s3c_rtc_resume(struct device *dev)
1add6781 607{
32e445aa 608 struct platform_device *pdev = to_platform_device(dev);
9f4123b7
MC
609 unsigned int tmp;
610
cefe4fbb 611 clk_enable(rtc_clk);
1add6781 612 s3c_rtc_enable(pdev, 1);
9a654518 613 writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
9f4123b7 614 if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) {
f61ae671
CY
615 tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
616 writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON);
9f4123b7 617 }
f501ed52 618
32e445aa 619 if (device_may_wakeup(dev) && wake_en) {
f501ed52 620 disable_irq_wake(s3c_rtc_alarmno);
52cd4e5c
BD
621 wake_en = false;
622 }
cefe4fbb 623 clk_disable(rtc_clk);
f501ed52 624
1add6781
BD
625 return 0;
626}
1add6781
BD
627#endif
628
32e445aa
JH
629static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume);
630
ecb41a77 631#ifdef CONFIG_OF
c3cba928
TB
632static struct s3c_rtc_drv_data s3c_rtc_drv_data_array[] = {
633 [TYPE_S3C2410] = { TYPE_S3C2410 },
634 [TYPE_S3C2416] = { TYPE_S3C2416 },
635 [TYPE_S3C2443] = { TYPE_S3C2443 },
636 [TYPE_S3C64XX] = { TYPE_S3C64XX },
637};
638
39ce4084 639static const struct of_device_id s3c_rtc_dt_match[] = {
d2524caa 640 {
cd1e6f9e 641 .compatible = "samsung,s3c2410-rtc",
c3cba928 642 .data = &s3c_rtc_drv_data_array[TYPE_S3C2410],
25c1a246 643 }, {
cd1e6f9e 644 .compatible = "samsung,s3c2416-rtc",
c3cba928 645 .data = &s3c_rtc_drv_data_array[TYPE_S3C2416],
25c1a246 646 }, {
cd1e6f9e 647 .compatible = "samsung,s3c2443-rtc",
c3cba928 648 .data = &s3c_rtc_drv_data_array[TYPE_S3C2443],
d2524caa 649 }, {
cd1e6f9e 650 .compatible = "samsung,s3c6410-rtc",
c3cba928 651 .data = &s3c_rtc_drv_data_array[TYPE_S3C64XX],
d2524caa 652 },
39ce4084
TA
653 {},
654};
655MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
39ce4084
TA
656#endif
657
9f4123b7
MC
658static struct platform_device_id s3c_rtc_driver_ids[] = {
659 {
660 .name = "s3c2410-rtc",
661 .driver_data = TYPE_S3C2410,
25c1a246
HS
662 }, {
663 .name = "s3c2416-rtc",
664 .driver_data = TYPE_S3C2416,
665 }, {
666 .name = "s3c2443-rtc",
667 .driver_data = TYPE_S3C2443,
9f4123b7
MC
668 }, {
669 .name = "s3c64xx-rtc",
670 .driver_data = TYPE_S3C64XX,
671 },
672 { }
673};
674
675MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
676
677static struct platform_driver s3c_rtc_driver = {
1add6781 678 .probe = s3c_rtc_probe,
5a167f45 679 .remove = s3c_rtc_remove,
9f4123b7 680 .id_table = s3c_rtc_driver_ids,
1add6781 681 .driver = {
9f4123b7 682 .name = "s3c-rtc",
1add6781 683 .owner = THIS_MODULE,
32e445aa 684 .pm = &s3c_rtc_pm_ops,
04a373fd 685 .of_match_table = of_match_ptr(s3c_rtc_dt_match),
1add6781
BD
686 },
687};
688
0c4eae66 689module_platform_driver(s3c_rtc_driver);
1add6781
BD
690
691MODULE_DESCRIPTION("Samsung S3C RTC Driver");
692MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
693MODULE_LICENSE("GPL");
ad28a07b 694MODULE_ALIAS("platform:s3c2410-rtc");