[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / rtc / rtc-bfin.c

/*
 * Blackfin On-Chip Real Time Clock Driver
 *  Supports BF51x/BF52x/BF53[123]/BF53[467]/BF54x
 *
 * Copyright 2004-2010 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

/* The biggest issue we deal with in this driver is that register writes are
 * synced to the RTC frequency of 1Hz.  So if you write to a register and
 * attempt to write again before the first write has completed, the new write
 * is simply discarded.  This can easily be troublesome if userspace disables
 * one event (say periodic) and then right after enables an event (say alarm).
 * Since all events are maintained in the same interrupt mask register, if
 * we wrote to it to disable the first event and then wrote to it again to
 * enable the second event, that second event would not be enabled as the
 * write would be discarded and things quickly fall apart.
 *
 * To keep this delay from significantly degrading performance (we, in theory,
 * would have to sleep for up to 1 second every time we wanted to write a
 * register), we only check the write pending status before we start to issue
 * a new write.  We bank on the idea that it doesn't matter when the sync
 * happens so long as we don't attempt another write before it does.  The only
 * time userspace would take this penalty is when they try and do multiple
 * operations right after another ... but in this case, they need to take the
 * sync penalty, so we should be OK.
 *
 * Also note that the RTC_ISTAT register does not suffer this penalty; its
 * writes to clear status registers complete immediately.
 */

/* It may seem odd that there is no SWCNT code in here (which would be exposed
 * via the periodic interrupt event, or PIE).  Since the Blackfin RTC peripheral
 * runs in units of seconds (N/HZ) but the Linux framework runs in units of HZ
 * (2^N HZ), there is no point in keeping code that only provides 1 HZ PIEs.
 * The same exact behavior can be accomplished by using the update interrupt
 * event (UIE).  Maybe down the line the RTC peripheral will suck less in which
 * case we can re-introduce PIE support.
 */

#include <linux/bcd.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/seq_file.h>
#include <linux/slab.h>

#include <asm/blackfin.h>

#define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__)

struct bfin_rtc {
	struct rtc_device *rtc_dev;
	struct rtc_time rtc_alarm;
	u16 rtc_wrote_regs;
};

/* Bit values for the ISTAT / ICTL registers */
#define RTC_ISTAT_WRITE_COMPLETE  0x8000
#define RTC_ISTAT_WRITE_PENDING   0x4000
#define RTC_ISTAT_ALARM_DAY       0x0040
#define RTC_ISTAT_24HR            0x0020
#define RTC_ISTAT_HOUR            0x0010
#define RTC_ISTAT_MIN             0x0008
#define RTC_ISTAT_SEC             0x0004
#define RTC_ISTAT_ALARM           0x0002
#define RTC_ISTAT_STOPWATCH       0x0001

/* Shift values for RTC_STAT register */
#define DAY_BITS_OFF    17
#define HOUR_BITS_OFF   12
#define MIN_BITS_OFF    6
#define SEC_BITS_OFF    0

/* Some helper functions to convert between the common RTC notion of time
 * and the internal Blackfin notion that is encoded in 32bits.
 */
static inline u32 rtc_time_to_bfin(unsigned long now)
{
	u32 sec  = (now % 60);
	u32 min  = (now % (60 * 60)) / 60;
	u32 hour = (now % (60 * 60 * 24)) / (60 * 60);
	u32 days = (now / (60 * 60 * 24));
	return (sec  << SEC_BITS_OFF) +
	       (min  << MIN_BITS_OFF) +
	       (hour << HOUR_BITS_OFF) +
	       (days << DAY_BITS_OFF);
}
static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin)
{
	return (((rtc_bfin >> SEC_BITS_OFF)  & 0x003F)) +
	       (((rtc_bfin >> MIN_BITS_OFF)  & 0x003F) * 60) +
	       (((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) +
	       (((rtc_bfin >> DAY_BITS_OFF)  & 0x7FFF) * 60 * 60 * 24);
}
static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm)
{
	rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm);
}

/**
 *	bfin_rtc_sync_pending - make sure pending writes have complete
 *
 * Wait for the previous write to a RTC register to complete.
 * Unfortunately, we can't sleep here as that introduces a race condition when
 * turning on interrupt events.  Consider this:
 *  - process sets alarm
 *  - process enables alarm
 *  - process sleeps while waiting for rtc write to sync
 *  - interrupt fires while process is sleeping
 *  - interrupt acks the event by writing to ISTAT
 *  - interrupt sets the WRITE PENDING bit
 *  - interrupt handler finishes
 *  - process wakes up, sees WRITE PENDING bit set, goes to sleep
 *  - interrupt fires while process is sleeping
 * If anyone can point out the obvious solution here, i'm listening :).  This
 * shouldn't be an issue on an SMP or preempt system as this function should
 * only be called with the rtc lock held.
 *
 * Other options:
 *  - disable PREN so the sync happens at 32.768kHZ ... but this changes the
 *    inc rate for all RTC registers from 1HZ to 32.768kHZ ...
 *  - use the write complete IRQ
 */
/*
static void bfin_rtc_sync_pending_polled(void)
{
	while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE))
		if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING))
			break;
	bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
}
*/
static DECLARE_COMPLETION(bfin_write_complete);
static void bfin_rtc_sync_pending(struct device *dev)
{
	dev_dbg_stamp(dev);
	while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
		wait_for_completion_timeout(&bfin_write_complete, HZ * 5);
	dev_dbg_stamp(dev);
}

/**
 *	bfin_rtc_reset - set RTC to sane/known state
 *
 * Initialize the RTC.  Enable pre-scaler to scale RTC clock
 * to 1Hz and clear interrupt/status registers.
 */
static void bfin_rtc_reset(struct device *dev, u16 rtc_ictl)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	dev_dbg_stamp(dev);
	bfin_rtc_sync_pending(dev);
	bfin_write_RTC_PREN(0x1);
	bfin_write_RTC_ICTL(rtc_ictl);
	bfin_write_RTC_ALARM(0);
	bfin_write_RTC_ISTAT(0xFFFF);
	rtc->rtc_wrote_regs = 0;
}

/**
 *	bfin_rtc_interrupt - handle interrupt from RTC
 *
 * Since we handle all RTC events here, we have to make sure the requested
 * interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT)
 * always gets updated regardless of the interrupt being enabled.  So when one
 * even we care about (e.g. stopwatch) goes off, we don't want to turn around
 * and say that other events have happened as well (e.g. second).  We do not
 * have to worry about pending writes to the RTC_ICTL register as interrupts
 * only fire if they are enabled in the RTC_ICTL register.
 */
static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
{
	struct device *dev = dev_id;
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	unsigned long events = 0;
	bool write_complete = false;
	u16 rtc_istat, rtc_istat_clear, rtc_ictl, bits;

	dev_dbg_stamp(dev);

	rtc_istat = bfin_read_RTC_ISTAT();
	rtc_ictl = bfin_read_RTC_ICTL();
	rtc_istat_clear = 0;

	bits = RTC_ISTAT_WRITE_COMPLETE;
	if (rtc_istat & bits) {
		rtc_istat_clear |= bits;
		write_complete = true;
		complete(&bfin_write_complete);
	}

	bits = (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY);
	if (rtc_ictl & bits) {
		if (rtc_istat & bits) {
			rtc_istat_clear |= bits;
			events |= RTC_AF | RTC_IRQF;
		}
	}

	bits = RTC_ISTAT_SEC;
	if (rtc_ictl & bits) {
		if (rtc_istat & bits) {
			rtc_istat_clear |= bits;
			events |= RTC_UF | RTC_IRQF;
		}
	}

	if (events)
		rtc_update_irq(rtc->rtc_dev, 1, events);

	if (write_complete || events) {
		bfin_write_RTC_ISTAT(rtc_istat_clear);
		return IRQ_HANDLED;
	} else
		return IRQ_NONE;
}

static void bfin_rtc_int_set(u16 rtc_int)
{
	bfin_write_RTC_ISTAT(rtc_int);
	bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | rtc_int);
}
static void bfin_rtc_int_clear(u16 rtc_int)
{
	bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int);
}
static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc)
{
	/* Blackfin has different bits for whether the alarm is
	 * more than 24 hours away.
	 */
	bfin_rtc_int_set(rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY);
}

static int bfin_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);

	dev_dbg_stamp(dev);
	if (enabled)
		bfin_rtc_int_set_alarm(rtc);
	else
		bfin_rtc_int_clear(~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));

	return 0;
}

static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);

	dev_dbg_stamp(dev);

	if (rtc->rtc_wrote_regs & 0x1)
		bfin_rtc_sync_pending(dev);

	rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm);

	return 0;
}

static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	int ret;
	unsigned long now;

	dev_dbg_stamp(dev);

	ret = rtc_tm_to_time(tm, &now);
	if (ret == 0) {
		if (rtc->rtc_wrote_regs & 0x1)
			bfin_rtc_sync_pending(dev);
		bfin_write_RTC_STAT(rtc_time_to_bfin(now));
		rtc->rtc_wrote_regs = 0x1;
	}

	return ret;
}

static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	dev_dbg_stamp(dev);
	alrm->time = rtc->rtc_alarm;
	bfin_rtc_sync_pending(dev);
	alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
	return 0;
}

static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	unsigned long rtc_alarm;

	dev_dbg_stamp(dev);

	if (rtc_tm_to_time(&alrm->time, &rtc_alarm))
		return -EINVAL;

	rtc->rtc_alarm = alrm->time;

	bfin_rtc_sync_pending(dev);
	bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm));
	if (alrm->enabled)
		bfin_rtc_int_set_alarm(rtc);

	return 0;
}

static int bfin_rtc_proc(struct device *dev, struct seq_file *seq)
{
#define yesno(x) ((x) ? "yes" : "no")
	u16 ictl = bfin_read_RTC_ICTL();
	dev_dbg_stamp(dev);
	seq_printf(seq,
		"alarm_IRQ\t: %s\n"
		"wkalarm_IRQ\t: %s\n"
		"seconds_IRQ\t: %s\n",
		yesno(ictl & RTC_ISTAT_ALARM),
		yesno(ictl & RTC_ISTAT_ALARM_DAY),
		yesno(ictl & RTC_ISTAT_SEC));
	return 0;
#undef yesno
}

static struct rtc_class_ops bfin_rtc_ops = {
	.read_time     = bfin_rtc_read_time,
	.set_time      = bfin_rtc_set_time,
	.read_alarm    = bfin_rtc_read_alarm,
	.set_alarm     = bfin_rtc_set_alarm,
	.proc          = bfin_rtc_proc,
	.alarm_irq_enable = bfin_rtc_alarm_irq_enable,
};

static int bfin_rtc_probe(struct platform_device *pdev)
{
	struct bfin_rtc *rtc;
	struct device *dev = &pdev->dev;
	int ret = 0;
	unsigned long timeout = jiffies + HZ;

	dev_dbg_stamp(dev);

	/* Allocate memory for our RTC struct */
	rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
	if (unlikely(!rtc))
		return -ENOMEM;
	platform_set_drvdata(pdev, rtc);
	device_init_wakeup(dev, 1);

	/* Register our RTC with the RTC framework */
	rtc->rtc_dev = devm_rtc_device_register(dev, pdev->name, &bfin_rtc_ops,
						THIS_MODULE);
	if (unlikely(IS_ERR(rtc->rtc_dev))) {
		ret = PTR_ERR(rtc->rtc_dev);
		goto err;
	}

	/* Grab the IRQ and init the hardware */
	ret = devm_request_irq(dev, IRQ_RTC, bfin_rtc_interrupt, 0,
				pdev->name, dev);
	if (unlikely(ret))
		goto err;
	/* sometimes the bootloader touched things, but the write complete was not
	 * enabled, so let's just do a quick timeout here since the IRQ will not fire ...
	 */
	while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
		if (time_after(jiffies, timeout))
			break;
	bfin_rtc_reset(dev, RTC_ISTAT_WRITE_COMPLETE);
	bfin_write_RTC_SWCNT(0);

	return 0;

err:
	return ret;
}

static int bfin_rtc_remove(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;

	bfin_rtc_reset(dev, 0);
	platform_set_drvdata(pdev, NULL);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int bfin_rtc_suspend(struct device *dev)
{
	dev_dbg_stamp(dev);

	if (device_may_wakeup(dev)) {
		enable_irq_wake(IRQ_RTC);
		bfin_rtc_sync_pending(dev);
	} else
		bfin_rtc_int_clear(0);

	return 0;
}

static int bfin_rtc_resume(struct device *dev)
{
	dev_dbg_stamp(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(IRQ_RTC);

	/*
	 * Since only some of the RTC bits are maintained externally in the
	 * Vbat domain, we need to wait for the RTC MMRs to be synced into
	 * the core after waking up.  This happens every RTC 1HZ.  Once that
	 * has happened, we can go ahead and re-enable the important write
	 * complete interrupt event.
	 */
	while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_SEC))
		continue;
	bfin_rtc_int_set(RTC_ISTAT_WRITE_COMPLETE);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(bfin_rtc_pm_ops, bfin_rtc_suspend, bfin_rtc_resume);

static struct platform_driver bfin_rtc_driver = {
	.driver		= {
		.name	= "rtc-bfin",
		.owner	= THIS_MODULE,
		.pm	= &bfin_rtc_pm_ops,
	},
	.probe		= bfin_rtc_probe,
	.remove		= bfin_rtc_remove,
};

module_platform_driver(bfin_rtc_driver);

MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver");
MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:rtc-bfin");
Commit	Line	Data
8cc75c9a WB	1	/*
8cc75c9a WB	2	* Blackfin On-Chip Real Time Clock Driver
9980060b	3	* Supports BF51x/BF52x/BF53[123]/BF53[467]/BF54x
8cc75c9a	4	*
d7c7ef90	5	* Copyright 2004-2010 Analog Devices Inc.
8cc75c9a WB	6	*
	7	* Enter bugs at http://blackfin.uclinux.org/
	8	*
	9	* Licensed under the GPL-2 or later.
	10	*/
	11
	12	/* The biggest issue we deal with in this driver is that register writes are
	13	* synced to the RTC frequency of 1Hz. So if you write to a register and
	14	* attempt to write again before the first write has completed, the new write
	15	* is simply discarded. This can easily be troublesome if userspace disables
	16	* one event (say periodic) and then right after enables an event (say alarm).
	17	* Since all events are maintained in the same interrupt mask register, if
	18	* we wrote to it to disable the first event and then wrote to it again to
	19	* enable the second event, that second event would not be enabled as the
	20	* write would be discarded and things quickly fall apart.
	21	*
	22	* To keep this delay from significantly degrading performance (we, in theory,
25985edc	23	* would have to sleep for up to 1 second every time we wanted to write a
8cc75c9a	24	* register), we only check the write pending status before we start to issue
25985edc	25	* a new write. We bank on the idea that it doesn't matter when the sync
8cc75c9a WB	26	* happens so long as we don't attempt another write before it does. The only
	27	* time userspace would take this penalty is when they try and do multiple
	28	* operations right after another ... but in this case, they need to take the
	29	* sync penalty, so we should be OK.
	30	*
	31	* Also note that the RTC_ISTAT register does not suffer this penalty; its
	32	* writes to clear status registers complete immediately.
	33	*/
	34
26cb8bb2 MF	35	/* It may seem odd that there is no SWCNT code in here (which would be exposed
	36	* via the periodic interrupt event, or PIE). Since the Blackfin RTC peripheral
	37	* runs in units of seconds (N/HZ) but the Linux framework runs in units of HZ
	38	* (2^N HZ), there is no point in keeping code that only provides 1 HZ PIEs.
	39	* The same exact behavior can be accomplished by using the update interrupt
	40	* event (UIE). Maybe down the line the RTC peripheral will suck less in which
	41	* case we can re-introduce PIE support.
	42	*/
	43
8cc75c9a	44	#include <linux/bcd.h>
095b9d54 MF	45	#include <linux/completion.h>
095b9d54 MF	46	#include <linux/delay.h>
8cc75c9a	47	#include <linux/init.h>
095b9d54 MF	48	#include <linux/interrupt.h>
	49	#include <linux/kernel.h>
	50	#include <linux/module.h>
8cc75c9a	51	#include <linux/platform_device.h>
095b9d54	52	#include <linux/rtc.h>
8cc75c9a	53	#include <linux/seq_file.h>
5a0e3ad6	54	#include <linux/slab.h>
8cc75c9a WB	55
	56	#include <asm/blackfin.h>
	57
5438de44	58	#define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__)
8cc75c9a WB	59
	60	struct bfin_rtc {
	61	struct rtc_device *rtc_dev;
	62	struct rtc_time rtc_alarm;
095b9d54	63	u16 rtc_wrote_regs;
8cc75c9a WB	64	};
	65
	66	/* Bit values for the ISTAT / ICTL registers */
	67	#define RTC_ISTAT_WRITE_COMPLETE 0x8000
	68	#define RTC_ISTAT_WRITE_PENDING 0x4000
	69	#define RTC_ISTAT_ALARM_DAY 0x0040
	70	#define RTC_ISTAT_24HR 0x0020
	71	#define RTC_ISTAT_HOUR 0x0010
	72	#define RTC_ISTAT_MIN 0x0008
	73	#define RTC_ISTAT_SEC 0x0004
	74	#define RTC_ISTAT_ALARM 0x0002
	75	#define RTC_ISTAT_STOPWATCH 0x0001
	76
	77	/* Shift values for RTC_STAT register */
	78	#define DAY_BITS_OFF 17
	79	#define HOUR_BITS_OFF 12
	80	#define MIN_BITS_OFF 6
	81	#define SEC_BITS_OFF 0
	82
	83	/* Some helper functions to convert between the common RTC notion of time
5c236343	84	* and the internal Blackfin notion that is encoded in 32bits.
8cc75c9a WB	85	*/
	86	static inline u32 rtc_time_to_bfin(unsigned long now)
	87	{
	88	u32 sec = (now % 60);
	89	u32 min = (now % (60 * 60)) / 60;
	90	u32 hour = (now % (60 * 60 * 24)) / (60 * 60);
	91	u32 days = (now / (60 * 60 * 24));
	92	return (sec << SEC_BITS_OFF) +
	93	(min << MIN_BITS_OFF) +
	94	(hour << HOUR_BITS_OFF) +
	95	(days << DAY_BITS_OFF);
	96	}
	97	static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin)
	98	{
	99	return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) +
	100	(((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) +
	101	(((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) +
	102	(((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24);
	103	}
	104	static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm)
	105	{
	106	rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm);
	107	}
	108
095b9d54 MF	109	/**
	110	* bfin_rtc_sync_pending - make sure pending writes have complete
	111	*
	112	* Wait for the previous write to a RTC register to complete.
8cc75c9a WB	113	* Unfortunately, we can't sleep here as that introduces a race condition when
	114	* turning on interrupt events. Consider this:
	115	* - process sets alarm
	116	* - process enables alarm
	117	* - process sleeps while waiting for rtc write to sync
	118	* - interrupt fires while process is sleeping
	119	* - interrupt acks the event by writing to ISTAT
	120	* - interrupt sets the WRITE PENDING bit
	121	* - interrupt handler finishes
	122	* - process wakes up, sees WRITE PENDING bit set, goes to sleep
	123	* - interrupt fires while process is sleeping
	124	* If anyone can point out the obvious solution here, i'm listening :). This
	125	* shouldn't be an issue on an SMP or preempt system as this function should
	126	* only be called with the rtc lock held.
5c236343 MF	127	*
	128	* Other options:
	129	* - disable PREN so the sync happens at 32.768kHZ ... but this changes the
	130	* inc rate for all RTC registers from 1HZ to 32.768kHZ ...
	131	* - use the write complete IRQ
8cc75c9a	132	*/
095b9d54 MF	133	/*
095b9d54 MF	134	static void bfin_rtc_sync_pending_polled(void)
8cc75c9a	135	{
095b9d54	136	while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE))
8cc75c9a WB	137	if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING))
8cc75c9a WB	138	break;
8cc75c9a WB	139	bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
8cc75c9a WB	140	}
095b9d54 MF	141	*/
	142	static DECLARE_COMPLETION(bfin_write_complete);
	143	static void bfin_rtc_sync_pending(struct device *dev)
	144	{
	145	dev_dbg_stamp(dev);
	146	while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
	147	wait_for_completion_timeout(&bfin_write_complete, HZ * 5);
	148	dev_dbg_stamp(dev);
	149	}
8cc75c9a	150
095b9d54 MF	151	/**
	152	* bfin_rtc_reset - set RTC to sane/known state
	153	*
	154	* Initialize the RTC. Enable pre-scaler to scale RTC clock
	155	* to 1Hz and clear interrupt/status registers.
	156	*/
3b128fe0	157	static void bfin_rtc_reset(struct device *dev, u16 rtc_ictl)
8cc75c9a	158	{
5438de44	159	struct bfin_rtc *rtc = dev_get_drvdata(dev);
095b9d54 MF	160	dev_dbg_stamp(dev);
095b9d54 MF	161	bfin_rtc_sync_pending(dev);
8cc75c9a	162	bfin_write_RTC_PREN(0x1);
3b128fe0	163	bfin_write_RTC_ICTL(rtc_ictl);
8cc75c9a WB	164	bfin_write_RTC_ALARM(0);
8cc75c9a WB	165	bfin_write_RTC_ISTAT(0xFFFF);
095b9d54	166	rtc->rtc_wrote_regs = 0;
8cc75c9a WB	167	}
8cc75c9a WB	168
095b9d54 MF	169	/**
	170	* bfin_rtc_interrupt - handle interrupt from RTC
	171	*
	172	* Since we handle all RTC events here, we have to make sure the requested
	173	* interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT)
	174	* always gets updated regardless of the interrupt being enabled. So when one
	175	* even we care about (e.g. stopwatch) goes off, we don't want to turn around
	176	* and say that other events have happened as well (e.g. second). We do not
	177	* have to worry about pending writes to the RTC_ICTL register as interrupts
	178	* only fire if they are enabled in the RTC_ICTL register.
	179	*/
8cc75c9a WB	180	static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
8cc75c9a WB	181	{
d7827d88 MF	182	struct device *dev = dev_id;
d7827d88 MF	183	struct bfin_rtc *rtc = dev_get_drvdata(dev);
8cc75c9a	184	unsigned long events = 0;
095b9d54	185	bool write_complete = false;
286f9f95	186	u16 rtc_istat, rtc_istat_clear, rtc_ictl, bits;
8cc75c9a	187
5438de44	188	dev_dbg_stamp(dev);
8cc75c9a	189
8cc75c9a	190	rtc_istat = bfin_read_RTC_ISTAT();
095b9d54	191	rtc_ictl = bfin_read_RTC_ICTL();
286f9f95	192	rtc_istat_clear = 0;
8cc75c9a	193
286f9f95 MF	194	bits = RTC_ISTAT_WRITE_COMPLETE;
	195	if (rtc_istat & bits) {
	196	rtc_istat_clear \|= bits;
095b9d54 MF	197	write_complete = true;
095b9d54 MF	198	complete(&bfin_write_complete);
8cc75c9a WB	199	}
8cc75c9a WB	200
286f9f95 MF	201	bits = (RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY);
	202	if (rtc_ictl & bits) {
	203	if (rtc_istat & bits) {
	204	rtc_istat_clear \|= bits;
095b9d54 MF	205	events \|= RTC_AF \| RTC_IRQF;
095b9d54 MF	206	}
8cc75c9a WB	207	}
8cc75c9a WB	208
286f9f95 MF	209	bits = RTC_ISTAT_SEC;
	210	if (rtc_ictl & bits) {
	211	if (rtc_istat & bits) {
	212	rtc_istat_clear \|= bits;
095b9d54 MF	213	events \|= RTC_UF \| RTC_IRQF;
	214	}
	215	}
8cc75c9a	216
095b9d54 MF	217	if (events)
095b9d54 MF	218	rtc_update_irq(rtc->rtc_dev, 1, events);
8cc75c9a	219
286f9f95 MF	220	if (write_complete \|\| events) {
286f9f95 MF	221	bfin_write_RTC_ISTAT(rtc_istat_clear);
095b9d54	222	return IRQ_HANDLED;
286f9f95	223	} else
095b9d54	224	return IRQ_NONE;
8cc75c9a WB	225	}
8cc75c9a WB	226
605eb8b3	227	static void bfin_rtc_int_set(u16 rtc_int)
095b9d54 MF	228	{
	229	bfin_write_RTC_ISTAT(rtc_int);
	230	bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() \| rtc_int);
	231	}
605eb8b3	232	static void bfin_rtc_int_clear(u16 rtc_int)
095b9d54 MF	233	{
	234	bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int);
	235	}
	236	static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc)
	237	{
	238	/* Blackfin has different bits for whether the alarm is
	239	* more than 24 hours away.
	240	*/
605eb8b3	241	bfin_rtc_int_set(rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY);
095b9d54	242	}
8cc75c9a	243
16380c15 JS	244	static int bfin_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	245	{
	246	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	247
	248	dev_dbg_stamp(dev);
	249	if (enabled)
	250	bfin_rtc_int_set_alarm(rtc);
	251	else
	252	bfin_rtc_int_clear(~(RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY));
8c122b96 MF	253
8c122b96 MF	254	return 0;
16380c15 JS	255	}
16380c15 JS	256
8cc75c9a WB	257	static int bfin_rtc_read_time(struct device dev, struct rtc_time tm)
	258	{
	259	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	260
5438de44	261	dev_dbg_stamp(dev);
8cc75c9a	262
095b9d54 MF	263	if (rtc->rtc_wrote_regs & 0x1)
	264	bfin_rtc_sync_pending(dev);
	265
8cc75c9a	266	rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm);
8cc75c9a WB	267
	268	return 0;
	269	}
	270
	271	static int bfin_rtc_set_time(struct device dev, struct rtc_time tm)
	272	{
	273	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	274	int ret;
	275	unsigned long now;
	276
5438de44	277	dev_dbg_stamp(dev);
8cc75c9a	278
8cc75c9a WB	279	ret = rtc_tm_to_time(tm, &now);
8cc75c9a WB	280	if (ret == 0) {
095b9d54 MF	281	if (rtc->rtc_wrote_regs & 0x1)
095b9d54 MF	282	bfin_rtc_sync_pending(dev);
8cc75c9a	283	bfin_write_RTC_STAT(rtc_time_to_bfin(now));
095b9d54	284	rtc->rtc_wrote_regs = 0x1;
8cc75c9a WB	285	}
8cc75c9a WB	286
8cc75c9a WB	287	return ret;
	288	}
	289
	290	static int bfin_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	291	{
	292	struct bfin_rtc *rtc = dev_get_drvdata(dev);
5438de44	293	dev_dbg_stamp(dev);
48c1a56b	294	alrm->time = rtc->rtc_alarm;
095b9d54	295	bfin_rtc_sync_pending(dev);
68db3047	296	alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY));
8cc75c9a WB	297	return 0;
	298	}
	299
	300	static int bfin_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	301	{
	302	struct bfin_rtc *rtc = dev_get_drvdata(dev);
095b9d54 MF	303	unsigned long rtc_alarm;
095b9d54 MF	304
5438de44	305	dev_dbg_stamp(dev);
095b9d54 MF	306
	307	if (rtc_tm_to_time(&alrm->time, &rtc_alarm))
	308	return -EINVAL;
	309
68db3047	310	rtc->rtc_alarm = alrm->time;
095b9d54 MF	311
	312	bfin_rtc_sync_pending(dev);
	313	bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm));
	314	if (alrm->enabled)
	315	bfin_rtc_int_set_alarm(rtc);
	316
8cc75c9a WB	317	return 0;
	318	}
	319
	320	static int bfin_rtc_proc(struct device dev, struct seq_file seq)
	321	{
64061160	322	#define yesno(x) ((x) ? "yes" : "no")
8cc75c9a	323	u16 ictl = bfin_read_RTC_ICTL();
5438de44	324	dev_dbg_stamp(dev);
64061160 MF	325	seq_printf(seq,
	326	"alarm_IRQ\t: %s\n"
	327	"wkalarm_IRQ\t: %s\n"
26cb8bb2	328	"seconds_IRQ\t: %s\n",
64061160 MF	329	yesno(ictl & RTC_ISTAT_ALARM),
64061160 MF	330	yesno(ictl & RTC_ISTAT_ALARM_DAY),
26cb8bb2	331	yesno(ictl & RTC_ISTAT_SEC));
8cc75c9a	332	return 0;
64061160	333	#undef yesno
8cc75c9a WB	334	}
8cc75c9a WB	335
8cc75c9a	336	static struct rtc_class_ops bfin_rtc_ops = {
8cc75c9a WB	337	.read_time = bfin_rtc_read_time,
	338	.set_time = bfin_rtc_set_time,
	339	.read_alarm = bfin_rtc_read_alarm,
	340	.set_alarm = bfin_rtc_set_alarm,
	341	.proc = bfin_rtc_proc,
16380c15	342	.alarm_irq_enable = bfin_rtc_alarm_irq_enable,
8cc75c9a WB	343	};
8cc75c9a WB	344
5a167f45	345	static int bfin_rtc_probe(struct platform_device *pdev)
8cc75c9a WB	346	{
8cc75c9a WB	347	struct bfin_rtc *rtc;
fe2e1cf8	348	struct device *dev = &pdev->dev;
8cc75c9a	349	int ret = 0;
9980060b	350	unsigned long timeout = jiffies + HZ;
8cc75c9a	351
fe2e1cf8	352	dev_dbg_stamp(dev);
8cc75c9a	353
fe2e1cf8	354	/* Allocate memory for our RTC struct */
87e7d520	355	rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
8cc75c9a WB	356	if (unlikely(!rtc))
8cc75c9a WB	357	return -ENOMEM;
fe2e1cf8	358	platform_set_drvdata(pdev, rtc);
8c9166f7	359	device_init_wakeup(dev, 1);
8cc75c9a	360
9980060b	361	/* Register our RTC with the RTC framework */
87e7d520	362	rtc->rtc_dev = devm_rtc_device_register(dev, pdev->name, &bfin_rtc_ops,
9980060b MF	363	THIS_MODULE);
	364	if (unlikely(IS_ERR(rtc->rtc_dev))) {
	365	ret = PTR_ERR(rtc->rtc_dev);
	366	goto err;
	367	}
	368
fe2e1cf8	369	/* Grab the IRQ and init the hardware */
87e7d520 JH	370	ret = devm_request_irq(dev, IRQ_RTC, bfin_rtc_interrupt, 0,
87e7d520 JH	371	pdev->name, dev);
fe2e1cf8	372	if (unlikely(ret))
87e7d520	373	goto err;
d0fd9378 MF	374	/* sometimes the bootloader touched things, but the write complete was not
	375	* enabled, so let's just do a quick timeout here since the IRQ will not fire ...
	376	*/
d0fd9378 MF	377	while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
	378	if (time_after(jiffies, timeout))
	379	break;
fe2e1cf8	380	bfin_rtc_reset(dev, RTC_ISTAT_WRITE_COMPLETE);
26cb8bb2	381	bfin_write_RTC_SWCNT(0);
8cc75c9a	382
8cc75c9a WB	383	return 0;
8cc75c9a WB	384
9980060b	385	err:
8cc75c9a WB	386	return ret;
	387	}
	388
5a167f45	389	static int bfin_rtc_remove(struct platform_device *pdev)
8cc75c9a	390	{
fe2e1cf8	391	struct device *dev = &pdev->dev;
8cc75c9a	392
fe2e1cf8	393	bfin_rtc_reset(dev, 0);
8cc75c9a	394	platform_set_drvdata(pdev, NULL);
8cc75c9a WB	395
	396	return 0;
	397	}
	398
b4df8f6c JH	399	#ifdef CONFIG_PM_SLEEP
b4df8f6c JH	400	static int bfin_rtc_suspend(struct device *dev)
5aeb776d	401	{
d7c7ef90 MF	402	dev_dbg_stamp(dev);
	403
	404	if (device_may_wakeup(dev)) {
813006f4	405	enable_irq_wake(IRQ_RTC);
d7c7ef90	406	bfin_rtc_sync_pending(dev);
140fab14	407	} else
110b7e96	408	bfin_rtc_int_clear(0);
813006f4	409
5aeb776d SZ	410	return 0;
	411	}
	412
b4df8f6c	413	static int bfin_rtc_resume(struct device *dev)
5aeb776d	414	{
d7c7ef90 MF	415	dev_dbg_stamp(dev);
	416
	417	if (device_may_wakeup(dev))
813006f4	418	disable_irq_wake(IRQ_RTC);
b6de8606 MF	419
	420	/*
	421	* Since only some of the RTC bits are maintained externally in the
	422	* Vbat domain, we need to wait for the RTC MMRs to be synced into
	423	* the core after waking up. This happens every RTC 1HZ. Once that
	424	* has happened, we can go ahead and re-enable the important write
	425	* complete interrupt event.
	426	*/
	427	while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_SEC))
	428	continue;
	429	bfin_rtc_int_set(RTC_ISTAT_WRITE_COMPLETE);
813006f4	430
5aeb776d SZ	431	return 0;
	432	}
	433	#endif
	434
b4df8f6c JH	435	static SIMPLE_DEV_PM_OPS(bfin_rtc_pm_ops, bfin_rtc_suspend, bfin_rtc_resume);
b4df8f6c JH	436
8cc75c9a WB	437	static struct platform_driver bfin_rtc_driver = {
	438	.driver = {
	439	.name = "rtc-bfin",
	440	.owner = THIS_MODULE,
b4df8f6c	441	.pm = &bfin_rtc_pm_ops,
8cc75c9a WB	442	},
8cc75c9a WB	443	.probe = bfin_rtc_probe,
5a167f45	444	.remove = bfin_rtc_remove,
8cc75c9a WB	445	};
8cc75c9a WB	446
0c4eae66	447	module_platform_driver(bfin_rtc_driver);
8cc75c9a WB	448
	449	MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver");
	450	MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
	451	MODULE_LICENSE("GPL");
ad28a07b	452	MODULE_ALIAS("platform:rtc-bfin");