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Merge tag 'v3.10.108' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / regulator / s5m8767.c
CommitLineData
9767ec7f
SK		 1/*
2 * s5m8767.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/bug.h>
9767ec7f
SK		 15#include <linux/err.h>
16#include <linux/gpio.h>
26aec009 17#include <linux/of_gpio.h>
9767ec7f
SK		 18#include <linux/slab.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
54227bcf
SK		 23#include <linux/mfd/samsung/core.h>
24#include <linux/mfd/samsung/s5m8767.h>
26aec009
ADK		 25#include <linux/regulator/of_regulator.h>
26
27#define S5M8767_OPMODE_NORMAL_MODE 0x1
9767ec7f
SK		 28
29struct s5m8767_info {
30 struct device *dev;
63063bfb 31 struct sec_pmic_dev *iodev;
9767ec7f
SK		 32 int num_regulators;
33 struct regulator_dev **rdev;
63063bfb 34 struct sec_opmode_data *opmode;
9767ec7f
SK		 35
36 int ramp_delay;
37 bool buck2_ramp;
38 bool buck3_ramp;
39 bool buck4_ramp;
40
41 bool buck2_gpiodvs;
42 bool buck3_gpiodvs;
43 bool buck4_gpiodvs;
44 u8 buck2_vol[8];
45 u8 buck3_vol[8];
46 u8 buck4_vol[8];
47 int buck_gpios[3];
c848bc85 48 int buck_ds[3];
9767ec7f
SK		 49 int buck_gpioindex;
50};
51
63063bfb 52struct sec_voltage_desc {
9767ec7f
SK		 53 int max;
54 int min;
55 int step;
56};
57
63063bfb 58static const struct sec_voltage_desc buck_voltage_val1 = {
9767ec7f
SK		 59 .max = 2225000,
60 .min = 650000,
61 .step = 6250,
62};
63
63063bfb 64static const struct sec_voltage_desc buck_voltage_val2 = {
9767ec7f
SK		 65 .max = 1600000,
66 .min = 600000,
67 .step = 6250,
68};
69
63063bfb 70static const struct sec_voltage_desc buck_voltage_val3 = {
9767ec7f
SK		 71 .max = 3000000,
72 .min = 750000,
73 .step = 12500,
74};
75
63063bfb 76static const struct sec_voltage_desc ldo_voltage_val1 = {
9767ec7f
SK		 77 .max = 3950000,
78 .min = 800000,
79 .step = 50000,
80};
81
63063bfb 82static const struct sec_voltage_desc ldo_voltage_val2 = {
9767ec7f
SK		 83 .max = 2375000,
84 .min = 800000,
85 .step = 25000,
86};
87
63063bfb 88static const struct sec_voltage_desc *reg_voltage_map[] = {
9767ec7f
SK		 89 [S5M8767_LDO1] = &ldo_voltage_val2,
90 [S5M8767_LDO2] = &ldo_voltage_val2,
91 [S5M8767_LDO3] = &ldo_voltage_val1,
92 [S5M8767_LDO4] = &ldo_voltage_val1,
93 [S5M8767_LDO5] = &ldo_voltage_val1,
94 [S5M8767_LDO6] = &ldo_voltage_val2,
95 [S5M8767_LDO7] = &ldo_voltage_val2,
96 [S5M8767_LDO8] = &ldo_voltage_val2,
97 [S5M8767_LDO9] = &ldo_voltage_val1,
98 [S5M8767_LDO10] = &ldo_voltage_val1,
99 [S5M8767_LDO11] = &ldo_voltage_val1,
100 [S5M8767_LDO12] = &ldo_voltage_val1,
101 [S5M8767_LDO13] = &ldo_voltage_val1,
102 [S5M8767_LDO14] = &ldo_voltage_val1,
103 [S5M8767_LDO15] = &ldo_voltage_val2,
104 [S5M8767_LDO16] = &ldo_voltage_val1,
105 [S5M8767_LDO17] = &ldo_voltage_val1,
106 [S5M8767_LDO18] = &ldo_voltage_val1,
107 [S5M8767_LDO19] = &ldo_voltage_val1,
108 [S5M8767_LDO20] = &ldo_voltage_val1,
109 [S5M8767_LDO21] = &ldo_voltage_val1,
110 [S5M8767_LDO22] = &ldo_voltage_val1,
111 [S5M8767_LDO23] = &ldo_voltage_val1,
112 [S5M8767_LDO24] = &ldo_voltage_val1,
113 [S5M8767_LDO25] = &ldo_voltage_val1,
114 [S5M8767_LDO26] = &ldo_voltage_val1,
115 [S5M8767_LDO27] = &ldo_voltage_val1,
116 [S5M8767_LDO28] = &ldo_voltage_val1,
117 [S5M8767_BUCK1] = &buck_voltage_val1,
118 [S5M8767_BUCK2] = &buck_voltage_val2,
119 [S5M8767_BUCK3] = &buck_voltage_val2,
120 [S5M8767_BUCK4] = &buck_voltage_val2,
121 [S5M8767_BUCK5] = &buck_voltage_val1,
122 [S5M8767_BUCK6] = &buck_voltage_val1,
123 [S5M8767_BUCK7] = NULL,
124 [S5M8767_BUCK8] = NULL,
125 [S5M8767_BUCK9] = &buck_voltage_val3,
126};
127
5ceba7ba 128static unsigned int s5m8767_opmode_reg[][4] = {
7e44bb83
SK		 129 /* {OFF, ON, LOWPOWER, SUSPEND} */
130 /* LDO1 ... LDO28 */
131 {0x0, 0x3, 0x2, 0x1}, /* LDO1 */
132 {0x0, 0x3, 0x2, 0x1},
133 {0x0, 0x3, 0x2, 0x1},
134 {0x0, 0x0, 0x0, 0x0},
135 {0x0, 0x3, 0x2, 0x1}, /* LDO5 */
136 {0x0, 0x3, 0x2, 0x1},
137 {0x0, 0x3, 0x2, 0x1},
138 {0x0, 0x3, 0x2, 0x1},
139 {0x0, 0x3, 0x2, 0x1},
140 {0x0, 0x3, 0x2, 0x1}, /* LDO10 */
141 {0x0, 0x3, 0x2, 0x1},
142 {0x0, 0x3, 0x2, 0x1},
143 {0x0, 0x3, 0x2, 0x1},
144 {0x0, 0x3, 0x2, 0x1},
145 {0x0, 0x3, 0x2, 0x1}, /* LDO15 */
146 {0x0, 0x3, 0x2, 0x1},
147 {0x0, 0x3, 0x2, 0x1},
148 {0x0, 0x0, 0x0, 0x0},
149 {0x0, 0x3, 0x2, 0x1},
150 {0x0, 0x3, 0x2, 0x1}, /* LDO20 */
151 {0x0, 0x3, 0x2, 0x1},
152 {0x0, 0x3, 0x2, 0x1},
153 {0x0, 0x0, 0x0, 0x0},
154 {0x0, 0x3, 0x2, 0x1},
155 {0x0, 0x3, 0x2, 0x1}, /* LDO25 */
156 {0x0, 0x3, 0x2, 0x1},
157 {0x0, 0x3, 0x2, 0x1},
158 {0x0, 0x3, 0x2, 0x1}, /* LDO28 */
159
160 /* BUCK1 ... BUCK9 */
161 {0x0, 0x3, 0x1, 0x1}, /* BUCK1 */
162 {0x0, 0x3, 0x1, 0x1},
163 {0x0, 0x3, 0x1, 0x1},
164 {0x0, 0x3, 0x1, 0x1},
165 {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */
166 {0x0, 0x3, 0x1, 0x1},
167 {0x0, 0x3, 0x1, 0x1},
168 {0x0, 0x3, 0x1, 0x1},
169 {0x0, 0x3, 0x1, 0x1}, /* BUCK9 */
170};
171
172static int s5m8767_get_register(struct regulator_dev *rdev, int *reg,
173 int *enable_ctrl)
9767ec7f 174{
9bb096ff 175 int i, reg_id = rdev_get_id(rdev);
7e44bb83
SK		 176 unsigned int mode;
177 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
9767ec7f
SK		 178
179 switch (reg_id) {
180 case S5M8767_LDO1 ... S5M8767_LDO2:
181 *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
182 break;
183 case S5M8767_LDO3 ... S5M8767_LDO28:
184 *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
185 break;
186 case S5M8767_BUCK1:
187 *reg = S5M8767_REG_BUCK1CTRL1;
188 break;
189 case S5M8767_BUCK2 ... S5M8767_BUCK4:
190 *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9;
191 break;
192 case S5M8767_BUCK5:
193 *reg = S5M8767_REG_BUCK5CTRL1;
194 break;
195 case S5M8767_BUCK6 ... S5M8767_BUCK9:
196 *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2;
197 break;
198 default:
199 return -EINVAL;
200 }
201
9bb096ff
ADK		 202 for (i = 0; i < s5m8767->num_regulators; i++) {
203 if (s5m8767->opmode[i].id == reg_id) {
204 mode = s5m8767->opmode[i].mode;
205 break;
206 }
207 }
208
209 if (i < s5m8767->num_regulators)
210 *enable_ctrl =
211 s5m8767_opmode_reg[reg_id][mode] << S5M8767_ENCTRL_SHIFT;
212
9767ec7f
SK		 213 return 0;
214}
215
216static int s5m8767_reg_is_enabled(struct regulator_dev *rdev)
217{
218 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
219 int ret, reg;
7e44bb83 220 int mask = 0xc0, enable_ctrl;
3ef30398 221 unsigned int val;
9767ec7f 222
7e44bb83 223 ret = s5m8767_get_register(rdev, &reg, &enable_ctrl);
9767ec7f
SK		 224 if (ret == -EINVAL)
225 return 1;
226 else if (ret)
227 return ret;
228
63063bfb 229 ret = sec_reg_read(s5m8767->iodev, reg, &val);
9767ec7f
SK		 230 if (ret)
231 return ret;
232
7e44bb83 233 return (val & mask) == enable_ctrl;
9767ec7f
SK		 234}
235
236static int s5m8767_reg_enable(struct regulator_dev *rdev)
237{
238 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
239 int ret, reg;
7e44bb83 240 int mask = 0xc0, enable_ctrl;
9767ec7f 241
7e44bb83 242 ret = s5m8767_get_register(rdev, &reg, &enable_ctrl);
9767ec7f
SK		 243 if (ret)
244 return ret;
245
63063bfb 246 return sec_reg_update(s5m8767->iodev, reg, enable_ctrl, mask);
9767ec7f
SK		 247}
248
249static int s5m8767_reg_disable(struct regulator_dev *rdev)
250{
251 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
252 int ret, reg;
7e44bb83 253 int mask = 0xc0, enable_ctrl;
9767ec7f 254
7e44bb83 255 ret = s5m8767_get_register(rdev, &reg, &enable_ctrl);
9767ec7f
SK		 256 if (ret)
257 return ret;
258
63063bfb 259 return sec_reg_update(s5m8767->iodev, reg, ~mask, mask);
9767ec7f
SK		 260}
261
31a932e1 262static int s5m8767_get_vsel_reg(int reg_id, struct s5m8767_info *s5m8767)
9767ec7f 263{
9767ec7f
SK		 264 int reg;
265
266 switch (reg_id) {
267 case S5M8767_LDO1 ... S5M8767_LDO2:
268 reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
269 break;
270 case S5M8767_LDO3 ... S5M8767_LDO28:
271 reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
272 break;
273 case S5M8767_BUCK1:
274 reg = S5M8767_REG_BUCK1CTRL2;
275 break;
276 case S5M8767_BUCK2:
da130ab2 277 reg = S5M8767_REG_BUCK2DVS1;
0a41685f
AL		 278 if (s5m8767->buck2_gpiodvs)
279 reg += s5m8767->buck_gpioindex;
9767ec7f
SK		 280 break;
281 case S5M8767_BUCK3:
da130ab2 282 reg = S5M8767_REG_BUCK3DVS1;
0a41685f
AL		 283 if (s5m8767->buck3_gpiodvs)
284 reg += s5m8767->buck_gpioindex;
9767ec7f
SK		 285 break;
286 case S5M8767_BUCK4:
da130ab2 287 reg = S5M8767_REG_BUCK4DVS1;
0a41685f
AL		 288 if (s5m8767->buck4_gpiodvs)
289 reg += s5m8767->buck_gpioindex;
9767ec7f
SK		 290 break;
291 case S5M8767_BUCK5:
292 reg = S5M8767_REG_BUCK5CTRL2;
293 break;
294 case S5M8767_BUCK6 ... S5M8767_BUCK9:
295 reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2;
296 break;
297 default:
298 return -EINVAL;
299 }
300
31a932e1 301 return reg;
9767ec7f
SK		 302}
303
854f73ec
AL		 304static int s5m8767_convert_voltage_to_sel(const struct sec_voltage_desc *desc,
305 int min_vol)
9767ec7f 306{
5b5e977c 307 int selector = 0;
9767ec7f
SK		 308
309 if (desc == NULL)
310 return -EINVAL;
311
854f73ec 312 if (min_vol > desc->max)
9767ec7f
SK		 313 return -EINVAL;
314
94e85a3c
AL		 315 if (min_vol < desc->min)
316 min_vol = desc->min;
317
318 selector = DIV_ROUND_UP(min_vol - desc->min, desc->step);
9767ec7f 319
854f73ec 320 if (desc->min + desc->step * selector > desc->max)
9767ec7f
SK		 321 return -EINVAL;
322
5b5e977c 323 return selector;
9767ec7f
SK		 324}
325
df2643cf 326static inline int s5m8767_set_high(struct s5m8767_info *s5m8767)
321d2aba
AL		 327{
328 int temp_index = s5m8767->buck_gpioindex;
329
330 gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
331 gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
332 gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
df2643cf
SK		 333
334 return 0;
321d2aba
AL		 335}
336
df2643cf 337static inline int s5m8767_set_low(struct s5m8767_info *s5m8767)
321d2aba
AL		 338{
339 int temp_index = s5m8767->buck_gpioindex;
340
341 gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
342 gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
343 gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
df2643cf
SK		 344
345 return 0;
321d2aba
AL		 346}
347
df2643cf
SK		 348static int s5m8767_set_voltage_sel(struct regulator_dev *rdev,
349 unsigned selector)
9767ec7f
SK		 350{
351 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
20a14b84 352 int reg_id = rdev_get_id(rdev);
31a932e1 353 int old_index, index = 0;
321d2aba 354 u8 *buck234_vol = NULL;
9767ec7f
SK		 355
356 switch (reg_id) {
357 case S5M8767_LDO1 ... S5M8767_LDO28:
9767ec7f
SK		 358 break;
359 case S5M8767_BUCK1 ... S5M8767_BUCK6:
321d2aba
AL		 360 if (reg_id == S5M8767_BUCK2 && s5m8767->buck2_gpiodvs)
361 buck234_vol = &s5m8767->buck2_vol[0];
362 else if (reg_id == S5M8767_BUCK3 && s5m8767->buck3_gpiodvs)
363 buck234_vol = &s5m8767->buck3_vol[0];
364 else if (reg_id == S5M8767_BUCK4 && s5m8767->buck4_gpiodvs)
365 buck234_vol = &s5m8767->buck4_vol[0];
9767ec7f
SK		 366 break;
367 case S5M8767_BUCK7 ... S5M8767_BUCK8:
368 return -EINVAL;
369 case S5M8767_BUCK9:
9767ec7f
SK		 370 break;
371 default:
372 return -EINVAL;
373 }
374
321d2aba
AL		 375 /* buck234_vol != NULL means to control buck234 voltage via DVS GPIO */
376 if (buck234_vol) {
df2643cf 377 while (*buck234_vol != selector) {
321d2aba
AL		 378 buck234_vol++;
379 index++;
380 }
381 old_index = s5m8767->buck_gpioindex;
382 s5m8767->buck_gpioindex = index;
383
384 if (index > old_index)
df2643cf 385 return s5m8767_set_high(s5m8767);
321d2aba 386 else
df2643cf 387 return s5m8767_set_low(s5m8767);
321d2aba 388 } else {
31a932e1 389 return regulator_set_voltage_sel_regmap(rdev, selector);
321d2aba 390 }
9767ec7f
SK		 391}
392
9767ec7f
SK		 393static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev,
394 unsigned int old_sel,
395 unsigned int new_sel)
396{
397 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
63063bfb 398 const struct sec_voltage_desc *desc;
20a14b84 399 int reg_id = rdev_get_id(rdev);
9767ec7f 400
9767ec7f
SK		 401 desc = reg_voltage_map[reg_id];
402
9d88fc0b 403 if ((old_sel < new_sel) && s5m8767->ramp_delay)
89e0f0e4 404 return DIV_ROUND_UP(desc->step * (new_sel - old_sel),
0f8b9c77 405 s5m8767->ramp_delay * 1000);
89e0f0e4 406 return 0;
9767ec7f
SK		 407}
408
d35aad0c 409static struct regulator_ops s5m8767_ops = {
e2eb169b 410 .list_voltage = regulator_list_voltage_linear,
9767ec7f
SK		 411 .is_enabled = s5m8767_reg_is_enabled,
412 .enable = s5m8767_reg_enable,
413 .disable = s5m8767_reg_disable,
31a932e1 414 .get_voltage_sel = regulator_get_voltage_sel_regmap,
df2643cf 415 .set_voltage_sel = s5m8767_set_voltage_sel,
9767ec7f
SK		 416 .set_voltage_time_sel = s5m8767_set_voltage_time_sel,
417};
418
e2eb169b
AL		 419static struct regulator_ops s5m8767_buck78_ops = {
420 .is_enabled = s5m8767_reg_is_enabled,
421 .enable = s5m8767_reg_enable,
422 .disable = s5m8767_reg_disable,
423};
424
65896e73
AL		 425#define s5m8767_regulator_desc(_name) { \
426 .name = #_name, \
427 .id = S5M8767_##_name, \
428 .ops = &s5m8767_ops, \
9767ec7f
SK		 429 .type = REGULATOR_VOLTAGE, \
430 .owner = THIS_MODULE, \
431}
432
e2eb169b
AL		 433#define s5m8767_regulator_buck78_desc(_name) { \
434 .name = #_name, \
435 .id = S5M8767_##_name, \
436 .ops = &s5m8767_buck78_ops, \
437 .type = REGULATOR_VOLTAGE, \
438 .owner = THIS_MODULE, \
439}
440
9767ec7f 441static struct regulator_desc regulators[] = {
65896e73
AL		 442 s5m8767_regulator_desc(LDO1),
443 s5m8767_regulator_desc(LDO2),
444 s5m8767_regulator_desc(LDO3),
445 s5m8767_regulator_desc(LDO4),
446 s5m8767_regulator_desc(LDO5),
447 s5m8767_regulator_desc(LDO6),
448 s5m8767_regulator_desc(LDO7),
449 s5m8767_regulator_desc(LDO8),
450 s5m8767_regulator_desc(LDO9),
451 s5m8767_regulator_desc(LDO10),
452 s5m8767_regulator_desc(LDO11),
453 s5m8767_regulator_desc(LDO12),
454 s5m8767_regulator_desc(LDO13),
455 s5m8767_regulator_desc(LDO14),
456 s5m8767_regulator_desc(LDO15),
457 s5m8767_regulator_desc(LDO16),
458 s5m8767_regulator_desc(LDO17),
459 s5m8767_regulator_desc(LDO18),
460 s5m8767_regulator_desc(LDO19),
461 s5m8767_regulator_desc(LDO20),
462 s5m8767_regulator_desc(LDO21),
463 s5m8767_regulator_desc(LDO22),
464 s5m8767_regulator_desc(LDO23),
465 s5m8767_regulator_desc(LDO24),
466 s5m8767_regulator_desc(LDO25),
467 s5m8767_regulator_desc(LDO26),
468 s5m8767_regulator_desc(LDO27),
469 s5m8767_regulator_desc(LDO28),
470 s5m8767_regulator_desc(BUCK1),
471 s5m8767_regulator_desc(BUCK2),
472 s5m8767_regulator_desc(BUCK3),
473 s5m8767_regulator_desc(BUCK4),
474 s5m8767_regulator_desc(BUCK5),
475 s5m8767_regulator_desc(BUCK6),
e2eb169b
AL		 476 s5m8767_regulator_buck78_desc(BUCK7),
477 s5m8767_regulator_buck78_desc(BUCK8),
65896e73 478 s5m8767_regulator_desc(BUCK9),
9767ec7f
SK		 479};
480
26aec009
ADK		 481#ifdef CONFIG_OF
482static int s5m8767_pmic_dt_parse_dvs_gpio(struct sec_pmic_dev *iodev,
483 struct sec_platform_data *pdata,
484 struct device_node *pmic_np)
485{
486 int i, gpio;
487
488 for (i = 0; i < 3; i++) {
489 gpio = of_get_named_gpio(pmic_np,
490 "s5m8767,pmic-buck-dvs-gpios", i);
491 if (!gpio_is_valid(gpio)) {
492 dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
493 return -EINVAL;
494 }
495 pdata->buck_gpios[i] = gpio;
496 }
497 return 0;
498}
499
500static int s5m8767_pmic_dt_parse_ds_gpio(struct sec_pmic_dev *iodev,
501 struct sec_platform_data *pdata,
502 struct device_node *pmic_np)
503{
504 int i, gpio;
505
506 for (i = 0; i < 3; i++) {
507 gpio = of_get_named_gpio(pmic_np,
508 "s5m8767,pmic-buck-ds-gpios", i);
509 if (!gpio_is_valid(gpio)) {
510 dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
511 return -EINVAL;
512 }
513 pdata->buck_ds[i] = gpio;
514 }
515 return 0;
516}
517
cbb0ed49 518static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
26aec009
ADK		 519 struct sec_platform_data *pdata)
520{
cbb0ed49 521 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
26aec009
ADK		 522 struct device_node *pmic_np, *regulators_np, *reg_np;
523 struct sec_regulator_data *rdata;
524 struct sec_opmode_data *rmode;
525 unsigned int i, dvs_voltage_nr = 1, ret;
526
527 pmic_np = iodev->dev->of_node;
528 if (!pmic_np) {
529 dev_err(iodev->dev, "could not find pmic sub-node\n");
530 return -ENODEV;
531 }
532
533 regulators_np = of_find_node_by_name(pmic_np, "regulators");
534 if (!regulators_np) {
535 dev_err(iodev->dev, "could not find regulators sub-node\n");
536 return -EINVAL;
537 }
538
539 /* count the number of regulators to be supported in pmic */
1f91b6f6 540 pdata->num_regulators = of_get_child_count(regulators_np);
26aec009 541
cbb0ed49 542 rdata = devm_kzalloc(&pdev->dev, sizeof(*rdata) *
26aec009
ADK		 543 pdata->num_regulators, GFP_KERNEL);
544 if (!rdata) {
545 dev_err(iodev->dev,
546 "could not allocate memory for regulator data\n");
547 return -ENOMEM;
548 }
549
cbb0ed49 550 rmode = devm_kzalloc(&pdev->dev, sizeof(*rmode) *
26aec009 551 pdata->num_regulators, GFP_KERNEL);
720a9717 552 if (!rmode) {
26aec009
ADK		 553 dev_err(iodev->dev,
554 "could not allocate memory for regulator mode\n");
555 return -ENOMEM;
556 }
557
558 pdata->regulators = rdata;
559 pdata->opmode = rmode;
560 for_each_child_of_node(regulators_np, reg_np) {
561 for (i = 0; i < ARRAY_SIZE(regulators); i++)
562 if (!of_node_cmp(reg_np->name, regulators[i].name))
563 break;
564
565 if (i == ARRAY_SIZE(regulators)) {
566 dev_warn(iodev->dev,
567 "don't know how to configure regulator %s\n",
568 reg_np->name);
569 continue;
570 }
571
572 rdata->id = i;
573 rdata->initdata = of_get_regulator_init_data(
cbb0ed49 574 &pdev->dev, reg_np);
26aec009
ADK		 575 rdata->reg_node = reg_np;
576 rdata++;
577 rmode->id = i;
578 if (of_property_read_u32(reg_np, "op_mode",
579 &rmode->mode)) {
580 dev_warn(iodev->dev,
581 "no op_mode property property at %s\n",
582 reg_np->full_name);
583
584 rmode->mode = S5M8767_OPMODE_NORMAL_MODE;
585 }
586 rmode++;
587 }
588
589 if (of_get_property(pmic_np, "s5m8767,pmic-buck2-uses-gpio-dvs", NULL))
590 pdata->buck2_gpiodvs = true;
591
592 if (of_get_property(pmic_np, "s5m8767,pmic-buck3-uses-gpio-dvs", NULL))
593 pdata->buck3_gpiodvs = true;
594
595 if (of_get_property(pmic_np, "s5m8767,pmic-buck4-uses-gpio-dvs", NULL))
596 pdata->buck4_gpiodvs = true;
597
598 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
599 pdata->buck4_gpiodvs) {
600 ret = s5m8767_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np);
601 if (ret)
602 return -EINVAL;
603
604 if (of_property_read_u32(pmic_np,
605 "s5m8767,pmic-buck-default-dvs-idx",
606 &pdata->buck_default_idx)) {
607 pdata->buck_default_idx = 0;
608 } else {
609 if (pdata->buck_default_idx >= 8) {
610 pdata->buck_default_idx = 0;
611 dev_info(iodev->dev,
612 "invalid value for default dvs index, use 0\n");
613 }
614 }
615 dvs_voltage_nr = 8;
616 }
617
618 ret = s5m8767_pmic_dt_parse_ds_gpio(iodev, pdata, pmic_np);
619 if (ret)
620 return -EINVAL;
621
622 if (of_property_read_u32_array(pmic_np,
623 "s5m8767,pmic-buck2-dvs-voltage",
624 pdata->buck2_voltage, dvs_voltage_nr)) {
625 dev_err(iodev->dev, "buck2 voltages not specified\n");
626 return -EINVAL;
627 }
628
629 if (of_property_read_u32_array(pmic_np,
630 "s5m8767,pmic-buck3-dvs-voltage",
631 pdata->buck3_voltage, dvs_voltage_nr)) {
632 dev_err(iodev->dev, "buck3 voltages not specified\n");
633 return -EINVAL;
634 }
635
636 if (of_property_read_u32_array(pmic_np,
637 "s5m8767,pmic-buck4-dvs-voltage",
638 pdata->buck4_voltage, dvs_voltage_nr)) {
639 dev_err(iodev->dev, "buck4 voltages not specified\n");
640 return -EINVAL;
641 }
642
643 return 0;
644}
645#else
cbb0ed49 646static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
26aec009
ADK		 647 struct sec_platform_data *pdata)
648{
649 return 0;
650}
651#endif /* CONFIG_OF */
652
a5023574 653static int s5m8767_pmic_probe(struct platform_device *pdev)
9767ec7f 654{
63063bfb 655 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
26aec009 656 struct sec_platform_data *pdata = iodev->pdata;
c172708d 657 struct regulator_config config = { };
9767ec7f
SK		 658 struct regulator_dev **rdev;
659 struct s5m8767_info *s5m8767;
c848bc85 660 int i, ret, size, buck_init;
9767ec7f 661
e81d7bc8
AL		 662 if (!pdata) {
663 dev_err(pdev->dev.parent, "Platform data not supplied\n");
664 return -ENODEV;
665 }
666
26aec009 667 if (iodev->dev->of_node) {
cbb0ed49 668 ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata);
26aec009
ADK		 669 if (ret)
670 return ret;
671 }
672
6c4efe24
AL		 673 if (pdata->buck2_gpiodvs) {
674 if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) {
675 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
676 return -EINVAL;
677 }
678 }
679
680 if (pdata->buck3_gpiodvs) {
681 if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) {
682 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
683 return -EINVAL;
684 }
685 }
686
687 if (pdata->buck4_gpiodvs) {
688 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) {
689 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
690 return -EINVAL;
691 }
692 }
693
9767ec7f
SK		 694 s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info),
695 GFP_KERNEL);
696 if (!s5m8767)
697 return -ENOMEM;
698
699 size = sizeof(struct regulator_dev *) * (S5M8767_REG_MAX - 2);
700 s5m8767->rdev = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
701 if (!s5m8767->rdev)
702 return -ENOMEM;
703
704 rdev = s5m8767->rdev;
705 s5m8767->dev = &pdev->dev;
706 s5m8767->iodev = iodev;
9bb096ff 707 s5m8767->num_regulators = pdata->num_regulators;
9767ec7f 708 platform_set_drvdata(pdev, s5m8767);
9767ec7f
SK		 709
710 s5m8767->buck_gpioindex = pdata->buck_default_idx;
711 s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs;
712 s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs;
713 s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs;
714 s5m8767->buck_gpios[0] = pdata->buck_gpios[0];
715 s5m8767->buck_gpios[1] = pdata->buck_gpios[1];
716 s5m8767->buck_gpios[2] = pdata->buck_gpios[2];
c848bc85
SK		 717 s5m8767->buck_ds[0] = pdata->buck_ds[0];
718 s5m8767->buck_ds[1] = pdata->buck_ds[1];
719 s5m8767->buck_ds[2] = pdata->buck_ds[2];
720
9767ec7f
SK		 721 s5m8767->ramp_delay = pdata->buck_ramp_delay;
722 s5m8767->buck2_ramp = pdata->buck2_ramp_enable;
723 s5m8767->buck3_ramp = pdata->buck3_ramp_enable;
724 s5m8767->buck4_ramp = pdata->buck4_ramp_enable;
7e44bb83 725 s5m8767->opmode = pdata->opmode;
9767ec7f 726
c848bc85 727 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 728 pdata->buck2_init);
c848bc85 729
938e05bf 730 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK2DVS2, buck_init);
c848bc85
SK		 731
732 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 733 pdata->buck3_init);
c848bc85 734
938e05bf 735 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK3DVS2, buck_init);
c848bc85
SK		 736
737 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 738 pdata->buck4_init);
c848bc85 739
938e05bf 740 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK4DVS2, buck_init);
c848bc85 741
9767ec7f
SK		 742 for (i = 0; i < 8; i++) {
743 if (s5m8767->buck2_gpiodvs) {
744 s5m8767->buck2_vol[i] =
5b5e977c 745 s5m8767_convert_voltage_to_sel(
9767ec7f 746 &buck_voltage_val2,
854f73ec 747 pdata->buck2_voltage[i]);
9767ec7f
SK		 748 }
749
750 if (s5m8767->buck3_gpiodvs) {
751 s5m8767->buck3_vol[i] =
5b5e977c 752 s5m8767_convert_voltage_to_sel(
9767ec7f 753 &buck_voltage_val2,
854f73ec 754 pdata->buck3_voltage[i]);
9767ec7f
SK		 755 }
756
757 if (s5m8767->buck4_gpiodvs) {
758 s5m8767->buck4_vol[i] =
5b5e977c 759 s5m8767_convert_voltage_to_sel(
9767ec7f 760 &buck_voltage_val2,
854f73ec 761 pdata->buck4_voltage[i]);
9767ec7f
SK		 762 }
763 }
764
76c854d1
ADK		 765 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
766 pdata->buck4_gpiodvs) {
767
768 if (!gpio_is_valid(pdata->buck_gpios[0]) ||
769 !gpio_is_valid(pdata->buck_gpios[1]) ||
770 !gpio_is_valid(pdata->buck_gpios[2])) {
771 dev_err(&pdev->dev, "GPIO NOT VALID\n");
772 return -EINVAL;
773 }
774
5febb3c9
AL		 775 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[0],
776 "S5M8767 SET1");
777 if (ret)
778 return ret;
779
780 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[1],
781 "S5M8767 SET2");
782 if (ret)
783 return ret;
784
785 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[2],
786 "S5M8767 SET3");
787 if (ret)
788 return ret;
789
c848bc85
SK		 790 /* SET1 GPIO */
791 gpio_direction_output(pdata->buck_gpios[0],
792 (s5m8767->buck_gpioindex >> 2) & 0x1);
793 /* SET2 GPIO */
794 gpio_direction_output(pdata->buck_gpios[1],
795 (s5m8767->buck_gpioindex >> 1) & 0x1);
796 /* SET3 GPIO */
797 gpio_direction_output(pdata->buck_gpios[2],
798 (s5m8767->buck_gpioindex >> 0) & 0x1);
9767ec7f
SK		 799 }
800
5febb3c9
AL		 801 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[0], "S5M8767 DS2");
802 if (ret)
803 return ret;
c848bc85 804
5febb3c9
AL		 805 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[1], "S5M8767 DS3");
806 if (ret)
807 return ret;
c848bc85 808
5febb3c9
AL		 809 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[2], "S5M8767 DS4");
810 if (ret)
811 return ret;
c848bc85
SK		 812
813 /* DS2 GPIO */
814 gpio_direction_output(pdata->buck_ds[0], 0x0);
815 /* DS3 GPIO */
816 gpio_direction_output(pdata->buck_ds[1], 0x0);
817 /* DS4 GPIO */
818 gpio_direction_output(pdata->buck_ds[2], 0x0);
819
820 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
821 pdata->buck4_gpiodvs) {
3e701cdf 822 sec_reg_update(s5m8767->iodev, S5M8767_REG_BUCK2CTRL,
c848bc85
SK		 823 (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1),
824 1 << 1);
3e701cdf 825 sec_reg_update(s5m8767->iodev, S5M8767_REG_BUCK3CTRL,
c848bc85
SK		 826 (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1),
827 1 << 1);
3e701cdf 828 sec_reg_update(s5m8767->iodev, S5M8767_REG_BUCK4CTRL,
c848bc85
SK		 829 (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1),
830 1 << 1);
831 }
9767ec7f
SK		 832
833 /* Initialize GPIO DVS registers */
834 for (i = 0; i < 8; i++) {
835 if (s5m8767->buck2_gpiodvs) {
63063bfb 836 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK2DVS1 + i,
9767ec7f
SK		 837 s5m8767->buck2_vol[i]);
838 }
839
840 if (s5m8767->buck3_gpiodvs) {
63063bfb 841 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK3DVS1 + i,
9767ec7f
SK		 842 s5m8767->buck3_vol[i]);
843 }
844
845 if (s5m8767->buck4_gpiodvs) {
63063bfb 846 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK4DVS1 + i,
9767ec7f
SK		 847 s5m8767->buck4_vol[i]);
848 }
849 }
9767ec7f
SK		 850
851 if (s5m8767->buck2_ramp)
63063bfb 852 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x08, 0x08);
9767ec7f
SK		 853
854 if (s5m8767->buck3_ramp)
63063bfb 855 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x04, 0x04);
9767ec7f
SK		 856
857 if (s5m8767->buck4_ramp)
63063bfb 858 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x02, 0x02);
9767ec7f
SK		 859
860 if (s5m8767->buck2_ramp || s5m8767->buck3_ramp
861 || s5m8767->buck4_ramp) {
862 switch (s5m8767->ramp_delay) {
1af142c6 863 case 5:
63063bfb 864 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
1af142c6
SK		 865 0x40, 0xf0);
866 break;
867 case 10:
3e701cdf 868 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
1af142c6 869 0x90, 0xf0);
047ec220 870 break;
9767ec7f 871 case 25:
63063bfb 872 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
9767ec7f 873 0xd0, 0xf0);
047ec220 874 break;
9767ec7f 875 case 50:
63063bfb 876 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
9767ec7f 877 0xe0, 0xf0);
047ec220 878 break;
9767ec7f 879 case 100:
63063bfb 880 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
9767ec7f 881 0xf0, 0xf0);
047ec220 882 break;
9767ec7f 883 default:
63063bfb 884 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
9767ec7f
SK		 885 0x90, 0xf0);
886 }
887 }
888
889 for (i = 0; i < pdata->num_regulators; i++) {
63063bfb 890 const struct sec_voltage_desc *desc;
9767ec7f
SK		 891 int id = pdata->regulators[i].id;
892
893 desc = reg_voltage_map[id];
e2eb169b 894 if (desc) {
9767ec7f
SK		 895 regulators[id].n_voltages =
896 (desc->max - desc->min) / desc->step + 1;
e2eb169b
AL		 897 regulators[id].min_uV = desc->min;
898 regulators[id].uV_step = desc->step;
31a932e1
AL		 899 regulators[id].vsel_reg =
900 s5m8767_get_vsel_reg(id, s5m8767);
901 if (id < S5M8767_BUCK1)
902 regulators[id].vsel_mask = 0x3f;
903 else
904 regulators[id].vsel_mask = 0xff;
e2eb169b 905 }
9767ec7f 906
c172708d
MB		 907 config.dev = s5m8767->dev;
908 config.init_data = pdata->regulators[i].initdata;
909 config.driver_data = s5m8767;
31a932e1 910 config.regmap = iodev->regmap;
26aec009 911 config.of_node = pdata->regulators[i].reg_node;
c172708d
MB		 912
913 rdev[i] = regulator_register(&regulators[id], &config);
9767ec7f
SK		 914 if (IS_ERR(rdev[i])) {
915 ret = PTR_ERR(rdev[i]);
916 dev_err(s5m8767->dev, "regulator init failed for %d\n",
917 id);
918 rdev[i] = NULL;
919 goto err;
920 }
921 }
922
923 return 0;
924err:
925 for (i = 0; i < s5m8767->num_regulators; i++)
020501f1 926 regulator_unregister(rdev[i]);
9767ec7f
SK		 927
928 return ret;
929}
930
8dc995f5 931static int s5m8767_pmic_remove(struct platform_device *pdev)
9767ec7f
SK		 932{
933 struct s5m8767_info *s5m8767 = platform_get_drvdata(pdev);
934 struct regulator_dev **rdev = s5m8767->rdev;
935 int i;
936
937 for (i = 0; i < s5m8767->num_regulators; i++)
020501f1 938 regulator_unregister(rdev[i]);
9767ec7f
SK		 939
940 return 0;
941}
942
943static const struct platform_device_id s5m8767_pmic_id[] = {
944 { "s5m8767-pmic", 0},
945 { },
946};
947MODULE_DEVICE_TABLE(platform, s5m8767_pmic_id);
948
949static struct platform_driver s5m8767_pmic_driver = {
950 .driver = {
951 .name = "s5m8767-pmic",
952 .owner = THIS_MODULE,
953 },
954 .probe = s5m8767_pmic_probe,
5eb9f2b9 955 .remove = s5m8767_pmic_remove,
9767ec7f
SK		 956 .id_table = s5m8767_pmic_id,
957};
958
959static int __init s5m8767_pmic_init(void)
960{
961 return platform_driver_register(&s5m8767_pmic_driver);
962}
963subsys_initcall(s5m8767_pmic_init);
964
965static void __exit s5m8767_pmic_exit(void)
966{
967 platform_driver_unregister(&s5m8767_pmic_driver);
968}
969module_exit(s5m8767_pmic_exit);
970
971/* Module information */
972MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
973MODULE_DESCRIPTION("SAMSUNG S5M8767 Regulator Driver");
974MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)