Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pwm / pwm-pxa.c
CommitLineData
75540c1a 1/*
45b301d2 2 * drivers/pwm/pwm-pxa.c
75540c1a 3 *
4 * simple driver for PWM (Pulse Width Modulator) controller
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * 2008-02-13 initial version
11 * eric miao <eric.miao@marvell.com>
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
5a0e3ad6 17#include <linux/slab.h>
75540c1a 18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21#include <linux/pwm.h>
22
23#include <asm/div64.h>
75540c1a 24
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25#define HAS_SECONDARY_PWM 0x10
26
27static const struct platform_device_id pwm_id_table[] = {
28 /* PWM has_secondary_pwm? */
29 { "pxa25x-pwm", 0 },
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30 { "pxa27x-pwm", HAS_SECONDARY_PWM },
31 { "pxa168-pwm", 0 },
32 { "pxa910-pwm", 0 },
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EM
33 { },
34};
35MODULE_DEVICE_TABLE(platform, pwm_id_table);
36
75540c1a 37/* PWM registers and bits definitions */
38#define PWMCR (0x00)
39#define PWMDCR (0x04)
40#define PWMPCR (0x08)
41
42#define PWMCR_SD (1 << 6)
43#define PWMDCR_FD (1 << 10)
44
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TR
45struct pxa_pwm_chip {
46 struct pwm_chip chip;
47 struct device *dev;
75540c1a 48
75540c1a 49 struct clk *clk;
50 void __iomem *mmio_base;
75540c1a 51};
52
17b2b478
TR
53static inline struct pxa_pwm_chip *to_pxa_pwm_chip(struct pwm_chip *chip)
54{
55 return container_of(chip, struct pxa_pwm_chip, chip);
56}
57
75540c1a 58/*
59 * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
60 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
61 */
17b2b478
TR
62static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
63 int duty_ns, int period_ns)
75540c1a 64{
17b2b478 65 struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
75540c1a 66 unsigned long long c;
67 unsigned long period_cycles, prescale, pv, dc;
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TR
68 unsigned long offset;
69 int rc;
75540c1a 70
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71 offset = pwm->hwpwm ? 0x10 : 0;
72
73 c = clk_get_rate(pc->clk);
75540c1a 74 c = c * period_ns;
75 do_div(c, 1000000000);
76 period_cycles = c;
77
71a35d75 78 if (period_cycles < 1)
75540c1a 79 period_cycles = 1;
80 prescale = (period_cycles - 1) / 1024;
81 pv = period_cycles / (prescale + 1) - 1;
82
83 if (prescale > 63)
84 return -EINVAL;
85
86 if (duty_ns == period_ns)
87 dc = PWMDCR_FD;
88 else
89 dc = (pv + 1) * duty_ns / period_ns;
90
91 /* NOTE: the clock to PWM has to be enabled first
92 * before writing to the registers
93 */
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94 rc = clk_prepare_enable(pc->clk);
95 if (rc < 0)
96 return rc;
97
98 writel(prescale, pc->mmio_base + offset + PWMCR);
99 writel(dc, pc->mmio_base + offset + PWMDCR);
100 writel(pv, pc->mmio_base + offset + PWMPCR);
75540c1a 101
17b2b478 102 clk_disable_unprepare(pc->clk);
75540c1a 103 return 0;
104}
75540c1a 105
17b2b478 106static int pxa_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
75540c1a 107{
17b2b478 108 struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
c860d701 109
b014a30c 110 return clk_prepare_enable(pc->clk);
75540c1a 111}
75540c1a 112
17b2b478 113static void pxa_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
75540c1a 114{
17b2b478 115 struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
75540c1a 116
b014a30c 117 clk_disable_unprepare(pc->clk);
75540c1a 118}
75540c1a 119
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120static struct pwm_ops pxa_pwm_ops = {
121 .config = pxa_pwm_config,
122 .enable = pxa_pwm_enable,
123 .disable = pxa_pwm_disable,
124 .owner = THIS_MODULE,
125};
75540c1a 126
3e9fe83d 127static int pwm_probe(struct platform_device *pdev)
75540c1a 128{
b3282ab1 129 const struct platform_device_id *id = platform_get_device_id(pdev);
17b2b478 130 struct pxa_pwm_chip *pwm;
75540c1a 131 struct resource *r;
132 int ret = 0;
133
45b301d2 134 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
75540c1a 135 if (pwm == NULL) {
136 dev_err(&pdev->dev, "failed to allocate memory\n");
3d2a98cd 137 return -ENOMEM;
75540c1a 138 }
139
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140 pwm->clk = devm_clk_get(&pdev->dev, NULL);
141 if (IS_ERR(pwm->clk))
142 return PTR_ERR(pwm->clk);
143
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144 pwm->chip.dev = &pdev->dev;
145 pwm->chip.ops = &pxa_pwm_ops;
146 pwm->chip.base = -1;
147 pwm->chip.npwm = (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1;
75540c1a 148
75540c1a 149 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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150 pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r);
151 if (IS_ERR(pwm->mmio_base))
152 return PTR_ERR(pwm->mmio_base);
75540c1a 153
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TR
154 ret = pwmchip_add(&pwm->chip);
155 if (ret < 0) {
156 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
157 return ret;
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EM
158 }
159
75540c1a 160 platform_set_drvdata(pdev, pwm);
3d2a98cd 161 return 0;
75540c1a 162}
163
77f37917 164static int pwm_remove(struct platform_device *pdev)
75540c1a 165{
17b2b478 166 struct pxa_pwm_chip *chip;
75540c1a 167
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168 chip = platform_get_drvdata(pdev);
169 if (chip == NULL)
75540c1a 170 return -ENODEV;
171
abeaf755 172 return pwmchip_remove(&chip->chip);
75540c1a 173}
174
3d2a98cd 175static struct platform_driver pwm_driver = {
75540c1a 176 .driver = {
177 .name = "pxa25x-pwm",
3d2a98cd 178 .owner = THIS_MODULE,
75540c1a 179 },
3d2a98cd 180 .probe = pwm_probe,
fd109112 181 .remove = pwm_remove,
3d2a98cd 182 .id_table = pwm_id_table,
75540c1a 183};
184
185static int __init pwm_init(void)
186{
3d2a98cd 187 return platform_driver_register(&pwm_driver);
75540c1a 188}
189arch_initcall(pwm_init);
190
191static void __exit pwm_exit(void)
192{
3d2a98cd 193 platform_driver_unregister(&pwm_driver);
75540c1a 194}
195module_exit(pwm_exit);
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GL
196
197MODULE_LICENSE("GPL v2");