[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pwm / pwm-mxs.c

/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/stmp_device.h>

#define SET	0x4
#define CLR	0x8
#define TOG	0xc

#define PWM_CTRL		0x0
#define PWM_ACTIVE0		0x10
#define PWM_PERIOD0		0x20
#define  PERIOD_PERIOD(p)	((p) & 0xffff)
#define  PERIOD_PERIOD_MAX	0x10000
#define  PERIOD_ACTIVE_HIGH	(3 << 16)
#define  PERIOD_INACTIVE_LOW	(2 << 18)
#define  PERIOD_CDIV(div)	(((div) & 0x7) << 20)
#define  PERIOD_CDIV_MAX	8

struct mxs_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	void __iomem *base;
};

#define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)

static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			  int duty_ns, int period_ns)
{
	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	int ret, div = 0;
	unsigned int period_cycles, duty_cycles;
	unsigned long rate;
	unsigned long long c;

	rate = clk_get_rate(mxs->clk);
	while (1) {
		c = rate / (1 << div);
		c = c * period_ns;
		do_div(c, 1000000000);
		if (c < PERIOD_PERIOD_MAX)
			break;
		div++;
		if (div > PERIOD_CDIV_MAX)
			return -EINVAL;
	}

	period_cycles = c;
	c *= duty_ns;
	do_div(c, period_ns);
	duty_cycles = c;

	/*
	 * If the PWM channel is disabled, make sure to turn on the clock
	 * before writing the register. Otherwise, keep it enabled.
	 */
	if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
		ret = clk_prepare_enable(mxs->clk);
		if (ret)
			return ret;
	}

	writel(duty_cycles << 16,
			mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
	writel(PERIOD_PERIOD(period_cycles) | PERIOD_ACTIVE_HIGH |
	       PERIOD_INACTIVE_LOW | PERIOD_CDIV(div),
			mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);

	/*
	 * If the PWM is not enabled, turn the clock off again to save power.
	 */
	if (!test_bit(PWMF_ENABLED, &pwm->flags))
		clk_disable_unprepare(mxs->clk);

	return 0;
}

static int mxs_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	int ret;

	ret = clk_prepare_enable(mxs->clk);
	if (ret)
		return ret;

	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);

	return 0;
}

static void mxs_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);

	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);

	clk_disable_unprepare(mxs->clk);
}

static const struct pwm_ops mxs_pwm_ops = {
	.config = mxs_pwm_config,
	.enable = mxs_pwm_enable,
	.disable = mxs_pwm_disable,
	.owner = THIS_MODULE,
};

static int mxs_pwm_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mxs_pwm_chip *mxs;
	struct resource *res;
	struct pinctrl *pinctrl;
	int ret;

	mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
	if (!mxs)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mxs->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mxs->base))
		return PTR_ERR(mxs->base);

	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
	if (IS_ERR(pinctrl))
		return PTR_ERR(pinctrl);

	mxs->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(mxs->clk))
		return PTR_ERR(mxs->clk);

	mxs->chip.dev = &pdev->dev;
	mxs->chip.ops = &mxs_pwm_ops;
	mxs->chip.base = -1;
	ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
		return ret;
	}

	ret = pwmchip_add(&mxs->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, mxs);

	stmp_reset_block(mxs->base);

	return 0;
}

static int mxs_pwm_remove(struct platform_device *pdev)
{
	struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev);

	return pwmchip_remove(&mxs->chip);
}

static const struct of_device_id mxs_pwm_dt_ids[] = {
	{ .compatible = "fsl,imx23-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);

static struct platform_driver mxs_pwm_driver = {
	.driver = {
		.name = "mxs-pwm",
		.of_match_table = of_match_ptr(mxs_pwm_dt_ids),
	},
	.probe = mxs_pwm_probe,
	.remove = mxs_pwm_remove,
};
module_platform_driver(mxs_pwm_driver);

MODULE_ALIAS("platform:mxs-pwm");
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale MXS PWM Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
4dce82c1 SG	1	/*
	2	* Copyright 2012 Freescale Semiconductor, Inc.
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	#include <linux/clk.h>
	13	#include <linux/err.h>
	14	#include <linux/io.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/of.h>
	18	#include <linux/of_address.h>
1112fe88	19	#include <linux/pinctrl/consumer.h>
4dce82c1 SG	20	#include <linux/platform_device.h>
	21	#include <linux/pwm.h>
	22	#include <linux/slab.h>
01bf32e9	23	#include <linux/stmp_device.h>
4dce82c1 SG	24
	25	#define SET 0x4
	26	#define CLR 0x8
	27	#define TOG 0xc
	28
	29	#define PWM_CTRL 0x0
	30	#define PWM_ACTIVE0 0x10
	31	#define PWM_PERIOD0 0x20
	32	#define PERIOD_PERIOD(p) ((p) & 0xffff)
	33	#define PERIOD_PERIOD_MAX 0x10000
	34	#define PERIOD_ACTIVE_HIGH (3 << 16)
	35	#define PERIOD_INACTIVE_LOW (2 << 18)
	36	#define PERIOD_CDIV(div) (((div) & 0x7) << 20)
	37	#define PERIOD_CDIV_MAX 8
	38
	39	struct mxs_pwm_chip {
	40	struct pwm_chip chip;
4dce82c1 SG	41	struct clk *clk;
	42	void __iomem *base;
	43	};
	44
	45	#define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)
	46
	47	static int mxs_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	48	int duty_ns, int period_ns)
	49	{
	50	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	51	int ret, div = 0;
	52	unsigned int period_cycles, duty_cycles;
	53	unsigned long rate;
	54	unsigned long long c;
	55
	56	rate = clk_get_rate(mxs->clk);
	57	while (1) {
	58	c = rate / (1 << div);
	59	c = c * period_ns;
	60	do_div(c, 1000000000);
	61	if (c < PERIOD_PERIOD_MAX)
	62	break;
	63	div++;
	64	if (div > PERIOD_CDIV_MAX)
	65	return -EINVAL;
	66	}
	67
	68	period_cycles = c;
	69	c *= duty_ns;
	70	do_div(c, period_ns);
	71	duty_cycles = c;
	72
	73	/*
	74	* If the PWM channel is disabled, make sure to turn on the clock
	75	* before writing the register. Otherwise, keep it enabled.
	76	*/
	77	if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
	78	ret = clk_prepare_enable(mxs->clk);
	79	if (ret)
	80	return ret;
	81	}
	82
	83	writel(duty_cycles << 16,
	84	mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
	85	writel(PERIOD_PERIOD(period_cycles) \| PERIOD_ACTIVE_HIGH \|
	86	PERIOD_INACTIVE_LOW \| PERIOD_CDIV(div),
	87	mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
	88
	89	/*
	90	* If the PWM is not enabled, turn the clock off again to save power.
	91	*/
	92	if (!test_bit(PWMF_ENABLED, &pwm->flags))
	93	clk_disable_unprepare(mxs->clk);
	94
	95	return 0;
	96	}
	97
	98	static int mxs_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	99	{
	100	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	101	int ret;
	102
	103	ret = clk_prepare_enable(mxs->clk);
	104	if (ret)
105	return ret;
106
107	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
108
109	return 0;
110	}
111
112	static void mxs_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
113	{
114	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
115
116	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
117
118	clk_disable_unprepare(mxs->clk);
119	}
120
121	static const struct pwm_ops mxs_pwm_ops = {
122	.config = mxs_pwm_config,
123	.enable = mxs_pwm_enable,
124	.disable = mxs_pwm_disable,
125	.owner = THIS_MODULE,
126	};
127
128	static int mxs_pwm_probe(struct platform_device *pdev)
129	{
130	struct device_node *np = pdev->dev.of_node;
131	struct mxs_pwm_chip *mxs;
22d260bd	132	struct resource *res;
1112fe88	133	struct pinctrl *pinctrl;
4dce82c1 SG	134	int ret;
	135
	136	mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
	137	if (!mxs)
	138	return -ENOMEM;
	139
22d260bd	140	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6d4294d1 TR	141	mxs->base = devm_ioremap_resource(&pdev->dev, res);
	142	if (IS_ERR(mxs->base))
	143	return PTR_ERR(mxs->base);
4dce82c1	144
1112fe88 SG	145	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
	146	if (IS_ERR(pinctrl))
	147	return PTR_ERR(pinctrl);
	148
22d260bd SG	149	mxs->clk = devm_clk_get(&pdev->dev, NULL);
	150	if (IS_ERR(mxs->clk))
	151	return PTR_ERR(mxs->clk);
4dce82c1 SG	152
	153	mxs->chip.dev = &pdev->dev;
	154	mxs->chip.ops = &mxs_pwm_ops;
	155	mxs->chip.base = -1;
	156	ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
	157	if (ret < 0) {
	158	dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
22d260bd	159	return ret;
4dce82c1 SG	160	}
	161
	162	ret = pwmchip_add(&mxs->chip);
	163	if (ret < 0) {
	164	dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
22d260bd	165	return ret;
4dce82c1 SG	166	}
4dce82c1 SG	167
4dce82c1 SG	168	platform_set_drvdata(pdev, mxs);
4dce82c1 SG	169
01bf32e9	170	stmp_reset_block(mxs->base);
4dce82c1 SG	171
4dce82c1 SG	172	return 0;
4dce82c1 SG	173	}
4dce82c1 SG	174
77f37917	175	static int mxs_pwm_remove(struct platform_device *pdev)
4dce82c1 SG	176	{
	177	struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev);
	178
457fd768	179	return pwmchip_remove(&mxs->chip);
4dce82c1 SG	180	}
4dce82c1 SG	181
f1a8870a	182	static const struct of_device_id mxs_pwm_dt_ids[] = {
071407ee	183	{ .compatible = "fsl,imx23-pwm", },
4dce82c1 SG	184	{ /* sentinel */ }
	185	};
	186	MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
	187
	188	static struct platform_driver mxs_pwm_driver = {
	189	.driver = {
	190	.name = "mxs-pwm",
	191	.of_match_table = of_match_ptr(mxs_pwm_dt_ids),
	192	},
	193	.probe = mxs_pwm_probe,
fd109112	194	.remove = mxs_pwm_remove,
4dce82c1 SG	195	};
	196	module_platform_driver(mxs_pwm_driver);
	197
	198	MODULE_ALIAS("platform:mxs-pwm");
	199	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
	200	MODULE_DESCRIPTION("Freescale MXS PWM Driver");
	201	MODULE_LICENSE("GPL v2");