[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / power / pm2301_charger.h

/*
 * Copyright (C) ST-Ericsson SA 2012
 *
 * PM2301 power supply interface
 *
 * License terms:  GNU General Public License (GPL), version 2
 */

#ifndef PM2301_CHARGER_H
#define PM2301_CHARGER_H

#define MAIN_WDOG_ENA			0x01
#define MAIN_WDOG_KICK			0x02
#define MAIN_WDOG_DIS			0x00
#define CHARG_WD_KICK			0x01
#define MAIN_CH_ENA			0x01
#define MAIN_CH_NO_OVERSHOOT_ENA_N	0x02
#define MAIN_CH_DET			0x01
#define MAIN_CH_CV_ON			0x04
#define OTP_ENABLE_WD			0x01

#define MAIN_CH_INPUT_CURR_SHIFT	4

#define LED_INDICATOR_PWM_ENA		0x01
#define LED_INDICATOR_PWM_DIS		0x00
#define LED_IND_CUR_5MA			0x04
#define LED_INDICATOR_PWM_DUTY_252_256	0xBF

/* HW failure constants */
#define MAIN_CH_TH_PROT			0x02
#define MAIN_CH_NOK			0x01

/* Watchdog timeout constant */
#define WD_TIMER			0x30 /* 4min */
#define WD_KICK_INTERVAL		(30 * HZ)

#define PM2XXX_NUM_INT_REG		0x6

/* Constant voltage/current */
#define PM2XXX_CONST_CURR		0x0
#define PM2XXX_CONST_VOLT		0x1

/* Lowest charger voltage is 3.39V -> 0x4E */
#define LOW_VOLT_REG			0x4E

#define PM2XXX_BATT_CTRL_REG1		0x00
#define PM2XXX_BATT_CTRL_REG2		0x01
#define PM2XXX_BATT_CTRL_REG3		0x02
#define PM2XXX_BATT_CTRL_REG4		0x03
#define PM2XXX_BATT_CTRL_REG5		0x04
#define PM2XXX_BATT_CTRL_REG6		0x05
#define PM2XXX_BATT_CTRL_REG7		0x06
#define PM2XXX_BATT_CTRL_REG8		0x07
#define PM2XXX_NTC_CTRL_REG1		0x08
#define PM2XXX_NTC_CTRL_REG2		0x09
#define PM2XXX_BATT_CTRL_REG9		0x0A
#define PM2XXX_BATT_STAT_REG1		0x0B
#define PM2XXX_INP_VOLT_VPWR2		0x11
#define PM2XXX_INP_DROP_VPWR2		0x13
#define PM2XXX_INP_VOLT_VPWR1		0x15
#define PM2XXX_INP_DROP_VPWR1		0x17
#define PM2XXX_INP_MODE_VPWR		0x18
#define PM2XXX_BATT_WD_KICK		0x70
#define PM2XXX_DEV_VER_STAT		0x0C
#define PM2XXX_THERM_WARN_CTRL_REG	0x20
#define PM2XXX_BATT_DISC_REG		0x21
#define PM2XXX_BATT_LOW_LEV_COMP_REG	0x22
#define PM2XXX_BATT_LOW_LEV_VAL_REG	0x23
#define PM2XXX_I2C_PAD_CTRL_REG		0x24
#define PM2XXX_SW_CTRL_REG		0x26
#define PM2XXX_LED_CTRL_REG		0x28

#define PM2XXX_REG_INT1			0x40
#define PM2XXX_MASK_REG_INT1		0x50
#define PM2XXX_SRCE_REG_INT1		0x60
#define PM2XXX_REG_INT2			0x41
#define PM2XXX_MASK_REG_INT2		0x51
#define PM2XXX_SRCE_REG_INT2		0x61
#define PM2XXX_REG_INT3			0x42
#define PM2XXX_MASK_REG_INT3		0x52
#define PM2XXX_SRCE_REG_INT3		0x62
#define PM2XXX_REG_INT4			0x43
#define PM2XXX_MASK_REG_INT4		0x53
#define PM2XXX_SRCE_REG_INT4		0x63
#define PM2XXX_REG_INT5			0x44
#define PM2XXX_MASK_REG_INT5		0x54
#define PM2XXX_SRCE_REG_INT5		0x64
#define PM2XXX_REG_INT6			0x45
#define PM2XXX_MASK_REG_INT6		0x55
#define PM2XXX_SRCE_REG_INT6		0x65

#define VPWR_OVV			0x0
#define VSYSTEM_OVV			0x1

/* control Reg 1 */
#define PM2XXX_CH_RESUME_EN		0x1
#define PM2XXX_CH_RESUME_DIS		0x0

/* control Reg 2 */
#define PM2XXX_CH_AUTO_RESUME_EN	0X2
#define PM2XXX_CH_AUTO_RESUME_DIS	0X0
#define PM2XXX_CHARGER_ENA		0x4
#define PM2XXX_CHARGER_DIS		0x0

/* control Reg 3 */
#define PM2XXX_CH_WD_CC_PHASE_OFF	0x0
#define PM2XXX_CH_WD_CC_PHASE_5MIN	0x1
#define PM2XXX_CH_WD_CC_PHASE_10MIN	0x2
#define PM2XXX_CH_WD_CC_PHASE_30MIN	0x3
#define PM2XXX_CH_WD_CC_PHASE_60MIN	0x4
#define PM2XXX_CH_WD_CC_PHASE_120MIN	0x5
#define PM2XXX_CH_WD_CC_PHASE_240MIN	0x6
#define PM2XXX_CH_WD_CC_PHASE_360MIN	0x7

#define PM2XXX_CH_WD_CV_PHASE_OFF	(0x0<<3)
#define PM2XXX_CH_WD_CV_PHASE_5MIN	(0x1<<3)
#define PM2XXX_CH_WD_CV_PHASE_10MIN	(0x2<<3)
#define PM2XXX_CH_WD_CV_PHASE_30MIN	(0x3<<3)
#define PM2XXX_CH_WD_CV_PHASE_60MIN	(0x4<<3)
#define PM2XXX_CH_WD_CV_PHASE_120MIN	(0x5<<3)
#define PM2XXX_CH_WD_CV_PHASE_240MIN	(0x6<<3)
#define PM2XXX_CH_WD_CV_PHASE_360MIN	(0x7<<3)

/* control Reg 4 */
#define PM2XXX_CH_WD_PRECH_PHASE_OFF	0x0
#define PM2XXX_CH_WD_PRECH_PHASE_1MIN	0x1
#define PM2XXX_CH_WD_PRECH_PHASE_5MIN	0x2
#define PM2XXX_CH_WD_PRECH_PHASE_10MIN	0x3
#define PM2XXX_CH_WD_PRECH_PHASE_30MIN	0x4
#define PM2XXX_CH_WD_PRECH_PHASE_60MIN	0x5
#define PM2XXX_CH_WD_PRECH_PHASE_120MIN	0x6
#define PM2XXX_CH_WD_PRECH_PHASE_240MIN	0x7

/* control Reg 5 */
#define PM2XXX_CH_WD_AUTO_TIMEOUT_NONE	0x0
#define PM2XXX_CH_WD_AUTO_TIMEOUT_20MIN	0x1

/* control Reg 6 */
#define PM2XXX_DIR_CH_CC_CURRENT_MASK	0x0F
#define PM2XXX_DIR_CH_CC_CURRENT_200MA	0x0
#define PM2XXX_DIR_CH_CC_CURRENT_400MA	0x2
#define PM2XXX_DIR_CH_CC_CURRENT_600MA	0x3
#define PM2XXX_DIR_CH_CC_CURRENT_800MA	0x4
#define PM2XXX_DIR_CH_CC_CURRENT_1000MA	0x5
#define PM2XXX_DIR_CH_CC_CURRENT_1200MA	0x6
#define PM2XXX_DIR_CH_CC_CURRENT_1400MA	0x7
#define PM2XXX_DIR_CH_CC_CURRENT_1600MA	0x8
#define PM2XXX_DIR_CH_CC_CURRENT_1800MA	0x9
#define PM2XXX_DIR_CH_CC_CURRENT_2000MA	0xA
#define PM2XXX_DIR_CH_CC_CURRENT_2200MA	0xB
#define PM2XXX_DIR_CH_CC_CURRENT_2400MA	0xC
#define PM2XXX_DIR_CH_CC_CURRENT_2600MA	0xD
#define PM2XXX_DIR_CH_CC_CURRENT_2800MA	0xE
#define PM2XXX_DIR_CH_CC_CURRENT_3000MA	0xF

#define PM2XXX_CH_PRECH_CURRENT_MASK	0x30
#define PM2XXX_CH_PRECH_CURRENT_25MA	(0x0<<4)
#define PM2XXX_CH_PRECH_CURRENT_50MA	(0x1<<4)
#define PM2XXX_CH_PRECH_CURRENT_75MA	(0x2<<4)
#define PM2XXX_CH_PRECH_CURRENT_100MA	(0x3<<4)

#define PM2XXX_CH_EOC_CURRENT_MASK	0xC0
#define PM2XXX_CH_EOC_CURRENT_100MA	(0x0<<6)
#define PM2XXX_CH_EOC_CURRENT_150MA	(0x1<<6)
#define PM2XXX_CH_EOC_CURRENT_300MA	(0x2<<6)
#define PM2XXX_CH_EOC_CURRENT_400MA	(0x3<<6)

/* control Reg 7 */
#define PM2XXX_CH_PRECH_VOL_2_5		0x0
#define PM2XXX_CH_PRECH_VOL_2_7		0x1
#define PM2XXX_CH_PRECH_VOL_2_9		0x2
#define PM2XXX_CH_PRECH_VOL_3_1		0x3

#define PM2XXX_CH_VRESUME_VOL_3_2	(0x0<<2)
#define PM2XXX_CH_VRESUME_VOL_3_4	(0x1<<2)
#define PM2XXX_CH_VRESUME_VOL_3_6	(0x2<<2)
#define PM2XXX_CH_VRESUME_VOL_3_8	(0x3<<2)

/* control Reg 8 */
#define PM2XXX_CH_VOLT_MASK		0x3F
#define PM2XXX_CH_VOLT_3_5		0x0
#define PM2XXX_CH_VOLT_3_5225		0x1
#define PM2XXX_CH_VOLT_3_6		0x4
#define PM2XXX_CH_VOLT_3_7		0x8
#define PM2XXX_CH_VOLT_4_0		0x14
#define PM2XXX_CH_VOLT_4_175		0x1B
#define PM2XXX_CH_VOLT_4_2		0x1C
#define PM2XXX_CH_VOLT_4_275		0x1F
#define PM2XXX_CH_VOLT_4_3		0x20

/*NTC control register 1*/
#define PM2XXX_BTEMP_HIGH_TH_45		0x0
#define PM2XXX_BTEMP_HIGH_TH_50		0x1
#define PM2XXX_BTEMP_HIGH_TH_55		0x2
#define PM2XXX_BTEMP_HIGH_TH_60		0x3
#define PM2XXX_BTEMP_HIGH_TH_65		0x4

#define PM2XXX_BTEMP_LOW_TH_N5		(0x0<<3)
#define PM2XXX_BTEMP_LOW_TH_0		(0x1<<3)
#define PM2XXX_BTEMP_LOW_TH_5		(0x2<<3)
#define PM2XXX_BTEMP_LOW_TH_10		(0x3<<3)

/*NTC control register 2*/
#define PM2XXX_NTC_BETA_COEFF_3477	0x0
#define PM2XXX_NTC_BETA_COEFF_3964	0x1

#define PM2XXX_NTC_RES_10K		(0x0<<2)
#define PM2XXX_NTC_RES_47K		(0x1<<2)
#define PM2XXX_NTC_RES_100K		(0x2<<2)
#define PM2XXX_NTC_RES_NO_NTC		(0x3<<2)

/* control Reg 9 */
#define PM2XXX_CH_CC_MODEDROP_EN	1
#define PM2XXX_CH_CC_MODEDROP_DIS	0

#define PM2XXX_CH_CC_REDUCED_CURRENT_100MA	(0x0<<1)
#define PM2XXX_CH_CC_REDUCED_CURRENT_200MA	(0x1<<1)
#define PM2XXX_CH_CC_REDUCED_CURRENT_400MA	(0x2<<1)
#define PM2XXX_CH_CC_REDUCED_CURRENT_IDENT	(0x3<<1)

#define PM2XXX_CHARCHING_INFO_DIS	(0<<3)
#define PM2XXX_CHARCHING_INFO_EN	(1<<3)

#define PM2XXX_CH_150MV_DROP_300MV	(0<<4)
#define PM2XXX_CH_150MV_DROP_150MV	(1<<4)


/* charger status register */
#define PM2XXX_CHG_STATUS_OFF		0x0
#define PM2XXX_CHG_STATUS_ON		0x1
#define PM2XXX_CHG_STATUS_FULL		0x2
#define PM2XXX_CHG_STATUS_ERR		0x3
#define PM2XXX_CHG_STATUS_WAIT		0x4
#define PM2XXX_CHG_STATUS_NOBAT		0x5

/* Input charger voltage VPWR2 */
#define PM2XXX_VPWR2_OVV_6_0		0x0
#define PM2XXX_VPWR2_OVV_6_3		0x1
#define PM2XXX_VPWR2_OVV_10		0x2
#define PM2XXX_VPWR2_OVV_NONE		0x3

/* Input charger drop VPWR2 */
#define PM2XXX_VPWR2_HW_OPT_EN		(0x1<<4)
#define PM2XXX_VPWR2_HW_OPT_DIS		(0x0<<4)

#define PM2XXX_VPWR2_VALID_EN		(0x1<<3)
#define PM2XXX_VPWR2_VALID_DIS		(0x0<<3)

#define PM2XXX_VPWR2_DROP_EN		(0x1<<2)
#define PM2XXX_VPWR2_DROP_DIS		(0x0<<2)

/* Input charger voltage VPWR1 */
#define PM2XXX_VPWR1_OVV_6_0		0x0
#define PM2XXX_VPWR1_OVV_6_3		0x1
#define PM2XXX_VPWR1_OVV_10		0x2
#define PM2XXX_VPWR1_OVV_NONE		0x3

/* Input charger drop VPWR1 */
#define PM2XXX_VPWR1_HW_OPT_EN		(0x1<<4)
#define PM2XXX_VPWR1_HW_OPT_DIS		(0x0<<4)

#define PM2XXX_VPWR1_VALID_EN		(0x1<<3)
#define PM2XXX_VPWR1_VALID_DIS		(0x0<<3)

#define PM2XXX_VPWR1_DROP_EN		(0x1<<2)
#define PM2XXX_VPWR1_DROP_DIS		(0x0<<2)

/* Battery low level comparator control register */
#define PM2XXX_VBAT_LOW_MONITORING_DIS	0x0
#define PM2XXX_VBAT_LOW_MONITORING_ENA	0x1

/* Battery low level value control register */
#define PM2XXX_VBAT_LOW_LEVEL_2_3	0x0
#define PM2XXX_VBAT_LOW_LEVEL_2_4	0x1
#define PM2XXX_VBAT_LOW_LEVEL_2_5	0x2
#define PM2XXX_VBAT_LOW_LEVEL_2_6	0x3
#define PM2XXX_VBAT_LOW_LEVEL_2_7	0x4
#define PM2XXX_VBAT_LOW_LEVEL_2_8	0x5
#define PM2XXX_VBAT_LOW_LEVEL_2_9	0x6
#define PM2XXX_VBAT_LOW_LEVEL_3_0	0x7
#define PM2XXX_VBAT_LOW_LEVEL_3_1	0x8
#define PM2XXX_VBAT_LOW_LEVEL_3_2	0x9
#define PM2XXX_VBAT_LOW_LEVEL_3_3	0xA
#define PM2XXX_VBAT_LOW_LEVEL_3_4	0xB
#define PM2XXX_VBAT_LOW_LEVEL_3_5	0xC
#define PM2XXX_VBAT_LOW_LEVEL_3_6	0xD
#define PM2XXX_VBAT_LOW_LEVEL_3_7	0xE
#define PM2XXX_VBAT_LOW_LEVEL_3_8	0xF
#define PM2XXX_VBAT_LOW_LEVEL_3_9	0x10
#define PM2XXX_VBAT_LOW_LEVEL_4_0	0x11
#define PM2XXX_VBAT_LOW_LEVEL_4_1	0x12
#define PM2XXX_VBAT_LOW_LEVEL_4_2	0x13

/* SW CTRL */
#define PM2XXX_SWCTRL_HW		0x0
#define PM2XXX_SWCTRL_SW		0x1


/* LED Driver Control */
#define PM2XXX_LED_CURRENT_MASK		0x0C
#define PM2XXX_LED_CURRENT_2_5MA	(0X0<<2)
#define PM2XXX_LED_CURRENT_1MA		(0X1<<2)
#define PM2XXX_LED_CURRENT_5MA		(0X2<<2)
#define PM2XXX_LED_CURRENT_10MA		(0X3<<2)

#define PM2XXX_LED_SELECT_MASK		0x02
#define PM2XXX_LED_SELECT_EN		(0X0<<1)
#define PM2XXX_LED_SELECT_DIS		(0X1<<1)

#define PM2XXX_ANTI_OVERSHOOT_MASK	0x01
#define PM2XXX_ANTI_OVERSHOOT_DIS	0X0
#define PM2XXX_ANTI_OVERSHOOT_EN	0X1

enum pm2xxx_reg_int1 {
	PM2XXX_INT1_ITVBATDISCONNECT	= 0x02,
	PM2XXX_INT1_ITVBATLOWR		= 0x04,
	PM2XXX_INT1_ITVBATLOWF		= 0x08,
};

enum pm2xxx_mask_reg_int1 {
	PM2XXX_INT1_M_ITVBATDISCONNECT	= 0x02,
	PM2XXX_INT1_M_ITVBATLOWR	= 0x04,
	PM2XXX_INT1_M_ITVBATLOWF	= 0x08,
};

enum pm2xxx_source_reg_int1 {
	PM2XXX_INT1_S_ITVBATDISCONNECT	= 0x02,
	PM2XXX_INT1_S_ITVBATLOWR	= 0x04,
	PM2XXX_INT1_S_ITVBATLOWF	= 0x08,
};

enum pm2xxx_reg_int2 {
	PM2XXX_INT2_ITVPWR2PLUG		= 0x01,
	PM2XXX_INT2_ITVPWR2UNPLUG	= 0x02,
	PM2XXX_INT2_ITVPWR1PLUG		= 0x04,
	PM2XXX_INT2_ITVPWR1UNPLUG	= 0x08,
};

enum pm2xxx_mask_reg_int2 {
	PM2XXX_INT2_M_ITVPWR2PLUG	= 0x01,
	PM2XXX_INT2_M_ITVPWR2UNPLUG	= 0x02,
	PM2XXX_INT2_M_ITVPWR1PLUG	= 0x04,
	PM2XXX_INT2_M_ITVPWR1UNPLUG	= 0x08,
};

enum pm2xxx_source_reg_int2 {
	PM2XXX_INT2_S_ITVPWR2PLUG	= 0x03,
	PM2XXX_INT2_S_ITVPWR1PLUG	= 0x0c,
};

enum pm2xxx_reg_int3 {
	PM2XXX_INT3_ITCHPRECHARGEWD	= 0x01,
	PM2XXX_INT3_ITCHCCWD		= 0x02,
	PM2XXX_INT3_ITCHCVWD		= 0x04,
	PM2XXX_INT3_ITAUTOTIMEOUTWD	= 0x08,
};

enum pm2xxx_mask_reg_int3 {
	PM2XXX_INT3_M_ITCHPRECHARGEWD	= 0x01,
	PM2XXX_INT3_M_ITCHCCWD		= 0x02,
	PM2XXX_INT3_M_ITCHCVWD		= 0x04,
	PM2XXX_INT3_M_ITAUTOTIMEOUTWD	= 0x08,
};

enum pm2xxx_source_reg_int3 {
	PM2XXX_INT3_S_ITCHPRECHARGEWD	= 0x01,
	PM2XXX_INT3_S_ITCHCCWD		= 0x02,
	PM2XXX_INT3_S_ITCHCVWD		= 0x04,
	PM2XXX_INT3_S_ITAUTOTIMEOUTWD	= 0x08,
};

enum pm2xxx_reg_int4 {
	PM2XXX_INT4_ITBATTEMPCOLD	= 0x01,
	PM2XXX_INT4_ITBATTEMPHOT	= 0x02,
	PM2XXX_INT4_ITVPWR2OVV		= 0x04,
	PM2XXX_INT4_ITVPWR1OVV		= 0x08,
	PM2XXX_INT4_ITCHARGINGON	= 0x10,
	PM2XXX_INT4_ITVRESUME		= 0x20,
	PM2XXX_INT4_ITBATTFULL		= 0x40,
	PM2XXX_INT4_ITCVPHASE		= 0x80,
};

enum pm2xxx_mask_reg_int4 {
	PM2XXX_INT4_M_ITBATTEMPCOLD	= 0x01,
	PM2XXX_INT4_M_ITBATTEMPHOT	= 0x02,
	PM2XXX_INT4_M_ITVPWR2OVV	= 0x04,
	PM2XXX_INT4_M_ITVPWR1OVV	= 0x08,
	PM2XXX_INT4_M_ITCHARGINGON	= 0x10,
	PM2XXX_INT4_M_ITVRESUME		= 0x20,
	PM2XXX_INT4_M_ITBATTFULL	= 0x40,
	PM2XXX_INT4_M_ITCVPHASE		= 0x80,
};

enum pm2xxx_source_reg_int4 {
	PM2XXX_INT4_S_ITBATTEMPCOLD	= 0x01,
	PM2XXX_INT4_S_ITBATTEMPHOT	= 0x02,
	PM2XXX_INT4_S_ITVPWR2OVV	= 0x04,
	PM2XXX_INT4_S_ITVPWR1OVV	= 0x08,
	PM2XXX_INT4_S_ITCHARGINGON	= 0x10,
	PM2XXX_INT4_S_ITVRESUME		= 0x20,
	PM2XXX_INT4_S_ITBATTFULL	= 0x40,
	PM2XXX_INT4_S_ITCVPHASE		= 0x80,
};

enum pm2xxx_reg_int5 {
	PM2XXX_INT5_ITTHERMALSHUTDOWNRISE	= 0x01,
	PM2XXX_INT5_ITTHERMALSHUTDOWNFALL	= 0x02,
	PM2XXX_INT5_ITTHERMALWARNINGRISE	= 0x04,
	PM2XXX_INT5_ITTHERMALWARNINGFALL	= 0x08,
	PM2XXX_INT5_ITVSYSTEMOVV		= 0x10,
};

enum pm2xxx_mask_reg_int5 {
	PM2XXX_INT5_M_ITTHERMALSHUTDOWNRISE	= 0x01,
	PM2XXX_INT5_M_ITTHERMALSHUTDOWNFALL	= 0x02,
	PM2XXX_INT5_M_ITTHERMALWARNINGRISE	= 0x04,
	PM2XXX_INT5_M_ITTHERMALWARNINGFALL	= 0x08,
	PM2XXX_INT5_M_ITVSYSTEMOVV		= 0x10,
};

enum pm2xxx_source_reg_int5 {
	PM2XXX_INT5_S_ITTHERMALSHUTDOWNRISE	= 0x01,
	PM2XXX_INT5_S_ITTHERMALSHUTDOWNFALL	= 0x02,
	PM2XXX_INT5_S_ITTHERMALWARNINGRISE	= 0x04,
	PM2XXX_INT5_S_ITTHERMALWARNINGFALL	= 0x08,
	PM2XXX_INT5_S_ITVSYSTEMOVV		= 0x10,
};

enum pm2xxx_reg_int6 {
	PM2XXX_INT6_ITVPWR2DROP		= 0x01,
	PM2XXX_INT6_ITVPWR1DROP		= 0x02,
	PM2XXX_INT6_ITVPWR2VALIDRISE	= 0x04,
	PM2XXX_INT6_ITVPWR2VALIDFALL	= 0x08,
	PM2XXX_INT6_ITVPWR1VALIDRISE	= 0x10,
	PM2XXX_INT6_ITVPWR1VALIDFALL	= 0x20,
};

enum pm2xxx_mask_reg_int6 {
	PM2XXX_INT6_M_ITVPWR2DROP	= 0x01,
	PM2XXX_INT6_M_ITVPWR1DROP	= 0x02,
	PM2XXX_INT6_M_ITVPWR2VALIDRISE	= 0x04,
	PM2XXX_INT6_M_ITVPWR2VALIDFALL	= 0x08,
	PM2XXX_INT6_M_ITVPWR1VALIDRISE	= 0x10,
	PM2XXX_INT6_M_ITVPWR1VALIDFALL	= 0x20,
};

enum pm2xxx_source_reg_int6 {
	PM2XXX_INT6_S_ITVPWR2DROP	= 0x01,
	PM2XXX_INT6_S_ITVPWR1DROP	= 0x02,
	PM2XXX_INT6_S_ITVPWR2VALIDRISE	= 0x04,
	PM2XXX_INT6_S_ITVPWR2VALIDFALL	= 0x08,
	PM2XXX_INT6_S_ITVPWR1VALIDRISE	= 0x10,
	PM2XXX_INT6_S_ITVPWR1VALIDFALL	= 0x20,
};

struct pm2xxx_charger_info {
	int charger_connected;
	int charger_online;
	int cv_active;
	bool wd_expired;
};

struct pm2xxx_charger_event_flags {
	bool mainextchnotok;
	bool main_thermal_prot;
	bool ovv;
	bool chgwdexp;
};

struct pm2xxx_interrupts {
	u8 reg[PM2XXX_NUM_INT_REG];
	int (*handler[PM2XXX_NUM_INT_REG])(void *, int);
};

struct pm2xxx_config {
	struct i2c_client *pm2xxx_i2c;
	struct i2c_device_id *pm2xxx_id;
};

struct pm2xxx_irq {
	char *name;
	irqreturn_t (*isr)(int irq, void *data);
};

struct pm2xxx_charger {
	struct device *dev;
	u8 chip_id;
	bool vddadc_en_ac;
	struct pm2xxx_config config;
	bool ac_conn;
	unsigned int gpio_irq;
	int vbat;
	int old_vbat;
	int failure_case;
	int failure_input_ovv;
	unsigned int lpn_pin;
	struct pm2xxx_interrupts *pm2_int;
	struct ab8500_gpadc *gpadc;
	struct regulator *regu;
	struct pm2xxx_bm_data *bat;
	struct mutex lock;
	struct ab8500 *parent;
	struct pm2xxx_charger_info ac;
	struct pm2xxx_charger_platform_data *pdata;
	struct workqueue_struct *charger_wq;
	struct delayed_work check_vbat_work;
	struct work_struct ac_work;
	struct work_struct check_main_thermal_prot_work;
	struct ux500_charger ac_chg;
	struct pm2xxx_charger_event_flags flags;
};

#endif /* PM2301_CHARGER_H */
Commit	Line	Data
2fa5b0f4 LJ	1	/*
	2	* Copyright (C) ST-Ericsson SA 2012
	3	*
	4	* PM2301 power supply interface
	5	*
	6	* License terms: GNU General Public License (GPL), version 2
	7	*/
	8
	9	#ifndef PM2301_CHARGER_H
	10	#define PM2301_CHARGER_H
	11
	12	#define MAIN_WDOG_ENA 0x01
	13	#define MAIN_WDOG_KICK 0x02
	14	#define MAIN_WDOG_DIS 0x00
	15	#define CHARG_WD_KICK 0x01
	16	#define MAIN_CH_ENA 0x01
	17	#define MAIN_CH_NO_OVERSHOOT_ENA_N 0x02
	18	#define MAIN_CH_DET 0x01
	19	#define MAIN_CH_CV_ON 0x04
	20	#define OTP_ENABLE_WD 0x01
	21
	22	#define MAIN_CH_INPUT_CURR_SHIFT 4
	23
	24	#define LED_INDICATOR_PWM_ENA 0x01
	25	#define LED_INDICATOR_PWM_DIS 0x00
	26	#define LED_IND_CUR_5MA 0x04
	27	#define LED_INDICATOR_PWM_DUTY_252_256 0xBF
	28
	29	/* HW failure constants */
	30	#define MAIN_CH_TH_PROT 0x02
	31	#define MAIN_CH_NOK 0x01
	32
	33	/* Watchdog timeout constant */
	34	#define WD_TIMER 0x30 /* 4min */
e07a5645	35	#define WD_KICK_INTERVAL (30 * HZ)
2fa5b0f4	36
006f82d6 OC	37	#define PM2XXX_NUM_INT_REG 0x6
006f82d6 OC	38
2fa5b0f4 LJ	39	/* Constant voltage/current */
	40	#define PM2XXX_CONST_CURR 0x0
	41	#define PM2XXX_CONST_VOLT 0x1
	42
	43	/* Lowest charger voltage is 3.39V -> 0x4E */
	44	#define LOW_VOLT_REG 0x4E
	45
	46	#define PM2XXX_BATT_CTRL_REG1 0x00
	47	#define PM2XXX_BATT_CTRL_REG2 0x01
	48	#define PM2XXX_BATT_CTRL_REG3 0x02
	49	#define PM2XXX_BATT_CTRL_REG4 0x03
	50	#define PM2XXX_BATT_CTRL_REG5 0x04
	51	#define PM2XXX_BATT_CTRL_REG6 0x05
	52	#define PM2XXX_BATT_CTRL_REG7 0x06
	53	#define PM2XXX_BATT_CTRL_REG8 0x07
	54	#define PM2XXX_NTC_CTRL_REG1 0x08
	55	#define PM2XXX_NTC_CTRL_REG2 0x09
	56	#define PM2XXX_BATT_CTRL_REG9 0x0A
	57	#define PM2XXX_BATT_STAT_REG1 0x0B
	58	#define PM2XXX_INP_VOLT_VPWR2 0x11
	59	#define PM2XXX_INP_DROP_VPWR2 0x13
	60	#define PM2XXX_INP_VOLT_VPWR1 0x15
	61	#define PM2XXX_INP_DROP_VPWR1 0x17
	62	#define PM2XXX_INP_MODE_VPWR 0x18
	63	#define PM2XXX_BATT_WD_KICK 0x70
	64	#define PM2XXX_DEV_VER_STAT 0x0C
	65	#define PM2XXX_THERM_WARN_CTRL_REG 0x20
	66	#define PM2XXX_BATT_DISC_REG 0x21
	67	#define PM2XXX_BATT_LOW_LEV_COMP_REG 0x22
	68	#define PM2XXX_BATT_LOW_LEV_VAL_REG 0x23
	69	#define PM2XXX_I2C_PAD_CTRL_REG 0x24
	70	#define PM2XXX_SW_CTRL_REG 0x26
	71	#define PM2XXX_LED_CTRL_REG 0x28
	72
	73	#define PM2XXX_REG_INT1 0x40
	74	#define PM2XXX_MASK_REG_INT1 0x50
	75	#define PM2XXX_SRCE_REG_INT1 0x60
	76	#define PM2XXX_REG_INT2 0x41
	77	#define PM2XXX_MASK_REG_INT2 0x51
	78	#define PM2XXX_SRCE_REG_INT2 0x61
	79	#define PM2XXX_REG_INT3 0x42
	80	#define PM2XXX_MASK_REG_INT3 0x52
	81	#define PM2XXX_SRCE_REG_INT3 0x62
	82	#define PM2XXX_REG_INT4 0x43
	83	#define PM2XXX_MASK_REG_INT4 0x53
	84	#define PM2XXX_SRCE_REG_INT4 0x63
	85	#define PM2XXX_REG_INT5 0x44
	86	#define PM2XXX_MASK_REG_INT5 0x54
	87	#define PM2XXX_SRCE_REG_INT5 0x64
	88	#define PM2XXX_REG_INT6 0x45
	89	#define PM2XXX_MASK_REG_INT6 0x55
	90	#define PM2XXX_SRCE_REG_INT6 0x65
	91
	92	#define VPWR_OVV 0x0
	93	#define VSYSTEM_OVV 0x1
	94
	95	/* control Reg 1 */
	96	#define PM2XXX_CH_RESUME_EN 0x1
	97	#define PM2XXX_CH_RESUME_DIS 0x0
	98
	99	/* control Reg 2 */
	100	#define PM2XXX_CH_AUTO_RESUME_EN 0X2
	101	#define PM2XXX_CH_AUTO_RESUME_DIS 0X0
	102	#define PM2XXX_CHARGER_ENA 0x4
103	#define PM2XXX_CHARGER_DIS 0x0
104
105	/* control Reg 3 */
106	#define PM2XXX_CH_WD_CC_PHASE_OFF 0x0
107	#define PM2XXX_CH_WD_CC_PHASE_5MIN 0x1
108	#define PM2XXX_CH_WD_CC_PHASE_10MIN 0x2
109	#define PM2XXX_CH_WD_CC_PHASE_30MIN 0x3
110	#define PM2XXX_CH_WD_CC_PHASE_60MIN 0x4
111	#define PM2XXX_CH_WD_CC_PHASE_120MIN 0x5
112	#define PM2XXX_CH_WD_CC_PHASE_240MIN 0x6
113	#define PM2XXX_CH_WD_CC_PHASE_360MIN 0x7
114
115	#define PM2XXX_CH_WD_CV_PHASE_OFF (0x0<<3)
116	#define PM2XXX_CH_WD_CV_PHASE_5MIN (0x1<<3)
117	#define PM2XXX_CH_WD_CV_PHASE_10MIN (0x2<<3)
118	#define PM2XXX_CH_WD_CV_PHASE_30MIN (0x3<<3)
119	#define PM2XXX_CH_WD_CV_PHASE_60MIN (0x4<<3)
120	#define PM2XXX_CH_WD_CV_PHASE_120MIN (0x5<<3)
121	#define PM2XXX_CH_WD_CV_PHASE_240MIN (0x6<<3)
122	#define PM2XXX_CH_WD_CV_PHASE_360MIN (0x7<<3)
123
124	/* control Reg 4 */
125	#define PM2XXX_CH_WD_PRECH_PHASE_OFF 0x0
126	#define PM2XXX_CH_WD_PRECH_PHASE_1MIN 0x1
127	#define PM2XXX_CH_WD_PRECH_PHASE_5MIN 0x2
128	#define PM2XXX_CH_WD_PRECH_PHASE_10MIN 0x3
129	#define PM2XXX_CH_WD_PRECH_PHASE_30MIN 0x4
130	#define PM2XXX_CH_WD_PRECH_PHASE_60MIN 0x5
131	#define PM2XXX_CH_WD_PRECH_PHASE_120MIN 0x6
132	#define PM2XXX_CH_WD_PRECH_PHASE_240MIN 0x7
133
134	/* control Reg 5 */
135	#define PM2XXX_CH_WD_AUTO_TIMEOUT_NONE 0x0
136	#define PM2XXX_CH_WD_AUTO_TIMEOUT_20MIN 0x1
137
138	/* control Reg 6 */
139	#define PM2XXX_DIR_CH_CC_CURRENT_MASK 0x0F
140	#define PM2XXX_DIR_CH_CC_CURRENT_200MA 0x0
141	#define PM2XXX_DIR_CH_CC_CURRENT_400MA 0x2
142	#define PM2XXX_DIR_CH_CC_CURRENT_600MA 0x3
143	#define PM2XXX_DIR_CH_CC_CURRENT_800MA 0x4
144	#define PM2XXX_DIR_CH_CC_CURRENT_1000MA 0x5
145	#define PM2XXX_DIR_CH_CC_CURRENT_1200MA 0x6
146	#define PM2XXX_DIR_CH_CC_CURRENT_1400MA 0x7
147	#define PM2XXX_DIR_CH_CC_CURRENT_1600MA 0x8
148	#define PM2XXX_DIR_CH_CC_CURRENT_1800MA 0x9
149	#define PM2XXX_DIR_CH_CC_CURRENT_2000MA 0xA
150	#define PM2XXX_DIR_CH_CC_CURRENT_2200MA 0xB
151	#define PM2XXX_DIR_CH_CC_CURRENT_2400MA 0xC
152	#define PM2XXX_DIR_CH_CC_CURRENT_2600MA 0xD
153	#define PM2XXX_DIR_CH_CC_CURRENT_2800MA 0xE
154	#define PM2XXX_DIR_CH_CC_CURRENT_3000MA 0xF
155
156	#define PM2XXX_CH_PRECH_CURRENT_MASK 0x30
157	#define PM2XXX_CH_PRECH_CURRENT_25MA (0x0<<4)
158	#define PM2XXX_CH_PRECH_CURRENT_50MA (0x1<<4)
159	#define PM2XXX_CH_PRECH_CURRENT_75MA (0x2<<4)
160	#define PM2XXX_CH_PRECH_CURRENT_100MA (0x3<<4)
161
162	#define PM2XXX_CH_EOC_CURRENT_MASK 0xC0
163	#define PM2XXX_CH_EOC_CURRENT_100MA (0x0<<6)
164	#define PM2XXX_CH_EOC_CURRENT_150MA (0x1<<6)
165	#define PM2XXX_CH_EOC_CURRENT_300MA (0x2<<6)
166	#define PM2XXX_CH_EOC_CURRENT_400MA (0x3<<6)
167
168	/* control Reg 7 */
169	#define PM2XXX_CH_PRECH_VOL_2_5 0x0
170	#define PM2XXX_CH_PRECH_VOL_2_7 0x1
171	#define PM2XXX_CH_PRECH_VOL_2_9 0x2
172	#define PM2XXX_CH_PRECH_VOL_3_1 0x3
173
174	#define PM2XXX_CH_VRESUME_VOL_3_2 (0x0<<2)
175	#define PM2XXX_CH_VRESUME_VOL_3_4 (0x1<<2)
176	#define PM2XXX_CH_VRESUME_VOL_3_6 (0x2<<2)
177	#define PM2XXX_CH_VRESUME_VOL_3_8 (0x3<<2)
178
179	/* control Reg 8 */
180	#define PM2XXX_CH_VOLT_MASK 0x3F
181	#define PM2XXX_CH_VOLT_3_5 0x0
182	#define PM2XXX_CH_VOLT_3_5225 0x1
183	#define PM2XXX_CH_VOLT_3_6 0x4
184	#define PM2XXX_CH_VOLT_3_7 0x8
185	#define PM2XXX_CH_VOLT_4_0 0x14
186	#define PM2XXX_CH_VOLT_4_175 0x1B
187	#define PM2XXX_CH_VOLT_4_2 0x1C
188	#define PM2XXX_CH_VOLT_4_275 0x1F
189	#define PM2XXX_CH_VOLT_4_3 0x20
190
191	/NTC control register 1/
192	#define PM2XXX_BTEMP_HIGH_TH_45 0x0
193	#define PM2XXX_BTEMP_HIGH_TH_50 0x1
194	#define PM2XXX_BTEMP_HIGH_TH_55 0x2
195	#define PM2XXX_BTEMP_HIGH_TH_60 0x3
196	#define PM2XXX_BTEMP_HIGH_TH_65 0x4
197
198	#define PM2XXX_BTEMP_LOW_TH_N5 (0x0<<3)
199	#define PM2XXX_BTEMP_LOW_TH_0 (0x1<<3)
200	#define PM2XXX_BTEMP_LOW_TH_5 (0x2<<3)
201	#define PM2XXX_BTEMP_LOW_TH_10 (0x3<<3)
202
203	/NTC control register 2/
204	#define PM2XXX_NTC_BETA_COEFF_3477 0x0
205	#define PM2XXX_NTC_BETA_COEFF_3964 0x1
206
207	#define PM2XXX_NTC_RES_10K (0x0<<2)
208	#define PM2XXX_NTC_RES_47K (0x1<<2)
209	#define PM2XXX_NTC_RES_100K (0x2<<2)
210	#define PM2XXX_NTC_RES_NO_NTC (0x3<<2)
211
212	/* control Reg 9 */
213	#define PM2XXX_CH_CC_MODEDROP_EN 1
214	#define PM2XXX_CH_CC_MODEDROP_DIS 0
215
216	#define PM2XXX_CH_CC_REDUCED_CURRENT_100MA (0x0<<1)
217	#define PM2XXX_CH_CC_REDUCED_CURRENT_200MA (0x1<<1)
218	#define PM2XXX_CH_CC_REDUCED_CURRENT_400MA (0x2<<1)
219	#define PM2XXX_CH_CC_REDUCED_CURRENT_IDENT (0x3<<1)
220
221	#define PM2XXX_CHARCHING_INFO_DIS (0<<3)
222	#define PM2XXX_CHARCHING_INFO_EN (1<<3)
223
224	#define PM2XXX_CH_150MV_DROP_300MV (0<<4)
225	#define PM2XXX_CH_150MV_DROP_150MV (1<<4)
226
227
228	/* charger status register */
229	#define PM2XXX_CHG_STATUS_OFF 0x0
230	#define PM2XXX_CHG_STATUS_ON 0x1
231	#define PM2XXX_CHG_STATUS_FULL 0x2
232	#define PM2XXX_CHG_STATUS_ERR 0x3
233	#define PM2XXX_CHG_STATUS_WAIT 0x4
234	#define PM2XXX_CHG_STATUS_NOBAT 0x5
235
236	/* Input charger voltage VPWR2 */
237	#define PM2XXX_VPWR2_OVV_6_0 0x0
238	#define PM2XXX_VPWR2_OVV_6_3 0x1
239	#define PM2XXX_VPWR2_OVV_10 0x2
240	#define PM2XXX_VPWR2_OVV_NONE 0x3
241
006f82d6 OC	242	/* Input charger drop VPWR2 */
	243	#define PM2XXX_VPWR2_HW_OPT_EN (0x1<<4)
	244	#define PM2XXX_VPWR2_HW_OPT_DIS (0x0<<4)
	245
	246	#define PM2XXX_VPWR2_VALID_EN (0x1<<3)
	247	#define PM2XXX_VPWR2_VALID_DIS (0x0<<3)
	248
	249	#define PM2XXX_VPWR2_DROP_EN (0x1<<2)
	250	#define PM2XXX_VPWR2_DROP_DIS (0x0<<2)
	251
2fa5b0f4 LJ	252	/* Input charger voltage VPWR1 */
	253	#define PM2XXX_VPWR1_OVV_6_0 0x0
	254	#define PM2XXX_VPWR1_OVV_6_3 0x1
	255	#define PM2XXX_VPWR1_OVV_10 0x2
	256	#define PM2XXX_VPWR1_OVV_NONE 0x3
	257
006f82d6 OC	258	/* Input charger drop VPWR1 */
	259	#define PM2XXX_VPWR1_HW_OPT_EN (0x1<<4)
	260	#define PM2XXX_VPWR1_HW_OPT_DIS (0x0<<4)
	261
	262	#define PM2XXX_VPWR1_VALID_EN (0x1<<3)
	263	#define PM2XXX_VPWR1_VALID_DIS (0x0<<3)
	264
	265	#define PM2XXX_VPWR1_DROP_EN (0x1<<2)
	266	#define PM2XXX_VPWR1_DROP_DIS (0x0<<2)
	267
2fa5b0f4 LJ	268	/* Battery low level comparator control register */
	269	#define PM2XXX_VBAT_LOW_MONITORING_DIS 0x0
	270	#define PM2XXX_VBAT_LOW_MONITORING_ENA 0x1
	271
	272	/* Battery low level value control register */
	273	#define PM2XXX_VBAT_LOW_LEVEL_2_3 0x0
	274	#define PM2XXX_VBAT_LOW_LEVEL_2_4 0x1
	275	#define PM2XXX_VBAT_LOW_LEVEL_2_5 0x2
	276	#define PM2XXX_VBAT_LOW_LEVEL_2_6 0x3
	277	#define PM2XXX_VBAT_LOW_LEVEL_2_7 0x4
	278	#define PM2XXX_VBAT_LOW_LEVEL_2_8 0x5
	279	#define PM2XXX_VBAT_LOW_LEVEL_2_9 0x6
	280	#define PM2XXX_VBAT_LOW_LEVEL_3_0 0x7
	281	#define PM2XXX_VBAT_LOW_LEVEL_3_1 0x8
	282	#define PM2XXX_VBAT_LOW_LEVEL_3_2 0x9
	283	#define PM2XXX_VBAT_LOW_LEVEL_3_3 0xA
	284	#define PM2XXX_VBAT_LOW_LEVEL_3_4 0xB
	285	#define PM2XXX_VBAT_LOW_LEVEL_3_5 0xC
	286	#define PM2XXX_VBAT_LOW_LEVEL_3_6 0xD
	287	#define PM2XXX_VBAT_LOW_LEVEL_3_7 0xE
	288	#define PM2XXX_VBAT_LOW_LEVEL_3_8 0xF
	289	#define PM2XXX_VBAT_LOW_LEVEL_3_9 0x10
	290	#define PM2XXX_VBAT_LOW_LEVEL_4_0 0x11
	291	#define PM2XXX_VBAT_LOW_LEVEL_4_1 0x12
	292	#define PM2XXX_VBAT_LOW_LEVEL_4_2 0x13
	293
	294	/* SW CTRL */
	295	#define PM2XXX_SWCTRL_HW 0x0
	296	#define PM2XXX_SWCTRL_SW 0x1
	297
	298
	299	/* LED Driver Control */
	300	#define PM2XXX_LED_CURRENT_MASK 0x0C
	301	#define PM2XXX_LED_CURRENT_2_5MA (0X0<<2)
	302	#define PM2XXX_LED_CURRENT_1MA (0X1<<2)
	303	#define PM2XXX_LED_CURRENT_5MA (0X2<<2)
	304	#define PM2XXX_LED_CURRENT_10MA (0X3<<2)
	305
	306	#define PM2XXX_LED_SELECT_MASK 0x02
	307	#define PM2XXX_LED_SELECT_EN (0X0<<1)
	308	#define PM2XXX_LED_SELECT_DIS (0X1<<1)
	309
	310	#define PM2XXX_ANTI_OVERSHOOT_MASK 0x01
	311	#define PM2XXX_ANTI_OVERSHOOT_DIS 0X0
	312	#define PM2XXX_ANTI_OVERSHOOT_EN 0X1
	313
	314	enum pm2xxx_reg_int1 {
	315	PM2XXX_INT1_ITVBATDISCONNECT = 0x02,
	316	PM2XXX_INT1_ITVBATLOWR = 0x04,
	317	PM2XXX_INT1_ITVBATLOWF = 0x08,
	318	};
	319
	320	enum pm2xxx_mask_reg_int1 {
	321	PM2XXX_INT1_M_ITVBATDISCONNECT = 0x02,
	322	PM2XXX_INT1_M_ITVBATLOWR = 0x04,
	323	PM2XXX_INT1_M_ITVBATLOWF = 0x08,
	324	};
	325
	326	enum pm2xxx_source_reg_int1 {
	327	PM2XXX_INT1_S_ITVBATDISCONNECT = 0x02,
	328	PM2XXX_INT1_S_ITVBATLOWR = 0x04,
	329	PM2XXX_INT1_S_ITVBATLOWF = 0x08,
	330	};
	331
332	enum pm2xxx_reg_int2 {
333	PM2XXX_INT2_ITVPWR2PLUG = 0x01,
334	PM2XXX_INT2_ITVPWR2UNPLUG = 0x02,
335	PM2XXX_INT2_ITVPWR1PLUG = 0x04,
336	PM2XXX_INT2_ITVPWR1UNPLUG = 0x08,
337	};
338
339	enum pm2xxx_mask_reg_int2 {
340	PM2XXX_INT2_M_ITVPWR2PLUG = 0x01,
341	PM2XXX_INT2_M_ITVPWR2UNPLUG = 0x02,
342	PM2XXX_INT2_M_ITVPWR1PLUG = 0x04,
343	PM2XXX_INT2_M_ITVPWR1UNPLUG = 0x08,
344	};
345
346	enum pm2xxx_source_reg_int2 {
347	PM2XXX_INT2_S_ITVPWR2PLUG = 0x03,
348	PM2XXX_INT2_S_ITVPWR1PLUG = 0x0c,
349	};
350
351	enum pm2xxx_reg_int3 {
352	PM2XXX_INT3_ITCHPRECHARGEWD = 0x01,
353	PM2XXX_INT3_ITCHCCWD = 0x02,
354	PM2XXX_INT3_ITCHCVWD = 0x04,
355	PM2XXX_INT3_ITAUTOTIMEOUTWD = 0x08,
356	};
357
358	enum pm2xxx_mask_reg_int3 {
359	PM2XXX_INT3_M_ITCHPRECHARGEWD = 0x01,
360	PM2XXX_INT3_M_ITCHCCWD = 0x02,
361	PM2XXX_INT3_M_ITCHCVWD = 0x04,
362	PM2XXX_INT3_M_ITAUTOTIMEOUTWD = 0x08,
363	};
364
365	enum pm2xxx_source_reg_int3 {
366	PM2XXX_INT3_S_ITCHPRECHARGEWD = 0x01,
367	PM2XXX_INT3_S_ITCHCCWD = 0x02,
368	PM2XXX_INT3_S_ITCHCVWD = 0x04,
369	PM2XXX_INT3_S_ITAUTOTIMEOUTWD = 0x08,
370	};
371
372	enum pm2xxx_reg_int4 {
373	PM2XXX_INT4_ITBATTEMPCOLD = 0x01,
374	PM2XXX_INT4_ITBATTEMPHOT = 0x02,
375	PM2XXX_INT4_ITVPWR2OVV = 0x04,
376	PM2XXX_INT4_ITVPWR1OVV = 0x08,
377	PM2XXX_INT4_ITCHARGINGON = 0x10,
378	PM2XXX_INT4_ITVRESUME = 0x20,
379	PM2XXX_INT4_ITBATTFULL = 0x40,
380	PM2XXX_INT4_ITCVPHASE = 0x80,
381	};
382
383	enum pm2xxx_mask_reg_int4 {
384	PM2XXX_INT4_M_ITBATTEMPCOLD = 0x01,
385	PM2XXX_INT4_M_ITBATTEMPHOT = 0x02,
386	PM2XXX_INT4_M_ITVPWR2OVV = 0x04,
387	PM2XXX_INT4_M_ITVPWR1OVV = 0x08,
388	PM2XXX_INT4_M_ITCHARGINGON = 0x10,
389	PM2XXX_INT4_M_ITVRESUME = 0x20,
390	PM2XXX_INT4_M_ITBATTFULL = 0x40,
391	PM2XXX_INT4_M_ITCVPHASE = 0x80,
392	};
393
394	enum pm2xxx_source_reg_int4 {
395	PM2XXX_INT4_S_ITBATTEMPCOLD = 0x01,
396	PM2XXX_INT4_S_ITBATTEMPHOT = 0x02,
397	PM2XXX_INT4_S_ITVPWR2OVV = 0x04,
398	PM2XXX_INT4_S_ITVPWR1OVV = 0x08,
399	PM2XXX_INT4_S_ITCHARGINGON = 0x10,
400	PM2XXX_INT4_S_ITVRESUME = 0x20,
401	PM2XXX_INT4_S_ITBATTFULL = 0x40,
402	PM2XXX_INT4_S_ITCVPHASE = 0x80,
403	};
404
405	enum pm2xxx_reg_int5 {
406	PM2XXX_INT5_ITTHERMALSHUTDOWNRISE = 0x01,
407	PM2XXX_INT5_ITTHERMALSHUTDOWNFALL = 0x02,
408	PM2XXX_INT5_ITTHERMALWARNINGRISE = 0x04,
409	PM2XXX_INT5_ITTHERMALWARNINGFALL = 0x08,
410	PM2XXX_INT5_ITVSYSTEMOVV = 0x10,
411	};
412
413	enum pm2xxx_mask_reg_int5 {
414	PM2XXX_INT5_M_ITTHERMALSHUTDOWNRISE = 0x01,
415	PM2XXX_INT5_M_ITTHERMALSHUTDOWNFALL = 0x02,
416	PM2XXX_INT5_M_ITTHERMALWARNINGRISE = 0x04,
417	PM2XXX_INT5_M_ITTHERMALWARNINGFALL = 0x08,
418	PM2XXX_INT5_M_ITVSYSTEMOVV = 0x10,
419	};
420
421	enum pm2xxx_source_reg_int5 {
422	PM2XXX_INT5_S_ITTHERMALSHUTDOWNRISE = 0x01,
423	PM2XXX_INT5_S_ITTHERMALSHUTDOWNFALL = 0x02,
424	PM2XXX_INT5_S_ITTHERMALWARNINGRISE = 0x04,
425	PM2XXX_INT5_S_ITTHERMALWARNINGFALL = 0x08,
426	PM2XXX_INT5_S_ITVSYSTEMOVV = 0x10,
427	};
428
429	enum pm2xxx_reg_int6 {
430	PM2XXX_INT6_ITVPWR2DROP = 0x01,
431	PM2XXX_INT6_ITVPWR1DROP = 0x02,
432	PM2XXX_INT6_ITVPWR2VALIDRISE = 0x04,
433	PM2XXX_INT6_ITVPWR2VALIDFALL = 0x08,
434	PM2XXX_INT6_ITVPWR1VALIDRISE = 0x10,
435	PM2XXX_INT6_ITVPWR1VALIDFALL = 0x20,
436	};
437
438	enum pm2xxx_mask_reg_int6 {
439	PM2XXX_INT6_M_ITVPWR2DROP = 0x01,
440	PM2XXX_INT6_M_ITVPWR1DROP = 0x02,
441	PM2XXX_INT6_M_ITVPWR2VALIDRISE = 0x04,
442	PM2XXX_INT6_M_ITVPWR2VALIDFALL = 0x08,
443	PM2XXX_INT6_M_ITVPWR1VALIDRISE = 0x10,
444	PM2XXX_INT6_M_ITVPWR1VALIDFALL = 0x20,
445	};
446
447	enum pm2xxx_source_reg_int6 {
448	PM2XXX_INT6_S_ITVPWR2DROP = 0x01,
449	PM2XXX_INT6_S_ITVPWR1DROP = 0x02,
450	PM2XXX_INT6_S_ITVPWR2VALIDRISE = 0x04,
451	PM2XXX_INT6_S_ITVPWR2VALIDFALL = 0x08,
452	PM2XXX_INT6_S_ITVPWR1VALIDRISE = 0x10,
453	PM2XXX_INT6_S_ITVPWR1VALIDFALL = 0x20,
454	};
455
456	struct pm2xxx_charger_info {
457	int charger_connected;
458	int charger_online;
2fa5b0f4 LJ	459	int cv_active;
	460	bool wd_expired;
	461	};
	462
	463	struct pm2xxx_charger_event_flags {
	464	bool mainextchnotok;
	465	bool main_thermal_prot;
	466	bool ovv;
	467	bool chgwdexp;
	468	};
	469
006f82d6 OC	470	struct pm2xxx_interrupts {
	471	u8 reg[PM2XXX_NUM_INT_REG];
	472	int (handler[PM2XXX_NUM_INT_REG])(void , int);
	473	};
	474
2fa5b0f4 LJ	475	struct pm2xxx_config {
	476	struct i2c_client *pm2xxx_i2c;
	477	struct i2c_device_id *pm2xxx_id;
	478	};
	479
	480	struct pm2xxx_irq {
	481	char *name;
	482	irqreturn_t (isr)(int irq, void data);
	483	};
	484
	485	struct pm2xxx_charger {
	486	struct device *dev;
	487	u8 chip_id;
	488	bool vddadc_en_ac;
	489	struct pm2xxx_config config;
	490	bool ac_conn;
	491	unsigned int gpio_irq;
	492	int vbat;
	493	int old_vbat;
	494	int failure_case;
	495	int failure_input_ovv;
3988043b	496	unsigned int lpn_pin;
006f82d6	497	struct pm2xxx_interrupts *pm2_int;
2fa5b0f4 LJ	498	struct ab8500_gpadc *gpadc;
	499	struct regulator *regu;
	500	struct pm2xxx_bm_data *bat;
	501	struct mutex lock;
	502	struct ab8500 *parent;
	503	struct pm2xxx_charger_info ac;
	504	struct pm2xxx_charger_platform_data *pdata;
	505	struct workqueue_struct *charger_wq;
	506	struct delayed_work check_vbat_work;
	507	struct work_struct ac_work;
	508	struct work_struct check_main_thermal_prot_work;
	509	struct ux500_charger ac_chg;
	510	struct pm2xxx_charger_event_flags flags;
	511	};
	512
	513	#endif /* PM2301_CHARGER_H */