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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pinctrl / spear / pinctrl-spear1310.c
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85ed41a7
VK		 1/*
2 * Driver for the ST Microelectronics SPEAr1310 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
10d8935f 5 * Viresh Kumar <viresh.linux@gmail.com>
85ed41a7
VK		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear.h"
18
19#define DRIVER_NAME "spear1310-pinmux"
20
21/* pins */
22static const struct pinctrl_pin_desc spear1310_pins[] = {
23 SPEAR_PIN_0_TO_101,
24 SPEAR_PIN_102_TO_245,
25};
26
27/* registers */
28#define PERIP_CFG 0x32C
29 #define MCIF_SEL_SHIFT 3
30 #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
31 #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
32 #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
33 #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
34
35#define PCIE_SATA_CFG 0x3A4
36 #define PCIE_SATA2_SEL_PCIE (0 << 31)
37 #define PCIE_SATA1_SEL_PCIE (0 << 30)
38 #define PCIE_SATA0_SEL_PCIE (0 << 29)
39 #define PCIE_SATA2_SEL_SATA (1 << 31)
40 #define PCIE_SATA1_SEL_SATA (1 << 30)
41 #define PCIE_SATA0_SEL_SATA (1 << 29)
42 #define SATA2_CFG_TX_CLK_EN (1 << 27)
43 #define SATA2_CFG_RX_CLK_EN (1 << 26)
44 #define SATA2_CFG_POWERUP_RESET (1 << 25)
45 #define SATA2_CFG_PM_CLK_EN (1 << 24)
46 #define SATA1_CFG_TX_CLK_EN (1 << 23)
47 #define SATA1_CFG_RX_CLK_EN (1 << 22)
48 #define SATA1_CFG_POWERUP_RESET (1 << 21)
49 #define SATA1_CFG_PM_CLK_EN (1 << 20)
50 #define SATA0_CFG_TX_CLK_EN (1 << 19)
51 #define SATA0_CFG_RX_CLK_EN (1 << 18)
52 #define SATA0_CFG_POWERUP_RESET (1 << 17)
53 #define SATA0_CFG_PM_CLK_EN (1 << 16)
54 #define PCIE2_CFG_DEVICE_PRESENT (1 << 11)
55 #define PCIE2_CFG_POWERUP_RESET (1 << 10)
56 #define PCIE2_CFG_CORE_CLK_EN (1 << 9)
57 #define PCIE2_CFG_AUX_CLK_EN (1 << 8)
58 #define PCIE1_CFG_DEVICE_PRESENT (1 << 7)
59 #define PCIE1_CFG_POWERUP_RESET (1 << 6)
60 #define PCIE1_CFG_CORE_CLK_EN (1 << 5)
61 #define PCIE1_CFG_AUX_CLK_EN (1 << 4)
62 #define PCIE0_CFG_DEVICE_PRESENT (1 << 3)
63 #define PCIE0_CFG_POWERUP_RESET (1 << 2)
64 #define PCIE0_CFG_CORE_CLK_EN (1 << 1)
65 #define PCIE0_CFG_AUX_CLK_EN (1 << 0)
66
67#define PAD_FUNCTION_EN_0 0x650
68 #define PMX_UART0_MASK (1 << 1)
69 #define PMX_I2C0_MASK (1 << 2)
70 #define PMX_I2S0_MASK (1 << 3)
71 #define PMX_SSP0_MASK (1 << 4)
72 #define PMX_CLCD1_MASK (1 << 5)
73 #define PMX_EGPIO00_MASK (1 << 6)
74 #define PMX_EGPIO01_MASK (1 << 7)
75 #define PMX_EGPIO02_MASK (1 << 8)
76 #define PMX_EGPIO03_MASK (1 << 9)
77 #define PMX_EGPIO04_MASK (1 << 10)
78 #define PMX_EGPIO05_MASK (1 << 11)
79 #define PMX_EGPIO06_MASK (1 << 12)
80 #define PMX_EGPIO07_MASK (1 << 13)
81 #define PMX_EGPIO08_MASK (1 << 14)
82 #define PMX_EGPIO09_MASK (1 << 15)
83 #define PMX_SMI_MASK (1 << 16)
84 #define PMX_NAND8_MASK (1 << 17)
85 #define PMX_GMIICLK_MASK (1 << 18)
86 #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
87 #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
88 #define PMX_GMIID47_MASK (1 << 21)
89 #define PMX_MDC_MDIO_MASK (1 << 22)
90 #define PMX_MCI_DATA8_15_MASK (1 << 23)
91 #define PMX_NFAD23_MASK (1 << 24)
92 #define PMX_NFAD24_MASK (1 << 25)
93 #define PMX_NFAD25_MASK (1 << 26)
94 #define PMX_NFCE3_MASK (1 << 27)
95 #define PMX_NFWPRT3_MASK (1 << 28)
96 #define PMX_NFRSTPWDWN0_MASK (1 << 29)
97 #define PMX_NFRSTPWDWN1_MASK (1 << 30)
98 #define PMX_NFRSTPWDWN2_MASK (1 << 31)
99
100#define PAD_FUNCTION_EN_1 0x654
101 #define PMX_NFRSTPWDWN3_MASK (1 << 0)
102 #define PMX_SMINCS2_MASK (1 << 1)
103 #define PMX_SMINCS3_MASK (1 << 2)
104 #define PMX_CLCD2_MASK (1 << 3)
105 #define PMX_KBD_ROWCOL68_MASK (1 << 4)
106 #define PMX_EGPIO10_MASK (1 << 5)
107 #define PMX_EGPIO11_MASK (1 << 6)
108 #define PMX_EGPIO12_MASK (1 << 7)
109 #define PMX_EGPIO13_MASK (1 << 8)
110 #define PMX_EGPIO14_MASK (1 << 9)
111 #define PMX_EGPIO15_MASK (1 << 10)
112 #define PMX_UART0_MODEM_MASK (1 << 11)
113 #define PMX_GPT0_TMR0_MASK (1 << 12)
114 #define PMX_GPT0_TMR1_MASK (1 << 13)
115 #define PMX_GPT1_TMR0_MASK (1 << 14)
116 #define PMX_GPT1_TMR1_MASK (1 << 15)
117 #define PMX_I2S1_MASK (1 << 16)
118 #define PMX_KBD_ROWCOL25_MASK (1 << 17)
119 #define PMX_NFIO8_15_MASK (1 << 18)
120 #define PMX_KBD_COL1_MASK (1 << 19)
121 #define PMX_NFCE1_MASK (1 << 20)
122 #define PMX_KBD_COL0_MASK (1 << 21)
123 #define PMX_NFCE2_MASK (1 << 22)
124 #define PMX_KBD_ROW1_MASK (1 << 23)
125 #define PMX_NFWPRT1_MASK (1 << 24)
126 #define PMX_KBD_ROW0_MASK (1 << 25)
127 #define PMX_NFWPRT2_MASK (1 << 26)
128 #define PMX_MCIDATA0_MASK (1 << 27)
129 #define PMX_MCIDATA1_MASK (1 << 28)
130 #define PMX_MCIDATA2_MASK (1 << 29)
131 #define PMX_MCIDATA3_MASK (1 << 30)
132 #define PMX_MCIDATA4_MASK (1 << 31)
133
134#define PAD_FUNCTION_EN_2 0x658
135 #define PMX_MCIDATA5_MASK (1 << 0)
136 #define PMX_MCIDATA6_MASK (1 << 1)
137 #define PMX_MCIDATA7_MASK (1 << 2)
138 #define PMX_MCIDATA1SD_MASK (1 << 3)
139 #define PMX_MCIDATA2SD_MASK (1 << 4)
140 #define PMX_MCIDATA3SD_MASK (1 << 5)
141 #define PMX_MCIADDR0ALE_MASK (1 << 6)
142 #define PMX_MCIADDR1CLECLK_MASK (1 << 7)
143 #define PMX_MCIADDR2_MASK (1 << 8)
144 #define PMX_MCICECF_MASK (1 << 9)
145 #define PMX_MCICEXD_MASK (1 << 10)
146 #define PMX_MCICESDMMC_MASK (1 << 11)
147 #define PMX_MCICDCF1_MASK (1 << 12)
148 #define PMX_MCICDCF2_MASK (1 << 13)
149 #define PMX_MCICDXD_MASK (1 << 14)
150 #define PMX_MCICDSDMMC_MASK (1 << 15)
151 #define PMX_MCIDATADIR_MASK (1 << 16)
152 #define PMX_MCIDMARQWP_MASK (1 << 17)
153 #define PMX_MCIIORDRE_MASK (1 << 18)
154 #define PMX_MCIIOWRWE_MASK (1 << 19)
155 #define PMX_MCIRESETCF_MASK (1 << 20)
156 #define PMX_MCICS0CE_MASK (1 << 21)
157 #define PMX_MCICFINTR_MASK (1 << 22)
158 #define PMX_MCIIORDY_MASK (1 << 23)
159 #define PMX_MCICS1_MASK (1 << 24)
160 #define PMX_MCIDMAACK_MASK (1 << 25)
161 #define PMX_MCISDCMD_MASK (1 << 26)
162 #define PMX_MCILEDS_MASK (1 << 27)
163 #define PMX_TOUCH_XY_MASK (1 << 28)
164 #define PMX_SSP0_CS0_MASK (1 << 29)
165 #define PMX_SSP0_CS1_2_MASK (1 << 30)
166
167/* combined macros */
168#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
169 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
170 PMX_RXCLK_RDV_TXEN_D03_MASK | \
171 PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
172
173#define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
174 PMX_EGPIO02_MASK | \
175 PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
176 PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \
177 PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \
178 PMX_EGPIO09_MASK)
179#define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
180 PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \
181 PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
182
183#define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
184 PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
185 PMX_KBD_COL1_MASK)
186
187#define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \
188 PMX_NFAD24_MASK | PMX_NFAD25_MASK | \
189 PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
190 PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
191 PMX_NFCE3_MASK)
192#define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK
193
194#define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
195#define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \
196 PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \
197 PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
198 PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
199
200#define PMX_MCIFALL_1_MASK 0xF8000000
201#define PMX_MCIFALL_2_MASK 0x0FFFFFFF
202
203#define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \
204 PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
205 PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
206 PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
207 PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \
208 PMX_NFCE2_MASK)
209#define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
210 PMX_SSP0_CS1_2_MASK)
211
212#define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
213#define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \
214 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
215 PMX_GMIID47_MASK)
216#define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
217 PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \
218 PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
219#define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
220 PMX_SSP0_CS1_2_MASK)
221
222#define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \
223 PCIE##x##_CFG_AUX_CLK_EN | \
224 PCIE##x##_CFG_CORE_CLK_EN | \
225 PCIE##x##_CFG_POWERUP_RESET | \
226 PCIE##x##_CFG_DEVICE_PRESENT)
227#define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \
228 SATA##x##_CFG_PM_CLK_EN | \
229 SATA##x##_CFG_POWERUP_RESET | \
230 SATA##x##_CFG_RX_CLK_EN | \
231 SATA##x##_CFG_TX_CLK_EN)
232
233/* Pad multiplexing for i2c0 device */
234static const unsigned i2c0_pins[] = { 102, 103 };
235static struct spear_muxreg i2c0_muxreg[] = {
236 {
237 .reg = PAD_FUNCTION_EN_0,
238 .mask = PMX_I2C0_MASK,
239 .val = PMX_I2C0_MASK,
240 },
241};
242
243static struct spear_modemux i2c0_modemux[] = {
244 {
245 .muxregs = i2c0_muxreg,
246 .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
247 },
248};
249
250static struct spear_pingroup i2c0_pingroup = {
251 .name = "i2c0_grp",
252 .pins = i2c0_pins,
253 .npins = ARRAY_SIZE(i2c0_pins),
254 .modemuxs = i2c0_modemux,
255 .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
256};
257
258static const char *const i2c0_grps[] = { "i2c0_grp" };
259static struct spear_function i2c0_function = {
260 .name = "i2c0",
261 .groups = i2c0_grps,
262 .ngroups = ARRAY_SIZE(i2c0_grps),
263};
264
265/* Pad multiplexing for ssp0 device */
266static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
267static struct spear_muxreg ssp0_muxreg[] = {
268 {
269 .reg = PAD_FUNCTION_EN_0,
270 .mask = PMX_SSP0_MASK,
271 .val = PMX_SSP0_MASK,
272 },
273};
274
275static struct spear_modemux ssp0_modemux[] = {
276 {
277 .muxregs = ssp0_muxreg,
278 .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
279 },
280};
281
282static struct spear_pingroup ssp0_pingroup = {
283 .name = "ssp0_grp",
284 .pins = ssp0_pins,
285 .npins = ARRAY_SIZE(ssp0_pins),
286 .modemuxs = ssp0_modemux,
287 .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
288};
289
290/* Pad multiplexing for ssp0_cs0 device */
291static const unsigned ssp0_cs0_pins[] = { 96 };
292static struct spear_muxreg ssp0_cs0_muxreg[] = {
293 {
294 .reg = PAD_FUNCTION_EN_2,
295 .mask = PMX_SSP0_CS0_MASK,
296 .val = PMX_SSP0_CS0_MASK,
297 },
298};
299
300static struct spear_modemux ssp0_cs0_modemux[] = {
301 {
302 .muxregs = ssp0_cs0_muxreg,
303 .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
304 },
305};
306
307static struct spear_pingroup ssp0_cs0_pingroup = {
308 .name = "ssp0_cs0_grp",
309 .pins = ssp0_cs0_pins,
310 .npins = ARRAY_SIZE(ssp0_cs0_pins),
311 .modemuxs = ssp0_cs0_modemux,
312 .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
313};
314
315/* ssp0_cs1_2 device */
316static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
317static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
318 {
319 .reg = PAD_FUNCTION_EN_2,
320 .mask = PMX_SSP0_CS1_2_MASK,
321 .val = PMX_SSP0_CS1_2_MASK,
322 },
323};
324
325static struct spear_modemux ssp0_cs1_2_modemux[] = {
326 {
327 .muxregs = ssp0_cs1_2_muxreg,
328 .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
329 },
330};
331
332static struct spear_pingroup ssp0_cs1_2_pingroup = {
333 .name = "ssp0_cs1_2_grp",
334 .pins = ssp0_cs1_2_pins,
335 .npins = ARRAY_SIZE(ssp0_cs1_2_pins),
336 .modemuxs = ssp0_cs1_2_modemux,
337 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
338};
339
340static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
341 "ssp0_cs1_2_grp" };
342static struct spear_function ssp0_function = {
343 .name = "ssp0",
344 .groups = ssp0_grps,
345 .ngroups = ARRAY_SIZE(ssp0_grps),
346};
347
348/* Pad multiplexing for i2s0 device */
349static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
350static struct spear_muxreg i2s0_muxreg[] = {
351 {
352 .reg = PAD_FUNCTION_EN_0,
353 .mask = PMX_I2S0_MASK,
354 .val = PMX_I2S0_MASK,
355 },
356};
357
358static struct spear_modemux i2s0_modemux[] = {
359 {
360 .muxregs = i2s0_muxreg,
361 .nmuxregs = ARRAY_SIZE(i2s0_muxreg),
362 },
363};
364
365static struct spear_pingroup i2s0_pingroup = {
366 .name = "i2s0_grp",
367 .pins = i2s0_pins,
368 .npins = ARRAY_SIZE(i2s0_pins),
369 .modemuxs = i2s0_modemux,
370 .nmodemuxs = ARRAY_SIZE(i2s0_modemux),
371};
372
373static const char *const i2s0_grps[] = { "i2s0_grp" };
374static struct spear_function i2s0_function = {
375 .name = "i2s0",
376 .groups = i2s0_grps,
377 .ngroups = ARRAY_SIZE(i2s0_grps),
378};
379
380/* Pad multiplexing for i2s1 device */
381static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
382static struct spear_muxreg i2s1_muxreg[] = {
383 {
384 .reg = PAD_FUNCTION_EN_1,
385 .mask = PMX_I2S1_MASK,
386 .val = PMX_I2S1_MASK,
387 },
388};
389
390static struct spear_modemux i2s1_modemux[] = {
391 {
392 .muxregs = i2s1_muxreg,
393 .nmuxregs = ARRAY_SIZE(i2s1_muxreg),
394 },
395};
396
397static struct spear_pingroup i2s1_pingroup = {
398 .name = "i2s1_grp",
399 .pins = i2s1_pins,
400 .npins = ARRAY_SIZE(i2s1_pins),
401 .modemuxs = i2s1_modemux,
402 .nmodemuxs = ARRAY_SIZE(i2s1_modemux),
403};
404
405static const char *const i2s1_grps[] = { "i2s1_grp" };
406static struct spear_function i2s1_function = {
407 .name = "i2s1",
408 .groups = i2s1_grps,
409 .ngroups = ARRAY_SIZE(i2s1_grps),
410};
411
412/* Pad multiplexing for clcd device */
413static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
414 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
415 135, 136, 137, 138, 139, 140, 141, 142 };
416static struct spear_muxreg clcd_muxreg[] = {
417 {
418 .reg = PAD_FUNCTION_EN_0,
419 .mask = PMX_CLCD1_MASK,
420 .val = PMX_CLCD1_MASK,
421 },
422};
423
424static struct spear_modemux clcd_modemux[] = {
425 {
426 .muxregs = clcd_muxreg,
427 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
428 },
429};
430
431static struct spear_pingroup clcd_pingroup = {
432 .name = "clcd_grp",
433 .pins = clcd_pins,
434 .npins = ARRAY_SIZE(clcd_pins),
435 .modemuxs = clcd_modemux,
436 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
437};
438
439static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
eb3f995d 440 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
85ed41a7
VK		 441static struct spear_muxreg clcd_high_res_muxreg[] = {
442 {
443 .reg = PAD_FUNCTION_EN_1,
444 .mask = PMX_CLCD2_MASK,
445 .val = PMX_CLCD2_MASK,
446 },
447};
448
449static struct spear_modemux clcd_high_res_modemux[] = {
450 {
451 .muxregs = clcd_high_res_muxreg,
452 .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
453 },
454};
455
456static struct spear_pingroup clcd_high_res_pingroup = {
457 .name = "clcd_high_res_grp",
458 .pins = clcd_high_res_pins,
459 .npins = ARRAY_SIZE(clcd_high_res_pins),
460 .modemuxs = clcd_high_res_modemux,
461 .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
462};
463
464static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res" };
465static struct spear_function clcd_function = {
466 .name = "clcd",
467 .groups = clcd_grps,
468 .ngroups = ARRAY_SIZE(clcd_grps),
469};
470
471static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
472 146, 147, 148, 149, 150, 151, 152 };
473static struct spear_muxreg arm_gpio_muxreg[] = {
474 {
475 .reg = PAD_FUNCTION_EN_0,
476 .mask = PMX_EGPIO_0_GRP_MASK,
477 .val = PMX_EGPIO_0_GRP_MASK,
478 }, {
479 .reg = PAD_FUNCTION_EN_1,
480 .mask = PMX_EGPIO_1_GRP_MASK,
481 .val = PMX_EGPIO_1_GRP_MASK,
482 },
483};
484
485static struct spear_modemux arm_gpio_modemux[] = {
486 {
487 .muxregs = arm_gpio_muxreg,
488 .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
489 },
490};
491
492static struct spear_pingroup arm_gpio_pingroup = {
493 .name = "arm_gpio_grp",
494 .pins = arm_gpio_pins,
495 .npins = ARRAY_SIZE(arm_gpio_pins),
496 .modemuxs = arm_gpio_modemux,
497 .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
498};
499
500static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
501static struct spear_function arm_gpio_function = {
502 .name = "arm_gpio",
503 .groups = arm_gpio_grps,
504 .ngroups = ARRAY_SIZE(arm_gpio_grps),
505};
506
507/* Pad multiplexing for smi 2 chips device */
508static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
509static struct spear_muxreg smi_2_chips_muxreg[] = {
510 {
511 .reg = PAD_FUNCTION_EN_0,
512 .mask = PMX_SMI_MASK,
513 .val = PMX_SMI_MASK,
514 },
515};
516
517static struct spear_modemux smi_2_chips_modemux[] = {
518 {
519 .muxregs = smi_2_chips_muxreg,
520 .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
521 },
522};
523
524static struct spear_pingroup smi_2_chips_pingroup = {
525 .name = "smi_2_chips_grp",
526 .pins = smi_2_chips_pins,
527 .npins = ARRAY_SIZE(smi_2_chips_pins),
528 .modemuxs = smi_2_chips_modemux,
529 .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
530};
531
532static const unsigned smi_4_chips_pins[] = { 54, 55 };
533static struct spear_muxreg smi_4_chips_muxreg[] = {
534 {
535 .reg = PAD_FUNCTION_EN_0,
536 .mask = PMX_SMI_MASK,
537 .val = PMX_SMI_MASK,
538 }, {
539 .reg = PAD_FUNCTION_EN_1,
540 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
541 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
542 },
543};
544
545static struct spear_modemux smi_4_chips_modemux[] = {
546 {
547 .muxregs = smi_4_chips_muxreg,
548 .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
549 },
550};
551
552static struct spear_pingroup smi_4_chips_pingroup = {
553 .name = "smi_4_chips_grp",
554 .pins = smi_4_chips_pins,
555 .npins = ARRAY_SIZE(smi_4_chips_pins),
556 .modemuxs = smi_4_chips_modemux,
557 .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
558};
559
560static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
561static struct spear_function smi_function = {
562 .name = "smi",
563 .groups = smi_grps,
564 .ngroups = ARRAY_SIZE(smi_grps),
565};
566
567/* Pad multiplexing for gmii device */
568static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
569 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
570 195, 196, 197, 198, 199, 200 };
571static struct spear_muxreg gmii_muxreg[] = {
572 {
573 .reg = PAD_FUNCTION_EN_0,
574 .mask = PMX_GMII_MASK,
575 .val = PMX_GMII_MASK,
576 },
577};
578
579static struct spear_modemux gmii_modemux[] = {
580 {
581 .muxregs = gmii_muxreg,
582 .nmuxregs = ARRAY_SIZE(gmii_muxreg),
583 },
584};
585
586static struct spear_pingroup gmii_pingroup = {
587 .name = "gmii_grp",
588 .pins = gmii_pins,
589 .npins = ARRAY_SIZE(gmii_pins),
590 .modemuxs = gmii_modemux,
591 .nmodemuxs = ARRAY_SIZE(gmii_modemux),
592};
593
594static const char *const gmii_grps[] = { "gmii_grp" };
595static struct spear_function gmii_function = {
596 .name = "gmii",
597 .groups = gmii_grps,
598 .ngroups = ARRAY_SIZE(gmii_grps),
599};
600
601/* Pad multiplexing for rgmii device */
602static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
603 28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
604 180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
605static struct spear_muxreg rgmii_muxreg[] = {
606 {
607 .reg = PAD_FUNCTION_EN_0,
608 .mask = PMX_RGMII_REG0_MASK,
609 .val = 0,
610 }, {
611 .reg = PAD_FUNCTION_EN_1,
612 .mask = PMX_RGMII_REG1_MASK,
613 .val = 0,
614 }, {
615 .reg = PAD_FUNCTION_EN_2,
616 .mask = PMX_RGMII_REG2_MASK,
617 .val = 0,
618 },
619};
620
621static struct spear_modemux rgmii_modemux[] = {
622 {
623 .muxregs = rgmii_muxreg,
624 .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
625 },
626};
627
628static struct spear_pingroup rgmii_pingroup = {
629 .name = "rgmii_grp",
630 .pins = rgmii_pins,
631 .npins = ARRAY_SIZE(rgmii_pins),
632 .modemuxs = rgmii_modemux,
633 .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
634};
635
636static const char *const rgmii_grps[] = { "rgmii_grp" };
637static struct spear_function rgmii_function = {
638 .name = "rgmii",
639 .groups = rgmii_grps,
640 .ngroups = ARRAY_SIZE(rgmii_grps),
641};
642
643/* Pad multiplexing for smii_0_1_2 device */
644static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
645 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
646 51, 52, 53, 54, 55 };
647static struct spear_muxreg smii_0_1_2_muxreg[] = {
648 {
649 .reg = PAD_FUNCTION_EN_1,
650 .mask = PMX_SMII_0_1_2_MASK,
651 .val = 0,
652 },
653};
654
655static struct spear_modemux smii_0_1_2_modemux[] = {
656 {
657 .muxregs = smii_0_1_2_muxreg,
658 .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
659 },
660};
661
662static struct spear_pingroup smii_0_1_2_pingroup = {
663 .name = "smii_0_1_2_grp",
664 .pins = smii_0_1_2_pins,
665 .npins = ARRAY_SIZE(smii_0_1_2_pins),
666 .modemuxs = smii_0_1_2_modemux,
667 .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
668};
669
670static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
671static struct spear_function smii_0_1_2_function = {
672 .name = "smii_0_1_2",
673 .groups = smii_0_1_2_grps,
674 .ngroups = ARRAY_SIZE(smii_0_1_2_grps),
675};
676
677/* Pad multiplexing for ras_mii_txclk device */
678static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
679static struct spear_muxreg ras_mii_txclk_muxreg[] = {
680 {
681 .reg = PAD_FUNCTION_EN_1,
682 .mask = PMX_NFCE2_MASK,
683 .val = 0,
684 },
685};
686
687static struct spear_modemux ras_mii_txclk_modemux[] = {
688 {
689 .muxregs = ras_mii_txclk_muxreg,
690 .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
691 },
692};
693
694static struct spear_pingroup ras_mii_txclk_pingroup = {
695 .name = "ras_mii_txclk_grp",
696 .pins = ras_mii_txclk_pins,
697 .npins = ARRAY_SIZE(ras_mii_txclk_pins),
698 .modemuxs = ras_mii_txclk_modemux,
699 .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
700};
701
702static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
703static struct spear_function ras_mii_txclk_function = {
704 .name = "ras_mii_txclk",
705 .groups = ras_mii_txclk_grps,
706 .ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
707};
708
709/* Pad multiplexing for nand 8bit device (cs0 only) */
710static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
711 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
712 83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
713 170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
714 212 };
715static struct spear_muxreg nand_8bit_muxreg[] = {
716 {
717 .reg = PAD_FUNCTION_EN_0,
718 .mask = PMX_NAND8BIT_0_MASK,
719 .val = PMX_NAND8BIT_0_MASK,
720 }, {
721 .reg = PAD_FUNCTION_EN_1,
722 .mask = PMX_NAND8BIT_1_MASK,
723 .val = PMX_NAND8BIT_1_MASK,
724 },
725};
726
727static struct spear_modemux nand_8bit_modemux[] = {
728 {
729 .muxregs = nand_8bit_muxreg,
730 .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
731 },
732};
733
734static struct spear_pingroup nand_8bit_pingroup = {
735 .name = "nand_8bit_grp",
736 .pins = nand_8bit_pins,
737 .npins = ARRAY_SIZE(nand_8bit_pins),
738 .modemuxs = nand_8bit_modemux,
739 .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
740};
741
742/* Pad multiplexing for nand 16bit device */
743static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
744 210 };
745static struct spear_muxreg nand_16bit_muxreg[] = {
746 {
747 .reg = PAD_FUNCTION_EN_1,
748 .mask = PMX_NAND16BIT_1_MASK,
749 .val = PMX_NAND16BIT_1_MASK,
750 },
751};
752
753static struct spear_modemux nand_16bit_modemux[] = {
754 {
755 .muxregs = nand_16bit_muxreg,
756 .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
757 },
758};
759
760static struct spear_pingroup nand_16bit_pingroup = {
761 .name = "nand_16bit_grp",
762 .pins = nand_16bit_pins,
763 .npins = ARRAY_SIZE(nand_16bit_pins),
764 .modemuxs = nand_16bit_modemux,
765 .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
766};
767
768/* Pad multiplexing for nand 4 chips */
769static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
770static struct spear_muxreg nand_4_chips_muxreg[] = {
771 {
772 .reg = PAD_FUNCTION_EN_1,
773 .mask = PMX_NAND_4CHIPS_MASK,
774 .val = PMX_NAND_4CHIPS_MASK,
775 },
776};
777
778static struct spear_modemux nand_4_chips_modemux[] = {
779 {
780 .muxregs = nand_4_chips_muxreg,
781 .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
782 },
783};
784
785static struct spear_pingroup nand_4_chips_pingroup = {
786 .name = "nand_4_chips_grp",
787 .pins = nand_4_chips_pins,
788 .npins = ARRAY_SIZE(nand_4_chips_pins),
789 .modemuxs = nand_4_chips_modemux,
790 .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
791};
792
793static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
794 "nand_4_chips_grp" };
795static struct spear_function nand_function = {
796 .name = "nand",
797 .groups = nand_grps,
798 .ngroups = ARRAY_SIZE(nand_grps),
799};
800
801/* Pad multiplexing for keyboard_6x6 device */
802static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
803 208, 209, 210, 211, 212 };
804static struct spear_muxreg keyboard_6x6_muxreg[] = {
805 {
806 .reg = PAD_FUNCTION_EN_1,
807 .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
808 PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
809 PMX_NFWPRT2_MASK,
810 .val = PMX_KEYBOARD_6X6_MASK,
811 },
812};
813
814static struct spear_modemux keyboard_6x6_modemux[] = {
815 {
816 .muxregs = keyboard_6x6_muxreg,
817 .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
818 },
819};
820
821static struct spear_pingroup keyboard_6x6_pingroup = {
822 .name = "keyboard_6x6_grp",
823 .pins = keyboard_6x6_pins,
824 .npins = ARRAY_SIZE(keyboard_6x6_pins),
825 .modemuxs = keyboard_6x6_modemux,
826 .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
827};
828
829/* Pad multiplexing for keyboard_rowcol6_8 device */
830static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
831static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
832 {
833 .reg = PAD_FUNCTION_EN_1,
834 .mask = PMX_KBD_ROWCOL68_MASK,
835 .val = PMX_KBD_ROWCOL68_MASK,
836 },
837};
838
839static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
840 {
841 .muxregs = keyboard_rowcol6_8_muxreg,
842 .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
843 },
844};
845
846static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
847 .name = "keyboard_rowcol6_8_grp",
848 .pins = keyboard_rowcol6_8_pins,
849 .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
850 .modemuxs = keyboard_rowcol6_8_modemux,
851 .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
852};
853
854static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
855 "keyboard_rowcol6_8_grp" };
856static struct spear_function keyboard_function = {
857 .name = "keyboard",
858 .groups = keyboard_grps,
859 .ngroups = ARRAY_SIZE(keyboard_grps),
860};
861
862/* Pad multiplexing for uart0 device */
863static const unsigned uart0_pins[] = { 100, 101 };
864static struct spear_muxreg uart0_muxreg[] = {
865 {
866 .reg = PAD_FUNCTION_EN_0,
867 .mask = PMX_UART0_MASK,
868 .val = PMX_UART0_MASK,
869 },
870};
871
872static struct spear_modemux uart0_modemux[] = {
873 {
874 .muxregs = uart0_muxreg,
875 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
876 },
877};
878
879static struct spear_pingroup uart0_pingroup = {
880 .name = "uart0_grp",
881 .pins = uart0_pins,
882 .npins = ARRAY_SIZE(uart0_pins),
883 .modemuxs = uart0_modemux,
884 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
885};
886
887/* Pad multiplexing for uart0_modem device */
888static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
889static struct spear_muxreg uart0_modem_muxreg[] = {
890 {
891 .reg = PAD_FUNCTION_EN_1,
892 .mask = PMX_UART0_MODEM_MASK,
893 .val = PMX_UART0_MODEM_MASK,
894 },
895};
896
897static struct spear_modemux uart0_modem_modemux[] = {
898 {
899 .muxregs = uart0_modem_muxreg,
900 .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
901 },
902};
903
904static struct spear_pingroup uart0_modem_pingroup = {
905 .name = "uart0_modem_grp",
906 .pins = uart0_modem_pins,
907 .npins = ARRAY_SIZE(uart0_modem_pins),
908 .modemuxs = uart0_modem_modemux,
909 .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
910};
911
912static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
913static struct spear_function uart0_function = {
914 .name = "uart0",
915 .groups = uart0_grps,
916 .ngroups = ARRAY_SIZE(uart0_grps),
917};
918
919/* Pad multiplexing for gpt0_tmr0 device */
920static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
921static struct spear_muxreg gpt0_tmr0_muxreg[] = {
922 {
923 .reg = PAD_FUNCTION_EN_1,
924 .mask = PMX_GPT0_TMR0_MASK,
925 .val = PMX_GPT0_TMR0_MASK,
926 },
927};
928
929static struct spear_modemux gpt0_tmr0_modemux[] = {
930 {
931 .muxregs = gpt0_tmr0_muxreg,
932 .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
933 },
934};
935
936static struct spear_pingroup gpt0_tmr0_pingroup = {
937 .name = "gpt0_tmr0_grp",
938 .pins = gpt0_tmr0_pins,
939 .npins = ARRAY_SIZE(gpt0_tmr0_pins),
940 .modemuxs = gpt0_tmr0_modemux,
941 .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
942};
943
944/* Pad multiplexing for gpt0_tmr1 device */
945static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
946static struct spear_muxreg gpt0_tmr1_muxreg[] = {
947 {
948 .reg = PAD_FUNCTION_EN_1,
949 .mask = PMX_GPT0_TMR1_MASK,
950 .val = PMX_GPT0_TMR1_MASK,
951 },
952};
953
954static struct spear_modemux gpt0_tmr1_modemux[] = {
955 {
956 .muxregs = gpt0_tmr1_muxreg,
957 .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
958 },
959};
960
961static struct spear_pingroup gpt0_tmr1_pingroup = {
962 .name = "gpt0_tmr1_grp",
963 .pins = gpt0_tmr1_pins,
964 .npins = ARRAY_SIZE(gpt0_tmr1_pins),
965 .modemuxs = gpt0_tmr1_modemux,
966 .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
967};
968
969static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
970static struct spear_function gpt0_function = {
971 .name = "gpt0",
972 .groups = gpt0_grps,
973 .ngroups = ARRAY_SIZE(gpt0_grps),
974};
975
976/* Pad multiplexing for gpt1_tmr0 device */
977static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
978static struct spear_muxreg gpt1_tmr0_muxreg[] = {
979 {
980 .reg = PAD_FUNCTION_EN_1,
981 .mask = PMX_GPT1_TMR0_MASK,
982 .val = PMX_GPT1_TMR0_MASK,
983 },
984};
985
986static struct spear_modemux gpt1_tmr0_modemux[] = {
987 {
988 .muxregs = gpt1_tmr0_muxreg,
989 .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
990 },
991};
992
993static struct spear_pingroup gpt1_tmr0_pingroup = {
994 .name = "gpt1_tmr0_grp",
995 .pins = gpt1_tmr0_pins,
996 .npins = ARRAY_SIZE(gpt1_tmr0_pins),
997 .modemuxs = gpt1_tmr0_modemux,
998 .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
999};
1000
1001/* Pad multiplexing for gpt1_tmr1 device */
1002static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
1003static struct spear_muxreg gpt1_tmr1_muxreg[] = {
1004 {
1005 .reg = PAD_FUNCTION_EN_1,
1006 .mask = PMX_GPT1_TMR1_MASK,
1007 .val = PMX_GPT1_TMR1_MASK,
1008 },
1009};
1010
1011static struct spear_modemux gpt1_tmr1_modemux[] = {
1012 {
1013 .muxregs = gpt1_tmr1_muxreg,
1014 .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
1015 },
1016};
1017
1018static struct spear_pingroup gpt1_tmr1_pingroup = {
1019 .name = "gpt1_tmr1_grp",
1020 .pins = gpt1_tmr1_pins,
1021 .npins = ARRAY_SIZE(gpt1_tmr1_pins),
1022 .modemuxs = gpt1_tmr1_modemux,
1023 .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
1024};
1025
1026static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
1027static struct spear_function gpt1_function = {
1028 .name = "gpt1",
1029 .groups = gpt1_grps,
1030 .ngroups = ARRAY_SIZE(gpt1_grps),
1031};
1032
1033/* Pad multiplexing for mcif device */
1034static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
1035 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
1036 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
1037 243, 244, 245 };
1038#define MCIF_MUXREG \
1039 { \
1040 .reg = PAD_FUNCTION_EN_0, \
1041 .mask = PMX_MCI_DATA8_15_MASK, \
1042 .val = PMX_MCI_DATA8_15_MASK, \
1043 }, { \
1044 .reg = PAD_FUNCTION_EN_1, \
1045 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1046 PMX_NFWPRT2_MASK, \
1047 .val = PMX_MCIFALL_1_MASK, \
1048 }, { \
1049 .reg = PAD_FUNCTION_EN_2, \
1050 .mask = PMX_MCIFALL_2_MASK, \
1051 .val = PMX_MCIFALL_2_MASK, \
1052 }
1053
1054/* sdhci device */
1055static struct spear_muxreg sdhci_muxreg[] = {
1056 MCIF_MUXREG,
1057 {
1058 .reg = PERIP_CFG,
1059 .mask = MCIF_SEL_MASK,
1060 .val = MCIF_SEL_SD,
1061 },
1062};
1063
1064static struct spear_modemux sdhci_modemux[] = {
1065 {
1066 .muxregs = sdhci_muxreg,
1067 .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
1068 },
1069};
1070
1071static struct spear_pingroup sdhci_pingroup = {
1072 .name = "sdhci_grp",
1073 .pins = mcif_pins,
1074 .npins = ARRAY_SIZE(mcif_pins),
1075 .modemuxs = sdhci_modemux,
1076 .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
1077};
1078
1079static const char *const sdhci_grps[] = { "sdhci_grp" };
1080static struct spear_function sdhci_function = {
1081 .name = "sdhci",
1082 .groups = sdhci_grps,
1083 .ngroups = ARRAY_SIZE(sdhci_grps),
1084};
1085
1086/* cf device */
1087static struct spear_muxreg cf_muxreg[] = {
1088 MCIF_MUXREG,
1089 {
1090 .reg = PERIP_CFG,
1091 .mask = MCIF_SEL_MASK,
1092 .val = MCIF_SEL_CF,
1093 },
1094};
1095
1096static struct spear_modemux cf_modemux[] = {
1097 {
1098 .muxregs = cf_muxreg,
1099 .nmuxregs = ARRAY_SIZE(cf_muxreg),
1100 },
1101};
1102
1103static struct spear_pingroup cf_pingroup = {
1104 .name = "cf_grp",
1105 .pins = mcif_pins,
1106 .npins = ARRAY_SIZE(mcif_pins),
1107 .modemuxs = cf_modemux,
1108 .nmodemuxs = ARRAY_SIZE(cf_modemux),
1109};
1110
1111static const char *const cf_grps[] = { "cf_grp" };
1112static struct spear_function cf_function = {
1113 .name = "cf",
1114 .groups = cf_grps,
1115 .ngroups = ARRAY_SIZE(cf_grps),
1116};
1117
1118/* xd device */
1119static struct spear_muxreg xd_muxreg[] = {
1120 MCIF_MUXREG,
1121 {
1122 .reg = PERIP_CFG,
1123 .mask = MCIF_SEL_MASK,
1124 .val = MCIF_SEL_XD,
1125 },
1126};
1127
1128static struct spear_modemux xd_modemux[] = {
1129 {
1130 .muxregs = xd_muxreg,
1131 .nmuxregs = ARRAY_SIZE(xd_muxreg),
1132 },
1133};
1134
1135static struct spear_pingroup xd_pingroup = {
1136 .name = "xd_grp",
1137 .pins = mcif_pins,
1138 .npins = ARRAY_SIZE(mcif_pins),
1139 .modemuxs = xd_modemux,
1140 .nmodemuxs = ARRAY_SIZE(xd_modemux),
1141};
1142
1143static const char *const xd_grps[] = { "xd_grp" };
1144static struct spear_function xd_function = {
1145 .name = "xd",
1146 .groups = xd_grps,
1147 .ngroups = ARRAY_SIZE(xd_grps),
1148};
1149
1150/* Pad multiplexing for touch_xy device */
1151static const unsigned touch_xy_pins[] = { 97 };
1152static struct spear_muxreg touch_xy_muxreg[] = {
1153 {
1154 .reg = PAD_FUNCTION_EN_2,
1155 .mask = PMX_TOUCH_XY_MASK,
1156 .val = PMX_TOUCH_XY_MASK,
1157 },
1158};
1159
1160static struct spear_modemux touch_xy_modemux[] = {
1161 {
1162 .muxregs = touch_xy_muxreg,
1163 .nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
1164 },
1165};
1166
1167static struct spear_pingroup touch_xy_pingroup = {
1168 .name = "touch_xy_grp",
1169 .pins = touch_xy_pins,
1170 .npins = ARRAY_SIZE(touch_xy_pins),
1171 .modemuxs = touch_xy_modemux,
1172 .nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
1173};
1174
1175static const char *const touch_xy_grps[] = { "touch_xy_grp" };
1176static struct spear_function touch_xy_function = {
1177 .name = "touchscreen",
1178 .groups = touch_xy_grps,
1179 .ngroups = ARRAY_SIZE(touch_xy_grps),
1180};
1181
1182/* Pad multiplexing for uart1 device */
1183/* Muxed with I2C */
1184static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
1185static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
1186 {
1187 .reg = PAD_FUNCTION_EN_0,
1188 .mask = PMX_I2C0_MASK,
1189 .val = 0,
1190 },
1191};
1192
1193static struct spear_modemux uart1_dis_i2c_modemux[] = {
1194 {
1195 .muxregs = uart1_dis_i2c_muxreg,
1196 .nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
1197 },
1198};
1199
1200static struct spear_pingroup uart_1_dis_i2c_pingroup = {
1201 .name = "uart1_disable_i2c_grp",
1202 .pins = uart1_dis_i2c_pins,
1203 .npins = ARRAY_SIZE(uart1_dis_i2c_pins),
1204 .modemuxs = uart1_dis_i2c_modemux,
1205 .nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
1206};
1207
1208/* Muxed with SD/MMC */
1209static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
1210static struct spear_muxreg uart1_dis_sd_muxreg[] = {
1211 {
1212 .reg = PAD_FUNCTION_EN_1,
1213 .mask = PMX_MCIDATA1_MASK |
1214 PMX_MCIDATA2_MASK,
1215 .val = 0,
1216 },
1217};
1218
1219static struct spear_modemux uart1_dis_sd_modemux[] = {
1220 {
1221 .muxregs = uart1_dis_sd_muxreg,
1222 .nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
1223 },
1224};
1225
1226static struct spear_pingroup uart_1_dis_sd_pingroup = {
1227 .name = "uart1_disable_sd_grp",
1228 .pins = uart1_dis_sd_pins,
1229 .npins = ARRAY_SIZE(uart1_dis_sd_pins),
1230 .modemuxs = uart1_dis_sd_modemux,
1231 .nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
1232};
1233
1234static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
1235 "uart1_disable_sd_grp" };
1236static struct spear_function uart1_function = {
1237 .name = "uart1",
1238 .groups = uart1_grps,
1239 .ngroups = ARRAY_SIZE(uart1_grps),
1240};
1241
1242/* Pad multiplexing for uart2_3 device */
1243static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
1244static struct spear_muxreg uart2_3_muxreg[] = {
1245 {
1246 .reg = PAD_FUNCTION_EN_0,
1247 .mask = PMX_I2S0_MASK,
1248 .val = 0,
1249 },
1250};
1251
1252static struct spear_modemux uart2_3_modemux[] = {
1253 {
1254 .muxregs = uart2_3_muxreg,
1255 .nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
1256 },
1257};
1258
1259static struct spear_pingroup uart_2_3_pingroup = {
1260 .name = "uart2_3_grp",
1261 .pins = uart2_3_pins,
1262 .npins = ARRAY_SIZE(uart2_3_pins),
1263 .modemuxs = uart2_3_modemux,
1264 .nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
1265};
1266
1267static const char *const uart2_3_grps[] = { "uart2_3_grp" };
1268static struct spear_function uart2_3_function = {
1269 .name = "uart2_3",
1270 .groups = uart2_3_grps,
1271 .ngroups = ARRAY_SIZE(uart2_3_grps),
1272};
1273
1274/* Pad multiplexing for uart4 device */
1275static const unsigned uart4_pins[] = { 108, 113 };
1276static struct spear_muxreg uart4_muxreg[] = {
1277 {
1278 .reg = PAD_FUNCTION_EN_0,
1279 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1280 .val = 0,
1281 },
1282};
1283
1284static struct spear_modemux uart4_modemux[] = {
1285 {
1286 .muxregs = uart4_muxreg,
1287 .nmuxregs = ARRAY_SIZE(uart4_muxreg),
1288 },
1289};
1290
1291static struct spear_pingroup uart_4_pingroup = {
1292 .name = "uart4_grp",
1293 .pins = uart4_pins,
1294 .npins = ARRAY_SIZE(uart4_pins),
1295 .modemuxs = uart4_modemux,
1296 .nmodemuxs = ARRAY_SIZE(uart4_modemux),
1297};
1298
1299static const char *const uart4_grps[] = { "uart4_grp" };
1300static struct spear_function uart4_function = {
1301 .name = "uart4",
1302 .groups = uart4_grps,
1303 .ngroups = ARRAY_SIZE(uart4_grps),
1304};
1305
1306/* Pad multiplexing for uart5 device */
1307static const unsigned uart5_pins[] = { 114, 115 };
1308static struct spear_muxreg uart5_muxreg[] = {
1309 {
1310 .reg = PAD_FUNCTION_EN_0,
1311 .mask = PMX_CLCD1_MASK,
1312 .val = 0,
1313 },
1314};
1315
1316static struct spear_modemux uart5_modemux[] = {
1317 {
1318 .muxregs = uart5_muxreg,
1319 .nmuxregs = ARRAY_SIZE(uart5_muxreg),
1320 },
1321};
1322
1323static struct spear_pingroup uart_5_pingroup = {
1324 .name = "uart5_grp",
1325 .pins = uart5_pins,
1326 .npins = ARRAY_SIZE(uart5_pins),
1327 .modemuxs = uart5_modemux,
1328 .nmodemuxs = ARRAY_SIZE(uart5_modemux),
1329};
1330
1331static const char *const uart5_grps[] = { "uart5_grp" };
1332static struct spear_function uart5_function = {
1333 .name = "uart5",
1334 .groups = uart5_grps,
1335 .ngroups = ARRAY_SIZE(uart5_grps),
1336};
1337
1338/* Pad multiplexing for rs485_0_1_tdm_0_1 device */
1339static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
1340 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
1341 136, 137 };
1342static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
1343 {
1344 .reg = PAD_FUNCTION_EN_0,
1345 .mask = PMX_CLCD1_MASK,
1346 .val = 0,
1347 },
1348};
1349
1350static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
1351 {
1352 .muxregs = rs485_0_1_tdm_0_1_muxreg,
1353 .nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
1354 },
1355};
1356
1357static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
1358 .name = "rs485_0_1_tdm_0_1_grp",
1359 .pins = rs485_0_1_tdm_0_1_pins,
1360 .npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
1361 .modemuxs = rs485_0_1_tdm_0_1_modemux,
1362 .nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
1363};
1364
1365static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
1366static struct spear_function rs485_0_1_tdm_0_1_function = {
1367 .name = "rs485_0_1_tdm_0_1",
1368 .groups = rs485_0_1_tdm_0_1_grps,
1369 .ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
1370};
1371
1372/* Pad multiplexing for i2c_1_2 device */
1373static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
1374static struct spear_muxreg i2c_1_2_muxreg[] = {
1375 {
1376 .reg = PAD_FUNCTION_EN_0,
1377 .mask = PMX_CLCD1_MASK,
1378 .val = 0,
1379 },
1380};
1381
1382static struct spear_modemux i2c_1_2_modemux[] = {
1383 {
1384 .muxregs = i2c_1_2_muxreg,
1385 .nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
1386 },
1387};
1388
1389static struct spear_pingroup i2c_1_2_pingroup = {
1390 .name = "i2c_1_2_grp",
1391 .pins = i2c_1_2_pins,
1392 .npins = ARRAY_SIZE(i2c_1_2_pins),
1393 .modemuxs = i2c_1_2_modemux,
1394 .nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
1395};
1396
1397static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
1398static struct spear_function i2c_1_2_function = {
1399 .name = "i2c_1_2",
1400 .groups = i2c_1_2_grps,
1401 .ngroups = ARRAY_SIZE(i2c_1_2_grps),
1402};
1403
1404/* Pad multiplexing for i2c3_dis_smi_clcd device */
1405/* Muxed with SMI & CLCD */
1406static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
1407static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
1408 {
1409 .reg = PAD_FUNCTION_EN_0,
1410 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1411 .val = 0,
1412 },
1413};
1414
1415static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
1416 {
1417 .muxregs = i2c3_dis_smi_clcd_muxreg,
1418 .nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
1419 },
1420};
1421
1422static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
1423 .name = "i2c3_dis_smi_clcd_grp",
1424 .pins = i2c3_dis_smi_clcd_pins,
1425 .npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
1426 .modemuxs = i2c3_dis_smi_clcd_modemux,
1427 .nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
1428};
1429
1430/* Pad multiplexing for i2c3_dis_sd_i2s0 device */
1431/* Muxed with SD/MMC & I2S1 */
1432static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
1433static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
1434 {
1435 .reg = PAD_FUNCTION_EN_1,
1436 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1437 .val = 0,
1438 },
1439};
1440
1441static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
1442 {
1443 .muxregs = i2c3_dis_sd_i2s0_muxreg,
1444 .nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
1445 },
1446};
1447
1448static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
1449 .name = "i2c3_dis_sd_i2s0_grp",
1450 .pins = i2c3_dis_sd_i2s0_pins,
1451 .npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
1452 .modemuxs = i2c3_dis_sd_i2s0_modemux,
1453 .nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
1454};
1455
1456static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
1457 "i2c3_dis_sd_i2s0_grp" };
1458static struct spear_function i2c3_unction = {
1459 .name = "i2c3_i2s1",
1460 .groups = i2c3_grps,
1461 .ngroups = ARRAY_SIZE(i2c3_grps),
1462};
1463
1464/* Pad multiplexing for i2c_4_5_dis_smi device */
1465/* Muxed with SMI */
1466static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
1467static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
1468 {
1469 .reg = PAD_FUNCTION_EN_0,
1470 .mask = PMX_SMI_MASK,
1471 .val = 0,
1472 },
1473};
1474
1475static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
1476 {
1477 .muxregs = i2c_4_5_dis_smi_muxreg,
1478 .nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
1479 },
1480};
1481
1482static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
1483 .name = "i2c_4_5_dis_smi_grp",
1484 .pins = i2c_4_5_dis_smi_pins,
1485 .npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
1486 .modemuxs = i2c_4_5_dis_smi_modemux,
1487 .nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
1488};
1489
1490/* Pad multiplexing for i2c4_dis_sd device */
1491/* Muxed with SD/MMC */
1492static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
1493static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
1494 {
1495 .reg = PAD_FUNCTION_EN_1,
1496 .mask = PMX_MCIDATA4_MASK,
1497 .val = 0,
1498 }, {
1499 .reg = PAD_FUNCTION_EN_2,
1500 .mask = PMX_MCIDATA5_MASK,
1501 .val = 0,
1502 },
1503};
1504
1505static struct spear_modemux i2c4_dis_sd_modemux[] = {
1506 {
1507 .muxregs = i2c4_dis_sd_muxreg,
1508 .nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
1509 },
1510};
1511
1512static struct spear_pingroup i2c4_dis_sd_pingroup = {
1513 .name = "i2c4_dis_sd_grp",
1514 .pins = i2c4_dis_sd_pins,
1515 .npins = ARRAY_SIZE(i2c4_dis_sd_pins),
1516 .modemuxs = i2c4_dis_sd_modemux,
1517 .nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
1518};
1519
1520/* Pad multiplexing for i2c5_dis_sd device */
1521/* Muxed with SD/MMC */
1522static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
1523static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
1524 {
1525 .reg = PAD_FUNCTION_EN_2,
1526 .mask = PMX_MCIDATA6_MASK |
1527 PMX_MCIDATA7_MASK,
1528 .val = 0,
1529 },
1530};
1531
1532static struct spear_modemux i2c5_dis_sd_modemux[] = {
1533 {
1534 .muxregs = i2c5_dis_sd_muxreg,
1535 .nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
1536 },
1537};
1538
1539static struct spear_pingroup i2c5_dis_sd_pingroup = {
1540 .name = "i2c5_dis_sd_grp",
1541 .pins = i2c5_dis_sd_pins,
1542 .npins = ARRAY_SIZE(i2c5_dis_sd_pins),
1543 .modemuxs = i2c5_dis_sd_modemux,
1544 .nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
1545};
1546
1547static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
1548 "i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
1549static struct spear_function i2c_4_5_function = {
1550 .name = "i2c_4_5",
1551 .groups = i2c_4_5_grps,
1552 .ngroups = ARRAY_SIZE(i2c_4_5_grps),
1553};
1554
1555/* Pad multiplexing for i2c_6_7_dis_kbd device */
1556/* Muxed with KBD */
1557static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
1558static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
1559 {
1560 .reg = PAD_FUNCTION_EN_1,
1561 .mask = PMX_KBD_ROWCOL25_MASK,
1562 .val = 0,
1563 },
1564};
1565
1566static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
1567 {
1568 .muxregs = i2c_6_7_dis_kbd_muxreg,
1569 .nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
1570 },
1571};
1572
1573static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
1574 .name = "i2c_6_7_dis_kbd_grp",
1575 .pins = i2c_6_7_dis_kbd_pins,
1576 .npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
1577 .modemuxs = i2c_6_7_dis_kbd_modemux,
1578 .nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
1579};
1580
1581/* Pad multiplexing for i2c6_dis_sd device */
1582/* Muxed with SD/MMC */
1583static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
1584static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
1585 {
1586 .reg = PAD_FUNCTION_EN_2,
1587 .mask = PMX_MCIIORDRE_MASK |
1588 PMX_MCIIOWRWE_MASK,
1589 .val = 0,
1590 },
1591};
1592
1593static struct spear_modemux i2c6_dis_sd_modemux[] = {
1594 {
1595 .muxregs = i2c6_dis_sd_muxreg,
1596 .nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
1597 },
1598};
1599
1600static struct spear_pingroup i2c6_dis_sd_pingroup = {
1601 .name = "i2c6_dis_sd_grp",
1602 .pins = i2c6_dis_sd_pins,
1603 .npins = ARRAY_SIZE(i2c6_dis_sd_pins),
1604 .modemuxs = i2c6_dis_sd_modemux,
1605 .nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
1606};
1607
1608/* Pad multiplexing for i2c7_dis_sd device */
1609static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
1610static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
1611 {
1612 .reg = PAD_FUNCTION_EN_2,
1613 .mask = PMX_MCIRESETCF_MASK |
1614 PMX_MCICS0CE_MASK,
1615 .val = 0,
1616 },
1617};
1618
1619static struct spear_modemux i2c7_dis_sd_modemux[] = {
1620 {
1621 .muxregs = i2c7_dis_sd_muxreg,
1622 .nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
1623 },
1624};
1625
1626static struct spear_pingroup i2c7_dis_sd_pingroup = {
1627 .name = "i2c7_dis_sd_grp",
1628 .pins = i2c7_dis_sd_pins,
1629 .npins = ARRAY_SIZE(i2c7_dis_sd_pins),
1630 .modemuxs = i2c7_dis_sd_modemux,
1631 .nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
1632};
1633
1634static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
1635 "i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
1636static struct spear_function i2c_6_7_function = {
1637 .name = "i2c_6_7",
1638 .groups = i2c_6_7_grps,
1639 .ngroups = ARRAY_SIZE(i2c_6_7_grps),
1640};
1641
1642/* Pad multiplexing for can0_dis_nor device */
1643/* Muxed with NOR */
1644static const unsigned can0_dis_nor_pins[] = { 56, 57 };
1645static struct spear_muxreg can0_dis_nor_muxreg[] = {
1646 {
1647 .reg = PAD_FUNCTION_EN_0,
1648 .mask = PMX_NFRSTPWDWN2_MASK,
1649 .val = 0,
1650 }, {
1651 .reg = PAD_FUNCTION_EN_1,
1652 .mask = PMX_NFRSTPWDWN3_MASK,
1653 .val = 0,
1654 },
1655};
1656
1657static struct spear_modemux can0_dis_nor_modemux[] = {
1658 {
1659 .muxregs = can0_dis_nor_muxreg,
1660 .nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
1661 },
1662};
1663
1664static struct spear_pingroup can0_dis_nor_pingroup = {
1665 .name = "can0_dis_nor_grp",
1666 .pins = can0_dis_nor_pins,
1667 .npins = ARRAY_SIZE(can0_dis_nor_pins),
1668 .modemuxs = can0_dis_nor_modemux,
1669 .nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
1670};
1671
1672/* Pad multiplexing for can0_dis_sd device */
1673/* Muxed with SD/MMC */
1674static const unsigned can0_dis_sd_pins[] = { 240, 241 };
1675static struct spear_muxreg can0_dis_sd_muxreg[] = {
1676 {
1677 .reg = PAD_FUNCTION_EN_2,
1678 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1679 .val = 0,
1680 },
1681};
1682
1683static struct spear_modemux can0_dis_sd_modemux[] = {
1684 {
1685 .muxregs = can0_dis_sd_muxreg,
1686 .nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
1687 },
1688};
1689
1690static struct spear_pingroup can0_dis_sd_pingroup = {
1691 .name = "can0_dis_sd_grp",
1692 .pins = can0_dis_sd_pins,
1693 .npins = ARRAY_SIZE(can0_dis_sd_pins),
1694 .modemuxs = can0_dis_sd_modemux,
1695 .nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
1696};
1697
1698static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
1699};
1700static struct spear_function can0_function = {
1701 .name = "can0",
1702 .groups = can0_grps,
1703 .ngroups = ARRAY_SIZE(can0_grps),
1704};
1705
1706/* Pad multiplexing for can1_dis_sd device */
1707/* Muxed with SD/MMC */
1708static const unsigned can1_dis_sd_pins[] = { 242, 243 };
1709static struct spear_muxreg can1_dis_sd_muxreg[] = {
1710 {
1711 .reg = PAD_FUNCTION_EN_2,
1712 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1713 .val = 0,
1714 },
1715};
1716
1717static struct spear_modemux can1_dis_sd_modemux[] = {
1718 {
1719 .muxregs = can1_dis_sd_muxreg,
1720 .nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
1721 },
1722};
1723
1724static struct spear_pingroup can1_dis_sd_pingroup = {
1725 .name = "can1_dis_sd_grp",
1726 .pins = can1_dis_sd_pins,
1727 .npins = ARRAY_SIZE(can1_dis_sd_pins),
1728 .modemuxs = can1_dis_sd_modemux,
1729 .nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
1730};
1731
1732/* Pad multiplexing for can1_dis_kbd device */
1733/* Muxed with KBD */
1734static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
1735static struct spear_muxreg can1_dis_kbd_muxreg[] = {
1736 {
1737 .reg = PAD_FUNCTION_EN_1,
1738 .mask = PMX_KBD_ROWCOL25_MASK,
1739 .val = 0,
1740 },
1741};
1742
1743static struct spear_modemux can1_dis_kbd_modemux[] = {
1744 {
1745 .muxregs = can1_dis_kbd_muxreg,
1746 .nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
1747 },
1748};
1749
1750static struct spear_pingroup can1_dis_kbd_pingroup = {
1751 .name = "can1_dis_kbd_grp",
1752 .pins = can1_dis_kbd_pins,
1753 .npins = ARRAY_SIZE(can1_dis_kbd_pins),
1754 .modemuxs = can1_dis_kbd_modemux,
1755 .nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
1756};
1757
1758static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
1759};
1760static struct spear_function can1_function = {
1761 .name = "can1",
1762 .groups = can1_grps,
1763 .ngroups = ARRAY_SIZE(can1_grps),
1764};
1765
1766/* Pad multiplexing for pci device */
1767static const unsigned pci_sata_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
1768 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
1769 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
1770 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
1771#define PCI_SATA_MUXREG \
1772 { \
1773 .reg = PAD_FUNCTION_EN_0, \
1774 .mask = PMX_MCI_DATA8_15_MASK, \
1775 .val = 0, \
1776 }, { \
1777 .reg = PAD_FUNCTION_EN_1, \
1778 .mask = PMX_PCI_REG1_MASK, \
1779 .val = 0, \
1780 }, { \
1781 .reg = PAD_FUNCTION_EN_2, \
1782 .mask = PMX_PCI_REG2_MASK, \
1783 .val = 0, \
1784 }
1785
1786/* pad multiplexing for pcie0 device */
1787static struct spear_muxreg pcie0_muxreg[] = {
1788 PCI_SATA_MUXREG,
1789 {
1790 .reg = PCIE_SATA_CFG,
1791 .mask = PCIE_CFG_VAL(0),
1792 .val = PCIE_CFG_VAL(0),
1793 },
1794};
1795
1796static struct spear_modemux pcie0_modemux[] = {
1797 {
1798 .muxregs = pcie0_muxreg,
1799 .nmuxregs = ARRAY_SIZE(pcie0_muxreg),
1800 },
1801};
1802
1803static struct spear_pingroup pcie0_pingroup = {
1804 .name = "pcie0_grp",
1805 .pins = pci_sata_pins,
1806 .npins = ARRAY_SIZE(pci_sata_pins),
1807 .modemuxs = pcie0_modemux,
1808 .nmodemuxs = ARRAY_SIZE(pcie0_modemux),
1809};
1810
1811/* pad multiplexing for pcie1 device */
1812static struct spear_muxreg pcie1_muxreg[] = {
1813 PCI_SATA_MUXREG,
1814 {
1815 .reg = PCIE_SATA_CFG,
1816 .mask = PCIE_CFG_VAL(1),
1817 .val = PCIE_CFG_VAL(1),
1818 },
1819};
1820
1821static struct spear_modemux pcie1_modemux[] = {
1822 {
1823 .muxregs = pcie1_muxreg,
1824 .nmuxregs = ARRAY_SIZE(pcie1_muxreg),
1825 },
1826};
1827
1828static struct spear_pingroup pcie1_pingroup = {
1829 .name = "pcie1_grp",
1830 .pins = pci_sata_pins,
1831 .npins = ARRAY_SIZE(pci_sata_pins),
1832 .modemuxs = pcie1_modemux,
1833 .nmodemuxs = ARRAY_SIZE(pcie1_modemux),
1834};
1835
1836/* pad multiplexing for pcie2 device */
1837static struct spear_muxreg pcie2_muxreg[] = {
1838 PCI_SATA_MUXREG,
1839 {
1840 .reg = PCIE_SATA_CFG,
1841 .mask = PCIE_CFG_VAL(2),
1842 .val = PCIE_CFG_VAL(2),
1843 },
1844};
1845
1846static struct spear_modemux pcie2_modemux[] = {
1847 {
1848 .muxregs = pcie2_muxreg,
1849 .nmuxregs = ARRAY_SIZE(pcie2_muxreg),
1850 },
1851};
1852
1853static struct spear_pingroup pcie2_pingroup = {
1854 .name = "pcie2_grp",
1855 .pins = pci_sata_pins,
1856 .npins = ARRAY_SIZE(pci_sata_pins),
1857 .modemuxs = pcie2_modemux,
1858 .nmodemuxs = ARRAY_SIZE(pcie2_modemux),
1859};
1860
1861static const char *const pci_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" };
1862static struct spear_function pci_function = {
1863 .name = "pci",
1864 .groups = pci_grps,
1865 .ngroups = ARRAY_SIZE(pci_grps),
1866};
1867
1868/* pad multiplexing for sata0 device */
1869static struct spear_muxreg sata0_muxreg[] = {
1870 PCI_SATA_MUXREG,
1871 {
1872 .reg = PCIE_SATA_CFG,
1873 .mask = SATA_CFG_VAL(0),
1874 .val = SATA_CFG_VAL(0),
1875 },
1876};
1877
1878static struct spear_modemux sata0_modemux[] = {
1879 {
1880 .muxregs = sata0_muxreg,
1881 .nmuxregs = ARRAY_SIZE(sata0_muxreg),
1882 },
1883};
1884
1885static struct spear_pingroup sata0_pingroup = {
1886 .name = "sata0_grp",
1887 .pins = pci_sata_pins,
1888 .npins = ARRAY_SIZE(pci_sata_pins),
1889 .modemuxs = sata0_modemux,
1890 .nmodemuxs = ARRAY_SIZE(sata0_modemux),
1891};
1892
1893/* pad multiplexing for sata1 device */
1894static struct spear_muxreg sata1_muxreg[] = {
1895 PCI_SATA_MUXREG,
1896 {
1897 .reg = PCIE_SATA_CFG,
1898 .mask = SATA_CFG_VAL(1),
1899 .val = SATA_CFG_VAL(1),
1900 },
1901};
1902
1903static struct spear_modemux sata1_modemux[] = {
1904 {
1905 .muxregs = sata1_muxreg,
1906 .nmuxregs = ARRAY_SIZE(sata1_muxreg),
1907 },
1908};
1909
1910static struct spear_pingroup sata1_pingroup = {
1911 .name = "sata1_grp",
1912 .pins = pci_sata_pins,
1913 .npins = ARRAY_SIZE(pci_sata_pins),
1914 .modemuxs = sata1_modemux,
1915 .nmodemuxs = ARRAY_SIZE(sata1_modemux),
1916};
1917
1918/* pad multiplexing for sata2 device */
1919static struct spear_muxreg sata2_muxreg[] = {
1920 PCI_SATA_MUXREG,
1921 {
1922 .reg = PCIE_SATA_CFG,
1923 .mask = SATA_CFG_VAL(2),
1924 .val = SATA_CFG_VAL(2),
1925 },
1926};
1927
1928static struct spear_modemux sata2_modemux[] = {
1929 {
1930 .muxregs = sata2_muxreg,
1931 .nmuxregs = ARRAY_SIZE(sata2_muxreg),
1932 },
1933};
1934
1935static struct spear_pingroup sata2_pingroup = {
1936 .name = "sata2_grp",
1937 .pins = pci_sata_pins,
1938 .npins = ARRAY_SIZE(pci_sata_pins),
1939 .modemuxs = sata2_modemux,
1940 .nmodemuxs = ARRAY_SIZE(sata2_modemux),
1941};
1942
1943static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
1944};
1945static struct spear_function sata_function = {
1946 .name = "sata",
1947 .groups = sata_grps,
1948 .ngroups = ARRAY_SIZE(sata_grps),
1949};
1950
1951/* Pad multiplexing for ssp1_dis_kbd device */
1952static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
1953static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
1954 {
1955 .reg = PAD_FUNCTION_EN_1,
1956 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
1957 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
1958 PMX_NFCE2_MASK,
1959 .val = 0,
1960 },
1961};
1962
1963static struct spear_modemux ssp1_dis_kbd_modemux[] = {
1964 {
1965 .muxregs = ssp1_dis_kbd_muxreg,
1966 .nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
1967 },
1968};
1969
1970static struct spear_pingroup ssp1_dis_kbd_pingroup = {
1971 .name = "ssp1_dis_kbd_grp",
1972 .pins = ssp1_dis_kbd_pins,
1973 .npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
1974 .modemuxs = ssp1_dis_kbd_modemux,
1975 .nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
1976};
1977
1978/* Pad multiplexing for ssp1_dis_sd device */
1979static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
1980static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
1981 {
1982 .reg = PAD_FUNCTION_EN_2,
1983 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
1984 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
1985 .val = 0,
1986 },
1987};
1988
1989static struct spear_modemux ssp1_dis_sd_modemux[] = {
1990 {
1991 .muxregs = ssp1_dis_sd_muxreg,
1992 .nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
1993 },
1994};
1995
1996static struct spear_pingroup ssp1_dis_sd_pingroup = {
1997 .name = "ssp1_dis_sd_grp",
1998 .pins = ssp1_dis_sd_pins,
1999 .npins = ARRAY_SIZE(ssp1_dis_sd_pins),
2000 .modemuxs = ssp1_dis_sd_modemux,
2001 .nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
2002};
2003
2004static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
2005 "ssp1_dis_sd_grp" };
2006static struct spear_function ssp1_function = {
2007 .name = "ssp1",
2008 .groups = ssp1_grps,
2009 .ngroups = ARRAY_SIZE(ssp1_grps),
2010};
2011
2012/* Pad multiplexing for gpt64 device */
2013static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
2014static struct spear_muxreg gpt64_muxreg[] = {
2015 {
2016 .reg = PAD_FUNCTION_EN_2,
2017 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2018 | PMX_MCILEDS_MASK,
2019 .val = 0,
2020 },
2021};
2022
2023static struct spear_modemux gpt64_modemux[] = {
2024 {
2025 .muxregs = gpt64_muxreg,
2026 .nmuxregs = ARRAY_SIZE(gpt64_muxreg),
2027 },
2028};
2029
2030static struct spear_pingroup gpt64_pingroup = {
2031 .name = "gpt64_grp",
2032 .pins = gpt64_pins,
2033 .npins = ARRAY_SIZE(gpt64_pins),
2034 .modemuxs = gpt64_modemux,
2035 .nmodemuxs = ARRAY_SIZE(gpt64_modemux),
2036};
2037
2038static const char *const gpt64_grps[] = { "gpt64_grp" };
2039static struct spear_function gpt64_function = {
2040 .name = "gpt64",
2041 .groups = gpt64_grps,
2042 .ngroups = ARRAY_SIZE(gpt64_grps),
2043};
2044
2045/* pingroups */
2046static struct spear_pingroup *spear1310_pingroups[] = {
2047 &i2c0_pingroup,
2048 &ssp0_pingroup,
2049 &i2s0_pingroup,
2050 &i2s1_pingroup,
2051 &clcd_pingroup,
2052 &clcd_high_res_pingroup,
2053 &arm_gpio_pingroup,
2054 &smi_2_chips_pingroup,
2055 &smi_4_chips_pingroup,
2056 &gmii_pingroup,
2057 &rgmii_pingroup,
2058 &smii_0_1_2_pingroup,
2059 &ras_mii_txclk_pingroup,
2060 &nand_8bit_pingroup,
2061 &nand_16bit_pingroup,
2062 &nand_4_chips_pingroup,
2063 &keyboard_6x6_pingroup,
2064 &keyboard_rowcol6_8_pingroup,
2065 &uart0_pingroup,
2066 &uart0_modem_pingroup,
2067 &gpt0_tmr0_pingroup,
2068 &gpt0_tmr1_pingroup,
2069 &gpt1_tmr0_pingroup,
2070 &gpt1_tmr1_pingroup,
2071 &sdhci_pingroup,
2072 &cf_pingroup,
2073 &xd_pingroup,
2074 &touch_xy_pingroup,
2075 &ssp0_cs0_pingroup,
2076 &ssp0_cs1_2_pingroup,
2077 &uart_1_dis_i2c_pingroup,
2078 &uart_1_dis_sd_pingroup,
2079 &uart_2_3_pingroup,
2080 &uart_4_pingroup,
2081 &uart_5_pingroup,
2082 &rs485_0_1_tdm_0_1_pingroup,
2083 &i2c_1_2_pingroup,
2084 &i2c3_dis_smi_clcd_pingroup,
2085 &i2c3_dis_sd_i2s0_pingroup,
2086 &i2c_4_5_dis_smi_pingroup,
2087 &i2c4_dis_sd_pingroup,
2088 &i2c5_dis_sd_pingroup,
2089 &i2c_6_7_dis_kbd_pingroup,
2090 &i2c6_dis_sd_pingroup,
2091 &i2c7_dis_sd_pingroup,
2092 &can0_dis_nor_pingroup,
2093 &can0_dis_sd_pingroup,
2094 &can1_dis_sd_pingroup,
2095 &can1_dis_kbd_pingroup,
2096 &pcie0_pingroup,
2097 &pcie1_pingroup,
2098 &pcie2_pingroup,
2099 &sata0_pingroup,
2100 &sata1_pingroup,
2101 &sata2_pingroup,
2102 &ssp1_dis_kbd_pingroup,
2103 &ssp1_dis_sd_pingroup,
2104 &gpt64_pingroup,
2105};
2106
2107/* functions */
2108static struct spear_function *spear1310_functions[] = {
2109 &i2c0_function,
2110 &ssp0_function,
2111 &i2s0_function,
2112 &i2s1_function,
2113 &clcd_function,
2114 &arm_gpio_function,
2115 &smi_function,
2116 &gmii_function,
2117 &rgmii_function,
2118 &smii_0_1_2_function,
2119 &ras_mii_txclk_function,
2120 &nand_function,
2121 &keyboard_function,
2122 &uart0_function,
2123 &gpt0_function,
2124 &gpt1_function,
2125 &sdhci_function,
2126 &cf_function,
2127 &xd_function,
2128 &touch_xy_function,
2129 &uart1_function,
2130 &uart2_3_function,
2131 &uart4_function,
2132 &uart5_function,
2133 &rs485_0_1_tdm_0_1_function,
2134 &i2c_1_2_function,
2135 &i2c3_unction,
2136 &i2c_4_5_function,
2137 &i2c_6_7_function,
2138 &can0_function,
2139 &can1_function,
2140 &pci_function,
2141 &sata_function,
2142 &ssp1_function,
2143 &gpt64_function,
2144};
2145
2146static struct spear_pinctrl_machdata spear1310_machdata = {
2147 .pins = spear1310_pins,
2148 .npins = ARRAY_SIZE(spear1310_pins),
2149 .groups = spear1310_pingroups,
2150 .ngroups = ARRAY_SIZE(spear1310_pingroups),
2151 .functions = spear1310_functions,
2152 .nfunctions = ARRAY_SIZE(spear1310_functions),
2153 .modes_supported = false,
2154};
2155
2156static struct of_device_id spear1310_pinctrl_of_match[] __devinitdata = {
2157 {
2158 .compatible = "st,spear1310-pinmux",
2159 },
2160 {},
2161};
2162
2163static int __devinit spear1310_pinctrl_probe(struct platform_device *pdev)
2164{
2165 return spear_pinctrl_probe(pdev, &spear1310_machdata);
2166}
2167
2168static int __devexit spear1310_pinctrl_remove(struct platform_device *pdev)
2169{
2170 return spear_pinctrl_remove(pdev);
2171}
2172
2173static struct platform_driver spear1310_pinctrl_driver = {
2174 .driver = {
2175 .name = DRIVER_NAME,
2176 .owner = THIS_MODULE,
2177 .of_match_table = spear1310_pinctrl_of_match,
2178 },
2179 .probe = spear1310_pinctrl_probe,
2180 .remove = __devexit_p(spear1310_pinctrl_remove),
2181};
2182
2183static int __init spear1310_pinctrl_init(void)
2184{
2185 return platform_driver_register(&spear1310_pinctrl_driver);
2186}
2187arch_initcall(spear1310_pinctrl_init);
2188
2189static void __exit spear1310_pinctrl_exit(void)
2190{
2191 platform_driver_unregister(&spear1310_pinctrl_driver);
2192}
2193module_exit(spear1310_pinctrl_exit);
2194
10d8935f 2195MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
85ed41a7
VK		 2196MODULE_DESCRIPTION("ST Microelectronics SPEAr1310 pinctrl driver");
2197MODULE_LICENSE("GPL v2");
2198MODULE_DEVICE_TABLE(of, spear1310_pinctrl_of_match);
kernel source for telekom puls (alcatel/mediatek)