[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pinctrl / pinctrl-samsung.h

/*
 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 * Copyright (c) 2012 Linaro Ltd
 *		http://www.linaro.org
 *
 * Author: Thomas Abraham <thomas.ab@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __PINCTRL_SAMSUNG_H
#define __PINCTRL_SAMSUNG_H

#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>

#include <linux/gpio.h>

/* pinmux function number for pin as gpio output line */
#define FUNC_OUTPUT	0x1

/**
 * enum pincfg_type - possible pin configuration types supported.
 * @PINCFG_TYPE_FUNC: Function configuration.
 * @PINCFG_TYPE_DAT: Pin value configuration.
 * @PINCFG_TYPE_PUD: Pull up/down configuration.
 * @PINCFG_TYPE_DRV: Drive strength configuration.
 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
 * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
 */
enum pincfg_type {
	PINCFG_TYPE_FUNC,
	PINCFG_TYPE_DAT,
	PINCFG_TYPE_PUD,
	PINCFG_TYPE_DRV,
	PINCFG_TYPE_CON_PDN,
	PINCFG_TYPE_PUD_PDN,

	PINCFG_TYPE_NUM
};

/*
 * pin configuration (pull up/down and drive strength) type and its value are
 * packed together into a 16-bits. The upper 8-bits represent the configuration
 * type and the lower 8-bits hold the value of the configuration type.
 */
#define PINCFG_TYPE_MASK		0xFF
#define PINCFG_VALUE_SHIFT		8
#define PINCFG_VALUE_MASK		(0xFF << PINCFG_VALUE_SHIFT)
#define PINCFG_PACK(type, value)	(((value) << PINCFG_VALUE_SHIFT) | type)
#define PINCFG_UNPACK_TYPE(cfg)		((cfg) & PINCFG_TYPE_MASK)
#define PINCFG_UNPACK_VALUE(cfg)	(((cfg) & PINCFG_VALUE_MASK) >> \
						PINCFG_VALUE_SHIFT)
/**
 * enum eint_type - possible external interrupt types.
 * @EINT_TYPE_NONE: bank does not support external interrupts
 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
 *
 * Samsung GPIO controller groups all the available pins into banks. The pins
 * in a pin bank can support external gpio interrupts or external wakeup
 * interrupts or no interrupts at all. From a software perspective, the only
 * difference between external gpio and external wakeup interrupts is that
 * the wakeup interrupts can additionally wakeup the system if it is in
 * suspended state.
 */
enum eint_type {
	EINT_TYPE_NONE,
	EINT_TYPE_GPIO,
	EINT_TYPE_WKUP,
	EINT_TYPE_WKUP_MUX,
};

/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
#define PIN_NAME_LENGTH	10

#define PIN_GROUP(n, p, f)				\
	{						\
		.name		= n,			\
		.pins		= p,			\
		.num_pins	= ARRAY_SIZE(p),	\
		.func		= f			\
	}

#define PMX_FUNC(n, g)					\
	{						\
		.name		= n,			\
		.groups		= g,			\
		.num_groups	= ARRAY_SIZE(g),	\
	}

struct samsung_pinctrl_drv_data;

/**
 * struct samsung_pin_bank_type: pin bank type description
 * @fld_width: widths of configuration bitfields (0 if unavailable)
 * @reg_offset: offsets of configuration registers (don't care of width is 0)
 */
struct samsung_pin_bank_type {
	u8 fld_width[PINCFG_TYPE_NUM];
	u8 reg_offset[PINCFG_TYPE_NUM];
};

/**
 * struct samsung_pin_bank: represent a controller pin-bank.
 * @type: type of the bank (register offsets and bitfield widths)
 * @pctl_offset: starting offset of the pin-bank registers.
 * @pin_base: starting pin number of the bank.
 * @nr_pins: number of pins included in this bank.
 * @eint_func: function to set in CON register to configure pin as EINT.
 * @eint_type: type of the external interrupt supported by the bank.
 * @eint_mask: bit mask of pins which support EINT function.
 * @name: name to be prefixed for each pin in this pin bank.
 * @of_node: OF node of the bank.
 * @drvdata: link to controller driver data
 * @irq_domain: IRQ domain of the bank.
 * @gpio_chip: GPIO chip of the bank.
 * @grange: linux gpio pin range supported by this bank.
 * @slock: spinlock protecting bank registers
 * @pm_save: saved register values during suspend
 */
struct samsung_pin_bank {
	struct samsung_pin_bank_type *type;
	u32		pctl_offset;
	u32		pin_base;
	u8		nr_pins;
	u8		eint_func;
	enum eint_type	eint_type;
	u32		eint_mask;
	u32		eint_offset;
	char		*name;
	void		*soc_priv;
	struct device_node *of_node;
	struct samsung_pinctrl_drv_data *drvdata;
	struct irq_domain *irq_domain;
	struct gpio_chip gpio_chip;
	struct pinctrl_gpio_range grange;
	spinlock_t slock;

	u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
};

/**
 * struct samsung_pin_ctrl: represent a pin controller.
 * @pin_banks: list of pin banks included in this controller.
 * @nr_banks: number of pin banks.
 * @base: starting system wide pin number.
 * @nr_pins: number of pins supported by the controller.
 * @geint_con: offset of the ext-gpio controller registers.
 * @geint_mask: offset of the ext-gpio interrupt mask registers.
 * @geint_pend: offset of the ext-gpio interrupt pending registers.
 * @weint_con: offset of the ext-wakeup controller registers.
 * @weint_mask: offset of the ext-wakeup interrupt mask registers.
 * @weint_pend: offset of the ext-wakeup interrupt pending registers.
 * @svc: offset of the interrupt service register.
 * @eint_gpio_init: platform specific callback to setup the external gpio
 *	interrupts for the controller.
 * @eint_wkup_init: platform specific callback to setup the external wakeup
 *	interrupts for the controller.
 * @label: for debug information.
 */
struct samsung_pin_ctrl {
	struct samsung_pin_bank	*pin_banks;
	u32		nr_banks;

	u32		base;
	u32		nr_pins;

	u32		geint_con;
	u32		geint_mask;
	u32		geint_pend;

	u32		weint_con;
	u32		weint_mask;
	u32		weint_pend;

	u32		svc;

	int		(*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
	int		(*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
	void		(*suspend)(struct samsung_pinctrl_drv_data *);
	void		(*resume)(struct samsung_pinctrl_drv_data *);

	char		*label;
};

/**
 * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
 * @node: global list node
 * @virt_base: register base address of the controller.
 * @dev: device instance representing the controller.
 * @irq: interrpt number used by the controller to notify gpio interrupts.
 * @ctrl: pin controller instance managed by the driver.
 * @pctl: pin controller descriptor registered with the pinctrl subsystem.
 * @pctl_dev: cookie representing pinctrl device instance.
 * @pin_groups: list of pin groups available to the driver.
 * @nr_groups: number of such pin groups.
 * @pmx_functions: list of pin functions available to the driver.
 * @nr_function: number of such pin functions.
 */
struct samsung_pinctrl_drv_data {
	struct list_head		node;
	void __iomem			*virt_base;
	struct device			*dev;
	int				irq;

	struct samsung_pin_ctrl		*ctrl;
	struct pinctrl_desc		pctl;
	struct pinctrl_dev		*pctl_dev;

	const struct samsung_pin_group	*pin_groups;
	unsigned int			nr_groups;
	const struct samsung_pmx_func	*pmx_functions;
	unsigned int			nr_functions;
};

/**
 * struct samsung_pin_group: represent group of pins of a pinmux function.
 * @name: name of the pin group, used to lookup the group.
 * @pins: the pins included in this group.
 * @num_pins: number of pins included in this group.
 * @func: the function number to be programmed when selected.
 */
struct samsung_pin_group {
	const char		*name;
	const unsigned int	*pins;
	u8			num_pins;
	u8			func;
};

/**
 * struct samsung_pmx_func: represent a pin function.
 * @name: name of the pin function, used to lookup the function.
 * @groups: one or more names of pin groups that provide this function.
 * @num_groups: number of groups included in @groups.
 */
struct samsung_pmx_func {
	const char		*name;
	const char		**groups;
	u8			num_groups;
};

/* list of all exported SoC specific data */
extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];

#endif /* __PINCTRL_SAMSUNG_H */
Commit	Line	Data
30574f0d TA	1	/*
	2	* pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
	3	*
	4	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	* Copyright (c) 2012 Linaro Ltd
	7	* http://www.linaro.org
	8	*
	9	* Author: Thomas Abraham <thomas.ab@samsung.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
	17	#ifndef __PINCTRL_SAMSUNG_H
	18	#define __PINCTRL_SAMSUNG_H
	19
	20	#include <linux/pinctrl/pinctrl.h>
	21	#include <linux/pinctrl/pinmux.h>
	22	#include <linux/pinctrl/pinconf.h>
	23	#include <linux/pinctrl/consumer.h>
	24	#include <linux/pinctrl/machine.h>
	25
d3a7b9e3 TF	26	#include <linux/gpio.h>
d3a7b9e3 TF	27
30574f0d TA	28	/* pinmux function number for pin as gpio output line */
	29	#define FUNC_OUTPUT 0x1
	30
	31	/**
	32	* enum pincfg_type - possible pin configuration types supported.
499147c9 TF	33	* @PINCFG_TYPE_FUNC: Function configuration.
499147c9 TF	34	* @PINCFG_TYPE_DAT: Pin value configuration.
30574f0d TA	35	* @PINCFG_TYPE_PUD: Pull up/down configuration.
	36	* @PINCFG_TYPE_DRV: Drive strength configuration.
	37	* @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
	38	* @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
	39	*/
	40	enum pincfg_type {
499147c9 TF	41	PINCFG_TYPE_FUNC,
499147c9 TF	42	PINCFG_TYPE_DAT,
30574f0d TA	43	PINCFG_TYPE_PUD,
	44	PINCFG_TYPE_DRV,
	45	PINCFG_TYPE_CON_PDN,
	46	PINCFG_TYPE_PUD_PDN,
499147c9 TF	47
499147c9 TF	48	PINCFG_TYPE_NUM
30574f0d TA	49	};
	50
	51	/*
	52	* pin configuration (pull up/down and drive strength) type and its value are
	53	* packed together into a 16-bits. The upper 8-bits represent the configuration
	54	* type and the lower 8-bits hold the value of the configuration type.
	55	*/
	56	#define PINCFG_TYPE_MASK 0xFF
	57	#define PINCFG_VALUE_SHIFT 8
	58	#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
	59	#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) \| type)
	60	#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
	61	#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
	62	PINCFG_VALUE_SHIFT)
	63	/**
	64	* enum eint_type - possible external interrupt types.
	65	* @EINT_TYPE_NONE: bank does not support external interrupts
	66	* @EINT_TYPE_GPIO: bank supportes external gpio interrupts
	67	* @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
a04b07c0	68	* @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
30574f0d TA	69	*
	70	* Samsung GPIO controller groups all the available pins into banks. The pins
	71	* in a pin bank can support external gpio interrupts or external wakeup
	72	* interrupts or no interrupts at all. From a software perspective, the only
	73	* difference between external gpio and external wakeup interrupts is that
	74	* the wakeup interrupts can additionally wakeup the system if it is in
	75	* suspended state.
	76	*/
	77	enum eint_type {
	78	EINT_TYPE_NONE,
	79	EINT_TYPE_GPIO,
	80	EINT_TYPE_WKUP,
a04b07c0	81	EINT_TYPE_WKUP_MUX,
30574f0d TA	82	};
	83
	84	/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
	85	#define PIN_NAME_LENGTH 10
	86
	87	#define PIN_GROUP(n, p, f) \
	88	{ \
	89	.name = n, \
	90	.pins = p, \
	91	.num_pins = ARRAY_SIZE(p), \
	92	.func = f \
	93	}
	94
	95	#define PMX_FUNC(n, g) \
	96	{ \
	97	.name = n, \
	98	.groups = g, \
	99	.num_groups = ARRAY_SIZE(g), \
	100	}
	101
	102	struct samsung_pinctrl_drv_data;
	103
499147c9 TF	104	/**
	105	* struct samsung_pin_bank_type: pin bank type description
	106	* @fld_width: widths of configuration bitfields (0 if unavailable)
43fc9e7f	107	* @reg_offset: offsets of configuration registers (don't care of width is 0)
499147c9 TF	108	*/
	109	struct samsung_pin_bank_type {
	110	u8 fld_width[PINCFG_TYPE_NUM];
43fc9e7f	111	u8 reg_offset[PINCFG_TYPE_NUM];
499147c9 TF	112	};
499147c9 TF	113
30574f0d TA	114	/**
30574f0d TA	115	* struct samsung_pin_bank: represent a controller pin-bank.
499147c9	116	* @type: type of the bank (register offsets and bitfield widths)
88f2324f	117	* @pctl_offset: starting offset of the pin-bank registers.
30574f0d TA	118	* @pin_base: starting pin number of the bank.
30574f0d TA	119	* @nr_pins: number of pins included in this bank.
61dd7261	120	* @eint_func: function to set in CON register to configure pin as EINT.
30574f0d	121	* @eint_type: type of the external interrupt supported by the bank.
61dd7261	122	* @eint_mask: bit mask of pins which support EINT function.
30574f0d	123	* @name: name to be prefixed for each pin in this pin bank.
ab663789	124	* @of_node: OF node of the bank.
6defe9a0	125	* @drvdata: link to controller driver data
595be726	126	* @irq_domain: IRQ domain of the bank.
d3a7b9e3 TF	127	* @gpio_chip: GPIO chip of the bank.
d3a7b9e3 TF	128	* @grange: linux gpio pin range supported by this bank.
19846950	129	* @slock: spinlock protecting bank registers
d9f99863	130	* @pm_save: saved register values during suspend
30574f0d TA	131	*/
30574f0d TA	132	struct samsung_pin_bank {
499147c9	133	struct samsung_pin_bank_type *type;
30574f0d TA	134	u32 pctl_offset;
	135	u32 pin_base;
	136	u8 nr_pins;
61dd7261	137	u8 eint_func;
30574f0d	138	enum eint_type eint_type;
61dd7261	139	u32 eint_mask;
1b6056d6	140	u32 eint_offset;
30574f0d	141	char *name;
3385474c	142	void *soc_priv;
ab663789	143	struct device_node *of_node;
6defe9a0	144	struct samsung_pinctrl_drv_data *drvdata;
595be726	145	struct irq_domain *irq_domain;
d3a7b9e3 TF	146	struct gpio_chip gpio_chip;
d3a7b9e3 TF	147	struct pinctrl_gpio_range grange;
19846950	148	spinlock_t slock;
d9f99863 DA	149
d9f99863 DA	150	u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
30574f0d TA	151	};
	152
	153	/**
	154	* struct samsung_pin_ctrl: represent a pin controller.
	155	* @pin_banks: list of pin banks included in this controller.
	156	* @nr_banks: number of pin banks.
	157	* @base: starting system wide pin number.
	158	* @nr_pins: number of pins supported by the controller.
30574f0d TA	159	* @geint_con: offset of the ext-gpio controller registers.
	160	* @geint_mask: offset of the ext-gpio interrupt mask registers.
	161	* @geint_pend: offset of the ext-gpio interrupt pending registers.
	162	* @weint_con: offset of the ext-wakeup controller registers.
	163	* @weint_mask: offset of the ext-wakeup interrupt mask registers.
	164	* @weint_pend: offset of the ext-wakeup interrupt pending registers.
	165	* @svc: offset of the interrupt service register.
	166	* @eint_gpio_init: platform specific callback to setup the external gpio
	167	* interrupts for the controller.
	168	* @eint_wkup_init: platform specific callback to setup the external wakeup
	169	* interrupts for the controller.
	170	* @label: for debug information.
	171	*/
	172	struct samsung_pin_ctrl {
	173	struct samsung_pin_bank *pin_banks;
	174	u32 nr_banks;
	175
	176	u32 base;
	177	u32 nr_pins;
30574f0d TA	178
	179	u32 geint_con;
	180	u32 geint_mask;
	181	u32 geint_pend;
	182
	183	u32 weint_con;
	184	u32 weint_mask;
	185	u32 weint_pend;
	186
	187	u32 svc;
	188
	189	int (eint_gpio_init)(struct samsung_pinctrl_drv_data );
	190	int (eint_wkup_init)(struct samsung_pinctrl_drv_data );
21c21993 TF	191	void (suspend)(struct samsung_pinctrl_drv_data );
	192	void (resume)(struct samsung_pinctrl_drv_data );
	193
30574f0d TA	194	char *label;
	195	};
	196
	197	/**
	198	* struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
d9f99863	199	* @node: global list node
30574f0d TA	200	* @virt_base: register base address of the controller.
	201	* @dev: device instance representing the controller.
	202	* @irq: interrpt number used by the controller to notify gpio interrupts.
	203	* @ctrl: pin controller instance managed by the driver.
	204	* @pctl: pin controller descriptor registered with the pinctrl subsystem.
	205	* @pctl_dev: cookie representing pinctrl device instance.
	206	* @pin_groups: list of pin groups available to the driver.
	207	* @nr_groups: number of such pin groups.
	208	* @pmx_functions: list of pin functions available to the driver.
	209	* @nr_function: number of such pin functions.
30574f0d TA	210	*/
30574f0d TA	211	struct samsung_pinctrl_drv_data {
d9f99863	212	struct list_head node;
30574f0d TA	213	void __iomem *virt_base;
	214	struct device *dev;
	215	int irq;
	216
	217	struct samsung_pin_ctrl *ctrl;
	218	struct pinctrl_desc pctl;
	219	struct pinctrl_dev *pctl_dev;
	220
	221	const struct samsung_pin_group *pin_groups;
	222	unsigned int nr_groups;
	223	const struct samsung_pmx_func *pmx_functions;
	224	unsigned int nr_functions;
30574f0d TA	225	};
	226
	227	/**
	228	* struct samsung_pin_group: represent group of pins of a pinmux function.
	229	* @name: name of the pin group, used to lookup the group.
	230	* @pins: the pins included in this group.
	231	* @num_pins: number of pins included in this group.
	232	* @func: the function number to be programmed when selected.
	233	*/
	234	struct samsung_pin_group {
	235	const char *name;
	236	const unsigned int *pins;
	237	u8 num_pins;
	238	u8 func;
	239	};
	240
	241	/**
	242	* struct samsung_pmx_func: represent a pin function.
	243	* @name: name of the pin function, used to lookup the function.
	244	* @groups: one or more names of pin groups that provide this function.
	245	* @num_groups: number of groups included in @groups.
	246	*/
	247	struct samsung_pmx_func {
	248	const char *name;
	249	const char **groups;
	250	u8 num_groups;
	251	};
	252
	253	/* list of all exported SoC specific data */
	254	extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
6edc794a	255	extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
f67faf48	256	extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
61dd7261	257	extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
30574f0d TA	258
30574f0d TA	259	#endif /* __PINCTRL_SAMSUNG_H */