[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pinctrl / pinctrl-imx.c

/*
 * Core driver for the imx pin controller
 *
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 * Copyright (C) 2012 Linaro Ltd.
 *
 * Author: Dong Aisheng <dong.aisheng@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>

#include "core.h"
#include "pinctrl-imx.h"

#define IMX_PMX_DUMP(info, p, m, c, n)			\
{							\
	int i, j;					\
	printk(KERN_DEBUG "Format: Pin Mux Config\n");	\
	for (i = 0; i < n; i++) {			\
		j = p[i];				\
		printk(KERN_DEBUG "%s %d 0x%lx\n",	\
			info->pins[j].name,		\
			m[i], c[i]);			\
	}						\
}

/* The bits in CONFIG cell defined in binding doc*/
#define IMX_NO_PAD_CTL	0x80000000	/* no pin config need */
#define IMX_PAD_SION 0x40000000		/* set SION */

/**
 * @dev: a pointer back to containing device
 * @base: the offset to the controller in virtual memory
 */
struct imx_pinctrl {
	struct device *dev;
	struct pinctrl_dev *pctl;
	void __iomem *base;
	const struct imx_pinctrl_soc_info *info;
};

static const struct imx_pin_reg *imx_find_pin_reg(
				const struct imx_pinctrl_soc_info *info,
				unsigned pin, bool is_mux, unsigned mux)
{
	const struct imx_pin_reg *pin_reg = NULL;
	int i;

	for (i = 0; i < info->npin_regs; i++) {
		pin_reg = &info->pin_regs[i];
		if (pin_reg->pid != pin)
			continue;
		if (!is_mux)
			break;
		else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK))
			break;
	}

	if (i == info->npin_regs) {
		dev_err(info->dev, "Pin(%s): unable to find pin reg map\n",
			info->pins[pin].name);
		return NULL;
	}

	return pin_reg;
}

static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
				const struct imx_pinctrl_soc_info *info,
				const char *name)
{
	const struct imx_pin_group *grp = NULL;
	int i;

	for (i = 0; i < info->ngroups; i++) {
		if (!strcmp(info->groups[i].name, name)) {
			grp = &info->groups[i];
			break;
		}
	}

	return grp;
}

static int imx_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->ngroups;
}

static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
				       unsigned selector)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->groups[selector].name;
}

static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
			       const unsigned **pins,
			       unsigned *npins)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	if (selector >= info->ngroups)
		return -EINVAL;

	*pins = info->groups[selector].pins;
	*npins = info->groups[selector].npins;

	return 0;
}

static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
		   unsigned offset)
{
	seq_printf(s, "%s", dev_name(pctldev->dev));
}

static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
			struct device_node *np,
			struct pinctrl_map **map, unsigned *num_maps)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_group *grp;
	struct pinctrl_map *new_map;
	struct device_node *parent;
	int map_num = 1;
	int i, j;

	/*
	 * first find the group of this node and check if we need create
	 * config maps for pins
	 */
	grp = imx_pinctrl_find_group_by_name(info, np->name);
	if (!grp) {
		dev_err(info->dev, "unable to find group for node %s\n",
			np->name);
		return -EINVAL;
	}

	for (i = 0; i < grp->npins; i++) {
		if (!(grp->configs[i] & IMX_NO_PAD_CTL))
			map_num++;
	}

	new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
	if (!new_map)
		return -ENOMEM;

	*map = new_map;
	*num_maps = map_num;

	/* create mux map */
	parent = of_get_parent(np);
	if (!parent) {
		kfree(new_map);
		return -EINVAL;
	}
	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
	new_map[0].data.mux.function = parent->name;
	new_map[0].data.mux.group = np->name;
	of_node_put(parent);

	/* create config map */
	new_map++;
	for (i = j = 0; i < grp->npins; i++) {
		if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
			new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
			new_map[j].data.configs.group_or_pin =
					pin_get_name(pctldev, grp->pins[i]);
			new_map[j].data.configs.configs = &grp->configs[i];
			new_map[j].data.configs.num_configs = 1;
			j++;
		}
	}

	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
		(*map)->data.mux.function, (*map)->data.mux.group, map_num);

	return 0;
}

static void imx_dt_free_map(struct pinctrl_dev *pctldev,
				struct pinctrl_map *map, unsigned num_maps)
{
	kfree(map);
}

static const struct pinctrl_ops imx_pctrl_ops = {
	.get_groups_count = imx_get_groups_count,
	.get_group_name = imx_get_group_name,
	.get_group_pins = imx_get_group_pins,
	.pin_dbg_show = imx_pin_dbg_show,
	.dt_node_to_map = imx_dt_node_to_map,
	.dt_free_map = imx_dt_free_map,

};

static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
			   unsigned group)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg;
	const unsigned *pins, *mux;
	unsigned int npins, pin_id;
	int i;

	/*
	 * Configure the mux mode for each pin in the group for a specific
	 * function.
	 */
	pins = info->groups[group].pins;
	npins = info->groups[group].npins;
	mux = info->groups[group].mux_mode;

	WARN_ON(!pins || !npins || !mux);

	dev_dbg(ipctl->dev, "enable function %s group %s\n",
		info->functions[selector].name, info->groups[group].name);

	for (i = 0; i < npins; i++) {
		pin_id = pins[i];

		pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]);
		if (!pin_reg)
			return -EINVAL;

		if (!pin_reg->mux_reg) {
			dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
				info->pins[pin_id].name);
			return -EINVAL;
		}

		writel(mux[i], ipctl->base + pin_reg->mux_reg);
		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
			pin_reg->mux_reg, mux[i]);

		/* some pins also need select input setting, set it if found */
		if (pin_reg->input_reg) {
			writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg);
			dev_dbg(ipctl->dev,
				"==>select_input: offset 0x%x val 0x%x\n",
				pin_reg->input_reg, pin_reg->input_val);
		}
	}

	return 0;
}

static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->nfunctions;
}

static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
					  unsigned selector)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->functions[selector].name;
}

static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
			       const char * const **groups,
			       unsigned * const num_groups)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	*groups = info->functions[selector].groups;
	*num_groups = info->functions[selector].num_groups;

	return 0;
}

static const struct pinmux_ops imx_pmx_ops = {
	.get_functions_count = imx_pmx_get_funcs_count,
	.get_function_name = imx_pmx_get_func_name,
	.get_function_groups = imx_pmx_get_groups,
	.enable = imx_pmx_enable,
};

static int imx_pinconf_get(struct pinctrl_dev *pctldev,
			     unsigned pin_id, unsigned long *config)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg;

	pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
	if (!pin_reg)
		return -EINVAL;

	if (!pin_reg->conf_reg) {
		dev_err(info->dev, "Pin(%s) does not support config function\n",
			info->pins[pin_id].name);
		return -EINVAL;
	}

	*config = readl(ipctl->base + pin_reg->conf_reg);

	return 0;
}

static int imx_pinconf_set(struct pinctrl_dev *pctldev,
			     unsigned pin_id, unsigned long config)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg;

	pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
	if (!pin_reg)
		return -EINVAL;

	if (!pin_reg->conf_reg) {
		dev_err(info->dev, "Pin(%s) does not support config function\n",
			info->pins[pin_id].name);
		return -EINVAL;
	}

	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
		info->pins[pin_id].name);

	writel(config, ipctl->base + pin_reg->conf_reg);
	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
		pin_reg->conf_reg, config);

	return 0;
}

static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
				   struct seq_file *s, unsigned pin_id)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg;
	unsigned long config;

	pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
	if (!pin_reg || !pin_reg->conf_reg) {
		seq_printf(s, "N/A");
		return;
	}

	config = readl(ipctl->base + pin_reg->conf_reg);
	seq_printf(s, "0x%lx", config);
}

static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
					 struct seq_file *s, unsigned group)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	struct imx_pin_group *grp;
	unsigned long config;
	const char *name;
	int i, ret;

	if (group > info->ngroups)
		return;

	seq_printf(s, "\n");
	grp = &info->groups[group];
	for (i = 0; i < grp->npins; i++) {
		name = pin_get_name(pctldev, grp->pins[i]);
		ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
		if (ret)
			return;
		seq_printf(s, "%s: 0x%lx", name, config);
	}
}

static const struct pinconf_ops imx_pinconf_ops = {
	.pin_config_get = imx_pinconf_get,
	.pin_config_set = imx_pinconf_set,
	.pin_config_dbg_show = imx_pinconf_dbg_show,
	.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
};

static struct pinctrl_desc imx_pinctrl_desc = {
	.pctlops = &imx_pctrl_ops,
	.pmxops = &imx_pmx_ops,
	.confops = &imx_pinconf_ops,
	.owner = THIS_MODULE,
};

/* decode pin id and mux from pin function id got from device tree*/
static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info,
				unsigned int pin_func_id, unsigned int *pin_id,
				unsigned int *mux)
{
	if (pin_func_id > info->npin_regs)
		return -EINVAL;

	*pin_id = info->pin_regs[pin_func_id].pid;
	*mux = info->pin_regs[pin_func_id].mux_mode;

	return 0;
}

static int imx_pinctrl_parse_groups(struct device_node *np,
				    struct imx_pin_group *grp,
				    struct imx_pinctrl_soc_info *info,
				    u32 index)
{
	unsigned int pin_func_id;
	int ret, size;
	const __be32 *list;
	int i, j;
	u32 config;

	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);

	/* Initialise group */
	grp->name = np->name;

	/*
	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
	 * do sanity check and calculate pins number
	 */
	list = of_get_property(np, "fsl,pins", &size);
	/* we do not check return since it's safe node passed down */
	size /= sizeof(*list);
	if (!size || size % 2) {
		dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n");
		return -EINVAL;
	}

	grp->npins = size / 2;
	grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
				GFP_KERNEL);
	grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
				GFP_KERNEL);
	grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
				GFP_KERNEL);
	for (i = 0, j = 0; i < size; i += 2, j++) {
		pin_func_id = be32_to_cpu(*list++);
		ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id,
					&grp->pins[j], &grp->mux_mode[j]);
		if (ret) {
			dev_err(info->dev, "get invalid pin function id\n");
			return -EINVAL;
		}
		/* SION bit is in mux register */
		config = be32_to_cpu(*list++);
		if (config & IMX_PAD_SION)
			grp->mux_mode[j] |= IOMUXC_CONFIG_SION;
		grp->configs[j] = config & ~IMX_PAD_SION;
	}

#ifdef DEBUG
	IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
#endif

	return 0;
}

static int imx_pinctrl_parse_functions(struct device_node *np,
				       struct imx_pinctrl_soc_info *info,
				       u32 index)
{
	struct device_node *child;
	struct imx_pmx_func *func;
	struct imx_pin_group *grp;
	int ret;
	static u32 grp_index;
	u32 i = 0;

	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);

	func = &info->functions[index];

	/* Initialise function */
	func->name = np->name;
	func->num_groups = of_get_child_count(np);
	if (func->num_groups <= 0) {
		dev_err(info->dev, "no groups defined\n");
		return -EINVAL;
	}
	func->groups = devm_kzalloc(info->dev,
			func->num_groups * sizeof(char *), GFP_KERNEL);

	for_each_child_of_node(np, child) {
		func->groups[i] = child->name;
		grp = &info->groups[grp_index++];
		ret = imx_pinctrl_parse_groups(child, grp, info, i++);
		if (ret)
			return ret;
	}

	return 0;
}

static int imx_pinctrl_probe_dt(struct platform_device *pdev,
				struct imx_pinctrl_soc_info *info)
{
	struct device_node *np = pdev->dev.of_node;
	struct device_node *child;
	int ret;
	u32 nfuncs = 0;
	u32 i = 0;

	if (!np)
		return -ENODEV;

	nfuncs = of_get_child_count(np);
	if (nfuncs <= 0) {
		dev_err(&pdev->dev, "no functions defined\n");
		return -EINVAL;
	}

	info->nfunctions = nfuncs;
	info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
					GFP_KERNEL);
	if (!info->functions)
		return -ENOMEM;

	info->ngroups = 0;
	for_each_child_of_node(np, child)
		info->ngroups += of_get_child_count(child);
	info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
					GFP_KERNEL);
	if (!info->groups)
		return -ENOMEM;

	for_each_child_of_node(np, child) {
		ret = imx_pinctrl_parse_functions(child, info, i++);
		if (ret) {
			dev_err(&pdev->dev, "failed to parse function\n");
			return ret;
		}
	}

	return 0;
}

int imx_pinctrl_probe(struct platform_device *pdev,
		      struct imx_pinctrl_soc_info *info)
{
	struct imx_pinctrl *ipctl;
	struct resource *res;
	int ret;

	if (!info || !info->pins || !info->npins
		  || !info->pin_regs || !info->npin_regs) {
		dev_err(&pdev->dev, "wrong pinctrl info\n");
		return -EINVAL;
	}
	info->dev = &pdev->dev;

	/* Create state holders etc for this driver */
	ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
	if (!ipctl)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENOENT;

	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(ipctl->base))
		return PTR_ERR(ipctl->base);

	imx_pinctrl_desc.name = dev_name(&pdev->dev);
	imx_pinctrl_desc.pins = info->pins;
	imx_pinctrl_desc.npins = info->npins;

	ret = imx_pinctrl_probe_dt(pdev, info);
	if (ret) {
		dev_err(&pdev->dev, "fail to probe dt properties\n");
		return ret;
	}

	ipctl->info = info;
	ipctl->dev = info->dev;
	platform_set_drvdata(pdev, ipctl);
	ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
	if (!ipctl->pctl) {
		dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
		return -EINVAL;
	}

	dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");

	return 0;
}

int imx_pinctrl_remove(struct platform_device *pdev)
{
	struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);

	pinctrl_unregister(ipctl->pctl);

	return 0;
}
Commit	Line	Data
ae75ff81 DA	1	/*
	2	* Core driver for the imx pin controller
	3	*
	4	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	5	* Copyright (C) 2012 Linaro Ltd.
	6	*
	7	* Author: Dong Aisheng <dong.aisheng@linaro.org>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*/
	14
	15	#include <linux/err.h>
	16	#include <linux/init.h>
	17	#include <linux/io.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_device.h>
	21	#include <linux/pinctrl/machine.h>
	22	#include <linux/pinctrl/pinconf.h>
	23	#include <linux/pinctrl/pinctrl.h>
	24	#include <linux/pinctrl/pinmux.h>
	25	#include <linux/slab.h>
	26
	27	#include "core.h"
	28	#include "pinctrl-imx.h"
	29
3a86a5f8 DN	30	#define IMX_PMX_DUMP(info, p, m, c, n) \
	31	{ \
	32	int i, j; \
	33	printk(KERN_DEBUG "Format: Pin Mux Config\n"); \
	34	for (i = 0; i < n; i++) { \
	35	j = p[i]; \
	36	printk(KERN_DEBUG "%s %d 0x%lx\n", \
	37	info->pins[j].name, \
	38	m[i], c[i]); \
	39	} \
ae75ff81 DA	40	}
	41
	42	/* The bits in CONFIG cell defined in binding doc*/
	43	#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
	44	#define IMX_PAD_SION 0x40000000 /* set SION */
	45
	46	/**
	47	* @dev: a pointer back to containing device
	48	* @base: the offset to the controller in virtual memory
	49	*/
	50	struct imx_pinctrl {
	51	struct device *dev;
	52	struct pinctrl_dev *pctl;
	53	void __iomem *base;
	54	const struct imx_pinctrl_soc_info *info;
	55	};
	56
	57	static const struct imx_pin_reg *imx_find_pin_reg(
	58	const struct imx_pinctrl_soc_info *info,
	59	unsigned pin, bool is_mux, unsigned mux)
	60	{
	61	const struct imx_pin_reg *pin_reg = NULL;
	62	int i;
	63
	64	for (i = 0; i < info->npin_regs; i++) {
	65	pin_reg = &info->pin_regs[i];
	66	if (pin_reg->pid != pin)
	67	continue;
	68	if (!is_mux)
	69	break;
	70	else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK))
	71	break;
	72	}
	73
8d1c6ef6	74	if (i == info->npin_regs) {
ae75ff81 DA	75	dev_err(info->dev, "Pin(%s): unable to find pin reg map\n",
	76	info->pins[pin].name);
	77	return NULL;
	78	}
	79
	80	return pin_reg;
	81	}
	82
	83	static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
	84	const struct imx_pinctrl_soc_info *info,
	85	const char *name)
	86	{
	87	const struct imx_pin_group *grp = NULL;
	88	int i;
	89
	90	for (i = 0; i < info->ngroups; i++) {
	91	if (!strcmp(info->groups[i].name, name)) {
	92	grp = &info->groups[i];
	93	break;
	94	}
	95	}
	96
	97	return grp;
	98	}
	99
	100	static int imx_get_groups_count(struct pinctrl_dev *pctldev)
	101	{
	102	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	103	const struct imx_pinctrl_soc_info *info = ipctl->info;
	104
	105	return info->ngroups;
	106	}
	107
	108	static const char imx_get_group_name(struct pinctrl_dev pctldev,
	109	unsigned selector)
	110	{
	111	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	112	const struct imx_pinctrl_soc_info *info = ipctl->info;
	113
	114	return info->groups[selector].name;
	115	}
	116
	117	static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
	118	const unsigned **pins,
	119	unsigned *npins)
	120	{
	121	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	122	const struct imx_pinctrl_soc_info *info = ipctl->info;
	123
	124	if (selector >= info->ngroups)
	125	return -EINVAL;
	126
	127	*pins = info->groups[selector].pins;
	128	*npins = info->groups[selector].npins;
	129
	130	return 0;
	131	}
	132
	133	static void imx_pin_dbg_show(struct pinctrl_dev pctldev, struct seq_file s,
	134	unsigned offset)
	135	{
	136	seq_printf(s, "%s", dev_name(pctldev->dev));
	137	}
	138
139	static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
140	struct device_node *np,
141	struct pinctrl_map *map, unsigned num_maps)
142	{
143	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
144	const struct imx_pinctrl_soc_info *info = ipctl->info;
145	const struct imx_pin_group *grp;
146	struct pinctrl_map *new_map;
147	struct device_node *parent;
148	int map_num = 1;
18071610	149	int i, j;
ae75ff81 DA	150
	151	/*
	152	* first find the group of this node and check if we need create
	153	* config maps for pins
	154	*/
	155	grp = imx_pinctrl_find_group_by_name(info, np->name);
	156	if (!grp) {
	157	dev_err(info->dev, "unable to find group for node %s\n",
	158	np->name);
	159	return -EINVAL;
	160	}
	161
	162	for (i = 0; i < grp->npins; i++) {
	163	if (!(grp->configs[i] & IMX_NO_PAD_CTL))
	164	map_num++;
	165	}
	166
	167	new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
	168	if (!new_map)
	169	return -ENOMEM;
	170
	171	*map = new_map;
	172	*num_maps = map_num;
	173
	174	/* create mux map */
	175	parent = of_get_parent(np);
c71157c5 DN	176	if (!parent) {
c71157c5 DN	177	kfree(new_map);
ae75ff81	178	return -EINVAL;
c71157c5	179	}
ae75ff81 DA	180	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
	181	new_map[0].data.mux.function = parent->name;
	182	new_map[0].data.mux.group = np->name;
	183	of_node_put(parent);
	184
	185	/* create config map */
	186	new_map++;
18071610	187	for (i = j = 0; i < grp->npins; i++) {
ae75ff81	188	if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
18071610 HW	189	new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
18071610 HW	190	new_map[j].data.configs.group_or_pin =
ae75ff81	191	pin_get_name(pctldev, grp->pins[i]);
18071610 HW	192	new_map[j].data.configs.configs = &grp->configs[i];
	193	new_map[j].data.configs.num_configs = 1;
	194	j++;
ae75ff81 DA	195	}
	196	}
	197
	198	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
67695f2e	199	(map)->data.mux.function, (map)->data.mux.group, map_num);
ae75ff81 DA	200
	201	return 0;
	202	}
	203
	204	static void imx_dt_free_map(struct pinctrl_dev *pctldev,
	205	struct pinctrl_map *map, unsigned num_maps)
	206	{
3a86a5f8	207	kfree(map);
ae75ff81 DA	208	}
ae75ff81 DA	209
022ab148	210	static const struct pinctrl_ops imx_pctrl_ops = {
ae75ff81 DA	211	.get_groups_count = imx_get_groups_count,
	212	.get_group_name = imx_get_group_name,
	213	.get_group_pins = imx_get_group_pins,
	214	.pin_dbg_show = imx_pin_dbg_show,
	215	.dt_node_to_map = imx_dt_node_to_map,
	216	.dt_free_map = imx_dt_free_map,
	217
	218	};
	219
	220	static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
	221	unsigned group)
	222	{
	223	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	224	const struct imx_pinctrl_soc_info *info = ipctl->info;
	225	const struct imx_pin_reg *pin_reg;
	226	const unsigned pins, mux;
	227	unsigned int npins, pin_id;
	228	int i;
	229
	230	/*
	231	* Configure the mux mode for each pin in the group for a specific
	232	* function.
	233	*/
	234	pins = info->groups[group].pins;
	235	npins = info->groups[group].npins;
	236	mux = info->groups[group].mux_mode;
	237
	238	WARN_ON(!pins \|\| !npins \|\| !mux);
	239
	240	dev_dbg(ipctl->dev, "enable function %s group %s\n",
	241	info->functions[selector].name, info->groups[group].name);
	242
	243	for (i = 0; i < npins; i++) {
	244	pin_id = pins[i];
	245
	246	pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]);
	247	if (!pin_reg)
	248	return -EINVAL;
	249
	250	if (!pin_reg->mux_reg) {
	251	dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
	252	info->pins[pin_id].name);
	253	return -EINVAL;
	254	}
	255
	256	writel(mux[i], ipctl->base + pin_reg->mux_reg);
	257	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
	258	pin_reg->mux_reg, mux[i]);
	259
	260	/* some pins also need select input setting, set it if found */
	261	if (pin_reg->input_reg) {
	262	writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg);
	263	dev_dbg(ipctl->dev,
	264	"==>select_input: offset 0x%x val 0x%x\n",
	265	pin_reg->input_reg, pin_reg->input_val);
	266	}
	267	}
	268
	269	return 0;
	270	}
	271
ae75ff81 DA	272	static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
	273	{
	274	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	275	const struct imx_pinctrl_soc_info *info = ipctl->info;
	276
	277	return info->nfunctions;
	278	}
	279
	280	static const char imx_pmx_get_func_name(struct pinctrl_dev pctldev,
	281	unsigned selector)
	282	{
	283	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	284	const struct imx_pinctrl_soc_info *info = ipctl->info;
	285
	286	return info->functions[selector].name;
	287	}
	288
	289	static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
	290	const char * const **groups,
	291	unsigned * const num_groups)
	292	{
	293	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	294	const struct imx_pinctrl_soc_info *info = ipctl->info;
	295
	296	*groups = info->functions[selector].groups;
	297	*num_groups = info->functions[selector].num_groups;
	298
	299	return 0;
	300	}
	301
022ab148	302	static const struct pinmux_ops imx_pmx_ops = {
ae75ff81 DA	303	.get_functions_count = imx_pmx_get_funcs_count,
	304	.get_function_name = imx_pmx_get_func_name,
	305	.get_function_groups = imx_pmx_get_groups,
	306	.enable = imx_pmx_enable,
ae75ff81 DA	307	};
	308
	309	static int imx_pinconf_get(struct pinctrl_dev *pctldev,
	310	unsigned pin_id, unsigned long *config)
	311	{
	312	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	313	const struct imx_pinctrl_soc_info *info = ipctl->info;
	314	const struct imx_pin_reg *pin_reg;
	315
	316	pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
	317	if (!pin_reg)
	318	return -EINVAL;
	319
	320	if (!pin_reg->conf_reg) {
	321	dev_err(info->dev, "Pin(%s) does not support config function\n",
	322	info->pins[pin_id].name);
	323	return -EINVAL;
	324	}
	325
	326	*config = readl(ipctl->base + pin_reg->conf_reg);
	327
	328	return 0;
	329	}
	330
	331	static int imx_pinconf_set(struct pinctrl_dev *pctldev,
	332	unsigned pin_id, unsigned long config)
	333	{
	334	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	335	const struct imx_pinctrl_soc_info *info = ipctl->info;
	336	const struct imx_pin_reg *pin_reg;
	337
	338	pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
	339	if (!pin_reg)
	340	return -EINVAL;
	341
	342	if (!pin_reg->conf_reg) {
	343	dev_err(info->dev, "Pin(%s) does not support config function\n",
	344	info->pins[pin_id].name);
	345	return -EINVAL;
	346	}
	347
	348	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
	349	info->pins[pin_id].name);
	350
	351	writel(config, ipctl->base + pin_reg->conf_reg);
	352	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
	353	pin_reg->conf_reg, config);
	354
	355	return 0;
	356	}
	357
	358	static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
	359	struct seq_file *s, unsigned pin_id)
	360	{
	361	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	362	const struct imx_pinctrl_soc_info *info = ipctl->info;
	363	const struct imx_pin_reg *pin_reg;
	364	unsigned long config;
	365
	366	pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
	367	if (!pin_reg \|\| !pin_reg->conf_reg) {
	368	seq_printf(s, "N/A");
	369	return;
	370	}
371
372	config = readl(ipctl->base + pin_reg->conf_reg);
373	seq_printf(s, "0x%lx", config);
374	}
375
376	static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
377	struct seq_file *s, unsigned group)
378	{
379	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
380	const struct imx_pinctrl_soc_info *info = ipctl->info;
381	struct imx_pin_group *grp;
382	unsigned long config;
383	const char *name;
384	int i, ret;
385
386	if (group > info->ngroups)
387	return;
388
389	seq_printf(s, "\n");
390	grp = &info->groups[group];
391	for (i = 0; i < grp->npins; i++) {
392	name = pin_get_name(pctldev, grp->pins[i]);
393	ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
394	if (ret)
395	return;
396	seq_printf(s, "%s: 0x%lx", name, config);
397	}
398	}
399
022ab148	400	static const struct pinconf_ops imx_pinconf_ops = {
ae75ff81 DA	401	.pin_config_get = imx_pinconf_get,
	402	.pin_config_set = imx_pinconf_set,
	403	.pin_config_dbg_show = imx_pinconf_dbg_show,
	404	.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
	405	};
	406
	407	static struct pinctrl_desc imx_pinctrl_desc = {
	408	.pctlops = &imx_pctrl_ops,
	409	.pmxops = &imx_pmx_ops,
	410	.confops = &imx_pinconf_ops,
	411	.owner = THIS_MODULE,
	412	};
	413
	414	/* decode pin id and mux from pin function id got from device tree*/
	415	static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info,
	416	unsigned int pin_func_id, unsigned int *pin_id,
	417	unsigned int *mux)
	418	{
	419	if (pin_func_id > info->npin_regs)
	420	return -EINVAL;
	421
	422	*pin_id = info->pin_regs[pin_func_id].pid;
	423	*mux = info->pin_regs[pin_func_id].mux_mode;
	424
	425	return 0;
	426	}
	427
150632b0 GKH	428	static int imx_pinctrl_parse_groups(struct device_node *np,
	429	struct imx_pin_group *grp,
	430	struct imx_pinctrl_soc_info *info,
	431	u32 index)
ae75ff81 DA	432	{
	433	unsigned int pin_func_id;
	434	int ret, size;
a695145b	435	const __be32 *list;
ae75ff81 DA	436	int i, j;
	437	u32 config;
	438
	439	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
	440
	441	/* Initialise group */
	442	grp->name = np->name;
	443
	444	/*
	445	* the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
	446	* do sanity check and calculate pins number
	447	*/
	448	list = of_get_property(np, "fsl,pins", &size);
	449	/* we do not check return since it's safe node passed down */
	450	size /= sizeof(*list);
	451	if (!size \|\| size % 2) {
	452	dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n");
	453	return -EINVAL;
	454	}
	455
	456	grp->npins = size / 2;
	457	grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
	458	GFP_KERNEL);
	459	grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
	460	GFP_KERNEL);
	461	grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
	462	GFP_KERNEL);
	463	for (i = 0, j = 0; i < size; i += 2, j++) {
	464	pin_func_id = be32_to_cpu(*list++);
	465	ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id,
	466	&grp->pins[j], &grp->mux_mode[j]);
	467	if (ret) {
	468	dev_err(info->dev, "get invalid pin function id\n");
	469	return -EINVAL;
	470	}
	471	/* SION bit is in mux register */
	472	config = be32_to_cpu(*list++);
	473	if (config & IMX_PAD_SION)
	474	grp->mux_mode[j] \|= IOMUXC_CONFIG_SION;
	475	grp->configs[j] = config & ~IMX_PAD_SION;
	476	}
	477
a6e7360b	478	#ifdef DEBUG
ae75ff81	479	IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
a6e7360b	480	#endif
3a86a5f8	481
ae75ff81 DA	482	return 0;
	483	}
	484
150632b0 GKH	485	static int imx_pinctrl_parse_functions(struct device_node *np,
	486	struct imx_pinctrl_soc_info *info,
	487	u32 index)
ae75ff81 DA	488	{
	489	struct device_node *child;
	490	struct imx_pmx_func *func;
	491	struct imx_pin_group *grp;
	492	int ret;
	493	static u32 grp_index;
	494	u32 i = 0;
	495
	496	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
	497
	498	func = &info->functions[index];
	499
	500	/* Initialise function */
	501	func->name = np->name;
	502	func->num_groups = of_get_child_count(np);
	503	if (func->num_groups <= 0) {
	504	dev_err(info->dev, "no groups defined\n");
	505	return -EINVAL;
	506	}
	507	func->groups = devm_kzalloc(info->dev,
	508	func->num_groups * sizeof(char *), GFP_KERNEL);
	509
	510	for_each_child_of_node(np, child) {
	511	func->groups[i] = child->name;
	512	grp = &info->groups[grp_index++];
	513	ret = imx_pinctrl_parse_groups(child, grp, info, i++);
	514	if (ret)
	515	return ret;
	516	}
	517
	518	return 0;
	519	}
	520
150632b0	521	static int imx_pinctrl_probe_dt(struct platform_device *pdev,
ae75ff81 DA	522	struct imx_pinctrl_soc_info *info)
	523	{
	524	struct device_node *np = pdev->dev.of_node;
	525	struct device_node *child;
	526	int ret;
	527	u32 nfuncs = 0;
	528	u32 i = 0;
	529
	530	if (!np)
	531	return -ENODEV;
	532
	533	nfuncs = of_get_child_count(np);
	534	if (nfuncs <= 0) {
	535	dev_err(&pdev->dev, "no functions defined\n");
	536	return -EINVAL;
	537	}
	538
	539	info->nfunctions = nfuncs;
	540	info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
	541	GFP_KERNEL);
	542	if (!info->functions)
	543	return -ENOMEM;
	544
	545	info->ngroups = 0;
	546	for_each_child_of_node(np, child)
	547	info->ngroups += of_get_child_count(child);
	548	info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
	549	GFP_KERNEL);
	550	if (!info->groups)
	551	return -ENOMEM;
	552
	553	for_each_child_of_node(np, child) {
	554	ret = imx_pinctrl_parse_functions(child, info, i++);
	555	if (ret) {
	556	dev_err(&pdev->dev, "failed to parse function\n");
	557	return ret;
	558	}
	559	}
	560
	561	return 0;
	562	}
	563
150632b0 GKH	564	int imx_pinctrl_probe(struct platform_device *pdev,
150632b0 GKH	565	struct imx_pinctrl_soc_info *info)
ae75ff81 DA	566	{
	567	struct imx_pinctrl *ipctl;
	568	struct resource *res;
	569	int ret;
	570
	571	if (!info \|\| !info->pins \|\| !info->npins
	572	\|\| !info->pin_regs \|\| !info->npin_regs) {
	573	dev_err(&pdev->dev, "wrong pinctrl info\n");
	574	return -EINVAL;
	575	}
	576	info->dev = &pdev->dev;
	577
	578	/* Create state holders etc for this driver */
	579	ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
	580	if (!ipctl)
	581	return -ENOMEM;
	582
	583	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	584	if (!res)
	585	return -ENOENT;
	586
9e0c1fb2 TR	587	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
	588	if (IS_ERR(ipctl->base))
	589	return PTR_ERR(ipctl->base);
ae75ff81 DA	590
	591	imx_pinctrl_desc.name = dev_name(&pdev->dev);
	592	imx_pinctrl_desc.pins = info->pins;
	593	imx_pinctrl_desc.npins = info->npins;
	594
	595	ret = imx_pinctrl_probe_dt(pdev, info);
	596	if (ret) {
	597	dev_err(&pdev->dev, "fail to probe dt properties\n");
	598	return ret;
	599	}
	600
	601	ipctl->info = info;
	602	ipctl->dev = info->dev;
	603	platform_set_drvdata(pdev, ipctl);
	604	ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
	605	if (!ipctl->pctl) {
	606	dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
	607	return -EINVAL;
	608	}
	609
	610	dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
	611
	612	return 0;
	613	}
	614
f90f54b3	615	int imx_pinctrl_remove(struct platform_device *pdev)
ae75ff81 DA	616	{
	617	struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
	618
	619	pinctrl_unregister(ipctl->pctl);
	620
	621	return 0;
	622	}