[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pcmcia / sa1100_nanoengine.c

/*
 * drivers/pcmcia/sa1100_nanoengine.c
 *
 * PCMCIA implementation routines for BSI nanoEngine.
 *
 * In order to have a fully functional pcmcia subsystem in a BSE nanoEngine
 * board you should carefully read this:
 * http://cambuca.ldhs.cetuc.puc-rio.br/nanoengine/
 *
 * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
 *
 * Based on original work for kernel 2.4 by
 * Miguel Freitas <miguel@cpti.cetuc.puc-rio.br>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/signal.h>

#include <asm/mach-types.h>
#include <asm/irq.h>

#include <mach/hardware.h>
#include <mach/nanoengine.h>

#include "sa1100_generic.h"

struct nanoengine_pins {
	unsigned output_pins;
	unsigned clear_outputs;
	int gpio_cd;
	int gpio_rdy;
};

static struct nanoengine_pins nano_skts[] = {
	{
		.output_pins		= GPIO_PC_RESET0,
		.clear_outputs		= GPIO_PC_RESET0,
		.gpio_cd		= GPIO_PC_CD0,
		.gpio_rdy		= GPIO_PC_READY0,
	}, {
		.output_pins		= GPIO_PC_RESET1,
		.clear_outputs		= GPIO_PC_RESET1,
		.gpio_cd		= GPIO_PC_CD1,
		.gpio_rdy		= GPIO_PC_READY1,
	}
};

unsigned num_nano_pcmcia_sockets = ARRAY_SIZE(nano_skts);

static int nanoengine_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
{
	unsigned i = skt->nr;

	if (i >= num_nano_pcmcia_sockets)
		return -ENXIO;

	GPDR |= nano_skts[i].output_pins;
	GPCR = nano_skts[i].clear_outputs;

	skt->stat[SOC_STAT_CD].gpio = nano_skts[i].gpio_cd;
	skt->stat[SOC_STAT_CD].name = i ? "PC CD1" : "PC CD0";
	skt->stat[SOC_STAT_RDY].gpio = nano_skts[i].gpio_rdy;
	skt->stat[SOC_STAT_RDY].name = i ? "PC RDY1" : "PC RDY0";

	return 0;
}

static int nanoengine_pcmcia_configure_socket(
	struct soc_pcmcia_socket *skt, const socket_state_t *state)
{
	unsigned reset;
	unsigned i = skt->nr;

	if (i >= num_nano_pcmcia_sockets)
		return -ENXIO;

	switch (i) {
	case 0:
		reset = GPIO_PC_RESET0;
		break;
	case 1:
		reset = GPIO_PC_RESET1;
		break;
	default:
		return -ENXIO;
	}

	if (state->flags & SS_RESET)
		GPSR = reset;
	else
		GPCR = reset;

	return 0;
}

static void nanoengine_pcmcia_socket_state(
	struct soc_pcmcia_socket *skt, struct pcmcia_state *state)
{
	unsigned i = skt->nr;

	if (i >= num_nano_pcmcia_sockets)
		return;

	state->bvd1 = 1;
	state->bvd2 = 1;
	state->wrprot = 0; /* Not available */
	state->vs_3v = 1; /* Can only apply 3.3V */
	state->vs_Xv = 0;
}

static struct pcmcia_low_level nanoengine_pcmcia_ops = {
	.owner			= THIS_MODULE,

	.hw_init		= nanoengine_pcmcia_hw_init,

	.configure_socket	= nanoengine_pcmcia_configure_socket,
	.socket_state		= nanoengine_pcmcia_socket_state,
};

int pcmcia_nanoengine_init(struct device *dev)
{
	int ret = -ENODEV;

	if (machine_is_nanoengine())
		ret = sa11xx_drv_pcmcia_probe(
			dev, &nanoengine_pcmcia_ops, 0, 2);

	return ret;
}
Commit	Line	Data
fa87672a MRJ	1	/*
	2	* drivers/pcmcia/sa1100_nanoengine.c
	3	*
	4	* PCMCIA implementation routines for BSI nanoEngine.
	5	*
	6	* In order to have a fully functional pcmcia subsystem in a BSE nanoEngine
	7	* board you should carefully read this:
	8	* http://cambuca.ldhs.cetuc.puc-rio.br/nanoengine/
	9	*
	10	* Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
	11	*
	12	* Based on original work for kernel 2.4 by
	13	* Miguel Freitas <miguel@cpti.cetuc.puc-rio.br>
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*
	19	*/
	20	#include <linux/device.h>
	21	#include <linux/errno.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/irq.h>
	24	#include <linux/init.h>
	25	#include <linux/kernel.h>
	26	#include <linux/module.h>
	27	#include <linux/signal.h>
	28
	29	#include <asm/mach-types.h>
	30	#include <asm/irq.h>
	31
	32	#include <mach/hardware.h>
	33	#include <mach/nanoengine.h>
	34
	35	#include "sa1100_generic.h"
	36
fa87672a	37	struct nanoengine_pins {
fa87672a MRJ	38	unsigned output_pins;
fa87672a MRJ	39	unsigned clear_outputs;
7cf779cb RK	40	int gpio_cd;
7cf779cb RK	41	int gpio_rdy;
fa87672a MRJ	42	};
	43
	44	static struct nanoengine_pins nano_skts[] = {
	45	{
fa87672a MRJ	46	.output_pins = GPIO_PC_RESET0,
fa87672a MRJ	47	.clear_outputs = GPIO_PC_RESET0,
7cf779cb RK	48	.gpio_cd = GPIO_PC_CD0,
7cf779cb RK	49	.gpio_rdy = GPIO_PC_READY0,
fa87672a	50	}, {
fa87672a MRJ	51	.output_pins = GPIO_PC_RESET1,
fa87672a MRJ	52	.clear_outputs = GPIO_PC_RESET1,
7cf779cb RK	53	.gpio_cd = GPIO_PC_CD1,
7cf779cb RK	54	.gpio_rdy = GPIO_PC_READY1,
fa87672a MRJ	55	}
	56	};
	57
	58	unsigned num_nano_pcmcia_sockets = ARRAY_SIZE(nano_skts);
	59
	60	static int nanoengine_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
	61	{
	62	unsigned i = skt->nr;
	63
	64	if (i >= num_nano_pcmcia_sockets)
	65	return -ENXIO;
	66
fa87672a MRJ	67	GPDR \|= nano_skts[i].output_pins;
fa87672a MRJ	68	GPCR = nano_skts[i].clear_outputs;
fa87672a	69
7cf779cb RK	70	skt->stat[SOC_STAT_CD].gpio = nano_skts[i].gpio_cd;
	71	skt->stat[SOC_STAT_CD].name = i ? "PC CD1" : "PC CD0";
	72	skt->stat[SOC_STAT_RDY].gpio = nano_skts[i].gpio_rdy;
	73	skt->stat[SOC_STAT_RDY].name = i ? "PC RDY1" : "PC RDY0";
fa87672a	74
7cf779cb	75	return 0;
fa87672a MRJ	76	}
	77
	78	static int nanoengine_pcmcia_configure_socket(
	79	struct soc_pcmcia_socket skt, const socket_state_t state)
	80	{
	81	unsigned reset;
	82	unsigned i = skt->nr;
	83
	84	if (i >= num_nano_pcmcia_sockets)
	85	return -ENXIO;
	86
	87	switch (i) {
	88	case 0:
	89	reset = GPIO_PC_RESET0;
	90	break;
	91	case 1:
	92	reset = GPIO_PC_RESET1;
	93	break;
	94	default:
	95	return -ENXIO;
	96	}
	97
	98	if (state->flags & SS_RESET)
	99	GPSR = reset;
	100	else
	101	GPCR = reset;
	102
	103	return 0;
	104	}
	105
	106	static void nanoengine_pcmcia_socket_state(
	107	struct soc_pcmcia_socket skt, struct pcmcia_state state)
	108	{
fa87672a MRJ	109	unsigned i = skt->nr;
	110
	111	if (i >= num_nano_pcmcia_sockets)
	112	return;
	113
fa87672a MRJ	114	state->bvd1 = 1;
	115	state->bvd2 = 1;
	116	state->wrprot = 0; /* Not available */
	117	state->vs_3v = 1; /* Can only apply 3.3V */
	118	state->vs_Xv = 0;
	119	}
	120
fa87672a MRJ	121	static struct pcmcia_low_level nanoengine_pcmcia_ops = {
	122	.owner = THIS_MODULE,
	123
	124	.hw_init = nanoengine_pcmcia_hw_init,
fa87672a MRJ	125
	126	.configure_socket = nanoengine_pcmcia_configure_socket,
	127	.socket_state = nanoengine_pcmcia_socket_state,
fa87672a MRJ	128	};
	129
	130	int pcmcia_nanoengine_init(struct device *dev)
	131	{
	132	int ret = -ENODEV;
	133
	134	if (machine_is_nanoengine())
	135	ret = sa11xx_drv_pcmcia_probe(
	136	dev, &nanoengine_pcmcia_ops, 0, 2);
	137
	138	return ret;
	139	}
	140