[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pcmcia / pxa2xx_base.c

/*======================================================================

  Device driver for the PCMCIA control functionality of PXA2xx
  microprocessors.

    The contents of this file may be used under the
    terms of the GNU Public License version 2 (the "GPL")

    (c) Ian Molton (spyro@f2s.com) 2003
    (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4

    derived from sa11xx_base.c

     Portions created by John G. Dorsey are
     Copyright (C) 1999 John G. Dorsey.

  ======================================================================*/

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>

#include <mach/hardware.h>
#include <mach/smemc.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <mach/pxa2xx-regs.h>
#include <asm/mach-types.h>

#include <pcmcia/ss.h>
#include <pcmcia/cistpl.h>

#include "soc_common.h"
#include "pxa2xx_base.h"

/*
 * Personal Computer Memory Card International Association (PCMCIA) sockets
 */

#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
#define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]             */
#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]         */
#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]      */

#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]           */
#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]       */
#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */

#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]           */
#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]       */
#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */

#define _PCMCIA(Nb)			/* PCMCIA [0..1]                   */ \
			(0x20000000 + (Nb) * PCMCIASp)
#define _PCMCIAIO(Nb)	_PCMCIA(Nb)	/* PCMCIA I/O [0..1]               */
#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]         */ \
			(_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]            */ \
			(_PCMCIA(Nb) + 3 * PCMCIAPrtSp)

#define _PCMCIA0	_PCMCIA(0)	/* PCMCIA 0                        */
#define _PCMCIA0IO	_PCMCIAIO(0)	/* PCMCIA 0 I/O                    */
#define _PCMCIA0Attr	_PCMCIAAttr(0)	/* PCMCIA 0 Attribute              */
#define _PCMCIA0Mem	_PCMCIAMem(0)	/* PCMCIA 0 Memory                 */

#define _PCMCIA1	_PCMCIA(1)	/* PCMCIA 1                        */
#define _PCMCIA1IO	_PCMCIAIO(1)	/* PCMCIA 1 I/O                    */
#define _PCMCIA1Attr	_PCMCIAAttr(1)	/* PCMCIA 1 Attribute              */
#define _PCMCIA1Mem	_PCMCIAMem(1)	/* PCMCIA 1 Memory                 */


#define MCXX_SETUP_MASK     (0x7f)
#define MCXX_ASST_MASK      (0x1f)
#define MCXX_HOLD_MASK      (0x3f)
#define MCXX_SETUP_SHIFT    (0)
#define MCXX_ASST_SHIFT     (7)
#define MCXX_HOLD_SHIFT     (14)

static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
				     u_int mem_clk_10khz)
{
	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
}

static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
				     u_int mem_clk_10khz)
{
	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
}

static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
				      u_int mem_clk_10khz)
{
	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
}

/* This function returns the (approximate) command assertion period, in
 * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
 */
static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
					   u_int pcmcia_mcxx_asst)
{
	return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
}

static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
{
	uint32_t val;

	val = ((pxa2xx_mcxx_setup(speed, clock)
		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
		| ((pxa2xx_mcxx_asst(speed, clock)
		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
		| ((pxa2xx_mcxx_hold(speed, clock)
		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);

	__raw_writel(val, MCMEM(sock));

	return 0;
}

static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
{
	uint32_t val;

	val = ((pxa2xx_mcxx_setup(speed, clock)
		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
		| ((pxa2xx_mcxx_asst(speed, clock)
		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
		| ((pxa2xx_mcxx_hold(speed, clock)
		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);

	__raw_writel(val, MCIO(sock));

	return 0;
}

static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
{
	uint32_t val;

	val = ((pxa2xx_mcxx_setup(speed, clock)
		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
		| ((pxa2xx_mcxx_asst(speed, clock)
		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
		| ((pxa2xx_mcxx_hold(speed, clock)
		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);

	__raw_writel(val, MCATT(sock));

	return 0;
}

static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
{
	struct soc_pcmcia_timing timing;
	int sock = skt->nr;

	soc_common_pcmcia_get_timing(skt, &timing);

	pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
	pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
	pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);

	return 0;
}

static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
{
	unsigned long clk = clk_get_rate(skt->clk);
	return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000);
}

#ifdef CONFIG_CPU_FREQ

static int
pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
			       unsigned long val,
			       struct cpufreq_freqs *freqs)
{
	switch (val) {
	case CPUFREQ_PRECHANGE:
		if (freqs->new > freqs->old) {
			debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
			       "pre-updating\n",
			       freqs->new / 1000, (freqs->new / 100) % 10,
			       freqs->old / 1000, (freqs->old / 100) % 10);
			pxa2xx_pcmcia_set_timing(skt);
		}
		break;

	case CPUFREQ_POSTCHANGE:
		if (freqs->new < freqs->old) {
			debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
			       "post-updating\n",
			       freqs->new / 1000, (freqs->new / 100) % 10,
			       freqs->old / 1000, (freqs->old / 100) % 10);
			pxa2xx_pcmcia_set_timing(skt);
		}
		break;
	}
	return 0;
}
#endif

void pxa2xx_configure_sockets(struct device *dev)
{
	struct pcmcia_low_level *ops = dev->platform_data;
	/*
	 * We have at least one socket, so set MECR:CIT
	 * (Card Is There)
	 */
	uint32_t mecr = MECR_CIT;

	/* Set MECR:NOS (Number Of Sockets) */
	if ((ops->first + ops->nr) > 1 ||
	    machine_is_viper() || machine_is_arcom_zeus())
		mecr |= MECR_NOS;

	__raw_writel(mecr, MECR);
}
EXPORT_SYMBOL(pxa2xx_configure_sockets);

static const char *skt_names[] = {
	"PCMCIA socket 0",
	"PCMCIA socket 1",
};

#define SKT_DEV_INFO_SIZE(n) \
	(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))

int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
{
	skt->res_skt.start = _PCMCIA(skt->nr);
	skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
	skt->res_skt.name = skt_names[skt->nr];
	skt->res_skt.flags = IORESOURCE_MEM;

	skt->res_io.start = _PCMCIAIO(skt->nr);
	skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
	skt->res_io.name = "io";
	skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;

	skt->res_mem.start = _PCMCIAMem(skt->nr);
	skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
	skt->res_mem.name = "memory";
	skt->res_mem.flags = IORESOURCE_MEM;

	skt->res_attr.start = _PCMCIAAttr(skt->nr);
	skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
	skt->res_attr.name = "attribute";
	skt->res_attr.flags = IORESOURCE_MEM;

	return soc_pcmcia_add_one(skt);
}
EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);

void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
{
	/* Provide our PXA2xx specific timing routines. */
	ops->set_timing  = pxa2xx_pcmcia_set_timing;
#ifdef CONFIG_CPU_FREQ
	ops->frequency_change = pxa2xx_pcmcia_frequency_change;
#endif
}
EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);

static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
{
	int i, ret = 0;
	struct pcmcia_low_level *ops;
	struct skt_dev_info *sinfo;
	struct soc_pcmcia_socket *skt;
	struct clk *clk;

	ops = (struct pcmcia_low_level *)dev->dev.platform_data;
	if (!ops) {
		ret = -ENODEV;
		goto err0;
	}

	if (cpu_is_pxa320() && ops->nr > 1) {
		dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
		ret = -EINVAL;
		goto err0;
	}

	clk = clk_get(&dev->dev, NULL);
	if (IS_ERR(clk))
		return -ENODEV;

	pxa2xx_drv_pcmcia_ops(ops);

	sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL);
	if (!sinfo) {
		clk_put(clk);
		return -ENOMEM;
	}

	sinfo->nskt = ops->nr;
	sinfo->clk = clk;

	/* Initialize processor specific parameters */
	for (i = 0; i < ops->nr; i++) {
		skt = &sinfo->skt[i];

		skt->nr = ops->first + i;
		skt->clk = clk;
		soc_pcmcia_init_one(skt, ops, &dev->dev);

		ret = pxa2xx_drv_pcmcia_add_one(skt);
		if (ret)
			goto err1;
	}

	pxa2xx_configure_sockets(&dev->dev);
	dev_set_drvdata(&dev->dev, sinfo);

	return 0;

err1:
	while (--i >= 0)
		soc_pcmcia_remove_one(&sinfo->skt[i]);
	clk_put(clk);
	kfree(sinfo);
err0:
	return ret;
}

static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
{
	struct skt_dev_info *sinfo = platform_get_drvdata(dev);
	int i;

	platform_set_drvdata(dev, NULL);

	for (i = 0; i < sinfo->nskt; i++)
		soc_pcmcia_remove_one(&sinfo->skt[i]);

	clk_put(sinfo->clk);
	kfree(sinfo);
	return 0;
}

static int pxa2xx_drv_pcmcia_resume(struct device *dev)
{
	pxa2xx_configure_sockets(dev);
	return 0;
}

static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
	.resume		= pxa2xx_drv_pcmcia_resume,
};

static struct platform_driver pxa2xx_pcmcia_driver = {
	.probe		= pxa2xx_drv_pcmcia_probe,
	.remove		= pxa2xx_drv_pcmcia_remove,
	.driver		= {
		.name	= "pxa2xx-pcmcia",
		.owner	= THIS_MODULE,
		.pm	= &pxa2xx_drv_pcmcia_pm_ops,
	},
};

static int __init pxa2xx_pcmcia_init(void)
{
	return platform_driver_register(&pxa2xx_pcmcia_driver);
}

static void __exit pxa2xx_pcmcia_exit(void)
{
	platform_driver_unregister(&pxa2xx_pcmcia_driver);
}

fs_initcall(pxa2xx_pcmcia_init);
module_exit(pxa2xx_pcmcia_exit);

MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa2xx-pcmcia");
Commit	Line	Data
1da177e4 LT	1	/*======================================================================
	2
	3	Device driver for the PCMCIA control functionality of PXA2xx
	4	microprocessors.
	5
	6	The contents of this file may be used under the
	7	terms of the GNU Public License version 2 (the "GPL")
	8
	9	(c) Ian Molton (spyro@f2s.com) 2003
	10	(c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
	11
	12	derived from sa11xx_base.c
	13
	14	Portions created by John G. Dorsey are
	15	Copyright (C) 1999 John G. Dorsey.
	16
	17	======================================================================*/
	18
	19	#include <linux/module.h>
5a0e3ad6	20	#include <linux/slab.h>
1da177e4	21	#include <linux/init.h>
1da177e4 LT	22	#include <linux/cpufreq.h>
	23	#include <linux/ioport.h>
	24	#include <linux/kernel.h>
	25	#include <linux/spinlock.h>
d052d1be	26	#include <linux/platform_device.h>
1da177e4	27
a09e64fb	28	#include <mach/hardware.h>
ad68bb9f	29	#include <mach/smemc.h>
1da177e4 LT	30	#include <asm/io.h>
1da177e4 LT	31	#include <asm/irq.h>
a09e64fb	32	#include <mach/pxa2xx-regs.h>
20f18ff3	33	#include <asm/mach-types.h>
1da177e4	34
1da177e4	35	#include <pcmcia/ss.h>
1da177e4 LT	36	#include <pcmcia/cistpl.h>
1da177e4 LT	37
1da177e4 LT	38	#include "soc_common.h"
	39	#include "pxa2xx_base.h"
	40
b393c696 EM	41	/*
	42	* Personal Computer Memory Card International Association (PCMCIA) sockets
	43	*/
	44
	45	#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
	46	#define PCMCIASp (4PCMCIAPrtSp) / PCMCIA Space [byte] */
	47	#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
	48	#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
	49	#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
	50
	51	#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
	52	#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
	53	#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
	54	#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
	55
	56	#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
	57	#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
	58	#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
	59	#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
	60
	61	#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
	62	(0x20000000 + (Nb) * PCMCIASp)
	63	#define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
	64	#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
	65	(_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
	66	#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
	67	(_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
	68
	69	#define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
	70	#define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
	71	#define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
	72	#define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
	73
	74	#define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
	75	#define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
	76	#define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
	77	#define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
	78
1da177e4 LT	79
	80	#define MCXX_SETUP_MASK (0x7f)
	81	#define MCXX_ASST_MASK (0x1f)
	82	#define MCXX_HOLD_MASK (0x3f)
	83	#define MCXX_SETUP_SHIFT (0)
	84	#define MCXX_ASST_SHIFT (7)
	85	#define MCXX_HOLD_SHIFT (14)
	86
	87	static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
	88	u_int mem_clk_10khz)
	89	{
	90	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	91	return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
	92	}
	93
	94	static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
	95	u_int mem_clk_10khz)
	96	{
	97	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
24d6572b	98	return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
1da177e4 LT	99	}
	100
	101	static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
	102	u_int mem_clk_10khz)
	103	{
	104	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	105	return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
	106	}
	107
	108	/* This function returns the (approximate) command assertion period, in
	109	* nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
	110	*/
	111	static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
	112	u_int pcmcia_mcxx_asst)
	113	{
	114	return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
	115	}
	116
	117	static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
	118	{
ad68bb9f MV	119	uint32_t val;
	120
	121	val = ((pxa2xx_mcxx_setup(speed, clock)
1da177e4 LT	122	& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
	123	\| ((pxa2xx_mcxx_asst(speed, clock)
	124	& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
	125	\| ((pxa2xx_mcxx_hold(speed, clock)
	126	& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
	127
ad68bb9f MV	128	__raw_writel(val, MCMEM(sock));
ad68bb9f MV	129
1da177e4 LT	130	return 0;
	131	}
	132
	133	static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
	134	{
ad68bb9f MV	135	uint32_t val;
	136
	137	val = ((pxa2xx_mcxx_setup(speed, clock)
1da177e4 LT	138	& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
	139	\| ((pxa2xx_mcxx_asst(speed, clock)
	140	& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
	141	\| ((pxa2xx_mcxx_hold(speed, clock)
	142	& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
	143
ad68bb9f MV	144	__raw_writel(val, MCIO(sock));
ad68bb9f MV	145
1da177e4 LT	146	return 0;
	147	}
	148
	149	static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
	150	{
ad68bb9f MV	151	uint32_t val;
	152
	153	val = ((pxa2xx_mcxx_setup(speed, clock)
1da177e4 LT	154	& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
	155	\| ((pxa2xx_mcxx_asst(speed, clock)
	156	& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
	157	\| ((pxa2xx_mcxx_hold(speed, clock)
	158	& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
	159
ad68bb9f MV	160	__raw_writel(val, MCATT(sock));
ad68bb9f MV	161
1da177e4 LT	162	return 0;
	163	}
	164
	165	static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
	166	{
	167	struct soc_pcmcia_timing timing;
	168	int sock = skt->nr;
	169
	170	soc_common_pcmcia_get_timing(skt, &timing);
	171
	172	pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
	173	pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
	174	pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);
	175
	176	return 0;
	177	}
	178
	179	static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
	180	{
2a125dd5 EM	181	unsigned long clk = clk_get_rate(skt->clk);
2a125dd5 EM	182	return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000);
1da177e4 LT	183	}
	184
	185	#ifdef CONFIG_CPU_FREQ
	186
	187	static int
	188	pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
	189	unsigned long val,
	190	struct cpufreq_freqs *freqs)
	191	{
1da177e4 LT	192	switch (val) {
	193	case CPUFREQ_PRECHANGE:
	194	if (freqs->new > freqs->old) {
	195	debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
	196	"pre-updating\n",
	197	freqs->new / 1000, (freqs->new / 100) % 10,
	198	freqs->old / 1000, (freqs->old / 100) % 10);
d344a21a	199	pxa2xx_pcmcia_set_timing(skt);
1da177e4 LT	200	}
	201	break;
	202
	203	case CPUFREQ_POSTCHANGE:
	204	if (freqs->new < freqs->old) {
	205	debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
	206	"post-updating\n",
	207	freqs->new / 1000, (freqs->new / 100) % 10,
	208	freqs->old / 1000, (freqs->old / 100) % 10);
d344a21a	209	pxa2xx_pcmcia_set_timing(skt);
1da177e4 LT	210	}
	211	break;
	212	}
	213	return 0;
	214	}
	215	#endif
	216
5b703683	217	void pxa2xx_configure_sockets(struct device *dev)
20f18ff3 MZ	218	{
20f18ff3 MZ	219	struct pcmcia_low_level *ops = dev->platform_data;
20f18ff3 MZ	220	/*
	221	* We have at least one socket, so set MECR:CIT
	222	* (Card Is There)
	223	*/
ad68bb9f	224	uint32_t mecr = MECR_CIT;
20f18ff3 MZ	225
20f18ff3 MZ	226	/* Set MECR:NOS (Number Of Sockets) */
c2de1c38 MZ	227	if ((ops->first + ops->nr) > 1 \|\|
c2de1c38 MZ	228	machine_is_viper() \|\| machine_is_arcom_zeus())
ad68bb9f MV	229	mecr \|= MECR_NOS;
	230
	231	__raw_writel(mecr, MECR);
20f18ff3	232	}
d5240dfd	233	EXPORT_SYMBOL(pxa2xx_configure_sockets);
20f18ff3	234
b393c696 EM	235	static const char *skt_names[] = {
	236	"PCMCIA socket 0",
	237	"PCMCIA socket 1",
	238	};
	239
	240	#define SKT_DEV_INFO_SIZE(n) \
	241	(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
	242
701a5dc0	243	int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
da4f0073 RKAL	244	{
	245	skt->res_skt.start = _PCMCIA(skt->nr);
	246	skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
	247	skt->res_skt.name = skt_names[skt->nr];
	248	skt->res_skt.flags = IORESOURCE_MEM;
	249
	250	skt->res_io.start = _PCMCIAIO(skt->nr);
	251	skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
	252	skt->res_io.name = "io";
	253	skt->res_io.flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
	254
	255	skt->res_mem.start = _PCMCIAMem(skt->nr);
	256	skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
	257	skt->res_mem.name = "memory";
	258	skt->res_mem.flags = IORESOURCE_MEM;
	259
	260	skt->res_attr.start = _PCMCIAAttr(skt->nr);
	261	skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
	262	skt->res_attr.name = "attribute";
	263	skt->res_attr.flags = IORESOURCE_MEM;
	264
	265	return soc_pcmcia_add_one(skt);
	266	}
d0d26c33	267	EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);
da4f0073	268
701a5dc0 RKAL	269	void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
	270	{
	271	/* Provide our PXA2xx specific timing routines. */
	272	ops->set_timing = pxa2xx_pcmcia_set_timing;
	273	#ifdef CONFIG_CPU_FREQ
	274	ops->frequency_change = pxa2xx_pcmcia_frequency_change;
	275	#endif
	276	}
d0d26c33	277	EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);
701a5dc0	278
d0d26c33	279	static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
1da177e4	280	{
701a5dc0	281	int i, ret = 0;
1da177e4	282	struct pcmcia_low_level *ops;
b393c696 EM	283	struct skt_dev_info *sinfo;
b393c696 EM	284	struct soc_pcmcia_socket *skt;
2a125dd5	285	struct clk *clk;
1da177e4	286
d0d26c33	287	ops = (struct pcmcia_low_level *)dev->dev.platform_data;
a4257af5 MV	288	if (!ops) {
	289	ret = -ENODEV;
	290	goto err0;
	291	}
	292
	293	if (cpu_is_pxa320() && ops->nr > 1) {
	294	dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
	295	ret = -EINVAL;
	296	goto err0;
	297	}
1da177e4	298
2a125dd5	299	clk = clk_get(&dev->dev, NULL);
e09a7164	300	if (IS_ERR(clk))
2a125dd5 EM	301	return -ENODEV;
2a125dd5 EM	302
701a5dc0	303	pxa2xx_drv_pcmcia_ops(ops);
da4f0073	304
b393c696	305	sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL);
2a125dd5 EM	306	if (!sinfo) {
2a125dd5 EM	307	clk_put(clk);
b393c696	308	return -ENOMEM;
2a125dd5	309	}
b393c696 EM	310
b393c696 EM	311	sinfo->nskt = ops->nr;
2a125dd5	312	sinfo->clk = clk;
b393c696 EM	313
	314	/* Initialize processor specific parameters */
	315	for (i = 0; i < ops->nr; i++) {
	316	skt = &sinfo->skt[i];
	317
da4f0073	318	skt->nr = ops->first + i;
2a125dd5	319	skt->clk = clk;
e0d21178	320	soc_pcmcia_init_one(skt, ops, &dev->dev);
b393c696	321
da4f0073 RKAL	322	ret = pxa2xx_drv_pcmcia_add_one(skt);
da4f0073 RKAL	323	if (ret)
a4257af5	324	goto err1;
b393c696 EM	325	}
b393c696 EM	326
8fb28231 AL	327	pxa2xx_configure_sockets(&dev->dev);
8fb28231 AL	328	dev_set_drvdata(&dev->dev, sinfo);
1da177e4	329
a4257af5 MV	330	return 0;
	331
	332	err1:
	333	while (--i >= 0)
	334	soc_pcmcia_remove_one(&sinfo->skt[i]);
8fb28231	335	clk_put(clk);
a4257af5 MV	336	kfree(sinfo);
a4257af5 MV	337	err0:
1da177e4 LT	338	return ret;
1da177e4 LT	339	}
9468613b RK	340
	341	static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
	342	{
be85458e RKAL	343	struct skt_dev_info *sinfo = platform_get_drvdata(dev);
	344	int i;
	345
	346	platform_set_drvdata(dev, NULL);
	347
	348	for (i = 0; i < sinfo->nskt; i++)
	349	soc_pcmcia_remove_one(&sinfo->skt[i]);
	350
2a125dd5	351	clk_put(sinfo->clk);
be85458e RKAL	352	kfree(sinfo);
be85458e RKAL	353	return 0;
9468613b RK	354	}
9468613b RK	355
85c61021	356	static int pxa2xx_drv_pcmcia_resume(struct device *dev)
1da177e4	357	{
85c61021	358	pxa2xx_configure_sockets(dev);
d7646f76	359	return 0;
1da177e4 LT	360	}
1da177e4 LT	361
47145210	362	static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
85c61021 MR	363	.resume = pxa2xx_drv_pcmcia_resume,
	364	};
	365
9468613b	366	static struct platform_driver pxa2xx_pcmcia_driver = {
1da177e4	367	.probe = pxa2xx_drv_pcmcia_probe,
9468613b	368	.remove = pxa2xx_drv_pcmcia_remove,
9468613b RK	369	.driver = {
9468613b RK	370	.name = "pxa2xx-pcmcia",
12c2c019	371	.owner = THIS_MODULE,
85c61021	372	.pm = &pxa2xx_drv_pcmcia_pm_ops,
9468613b	373	},
1da177e4 LT	374	};
	375
	376	static int __init pxa2xx_pcmcia_init(void)
	377	{
9468613b	378	return platform_driver_register(&pxa2xx_pcmcia_driver);
1da177e4 LT	379	}
	380
	381	static void __exit pxa2xx_pcmcia_exit(void)
	382	{
9468613b	383	platform_driver_unregister(&pxa2xx_pcmcia_driver);
1da177e4 LT	384	}
1da177e4 LT	385
f36598ae	386	fs_initcall(pxa2xx_pcmcia_init);
1da177e4 LT	387	module_exit(pxa2xx_pcmcia_exit);
	388
	389	MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
	390	MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
	391	MODULE_LICENSE("GPL");
12c2c019	392	MODULE_ALIAS("platform:pxa2xx-pcmcia");