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[PATCH] remove many unneeded #includes of sched.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pcmcia / m8xx_pcmcia.c
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de957c89
MT		 1/*
2 * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
3 *
4 * (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
5 * (C) 2001-2002 Montavista Software, Inc.
6 * <mlocke@mvista.com>
7 *
8 * Support for two slots by Cyclades Corporation
9 * <oliver.kurth@cyclades.de>
10 * Further fixes, v2.6 kernel port
11 * <marcelo.tosatti@cyclades.com>
1371d3be
VB		 12 *
13 * Some fixes, additions (C) 2005 Montavista Software, Inc.
14 * <vbordug@ru.mvista.com>
de957c89
MT		 15 *
16 * "The ExCA standard specifies that socket controllers should provide
17 * two IO and five memory windows per socket, which can be independently
18 * configured and positioned in the host address space and mapped to
19 * arbitrary segments of card address space. " - David A Hinds. 1999
20 *
21 * This controller does _not_ meet the ExCA standard.
22 *
23 * m8xx pcmcia controller brief info:
24 * + 8 windows (attrib, mem, i/o)
25 * + up to two slots (SLOT_A and SLOT_B)
26 * + inputpins, outputpins, event and mask registers.
27 * - no offset register. sigh.
28 *
29 * Because of the lacking offset register we must map the whole card.
30 * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
31 * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
32 * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
33 * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
34 * They are maximum 64KByte each...
35 */
36
37#include <linux/module.h>
38#include <linux/init.h>
39#include <linux/types.h>
40#include <linux/fcntl.h>
41#include <linux/string.h>
42
43#include <asm/io.h>
44#include <asm/bitops.h>
de957c89
MT		 45#include <asm/system.h>
46
47#include <linux/kernel.h>
48#include <linux/errno.h>
de957c89
MT		 49#include <linux/slab.h>
50#include <linux/timer.h>
51#include <linux/ioport.h>
52#include <linux/delay.h>
53#include <linux/interrupt.h>
e3463150 54#include <linux/platform_device.h>
de957c89
MT		 55
56#include <asm/mpc8xx.h>
57#include <asm/8xx_immap.h>
58#include <asm/irq.h>
59
60#include <pcmcia/version.h>
61#include <pcmcia/cs_types.h>
62#include <pcmcia/cs.h>
63#include <pcmcia/ss.h>
64
65#ifdef PCMCIA_DEBUG
66static int pc_debug = PCMCIA_DEBUG;
67module_param(pc_debug, int, 0);
68#define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args);
69#else
70#define dprintk(args...)
71#endif
72
73#define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
74#define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
75
76static const char *version = "Version 0.06, Aug 2005";
77MODULE_LICENSE("Dual MPL/GPL");
78
79#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
80
81/* The RPX series use SLOT_B */
82#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
83#define CONFIG_PCMCIA_SLOT_B
84#define CONFIG_BD_IS_MHZ
85#endif
86
87/* The ADS board use SLOT_A */
88#ifdef CONFIG_ADS
89#define CONFIG_PCMCIA_SLOT_A
90#define CONFIG_BD_IS_MHZ
91#endif
92
93/* The FADS series are a mess */
94#ifdef CONFIG_FADS
95#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
96#define CONFIG_PCMCIA_SLOT_A
97#else
98#define CONFIG_PCMCIA_SLOT_B
99#endif
100#endif
101
1371d3be
VB		 102#if defined(CONFIG_MPC885ADS)
103#define CONFIG_PCMCIA_SLOT_A
104#define PCMCIA_GLITCHY_CD
105#endif
106
de957c89
MT		 107/* Cyclades ACS uses both slots */
108#ifdef CONFIG_PRxK
109#define CONFIG_PCMCIA_SLOT_A
110#define CONFIG_PCMCIA_SLOT_B
111#endif
112
113#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
114
115#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
116
117#define PCMCIA_SOCKETS_NO 2
118/* We have only 8 windows, dualsocket support will be limited. */
119#define PCMCIA_MEM_WIN_NO 2
120#define PCMCIA_IO_WIN_NO 2
121#define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
122
123#elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
124
125#define PCMCIA_SOCKETS_NO 1
126/* full support for one slot */
127#define PCMCIA_MEM_WIN_NO 5
128#define PCMCIA_IO_WIN_NO 2
129
130/* define _slot_ to be able to optimize macros */
131
132#ifdef CONFIG_PCMCIA_SLOT_A
133#define _slot_ 0
134#define PCMCIA_SLOT_MSG "SLOT_A"
135#else
136#define _slot_ 1
137#define PCMCIA_SLOT_MSG "SLOT_B"
138#endif
139
140#else
141#error m8xx_pcmcia: Bad configuration!
142#endif
143
144/* ------------------------------------------------------------------------- */
145
146#define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
147#define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
148#define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
149
150#define PCMCIA_SCHLVL PCMCIA_INTERRUPT /* Status Change Interrupt Level */
151
152/* ------------------------------------------------------------------------- */
153
154/* 2.4.x and newer has this always in HZ */
155#define M8XX_BUSFREQ ((((bd_t *)&(__res))->bi_busfreq))
156
157static int pcmcia_schlvl = PCMCIA_SCHLVL;
158
34af946a 159static DEFINE_SPINLOCK(events_lock);
de957c89
MT		 160
161
162#define PCMCIA_SOCKET_KEY_5V 1
163#define PCMCIA_SOCKET_KEY_LV 2
164
165/* look up table for pgcrx registers */
166static u32 *m8xx_pgcrx[2] = {
167 &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcra,
168 &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcrb
169};
170
171/*
172 * This structure is used to address each window in the PCMCIA controller.
173 *
174 * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
175 * after pcmcia_win[n]...
176 */
177
178struct pcmcia_win {
179 u32 br;
180 u32 or;
181};
182
183/*
184 * For some reason the hardware guys decided to make both slots share
185 * some registers.
186 *
187 * Could someone invent object oriented hardware ?
188 *
189 * The macros are used to get the right bit from the registers.
190 * SLOT_A : slot = 0
191 * SLOT_B : slot = 1
192 */
193
194#define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
195#define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
196#define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
197#define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
198
199#define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
200#define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
201#define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
202#define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
203#define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
204#define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
205#define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
206#define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
207#define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
208#define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
209#define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
210
211#define M8XX_PCMCIA_POR_VALID 0x00000001
212#define M8XX_PCMCIA_POR_WRPROT 0x00000002
213#define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
214#define M8XX_PCMCIA_POR_IO 0x00000018
215#define M8XX_PCMCIA_POR_16BIT 0x00000040
216
217#define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
218
219#define M8XX_PGCRX_CXOE 0x00000080
220#define M8XX_PGCRX_CXRESET 0x00000040
221
222/* we keep one lookup table per socket to check flags */
223
224#define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
225
226struct event_table {
227 u32 regbit;
228 u32 eventbit;
229};
230
231struct socket_info {
232 void (*handler)(void *info, u32 events);
233 void *info;
234
235 u32 slot;
236
237 socket_state_t state;
238 struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
239 struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
240 struct event_table events[PCMCIA_EVENTS_MAX];
241 struct pcmcia_socket socket;
242};
243
244static struct socket_info socket[PCMCIA_SOCKETS_NO];
245
246/*
247 * Search this table to see if the windowsize is
248 * supported...
249 */
250
251#define M8XX_SIZES_NO 32
252
253static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] =
254{
255 0x00000001, 0x00000002, 0x00000008, 0x00000004,
256 0x00000080, 0x00000040, 0x00000010, 0x00000020,
257 0x00008000, 0x00004000, 0x00001000, 0x00002000,
258 0x00000100, 0x00000200, 0x00000800, 0x00000400,
259
260 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
261 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
262 0x00010000, 0x00020000, 0x00080000, 0x00040000,
263 0x00800000, 0x00400000, 0x00100000, 0x00200000
264};
265
266/* ------------------------------------------------------------------------- */
267
7d12e780 268static irqreturn_t m8xx_interrupt(int irq, void *dev);
de957c89
MT		 269
270#define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
271
272/* ------------------------------------------------------------------------- */
273/* board specific stuff: */
274/* voltage_set(), hardware_enable() and hardware_disable() */
275/* ------------------------------------------------------------------------- */
276/* RPX Boards from Embedded Planet */
277
278#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
279
280/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
281 * SYPCR is write once only, therefore must the slowest memory be faster
282 * than the bus monitor or we will get a machine check due to the bus timeout.
283 */
284
285#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
286
287#undef PCMCIA_BMT_LIMIT
288#define PCMCIA_BMT_LIMIT (6*8)
289
290static int voltage_set(int slot, int vcc, int vpp)
291{
292 u32 reg = 0;
293
294 switch(vcc) {
295 case 0: break;
296 case 33:
297 reg |= BCSR1_PCVCTL4;
298 break;
299 case 50:
300 reg |= BCSR1_PCVCTL5;
301 break;
302 default:
303 return 1;
304 }
305
306 switch(vpp) {
307 case 0: break;
308 case 33:
309 case 50:
310 if(vcc == vpp)
311 reg |= BCSR1_PCVCTL6;
312 else
313 return 1;
314 break;
315 case 120:
316 reg |= BCSR1_PCVCTL7;
317 default:
318 return 1;
319 }
320
321 if(!((vcc == 50) || (vcc == 0)))
322 return 1;
323
324 /* first, turn off all power */
325
326 out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 | BCSR1_PCVCTL6 | BCSR1_PCVCTL7));
327
328 /* enable new powersettings */
329
330 out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) | reg);
331
332 return 0;
333}
334
335#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
336#define hardware_enable(_slot_) /* No hardware to enable */
337#define hardware_disable(_slot_) /* No hardware to disable */
338
339#endif /* CONFIG_RPXCLASSIC */
340
341/* FADS Boards from Motorola */
342
343#if defined(CONFIG_FADS)
344
345#define PCMCIA_BOARD_MSG "FADS"
346
347static int voltage_set(int slot, int vcc, int vpp)
348{
349 u32 reg = 0;
350
351 switch(vcc) {
352 case 0:
353 break;
354 case 33:
355 reg |= BCSR1_PCCVCC0;
356 break;
357 case 50:
358 reg |= BCSR1_PCCVCC1;
359 break;
360 default:
361 return 1;
362 }
363
364 switch(vpp) {
365 case 0:
366 break;
367 case 33:
368 case 50:
369 if(vcc == vpp)
370 reg |= BCSR1_PCCVPP1;
371 else
372 return 1;
373 break;
374 case 120:
375 if ((vcc == 33) || (vcc == 50))
376 reg |= BCSR1_PCCVPP0;
377 else
378 return 1;
379 default:
380 return 1;
381 }
382
383 /* first, turn off all power */
1371d3be
VB		 384 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK));
385
386 /* enable new powersettings */
387 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) | reg);
388
389 return 0;
390}
391
392#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
393
394static void hardware_enable(int slot)
395{
396 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) & ~BCSR1_PCCEN);
397}
398
399static void hardware_disable(int slot)
400{
401 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) | BCSR1_PCCEN);
402}
403
404#endif
405
406/* MPC885ADS Boards */
407
408#if defined(CONFIG_MPC885ADS)
409
410#define PCMCIA_BOARD_MSG "MPC885ADS"
411
412static int voltage_set(int slot, int vcc, int vpp)
413{
414 u32 reg = 0;
415 unsigned *bcsr_io;
416
417 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
418
419 switch(vcc) {
420 case 0:
421 break;
422 case 33:
423 reg |= BCSR1_PCCVCC0;
424 break;
425 case 50:
426 reg |= BCSR1_PCCVCC1;
427 break;
428 default:
3efa9970 429 goto out_unmap;
1371d3be
VB		 430 }
431
432 switch(vpp) {
433 case 0:
434 break;
435 case 33:
436 case 50:
437 if(vcc == vpp)
438 reg |= BCSR1_PCCVPP1;
439 else
3efa9970 440 goto out_unmap;
1371d3be
VB		 441 break;
442 case 120:
443 if ((vcc == 33) || (vcc == 50))
444 reg |= BCSR1_PCCVPP0;
445 else
3efa9970 446 goto out_unmap;
1371d3be 447 default:
3efa9970 448 goto out_unmap;
1371d3be
VB		 449 }
450
451 /* first, turn off all power */
452 out_be32(bcsr_io, in_be32(bcsr_io) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK));
de957c89
MT		 453
454 /* enable new powersettings */
1371d3be 455 out_be32(bcsr_io, in_be32(bcsr_io) | reg);
de957c89 456
1371d3be 457 iounmap(bcsr_io);
de957c89 458 return 0;
3efa9970
AL		 459
460out_unmap:
461 iounmap(bcsr_io);
462 return 1;
de957c89
MT		 463}
464
465#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
466
467static void hardware_enable(int slot)
468{
1371d3be
VB		 469 unsigned *bcsr_io;
470
471 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
472 out_be32(bcsr_io, in_be32(bcsr_io) & ~BCSR1_PCCEN);
473 iounmap(bcsr_io);
de957c89
MT		 474}
475
476static void hardware_disable(int slot)
477{
1371d3be
VB		 478 unsigned *bcsr_io;
479
480 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
481 out_be32(bcsr_io, in_be32(bcsr_io) | BCSR1_PCCEN);
482 iounmap(bcsr_io);
de957c89
MT		 483}
484
485#endif
486
487/* ------------------------------------------------------------------------- */
488/* Motorola MBX860 */
489
490#if defined(CONFIG_MBX)
491
492#define PCMCIA_BOARD_MSG "MBX"
493
494static int voltage_set(int slot, int vcc, int vpp)
495{
496 u8 reg = 0;
497
498 switch(vcc) {
499 case 0:
500 break;
501 case 33:
502 reg |= CSR2_VCC_33;
503 break;
504 case 50:
505 reg |= CSR2_VCC_50;
506 break;
507 default:
508 return 1;
509 }
510
511 switch(vpp) {
512 case 0:
513 break;
514 case 33:
515 case 50:
516 if(vcc == vpp)
517 reg |= CSR2_VPP_VCC;
518 else
519 return 1;
520 break;
521 case 120:
522 if ((vcc == 33) || (vcc == 50))
523 reg |= CSR2_VPP_12;
524 else
525 return 1;
526 default:
527 return 1;
528 }
529
530 /* first, turn off all power */
1371d3be 531 out_8((u8 *)MBX_CSR2_ADDR, in_8((u8 *)MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
de957c89
MT		 532
533 /* enable new powersettings */
1371d3be 534 out_8((u8 *)MBX_CSR2_ADDR, in_8((u8 *)MBX_CSR2_ADDR) | reg);
de957c89
MT		 535
536 return 0;
537}
538
539#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
540#define hardware_enable(_slot_) /* No hardware to enable */
541#define hardware_disable(_slot_) /* No hardware to disable */
542
543#endif /* CONFIG_MBX */
544
545#if defined(CONFIG_PRxK)
546#include <asm/cpld.h>
547extern volatile fpga_pc_regs *fpga_pc;
548
549#define PCMCIA_BOARD_MSG "MPC855T"
550
551static int voltage_set(int slot, int vcc, int vpp)
552{
553 u8 reg = 0;
554 u8 regread;
555 cpld_regs *ccpld = get_cpld();
556
557 switch(vcc) {
558 case 0:
559 break;
560 case 33:
561 reg |= PCMCIA_VCC_33;
562 break;
563 case 50:
564 reg |= PCMCIA_VCC_50;
565 break;
566 default:
567 return 1;
568 }
569
570 switch(vpp) {
571 case 0:
572 break;
573 case 33:
574 case 50:
575 if(vcc == vpp)
576 reg |= PCMCIA_VPP_VCC;
577 else
578 return 1;
579 break;
580 case 120:
581 if ((vcc == 33) || (vcc == 50))
582 reg |= PCMCIA_VPP_12;
583 else
584 return 1;
585 default:
586 return 1;
587 }
588
589 reg = reg >> (slot << 2);
590 regread = in_8(&ccpld->fpga_pc_ctl);
591 if (reg != (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
592 /* enable new powersettings */
593 regread = regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2));
594 out_8(&ccpld->fpga_pc_ctl, reg | regread);
595 msleep(100);
596 }
597
598 return 0;
599}
600
601#define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
602#define hardware_enable(_slot_) /* No hardware to enable */
603#define hardware_disable(_slot_) /* No hardware to disable */
604
605#endif /* CONFIG_PRxK */
606
607static void m8xx_shutdown(void)
608{
609 u32 m, i;
610 struct pcmcia_win *w;
611
612 for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
613 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
614
615 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, M8XX_PCMCIA_MASK(i));
616 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & ~M8XX_PCMCIA_MASK(i));
617
618 /* turn off interrupt and disable CxOE */
619 out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
620
621 /* turn off memory windows */
622 for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
623 out_be32(&w->or, 0); /* set to not valid */
624 w++;
625 }
626
627 /* turn off voltage */
628 voltage_set(i, 0, 0);
629
630 /* disable external hardware */
631 hardware_disable(i);
632 }
633
634 free_irq(pcmcia_schlvl, NULL);
635}
636
de957c89
MT		 637static struct device_driver m8xx_driver = {
638 .name = "m8xx-pcmcia",
639 .bus = &platform_bus_type,
e3463150
MT		 640 .suspend = pcmcia_socket_dev_suspend,
641 .resume = pcmcia_socket_dev_resume,
de957c89
MT		 642};
643
644static struct platform_device m8xx_device = {
645 .name = "m8xx-pcmcia",
646 .id = 0,
647};
648
649static u32 pending_events[PCMCIA_SOCKETS_NO];
34af946a 650static DEFINE_SPINLOCK(pending_event_lock);
de957c89 651
7d12e780 652static irqreturn_t m8xx_interrupt(int irq, void *dev)
de957c89
MT		 653{
654 struct socket_info *s;
655 struct event_table *e;
656 unsigned int i, events, pscr, pipr, per;
657
658 dprintk("Interrupt!\n");
659 /* get interrupt sources */
660
661 pscr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr);
662 pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
663 per = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per);
664
665 for(i = 0; i < PCMCIA_SOCKETS_NO; i++) {
666 s = &socket[i];
667 e = &s->events[0];
668 events = 0;
669
670 while(e->regbit) {
671 if(pscr & e->regbit)
672 events |= e->eventbit;
673
674 e++;
675 }
676
677 /*
678 * report only if both card detect signals are the same
679 * not too nice done,
680 * we depend on that CD2 is the bit to the left of CD1...
681 */
682 if(events & SS_DETECT)
683 if(((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
684 (pipr & M8XX_PCMCIA_CD1(i)))
685 {
686 events &= ~SS_DETECT;
687 }
688
689#ifdef PCMCIA_GLITCHY_CD
690 /*
691 * I've experienced CD problems with my ADS board.
692 * We make an extra check to see if there was a
693 * real change of Card detection.
694 */
695
696 if((events & SS_DETECT) &&
697 ((pipr &
698 (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
699 (s->state.Vcc | s->state.Vpp)) {
700 events &= ~SS_DETECT;
701 /*printk( "CD glitch workaround - CD = 0x%08x!\n",
702 (pipr & (M8XX_PCMCIA_CD2(i)
703 | M8XX_PCMCIA_CD1(i))));*/
704 }
705#endif
706
707 /* call the handler */
708
709 dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, "
710 "pipr = 0x%08x\n",
711 i, events, pscr, pipr);
712
713 if(events) {
714 spin_lock(&pending_event_lock);
715 pending_events[i] |= events;
716 spin_unlock(&pending_event_lock);
717 /*
718 * Turn off RDY_L bits in the PER mask on
719 * CD interrupt receival.
720 *
721 * They can generate bad interrupts on the
722 * ACS4,8,16,32. - marcelo
723 */
724 per &= ~M8XX_PCMCIA_RDY_L(0);
725 per &= ~M8XX_PCMCIA_RDY_L(1);
726
727 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, per);
728
729 if (events)
730 pcmcia_parse_events(&socket[i].socket, events);
731 }
732 }
733
734 /* clear the interrupt sources */
735 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, pscr);
736
737 dprintk("Interrupt done.\n");
738
739 return IRQ_HANDLED;
740}
741
742static u32 m8xx_get_graycode(u32 size)
743{
744 u32 k;
745
746 for(k = 0; k < M8XX_SIZES_NO; k++)
747 if(m8xx_size_to_gray[k] == size)
748 break;
749
750 if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
751 k = -1;
752
753 return k;
754}
755
756static u32 m8xx_get_speed(u32 ns, u32 is_io)
757{
758 u32 reg, clocks, psst, psl, psht;
759
760 if(!ns) {
761
762 /*
763 * We get called with IO maps setup to 0ns
764 * if not specified by the user.
765 * They should be 255ns.
766 */
767
768 if(is_io)
769 ns = 255;
770 else
771 ns = 100; /* fast memory if 0 */
772 }
773
774 /*
775 * In PSST, PSL, PSHT fields we tell the controller
776 * timing parameters in CLKOUT clock cycles.
777 * CLKOUT is the same as GCLK2_50.
778 */
779
780/* how we want to adjust the timing - in percent */
781
782#define ADJ 180 /* 80 % longer accesstime - to be sure */
783
784 clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
785 clocks = (clocks * ADJ) / (100*1000);
786 if(clocks >= PCMCIA_BMT_LIMIT) {
787 printk( "Max access time limit reached\n");
788 clocks = PCMCIA_BMT_LIMIT-1;
789 }
790
791 psst = clocks / 7; /* setup time */
792 psht = clocks / 7; /* hold time */
793 psl = (clocks * 5) / 7; /* strobe length */
794
795 psst += clocks - (psst + psht + psl);
796
797 reg = psst << 12;
798 reg |= psl << 7;
799 reg |= psht << 16;
800
801 return reg;
802}
803
804static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
805{
806 int lsock = container_of(sock, struct socket_info, socket)->slot;
807 struct socket_info *s = &socket[lsock];
808 unsigned int pipr, reg;
809
810 pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
811
812 *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
813 | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
814 *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
815
816 if (s->state.flags & SS_IOCARD)
817 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
818 else {
819 *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
820 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
821 *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
822 }
823
824 if (s->state.Vcc | s->state.Vpp)
825 *value |= SS_POWERON;
826
827 /*
828 * Voltage detection:
829 * This driver only supports 16-Bit pc-cards.
830 * Cardbus is not handled here.
831 *
832 * To determine what voltage to use we must read the VS1 and VS2 pin.
833 * Depending on what socket type is present,
834 * different combinations mean different things.
835 *
836 * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
837 *
838 * 5V 5V, LV* NC NC 5V only 5V (if available)
839 *
840 * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
841 *
842 * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
843 *
844 * LV* 5V - - shall not fit into socket
845 *
846 * LV* LV* GND NC 3.3V only 3.3V
847 *
848 * LV* LV* NC GND x.xV x.xV (if avail.)
849 *
850 * LV* LV* GND GND 3.3 or x.xV as low as possible
851 *
852 * *LV means Low Voltage
853 *
854 *
855 * That gives us the following table:
856 *
857 * Socket VS1 VS2 Voltage
858 *
859 * 5V NC NC 5V
860 * 5V NC GND none (should not be possible)
861 * 5V GND NC >= 3.3V
862 * 5V GND GND >= x.xV
863 *
864 * LV NC NC 5V (if available)
865 * LV NC GND x.xV (if available)
866 * LV GND NC 3.3V
867 * LV GND GND >= x.xV
868 *
869 * So, how do I determine if I have a 5V or a LV
870 * socket on my board? Look at the socket!
871 *
872 *
873 * Socket with 5V key:
874 * ++--------------------------------------------+
875 * || |
876 * || ||
877 * || ||
878 * | |
879 * +---------------------------------------------+
880 *
881 * Socket with LV key:
882 * ++--------------------------------------------+
883 * || |
884 * | ||
885 * | ||
886 * | |
887 * +---------------------------------------------+
888 *
889 *
890 * With other words - LV only cards does not fit
891 * into the 5V socket!
892 */
893
894 /* read out VS1 and VS2 */
895
896 reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
897 >> M8XX_PCMCIA_VS_SHIFT(lsock);
898
899 if(socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
900 switch(reg) {
901 case 1:
902 *value |= SS_3VCARD;
903 break; /* GND, NC - 3.3V only */
904 case 2:
905 *value |= SS_XVCARD;
906 break; /* NC. GND - x.xV only */
907 };
908 }
909
910 dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value);
911 return 0;
912}
913
de957c89
MT		 914static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
915{
916 int lsock = container_of(sock, struct socket_info, socket)->slot;
917 struct socket_info *s = &socket[lsock];
918 struct event_table *e;
919 unsigned int reg;
920 unsigned long flags;
921
922 dprintk( "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
923 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
924 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
925
926 /* First, set voltage - bail out if invalid */
927 if(voltage_set(lsock, state->Vcc, state->Vpp))
928 return -EINVAL;
929
930 /* Take care of reset... */
931 if(state->flags & SS_RESET)
932 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
933 else
934 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
935
936 /* ... and output enable. */
937
938 /* The CxOE signal is connected to a 74541 on the ADS.
939 I guess most other boards used the ADS as a reference.
940 I tried to control the CxOE signal with SS_OUTPUT_ENA,
941 but the reset signal seems connected via the 541.
942 If the CxOE is left high are some signals tristated and
943 no pullups are present -> the cards act wierd.
944 So right now the buffers are enabled if the power is on. */
945
946 if(state->Vcc || state->Vpp)
947 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
948 else
949 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
950
951 /*
952 * We'd better turn off interrupts before
953 * we mess with the events-table..
954 */
955
956 spin_lock_irqsave(&events_lock, flags);
957
958 /*
959 * Play around with the interrupt mask to be able to
960 * give the events the generic pcmcia driver wants us to.
961 */
962
963 e = &s->events[0];
964 reg = 0;
965
966 if(state->csc_mask & SS_DETECT) {
967 e->eventbit = SS_DETECT;
968 reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
969 | M8XX_PCMCIA_CD1(lsock));
970 e++;
971 }
972 if(state->flags & SS_IOCARD) {
973 /*
974 * I/O card
975 */
976 if(state->csc_mask & SS_STSCHG) {
977 e->eventbit = SS_STSCHG;
978 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
979 e++;
980 }
981 /*
982 * If io_irq is non-zero we should enable irq.
983 */
984 if(state->io_irq) {
985 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | mk_int_int_mask(state->io_irq) << 24);
986 /*
987 * Strange thing here:
988 * The manual does not tell us which interrupt
989 * the sources generate.
990 * Anyhow, I found out that RDY_L generates IREQLVL.
991 *
992 * We use level triggerd interrupts, and they don't
993 * have to be cleared in PSCR in the interrupt handler.
994 */
995 reg |= M8XX_PCMCIA_RDY_L(lsock);
996 }
997 else
998 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
999 }
1000 else {
1001 /*
1002 * Memory card
1003 */
1004 if(state->csc_mask & SS_BATDEAD) {
1005 e->eventbit = SS_BATDEAD;
1006 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
1007 e++;
1008 }
1009 if(state->csc_mask & SS_BATWARN) {
1010 e->eventbit = SS_BATWARN;
1011 reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
1012 e++;
1013 }
1014 /* What should I trigger on - low/high,raise,fall? */
1015 if(state->csc_mask & SS_READY) {
1016 e->eventbit = SS_READY;
1017 reg |= e->regbit = 0; //??
1018 e++;
1019 }
1020 }
1021
1022 e->regbit = 0; /* terminate list */
1023
1024 /*
1025 * Clear the status changed .
1026 * Port A and Port B share the same port.
1027 * Writing ones will clear the bits.
1028 */
1029
1030 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, reg);
1031
1032 /*
1033 * Write the mask.
1034 * Port A and Port B share the same port.
1035 * Need for read-modify-write.
1036 * Ones will enable the interrupt.
1037 */
1038
1039 /*
1040 reg |= ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per
1041 & M8XX_PCMCIA_MASK(lsock);
1042 */
1043
1044 reg |= in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
1045 (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1046
1047 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, reg);
1048
1049 spin_unlock_irqrestore(&events_lock, flags);
1050
1051 /* copy the struct and modify the copy */
1052
1053 s->state = *state;
1054
1055 return 0;
1056}
1057
1058static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
1059{
1060 int lsock = container_of(sock, struct socket_info, socket)->slot;
1061
1062 struct socket_info *s = &socket[lsock];
1063 struct pcmcia_win *w;
1064 unsigned int reg, winnr;
1065
1066#define M8XX_SIZE (io->stop - io->start + 1)
1067#define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
1068
1069 dprintk( "SetIOMap(%d, %d, %#2.2x, %d ns, "
1070 "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags,
1071 io->speed, io->start, io->stop);
1072
1073 if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
1074 || (io->stop > 0xffff) || (io->stop < io->start))
1075 return -EINVAL;
1076
1077 if((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
1078 return -EINVAL;
1079
1080 if(io->flags & MAP_ACTIVE) {
1081
1082 dprintk( "io->flags & MAP_ACTIVE\n");
1083
1084 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1085 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1086
1087 /* setup registers */
1088
1089 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1090 w += winnr;
1091
1092 out_be32(&w->or, 0); /* turn off window first */
1093 out_be32(&w->br, M8XX_BASE);
1094
1095 reg <<= 27;
1096 reg |= M8XX_PCMCIA_POR_IO |(lsock << 2);
1097
1098 reg |= m8xx_get_speed(io->speed, 1);
1099
1100 if(io->flags & MAP_WRPROT)
1101 reg |= M8XX_PCMCIA_POR_WRPROT;
1102
a94515fa 1103 if(io->flags & (MAP_16BIT | MAP_AUTOSZ))
de957c89
MT		 1104 reg |= M8XX_PCMCIA_POR_16BIT;
1105
1106 if(io->flags & MAP_ACTIVE)
1107 reg |= M8XX_PCMCIA_POR_VALID;
1108
1109 out_be32(&w->or, reg);
1110
1111 dprintk("Socket %u: Mapped io window %u at %#8.8x, "
1112 "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1113 } else {
1114 /* shutdown IO window */
1115 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1116 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1117
1118 /* setup registers */
1119
1120 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1121 w += winnr;
1122
1123 out_be32(&w->or, 0); /* turn off window */
1124 out_be32(&w->br, 0); /* turn off base address */
1125
1126 dprintk("Socket %u: Unmapped io window %u at %#8.8x, "
1127 "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1128 }
1129
1130 /* copy the struct and modify the copy */
1131 s->io_win[io->map] = *io;
1132 s->io_win[io->map].flags &= (MAP_WRPROT
1133 | MAP_16BIT
1134 | MAP_ACTIVE);
1135 dprintk("SetIOMap exit\n");
1136
1137 return 0;
1138}
1139
1140static int m8xx_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem)
1141{
1142 int lsock = container_of(sock, struct socket_info, socket)->slot;
1143 struct socket_info *s = &socket[lsock];
1144 struct pcmcia_win *w;
1145 struct pccard_mem_map *old;
1146 unsigned int reg, winnr;
1147
1148 dprintk( "SetMemMap(%d, %d, %#2.2x, %d ns, "
1149 "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
1150 mem->speed, mem->static_start, mem->card_start);
1151
1152 if ((mem->map >= PCMCIA_MEM_WIN_NO)
1153// || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
1154 || (mem->card_start >= 0x04000000)
1155 || (mem->static_start & 0xfff) /* 4KByte resolution */
1156 || (mem->card_start & 0xfff))
1157 return -EINVAL;
1158
1159 if((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1160 printk( "Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1161 return -EINVAL;
1162 }
1163 reg <<= 27;
1164
1165 winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1166
1167 /* Setup the window in the pcmcia controller */
1168
1169 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1170 w += winnr;
1171
1172 reg |= lsock << 2;
1173
1174 reg |= m8xx_get_speed(mem->speed, 0);
1175
1176 if(mem->flags & MAP_ATTRIB)
1177 reg |= M8XX_PCMCIA_POR_ATTRMEM;
1178
1179 if(mem->flags & MAP_WRPROT)
1180 reg |= M8XX_PCMCIA_POR_WRPROT;
1181
1182 if(mem->flags & MAP_16BIT)
1183 reg |= M8XX_PCMCIA_POR_16BIT;
1184
1185 if(mem->flags & MAP_ACTIVE)
1186 reg |= M8XX_PCMCIA_POR_VALID;
1187
1188 out_be32(&w->or, reg);
1189
1190 dprintk("Socket %u: Mapped memory window %u at %#8.8x, "
1191 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1192
1193 if(mem->flags & MAP_ACTIVE) {
1194 /* get the new base address */
1195 mem->static_start = PCMCIA_MEM_WIN_BASE +
1196 (PCMCIA_MEM_WIN_SIZE * winnr)
1197 + mem->card_start;
1198 }
1199
1200 dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, "
1201 "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
1202 mem->speed, mem->static_start, mem->card_start);
1203
1204 /* copy the struct and modify the copy */
1205
1206 old = &s->mem_win[mem->map];
1207
1208 *old = *mem;
1209 old->flags &= (MAP_ATTRIB
1210 | MAP_WRPROT
1211 | MAP_16BIT
1212 | MAP_ACTIVE);
1213
1214 return 0;
1215}
1216
1217static int m8xx_sock_init(struct pcmcia_socket *sock)
1218{
1219 int i;
1220 pccard_io_map io = { 0, 0, 0, 0, 1 };
1221 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1222
1223 dprintk( "sock_init(%d)\n", s);
1224
1225 m8xx_set_socket(sock, &dead_socket);
1226 for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1227 io.map = i;
1228 m8xx_set_io_map(sock, &io);
1229 }
1230 for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1231 mem.map = i;
1232 m8xx_set_mem_map(sock, &mem);
1233 }
1234
1235 return 0;
1236
1237}
1238
1239static int m8xx_suspend(struct pcmcia_socket *sock)
1240{
1241 return m8xx_set_socket(sock, &dead_socket);
1242}
1243
1244static struct pccard_operations m8xx_services = {
1245 .init = m8xx_sock_init,
1246 .suspend = m8xx_suspend,
1247 .get_status = m8xx_get_status,
de957c89
MT		 1248 .set_socket = m8xx_set_socket,
1249 .set_io_map = m8xx_set_io_map,
1250 .set_mem_map = m8xx_set_mem_map,
1251};
1252
1253static int __init m8xx_init(void)
1254{
1255 struct pcmcia_win *w;
1256 unsigned int i,m;
1257
1258 pcmcia_info("%s\n", version);
1259
1260 if (driver_register(&m8xx_driver))
1261 return -1;
1262
1263 pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1264 " with IRQ %u.\n", pcmcia_schlvl);
1265
1266 /* Configure Status change interrupt */
1267
1268 if(request_irq(pcmcia_schlvl, m8xx_interrupt, 0,
1269 "m8xx_pcmcia", NULL)) {
1270 pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
1271 pcmcia_schlvl);
1272 return -1;
1273 }
1274
1275 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1276
1277 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr,
1278 M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1));
1279
1280 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per,
1281 in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
1282 ~(M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1)));
1283
1284/* connect interrupt and disable CxOE */
1285
1286 out_be32(M8XX_PGCRX(0), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
1287 out_be32(M8XX_PGCRX(1), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
1288
1289/* intialize the fixed memory windows */
1290
1291 for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
1292 for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1293 out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
1294 (PCMCIA_MEM_WIN_SIZE
1295 * (m + i * PCMCIA_MEM_WIN_NO)));
1296
1297 out_be32(&w->or, 0); /* set to not valid */
1298
1299 w++;
1300 }
1301 }
1302
1303/* turn off voltage */
1304 voltage_set(0, 0, 0);
1305 voltage_set(1, 0, 0);
1306
1307/* Enable external hardware */
1308 hardware_enable(0);
1309 hardware_enable(1);
1310
1311 platform_device_register(&m8xx_device);
1312
1313 for (i = 0 ; i < PCMCIA_SOCKETS_NO; i++) {
1314 socket[i].slot = i;
1315 socket[i].socket.owner = THIS_MODULE;
1316 socket[i].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
1317 socket[i].socket.irq_mask = 0x000;
1318 socket[i].socket.map_size = 0x1000;
1319 socket[i].socket.io_offset = 0;
1320 socket[i].socket.pci_irq = i ? 7 : 9;
1321 socket[i].socket.ops = &m8xx_services;
3b27e942 1322 socket[i].socket.resource_ops = &pccard_iodyn_ops;
de957c89
MT		 1323 socket[i].socket.cb_dev = NULL;
1324 socket[i].socket.dev.dev = &m8xx_device.dev;
1325 }
1326
1327 for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1328 pcmcia_register_socket(&socket[i].socket);
1329
1330 return 0;
1331}
1332
1333static void __exit m8xx_exit(void)
1334{
1335 int i;
1336
1337 for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1338 pcmcia_unregister_socket(&socket[i].socket);
1339
1340 m8xx_shutdown();
1341
1342 platform_device_unregister(&m8xx_device);
1343 driver_unregister(&m8xx_driver);
1344}
1345
1346module_init(m8xx_init);
1347module_exit(m8xx_exit);
kernel source for telekom puls (alcatel/mediatek)