[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pcmcia / m32r_pcc.c

/*
 *  drivers/pcmcia/m32r_pcc.c
 *
 *  Device driver for the PCMCIA functionality of M32R.
 *
 *  Copyright (c) 2001, 2002, 2003, 2004
 *    Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/timer.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/bitops.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/addrspace.h>

#include <pcmcia/ss.h>

/* XXX: should be moved into asm/irq.h */
#define PCC0_IRQ 24
#define PCC1_IRQ 25

#include "m32r_pcc.h"

#define CHAOS_PCC_DEBUG
#ifdef CHAOS_PCC_DEBUG
	static volatile u_short dummy_readbuf;
#endif

#define PCC_DEBUG_DBEX


/* Poll status interval -- 0 means default to interrupt */
static int poll_interval = 0;

typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;

typedef struct pcc_socket {
	u_short			type, flags;
	struct pcmcia_socket	socket;
	unsigned int		number;
	unsigned int		ioaddr;
	u_long			mapaddr;
	u_long			base;	/* PCC register base */
	u_char			cs_irq, intr;
	pccard_io_map		io_map[MAX_IO_WIN];
	pccard_mem_map		mem_map[MAX_WIN];
	u_char			io_win;
	u_char			mem_win;
	pcc_as_t		current_space;
	u_char			last_iodbex;
#ifdef CHAOS_PCC_DEBUG
	u_char			last_iosize;
#endif
#ifdef CONFIG_PROC_FS
	struct proc_dir_entry *proc;
#endif
} pcc_socket_t;

static int pcc_sockets = 0;
static pcc_socket_t socket[M32R_MAX_PCC] = {
	{ 0, }, /* ... */
};

/*====================================================================*/

static unsigned int pcc_get(u_short, unsigned int);
static void pcc_set(u_short, unsigned int , unsigned int );

static DEFINE_SPINLOCK(pcc_lock);

void pcc_iorw(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int wr, int flag)
{
	u_long addr;
	u_long flags;
	int need_ex;
#ifdef PCC_DEBUG_DBEX
	int _dbex;
#endif
	pcc_socket_t *t = &socket[sock];
#ifdef CHAOS_PCC_DEBUG
	int map_changed = 0;
#endif

	/* Need lock ? */
	spin_lock_irqsave(&pcc_lock, flags);

	/*
	 * Check if need dbex
	 */
	need_ex = (size > 1 && flag == 0) ? PCMOD_DBEX : 0;
#ifdef PCC_DEBUG_DBEX
	_dbex = need_ex;
	need_ex = 0;
#endif

	/*
	 * calculate access address
	 */
	addr = t->mapaddr + port - t->ioaddr + KSEG1; /* XXX */

	/*
	 * Check current mapping
	 */
	if (t->current_space != as_io || t->last_iodbex != need_ex) {

		u_long cbsz;

		/*
		 * Disable first
		 */
		pcc_set(sock, PCCR, 0);

		/*
		 * Set mode and io address
		 */
		cbsz = (t->flags & MAP_16BIT) ? 0 : PCMOD_CBSZ;
		pcc_set(sock, PCMOD, PCMOD_AS_IO | cbsz | need_ex);
		pcc_set(sock, PCADR, addr & 0x1ff00000);

		/*
		 * Enable and read it
		 */
		pcc_set(sock, PCCR, 1);

#ifdef CHAOS_PCC_DEBUG
#if 0
		map_changed = (t->current_space == as_attr && size == 2); /* XXX */
#else
		map_changed = 1;
#endif
#endif
		t->current_space = as_io;
	}

	/*
	 * access to IO space
	 */
	if (size == 1) {
		/* Byte */
		unsigned char *bp = (unsigned char *)buf;

#ifdef CHAOS_DEBUG
		if (map_changed) {
			dummy_readbuf = readb(addr);
		}
#endif
		if (wr) {
			/* write Byte */
			while (nmemb--) {
				writeb(*bp++, addr);
			}
		} else {
			/* read Byte */
			while (nmemb--) {
	    		*bp++ = readb(addr);
			}
		}
	} else {
		/* Word */
		unsigned short *bp = (unsigned short *)buf;

#ifdef CHAOS_PCC_DEBUG
		if (map_changed) {
			dummy_readbuf = readw(addr);
		}
#endif
		if (wr) {
			/* write Word */
			while (nmemb--) {
#ifdef PCC_DEBUG_DBEX
				if (_dbex) {
					unsigned char *cp = (unsigned char *)bp;
					unsigned short tmp;
					tmp = cp[1] << 8 | cp[0];
					writew(tmp, addr);
					bp++;
				} else
#endif
				writew(*bp++, addr);
	    	}
	    } else {
	    	/* read Word */
	    	while (nmemb--) {
#ifdef  PCC_DEBUG_DBEX
				if (_dbex) {
					unsigned char *cp = (unsigned char *)bp;
					unsigned short tmp;
					tmp = readw(addr);
					cp[0] = tmp & 0xff;
					cp[1] = (tmp >> 8) & 0xff;
					bp++;
				} else
#endif
				*bp++ = readw(addr);
	    	}
	    }
	}

#if 1
	/* addr is no longer used */
	if ((addr = pcc_get(sock, PCIRC)) & PCIRC_BWERR) {
	  printk("m32r_pcc: BWERR detected : port 0x%04lx : iosize %dbit\n",
			 port, size * 8);
	  pcc_set(sock, PCIRC, addr);
	}
#endif
	/*
	 * save state
	 */
	t->last_iosize = size;
	t->last_iodbex = need_ex;

	/* Need lock ? */

	spin_unlock_irqrestore(&pcc_lock,flags);

	return;
}

void pcc_ioread(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
	pcc_iorw(sock, port, buf, size, nmemb, 0, flag);
}

void pcc_iowrite(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
    pcc_iorw(sock, port, buf, size, nmemb, 1, flag);
}

/*====================================================================*/

#define IS_REGISTERED		0x2000
#define IS_ALIVE		0x8000

typedef struct pcc_t {
	char			*name;
	u_short			flags;
} pcc_t;

static pcc_t pcc[] = {
	{ "xnux2", 0 }, { "xnux2", 0 },
};

static irqreturn_t pcc_interrupt(int, void *);

/*====================================================================*/

static struct timer_list poll_timer;

static unsigned int pcc_get(u_short sock, unsigned int reg)
{
	return inl(socket[sock].base + reg);
}


static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
{
  	outl(data, socket[sock].base + reg);
}

/*======================================================================

	See if a card is present, powered up, in IO mode, and already
	bound to a (non PC Card) Linux driver.  We leave these alone.

	We make an exception for cards that seem to be serial devices.

======================================================================*/

static int __init is_alive(u_short sock)
{
	unsigned int stat;
	unsigned int f;

	stat = pcc_get(sock, PCIRC);
	f = (stat & (PCIRC_CDIN1 | PCIRC_CDIN2)) >> 16;
	if(!f){
		printk("m32r_pcc: No Card is detected at socket %d : stat = 0x%08x\n",stat,sock);
		return 0;
	}
	if(f!=3)
		printk("m32r_pcc: Insertion fail (%.8x) at socket %d\n",stat,sock);
	else
		printk("m32r_pcc: Card is Inserted at socket %d(%.8x)\n",sock,stat);
	return 0;
}

static void add_pcc_socket(ulong base, int irq, ulong mapaddr,
			   unsigned int ioaddr)
{
  	pcc_socket_t *t = &socket[pcc_sockets];

	/* add sockets */
	t->ioaddr = ioaddr;
	t->mapaddr = mapaddr;
	t->base = base;
#ifdef CHAOS_PCC_DEBUG
	t->flags = MAP_16BIT;
#else
	t->flags = 0;
#endif
	if (is_alive(pcc_sockets))
		t->flags |= IS_ALIVE;

	/* add pcc */
	if (t->base > 0) {
		request_region(t->base, 0x20, "m32r-pcc");
	}

	printk(KERN_INFO "  %s ", pcc[pcc_sockets].name);
	printk("pcc at 0x%08lx\n", t->base);

	/* Update socket interrupt information, capabilities */
	t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
	t->socket.map_size = M32R_PCC_MAPSIZE;
	t->socket.io_offset = ioaddr;	/* use for io access offset */
	t->socket.irq_mask = 0;
	t->socket.pci_irq = 2 + pcc_sockets; /* XXX */

	request_irq(irq, pcc_interrupt, 0, "m32r-pcc", pcc_interrupt);

	pcc_sockets++;

	return;
}


/*====================================================================*/

static irqreturn_t pcc_interrupt(int irq, void *dev)
{
	int i, j, irc;
	u_int events, active;
	int handled = 0;

	pr_debug("m32r_pcc: pcc_interrupt(%d)\n", irq);

	for (j = 0; j < 20; j++) {
		active = 0;
		for (i = 0; i < pcc_sockets; i++) {
			if ((socket[i].cs_irq != irq) &&
				(socket[i].socket.pci_irq != irq))
				continue;
			handled = 1;
			irc = pcc_get(i, PCIRC);
			irc >>=16;
			pr_debug("m32r_pcc: interrupt: socket %d pcirc 0x%02x ",
				i, irc);
			if (!irc)
				continue;

			events = (irc) ? SS_DETECT : 0;
			events |= (pcc_get(i,PCCR) & PCCR_PCEN) ? SS_READY : 0;
			pr_debug("m32r_pcc: event 0x%02x\n", events);

			if (events)
				pcmcia_parse_events(&socket[i].socket, events);

			active |= events;
			active = 0;
		}
		if (!active) break;
	}
	if (j == 20)
		printk(KERN_NOTICE "m32r-pcc: infinite loop in interrupt handler\n");

	pr_debug("m32r_pcc: interrupt done\n");

	return IRQ_RETVAL(handled);
} /* pcc_interrupt */

static void pcc_interrupt_wrapper(u_long data)
{
	pcc_interrupt(0, NULL);
	init_timer(&poll_timer);
	poll_timer.expires = jiffies + poll_interval;
	add_timer(&poll_timer);
}

/*====================================================================*/

static int _pcc_get_status(u_short sock, u_int *value)
{
	u_int status;

	status = pcc_get(sock,PCIRC);
	*value = ((status & PCIRC_CDIN1) && (status & PCIRC_CDIN2))
		? SS_DETECT : 0;

	status = pcc_get(sock,PCCR);

#if 0
	*value |= (status & PCCR_PCEN) ? SS_READY : 0;
#else
	*value |= SS_READY; /* XXX: always */
#endif

	status = pcc_get(sock,PCCSIGCR);
	*value |= (status & PCCSIGCR_VEN) ? SS_POWERON : 0;

	pr_debug("m32r_pcc: GetStatus(%d) = %#4.4x\n", sock, *value);
	return 0;
} /* _get_status */

/*====================================================================*/

static int _pcc_set_socket(u_short sock, socket_state_t *state)
{
	u_long reg = 0;

	pr_debug("m32r_pcc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
		  "io_irq %d, csc_mask %#2.2x)", sock, state->flags,
		  state->Vcc, state->Vpp, state->io_irq, state->csc_mask);

	if (state->Vcc) {
		/*
		 * 5V only
		 */
		if (state->Vcc == 50) {
			reg |= PCCSIGCR_VEN;
		} else {
			return -EINVAL;
		}
	}

	if (state->flags & SS_RESET) {
		pr_debug("m32r_pcc: :RESET\n");
		reg |= PCCSIGCR_CRST;
	}
	if (state->flags & SS_OUTPUT_ENA){
		pr_debug("m32r_pcc: :OUTPUT_ENA\n");
		/* bit clear */
	} else {
		reg |= PCCSIGCR_SEN;
	}

	pcc_set(sock,PCCSIGCR,reg);

	if(state->flags & SS_IOCARD){
		pr_debug("m32r_pcc: :IOCARD");
	}
	if (state->flags & SS_PWR_AUTO) {
		pr_debug("m32r_pcc: :PWR_AUTO");
	}
	if (state->csc_mask & SS_DETECT)
		pr_debug("m32r_pcc: :csc-SS_DETECT");
	if (state->flags & SS_IOCARD) {
		if (state->csc_mask & SS_STSCHG)
			pr_debug("m32r_pcc: :STSCHG");
	} else {
		if (state->csc_mask & SS_BATDEAD)
			pr_debug("m32r_pcc: :BATDEAD");
		if (state->csc_mask & SS_BATWARN)
			pr_debug("m32r_pcc: :BATWARN");
		if (state->csc_mask & SS_READY)
			pr_debug("m32r_pcc: :READY");
	}
	pr_debug("m32r_pcc: \n");
	return 0;
} /* _set_socket */

/*====================================================================*/

static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
{
	u_char map;

	pr_debug("m32r_pcc: SetIOMap(%d, %d, %#2.2x, %d ns, "
		  "%#llx-%#llx)\n", sock, io->map, io->flags,
		  io->speed, (unsigned long long)io->start,
		  (unsigned long long)io->stop);
	map = io->map;

	return 0;
} /* _set_io_map */

/*====================================================================*/

static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
{

	u_char map = mem->map;
	u_long mode;
	u_long addr;
	pcc_socket_t *t = &socket[sock];
#ifdef CHAOS_PCC_DEBUG
#if 0
	pcc_as_t last = t->current_space;
#endif
#endif

	pr_debug("m32r_pcc: SetMemMap(%d, %d, %#2.2x, %d ns, "
		 "%#llx,  %#x)\n", sock, map, mem->flags,
		 mem->speed, (unsigned long long)mem->static_start,
		 mem->card_start);

	/*
	 * sanity check
	 */
	if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
		return -EINVAL;
	}

	/*
	 * de-activate
	 */
	if ((mem->flags & MAP_ACTIVE) == 0) {
		t->current_space = as_none;
		return 0;
	}

	/*
	 * Disable first
	 */
	pcc_set(sock, PCCR, 0);

	/*
	 * Set mode
	 */
	if (mem->flags & MAP_ATTRIB) {
		mode = PCMOD_AS_ATTRIB | PCMOD_CBSZ;
		t->current_space = as_attr;
	} else {
		mode = 0; /* common memory */
		t->current_space = as_comm;
	}
	pcc_set(sock, PCMOD, mode);

	/*
	 * Set address
	 */
	addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
	pcc_set(sock, PCADR, addr);

	mem->static_start = addr + mem->card_start;

	/*
	 * Enable again
	 */
	pcc_set(sock, PCCR, 1);

#ifdef CHAOS_PCC_DEBUG
#if 0
	if (last != as_attr) {
#else
	if (1) {
#endif
		dummy_readbuf = *(u_char *)(addr + KSEG1);
	}
#endif

	return 0;

} /* _set_mem_map */

#if 0 /* driver model ordering issue */
/*======================================================================

	Routines for accessing socket information and register dumps via
	/proc/bus/pccard/...

======================================================================*/

static ssize_t show_info(struct class_device *class_dev, char *buf)
{
	pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
		socket.dev);

	return sprintf(buf, "type:     %s\nbase addr:    0x%08lx\n",
		pcc[s->type].name, s->base);
}

static ssize_t show_exca(struct class_device *class_dev, char *buf)
{
	/* FIXME */

	return 0;
}

static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
#endif

/*====================================================================*/

/* this is horribly ugly... proper locking needs to be done here at
 * some time... */
#define LOCKED(x) do {					\
	int retval;					\
	unsigned long flags;				\
	spin_lock_irqsave(&pcc_lock, flags);		\
	retval = x;					\
	spin_unlock_irqrestore(&pcc_lock, flags);	\
	return retval;					\
} while (0)


static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
{
	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;

	if (socket[sock].flags & IS_ALIVE) {
		*value = 0;
		return -EINVAL;
	}
	LOCKED(_pcc_get_status(sock, value));
}

static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
{
	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;

	if (socket[sock].flags & IS_ALIVE)
		return -EINVAL;

	LOCKED(_pcc_set_socket(sock, state));
}

static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
{
	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;

	if (socket[sock].flags & IS_ALIVE)
		return -EINVAL;
	LOCKED(_pcc_set_io_map(sock, io));
}

static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
{
	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;

	if (socket[sock].flags & IS_ALIVE)
		return -EINVAL;
	LOCKED(_pcc_set_mem_map(sock, mem));
}

static int pcc_init(struct pcmcia_socket *s)
{
	pr_debug("m32r_pcc: init call\n");
	return 0;
}

static struct pccard_operations pcc_operations = {
	.init			= pcc_init,
	.get_status		= pcc_get_status,
	.set_socket		= pcc_set_socket,
	.set_io_map		= pcc_set_io_map,
	.set_mem_map		= pcc_set_mem_map,
};

/*====================================================================*/

static struct platform_driver pcc_driver = {
	.driver = {
		.name		= "pcc",
		.owner		= THIS_MODULE,
	},
};

static struct platform_device pcc_device = {
	.name = "pcc",
	.id = 0,
};

/*====================================================================*/

static int __init init_m32r_pcc(void)
{
	int i, ret;

	ret = platform_driver_register(&pcc_driver);
	if (ret)
		return ret;

	ret = platform_device_register(&pcc_device);
	if (ret){
		platform_driver_unregister(&pcc_driver);
		return ret;
	}

	printk(KERN_INFO "m32r PCC probe:\n");

	pcc_sockets = 0;

	add_pcc_socket(M32R_PCC0_BASE, PCC0_IRQ, M32R_PCC0_MAPBASE, 0x1000);

#ifdef CONFIG_M32RPCC_SLOT2
	add_pcc_socket(M32R_PCC1_BASE, PCC1_IRQ, M32R_PCC1_MAPBASE, 0x2000);
#endif

	if (pcc_sockets == 0) {
		printk("socket is not found.\n");
		platform_device_unregister(&pcc_device);
		platform_driver_unregister(&pcc_driver);
		return -ENODEV;
	}

	/* Set up interrupt handler(s) */

	for (i = 0 ; i < pcc_sockets ; i++) {
		socket[i].socket.dev.parent = &pcc_device.dev;
		socket[i].socket.ops = &pcc_operations;
		socket[i].socket.resource_ops = &pccard_static_ops;
		socket[i].socket.owner = THIS_MODULE;
		socket[i].number = i;
		ret = pcmcia_register_socket(&socket[i].socket);
		if (!ret)
			socket[i].flags |= IS_REGISTERED;

#if 0	/* driver model ordering issue */
		class_device_create_file(&socket[i].socket.dev,
					 &class_device_attr_info);
		class_device_create_file(&socket[i].socket.dev,
					 &class_device_attr_exca);
#endif
	}

	/* Finally, schedule a polling interrupt */
	if (poll_interval != 0) {
		poll_timer.function = pcc_interrupt_wrapper;
		poll_timer.data = 0;
		init_timer(&poll_timer);
		poll_timer.expires = jiffies + poll_interval;
		add_timer(&poll_timer);
	}

	return 0;
} /* init_m32r_pcc */

static void __exit exit_m32r_pcc(void)
{
	int i;

	for (i = 0; i < pcc_sockets; i++)
		if (socket[i].flags & IS_REGISTERED)
			pcmcia_unregister_socket(&socket[i].socket);

	platform_device_unregister(&pcc_device);
	if (poll_interval != 0)
		del_timer_sync(&poll_timer);

	platform_driver_unregister(&pcc_driver);
} /* exit_m32r_pcc */

module_init(init_m32r_pcc);
module_exit(exit_m32r_pcc);
MODULE_LICENSE("Dual MPL/GPL");
/*====================================================================*/
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pcmcia/m32r_pcc.c
	3	*
	4	* Device driver for the PCMCIA functionality of M32R.
	5	*
	6	* Copyright (c) 2001, 2002, 2003, 2004
	7	* Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/moduleparam.h>
	12	#include <linux/init.h>
1da177e4 LT	13	#include <linux/types.h>
	14	#include <linux/fcntl.h>
	15	#include <linux/string.h>
	16	#include <linux/kernel.h>
	17	#include <linux/errno.h>
	18	#include <linux/timer.h>
1da177e4 LT	19	#include <linux/ioport.h>
	20	#include <linux/delay.h>
	21	#include <linux/workqueue.h>
	22	#include <linux/interrupt.h>
d052d1be	23	#include <linux/platform_device.h>
1977f032	24	#include <linux/bitops.h>
1da177e4 LT	25	#include <asm/irq.h>
1da177e4 LT	26	#include <asm/io.h>
1da177e4 LT	27	#include <asm/addrspace.h>
1da177e4 LT	28
1da177e4	29	#include <pcmcia/ss.h>
1da177e4 LT	30
	31	/* XXX: should be moved into asm/irq.h */
	32	#define PCC0_IRQ 24
	33	#define PCC1_IRQ 25
	34
	35	#include "m32r_pcc.h"
	36
	37	#define CHAOS_PCC_DEBUG
	38	#ifdef CHAOS_PCC_DEBUG
	39	static volatile u_short dummy_readbuf;
	40	#endif
	41
	42	#define PCC_DEBUG_DBEX
	43
1da177e4 LT	44
	45	/* Poll status interval -- 0 means default to interrupt */
	46	static int poll_interval = 0;
	47
	48	typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
	49
	50	typedef struct pcc_socket {
	51	u_short type, flags;
	52	struct pcmcia_socket socket;
	53	unsigned int number;
906da809	54	unsigned int ioaddr;
1da177e4 LT	55	u_long mapaddr;
	56	u_long base; /* PCC register base */
	57	u_char cs_irq, intr;
	58	pccard_io_map io_map[MAX_IO_WIN];
	59	pccard_mem_map mem_map[MAX_WIN];
	60	u_char io_win;
	61	u_char mem_win;
	62	pcc_as_t current_space;
	63	u_char last_iodbex;
	64	#ifdef CHAOS_PCC_DEBUG
	65	u_char last_iosize;
	66	#endif
	67	#ifdef CONFIG_PROC_FS
	68	struct proc_dir_entry *proc;
	69	#endif
	70	} pcc_socket_t;
	71
	72	static int pcc_sockets = 0;
	73	static pcc_socket_t socket[M32R_MAX_PCC] = {
	74	{ 0, }, /* ... */
	75	};
	76
	77	/====================================================================/
	78
	79	static unsigned int pcc_get(u_short, unsigned int);
	80	static void pcc_set(u_short, unsigned int , unsigned int );
	81
	82	static DEFINE_SPINLOCK(pcc_lock);
	83
	84	void pcc_iorw(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int wr, int flag)
	85	{
	86	u_long addr;
	87	u_long flags;
	88	int need_ex;
	89	#ifdef PCC_DEBUG_DBEX
	90	int _dbex;
	91	#endif
	92	pcc_socket_t *t = &socket[sock];
	93	#ifdef CHAOS_PCC_DEBUG
	94	int map_changed = 0;
	95	#endif
	96
	97	/* Need lock ? */
	98	spin_lock_irqsave(&pcc_lock, flags);
	99
	100	/*
	101	* Check if need dbex
	102	*/
	103	need_ex = (size > 1 && flag == 0) ? PCMOD_DBEX : 0;
	104	#ifdef PCC_DEBUG_DBEX
	105	_dbex = need_ex;
	106	need_ex = 0;
	107	#endif
	108
	109	/*
	110	* calculate access address
	111	*/
	112	addr = t->mapaddr + port - t->ioaddr + KSEG1; /* XXX */
	113
	114	/*
	115	* Check current mapping
	116	*/
	117	if (t->current_space != as_io \|\| t->last_iodbex != need_ex) {
	118
119	u_long cbsz;
120
121	/*
122	* Disable first
123	*/
124	pcc_set(sock, PCCR, 0);
125
126	/*
127	* Set mode and io address
128	*/
129	cbsz = (t->flags & MAP_16BIT) ? 0 : PCMOD_CBSZ;
130	pcc_set(sock, PCMOD, PCMOD_AS_IO \| cbsz \| need_ex);
131	pcc_set(sock, PCADR, addr & 0x1ff00000);
132
133	/*
134	* Enable and read it
135	*/
136	pcc_set(sock, PCCR, 1);
137
138	#ifdef CHAOS_PCC_DEBUG
139	#if 0
140	map_changed = (t->current_space == as_attr && size == 2); /* XXX */
141	#else
142	map_changed = 1;
143	#endif
144	#endif
145	t->current_space = as_io;
146	}
147
148	/*
149	* access to IO space
150	*/
151	if (size == 1) {
152	/* Byte */
153	unsigned char bp = (unsigned char )buf;
154
155	#ifdef CHAOS_DEBUG
156	if (map_changed) {
157	dummy_readbuf = readb(addr);
158	}
159	#endif
160	if (wr) {
161	/* write Byte */
162	while (nmemb--) {
163	writeb(*bp++, addr);
164	}
165	} else {
166	/* read Byte */
167	while (nmemb--) {
168	*bp++ = readb(addr);
169	}
170	}
171	} else {
172	/* Word */
173	unsigned short bp = (unsigned short )buf;
174
175	#ifdef CHAOS_PCC_DEBUG
176	if (map_changed) {
177	dummy_readbuf = readw(addr);
178	}
179	#endif
180	if (wr) {
181	/* write Word */
182	while (nmemb--) {
183	#ifdef PCC_DEBUG_DBEX
184	if (_dbex) {
185	unsigned char cp = (unsigned char )bp;
186	unsigned short tmp;
187	tmp = cp[1] << 8 \| cp[0];
188	writew(tmp, addr);
189	bp++;
190	} else
191	#endif
192	writew(*bp++, addr);
193	}
194	} else {
195	/* read Word */
196	while (nmemb--) {
197	#ifdef PCC_DEBUG_DBEX
198	if (_dbex) {
199	unsigned char cp = (unsigned char )bp;
200	unsigned short tmp;
201	tmp = readw(addr);
202	cp[0] = tmp & 0xff;
203	cp[1] = (tmp >> 8) & 0xff;
204	bp++;
205	} else
206	#endif
207	*bp++ = readw(addr);
208	}
209	}
210	}
211
212	#if 1
213	/* addr is no longer used */
214	if ((addr = pcc_get(sock, PCIRC)) & PCIRC_BWERR) {
215	printk("m32r_pcc: BWERR detected : port 0x%04lx : iosize %dbit\n",
216	port, size * 8);
217	pcc_set(sock, PCIRC, addr);
218	}
219	#endif
220	/*
221	* save state
222	*/
223	t->last_iosize = size;
224	t->last_iodbex = need_ex;
225
226	/* Need lock ? */
227
228	spin_unlock_irqrestore(&pcc_lock,flags);
229
230	return;
231	}
232
233	void pcc_ioread(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
234	pcc_iorw(sock, port, buf, size, nmemb, 0, flag);
235	}
236
237	void pcc_iowrite(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
238	pcc_iorw(sock, port, buf, size, nmemb, 1, flag);
239	}
240
241	/====================================================================/
242
243	#define IS_REGISTERED 0x2000
244	#define IS_ALIVE 0x8000
245
246	typedef struct pcc_t {
247	char *name;
248	u_short flags;
249	} pcc_t;
250
251	static pcc_t pcc[] = {
252	{ "xnux2", 0 }, { "xnux2", 0 },
253	};
254
7d12e780	255	static irqreturn_t pcc_interrupt(int, void *);
1da177e4 LT	256
	257	/====================================================================/
	258
	259	static struct timer_list poll_timer;
	260
	261	static unsigned int pcc_get(u_short sock, unsigned int reg)
	262	{
	263	return inl(socket[sock].base + reg);
	264	}
	265
	266
	267	static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
	268	{
	269	outl(data, socket[sock].base + reg);
	270	}
	271
	272	/*======================================================================
	273
	274	See if a card is present, powered up, in IO mode, and already
	275	bound to a (non PC Card) Linux driver. We leave these alone.
	276
	277	We make an exception for cards that seem to be serial devices.
	278
	279	======================================================================*/
	280
	281	static int __init is_alive(u_short sock)
	282	{
	283	unsigned int stat;
	284	unsigned int f;
	285
	286	stat = pcc_get(sock, PCIRC);
	287	f = (stat & (PCIRC_CDIN1 \| PCIRC_CDIN2)) >> 16;
	288	if(!f){
	289	printk("m32r_pcc: No Card is detected at socket %d : stat = 0x%08x\n",stat,sock);
	290	return 0;
	291	}
	292	if(f!=3)
	293	printk("m32r_pcc: Insertion fail (%.8x) at socket %d\n",stat,sock);
	294	else
	295	printk("m32r_pcc: Card is Inserted at socket %d(%.8x)\n",sock,stat);
	296	return 0;
	297	}
	298
906da809 OJ	299	static void add_pcc_socket(ulong base, int irq, ulong mapaddr,
906da809 OJ	300	unsigned int ioaddr)
1da177e4 LT	301	{
	302	pcc_socket_t *t = &socket[pcc_sockets];
	303
	304	/* add sockets */
	305	t->ioaddr = ioaddr;
	306	t->mapaddr = mapaddr;
	307	t->base = base;
	308	#ifdef CHAOS_PCC_DEBUG
	309	t->flags = MAP_16BIT;
	310	#else
	311	t->flags = 0;
	312	#endif
	313	if (is_alive(pcc_sockets))
	314	t->flags \|= IS_ALIVE;
	315
	316	/* add pcc */
	317	if (t->base > 0) {
	318	request_region(t->base, 0x20, "m32r-pcc");
	319	}
	320
	321	printk(KERN_INFO " %s ", pcc[pcc_sockets].name);
	322	printk("pcc at 0x%08lx\n", t->base);
	323
	324	/* Update socket interrupt information, capabilities */
	325	t->socket.features \|= (SS_CAP_PCCARD \| SS_CAP_STATIC_MAP);
	326	t->socket.map_size = M32R_PCC_MAPSIZE;
	327	t->socket.io_offset = ioaddr; /* use for io access offset */
	328	t->socket.irq_mask = 0;
	329	t->socket.pci_irq = 2 + pcc_sockets; /* XXX */
	330
	331	request_irq(irq, pcc_interrupt, 0, "m32r-pcc", pcc_interrupt);
	332
	333	pcc_sockets++;
	334
	335	return;
	336	}
	337
	338
	339	/====================================================================/
	340
7d12e780	341	static irqreturn_t pcc_interrupt(int irq, void *dev)
1da177e4 LT	342	{
	343	int i, j, irc;
	344	u_int events, active;
	345	int handled = 0;
	346
c9f50ddd	347	pr_debug("m32r_pcc: pcc_interrupt(%d)\n", irq);
1da177e4 LT	348
	349	for (j = 0; j < 20; j++) {
	350	active = 0;
	351	for (i = 0; i < pcc_sockets; i++) {
	352	if ((socket[i].cs_irq != irq) &&
	353	(socket[i].socket.pci_irq != irq))
	354	continue;
	355	handled = 1;
	356	irc = pcc_get(i, PCIRC);
	357	irc >>=16;
c9f50ddd DB	358	pr_debug("m32r_pcc: interrupt: socket %d pcirc 0x%02x ",
c9f50ddd DB	359	i, irc);
1da177e4 LT	360	if (!irc)
	361	continue;
	362
	363	events = (irc) ? SS_DETECT : 0;
	364	events \|= (pcc_get(i,PCCR) & PCCR_PCEN) ? SS_READY : 0;
c9f50ddd	365	pr_debug("m32r_pcc: event 0x%02x\n", events);
1da177e4 LT	366
	367	if (events)
	368	pcmcia_parse_events(&socket[i].socket, events);
	369
	370	active \|= events;
	371	active = 0;
	372	}
	373	if (!active) break;
	374	}
	375	if (j == 20)
	376	printk(KERN_NOTICE "m32r-pcc: infinite loop in interrupt handler\n");
	377
c9f50ddd	378	pr_debug("m32r_pcc: interrupt done\n");
1da177e4 LT	379
	380	return IRQ_RETVAL(handled);
	381	} /* pcc_interrupt */
	382
	383	static void pcc_interrupt_wrapper(u_long data)
	384	{
9c8e7f5c	385	pcc_interrupt(0, NULL);
1da177e4 LT	386	init_timer(&poll_timer);
	387	poll_timer.expires = jiffies + poll_interval;
	388	add_timer(&poll_timer);
	389	}
	390
	391	/====================================================================/
	392
	393	static int _pcc_get_status(u_short sock, u_int *value)
	394	{
	395	u_int status;
	396
	397	status = pcc_get(sock,PCIRC);
	398	*value = ((status & PCIRC_CDIN1) && (status & PCIRC_CDIN2))
	399	? SS_DETECT : 0;
	400
	401	status = pcc_get(sock,PCCR);
	402
	403	#if 0
	404	*value \|= (status & PCCR_PCEN) ? SS_READY : 0;
	405	#else
	406	value \|= SS_READY; / XXX: always */
	407	#endif
	408
	409	status = pcc_get(sock,PCCSIGCR);
	410	*value \|= (status & PCCSIGCR_VEN) ? SS_POWERON : 0;
	411
c9f50ddd	412	pr_debug("m32r_pcc: GetStatus(%d) = %#4.4x\n", sock, *value);
1da177e4 LT	413	return 0;
	414	} /* _get_status */
	415
	416	/====================================================================/
	417
1da177e4 LT	418	static int _pcc_set_socket(u_short sock, socket_state_t *state)
	419	{
	420	u_long reg = 0;
	421
c9f50ddd	422	pr_debug("m32r_pcc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
1da177e4 LT	423	"io_irq %d, csc_mask %#2.2x)", sock, state->flags,
	424	state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
	425
	426	if (state->Vcc) {
	427	/*
	428	* 5V only
	429	*/
	430	if (state->Vcc == 50) {
	431	reg \|= PCCSIGCR_VEN;
	432	} else {
	433	return -EINVAL;
	434	}
	435	}
	436
	437	if (state->flags & SS_RESET) {
c9f50ddd	438	pr_debug("m32r_pcc: :RESET\n");
1da177e4 LT	439	reg \|= PCCSIGCR_CRST;
	440	}
	441	if (state->flags & SS_OUTPUT_ENA){
c9f50ddd	442	pr_debug("m32r_pcc: :OUTPUT_ENA\n");
1da177e4 LT	443	/* bit clear */
	444	} else {
	445	reg \|= PCCSIGCR_SEN;
	446	}
	447
	448	pcc_set(sock,PCCSIGCR,reg);
	449
1da177e4	450	if(state->flags & SS_IOCARD){
c9f50ddd	451	pr_debug("m32r_pcc: :IOCARD");
1da177e4 LT	452	}
1da177e4 LT	453	if (state->flags & SS_PWR_AUTO) {
c9f50ddd	454	pr_debug("m32r_pcc: :PWR_AUTO");
1da177e4 LT	455	}
1da177e4 LT	456	if (state->csc_mask & SS_DETECT)
c9f50ddd	457	pr_debug("m32r_pcc: :csc-SS_DETECT");
1da177e4 LT	458	if (state->flags & SS_IOCARD) {
1da177e4 LT	459	if (state->csc_mask & SS_STSCHG)
c9f50ddd	460	pr_debug("m32r_pcc: :STSCHG");
1da177e4 LT	461	} else {
1da177e4 LT	462	if (state->csc_mask & SS_BATDEAD)
c9f50ddd	463	pr_debug("m32r_pcc: :BATDEAD");
1da177e4	464	if (state->csc_mask & SS_BATWARN)
c9f50ddd	465	pr_debug("m32r_pcc: :BATWARN");
1da177e4	466	if (state->csc_mask & SS_READY)
c9f50ddd	467	pr_debug("m32r_pcc: :READY");
1da177e4	468	}
c9f50ddd	469	pr_debug("m32r_pcc: \n");
1da177e4 LT	470	return 0;
	471	} /* _set_socket */
	472
	473	/====================================================================/
	474
	475	static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
	476	{
	477	u_char map;
	478
c9f50ddd	479	pr_debug("m32r_pcc: SetIOMap(%d, %d, %#2.2x, %d ns, "
5f784336 WS	480	"%#llx-%#llx)\n", sock, io->map, io->flags,
	481	io->speed, (unsigned long long)io->start,
	482	(unsigned long long)io->stop);
1da177e4 LT	483	map = io->map;
	484
	485	return 0;
	486	} /* _set_io_map */
	487
	488	/====================================================================/
	489
	490	static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
	491	{
	492
	493	u_char map = mem->map;
	494	u_long mode;
	495	u_long addr;
	496	pcc_socket_t *t = &socket[sock];
	497	#ifdef CHAOS_PCC_DEBUG
	498	#if 0
	499	pcc_as_t last = t->current_space;
	500	#endif
	501	#endif
	502
c9f50ddd	503	pr_debug("m32r_pcc: SetMemMap(%d, %d, %#2.2x, %d ns, "
5f784336 WS	504	"%#llx, %#x)\n", sock, map, mem->flags,
	505	mem->speed, (unsigned long long)mem->static_start,
	506	mem->card_start);
1da177e4 LT	507
	508	/*
	509	* sanity check
	510	*/
	511	if ((map > MAX_WIN) \|\| (mem->card_start > 0x3ffffff)){
	512	return -EINVAL;
	513	}
	514
	515	/*
	516	* de-activate
	517	*/
	518	if ((mem->flags & MAP_ACTIVE) == 0) {
	519	t->current_space = as_none;
	520	return 0;
	521	}
	522
	523	/*
	524	* Disable first
	525	*/
	526	pcc_set(sock, PCCR, 0);
	527
	528	/*
	529	* Set mode
	530	*/
	531	if (mem->flags & MAP_ATTRIB) {
	532	mode = PCMOD_AS_ATTRIB \| PCMOD_CBSZ;
	533	t->current_space = as_attr;
	534	} else {
	535	mode = 0; /* common memory */
	536	t->current_space = as_comm;
	537	}
	538	pcc_set(sock, PCMOD, mode);
	539
	540	/*
	541	* Set address
	542	*/
	543	addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
	544	pcc_set(sock, PCADR, addr);
	545
	546	mem->static_start = addr + mem->card_start;
	547
	548	/*
	549	* Enable again
	550	*/
	551	pcc_set(sock, PCCR, 1);
	552
	553	#ifdef CHAOS_PCC_DEBUG
	554	#if 0
	555	if (last != as_attr) {
	556	#else
	557	if (1) {
	558	#endif
	559	dummy_readbuf = (u_char )(addr + KSEG1);
	560	}
	561	#endif
	562
	563	return 0;
	564
	565	} /* _set_mem_map */
	566
	567	#if 0 /* driver model ordering issue */
	568	/*======================================================================
	569
	570	Routines for accessing socket information and register dumps via
571	/proc/bus/pccard/...
572
573	======================================================================*/
574
575	static ssize_t show_info(struct class_device class_dev, char buf)
576	{
577	pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
578	socket.dev);
579
580	return sprintf(buf, "type: %s\nbase addr: 0x%08lx\n",
581	pcc[s->type].name, s->base);
582	}
583
584	static ssize_t show_exca(struct class_device class_dev, char buf)
585	{
586	/* FIXME */
587
588	return 0;
589	}
590
591	static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
592	static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
593	#endif
594
595	/====================================================================/
596
597	/* this is horribly ugly... proper locking needs to be done here at
598	* some time... */
599	#define LOCKED(x) do { \
600	int retval; \
601	unsigned long flags; \
602	spin_lock_irqsave(&pcc_lock, flags); \
603	retval = x; \
604	spin_unlock_irqrestore(&pcc_lock, flags); \
605	return retval; \
606	} while (0)
607
608
609	static int pcc_get_status(struct pcmcia_socket s, u_int value)
610	{
611	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
612
613	if (socket[sock].flags & IS_ALIVE) {
614	*value = 0;
615	return -EINVAL;
616	}
617	LOCKED(_pcc_get_status(sock, value));
618	}
619
1da177e4 LT	620	static int pcc_set_socket(struct pcmcia_socket s, socket_state_t state)
	621	{
	622	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
	623
	624	if (socket[sock].flags & IS_ALIVE)
	625	return -EINVAL;
	626
	627	LOCKED(_pcc_set_socket(sock, state));
	628	}
	629
	630	static int pcc_set_io_map(struct pcmcia_socket s, struct pccard_io_map io)
	631	{
	632	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
	633
	634	if (socket[sock].flags & IS_ALIVE)
	635	return -EINVAL;
	636	LOCKED(_pcc_set_io_map(sock, io));
	637	}
	638
	639	static int pcc_set_mem_map(struct pcmcia_socket s, struct pccard_mem_map mem)
	640	{
	641	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
	642
	643	if (socket[sock].flags & IS_ALIVE)
	644	return -EINVAL;
	645	LOCKED(_pcc_set_mem_map(sock, mem));
	646	}
	647
	648	static int pcc_init(struct pcmcia_socket *s)
	649	{
c9f50ddd	650	pr_debug("m32r_pcc: init call\n");
1da177e4 LT	651	return 0;
	652	}
	653
	654	static struct pccard_operations pcc_operations = {
	655	.init = pcc_init,
	656	.get_status = pcc_get_status,
1da177e4 LT	657	.set_socket = pcc_set_socket,
	658	.set_io_map = pcc_set_io_map,
	659	.set_mem_map = pcc_set_mem_map,
	660	};
	661
	662	/====================================================================/
	663
7a192ec3 ML	664	static struct platform_driver pcc_driver = {
	665	.driver = {
	666	.name = "pcc",
	667	.owner = THIS_MODULE,
	668	},
1da177e4 LT	669	};
	670
	671	static struct platform_device pcc_device = {
	672	.name = "pcc",
	673	.id = 0,
	674	};
	675
	676	/====================================================================/
	677
	678	static int __init init_m32r_pcc(void)
	679	{
	680	int i, ret;
	681
7a192ec3	682	ret = platform_driver_register(&pcc_driver);
1da177e4 LT	683	if (ret)
	684	return ret;
	685
	686	ret = platform_device_register(&pcc_device);
	687	if (ret){
7a192ec3	688	platform_driver_unregister(&pcc_driver);
1da177e4 LT	689	return ret;
	690	}
	691
	692	printk(KERN_INFO "m32r PCC probe:\n");
	693
	694	pcc_sockets = 0;
	695
	696	add_pcc_socket(M32R_PCC0_BASE, PCC0_IRQ, M32R_PCC0_MAPBASE, 0x1000);
	697
	698	#ifdef CONFIG_M32RPCC_SLOT2
	699	add_pcc_socket(M32R_PCC1_BASE, PCC1_IRQ, M32R_PCC1_MAPBASE, 0x2000);
	700	#endif
	701
	702	if (pcc_sockets == 0) {
	703	printk("socket is not found.\n");
	704	platform_device_unregister(&pcc_device);
7a192ec3	705	platform_driver_unregister(&pcc_driver);
1da177e4 LT	706	return -ENODEV;
	707	}
	708
	709	/* Set up interrupt handler(s) */
	710
	711	for (i = 0 ; i < pcc_sockets ; i++) {
ccbe48f7	712	socket[i].socket.dev.parent = &pcc_device.dev;
1da177e4 LT	713	socket[i].socket.ops = &pcc_operations;
	714	socket[i].socket.resource_ops = &pccard_static_ops;
	715	socket[i].socket.owner = THIS_MODULE;
	716	socket[i].number = i;
	717	ret = pcmcia_register_socket(&socket[i].socket);
	718	if (!ret)
	719	socket[i].flags \|= IS_REGISTERED;
	720
	721	#if 0 /* driver model ordering issue */
	722	class_device_create_file(&socket[i].socket.dev,
	723	&class_device_attr_info);
	724	class_device_create_file(&socket[i].socket.dev,
	725	&class_device_attr_exca);
	726	#endif
	727	}
	728
	729	/* Finally, schedule a polling interrupt */
	730	if (poll_interval != 0) {
	731	poll_timer.function = pcc_interrupt_wrapper;
	732	poll_timer.data = 0;
	733	init_timer(&poll_timer);
	734	poll_timer.expires = jiffies + poll_interval;
	735	add_timer(&poll_timer);
	736	}
	737
	738	return 0;
	739	} /* init_m32r_pcc */
	740
	741	static void __exit exit_m32r_pcc(void)
	742	{
	743	int i;
	744
	745	for (i = 0; i < pcc_sockets; i++)
	746	if (socket[i].flags & IS_REGISTERED)
	747	pcmcia_unregister_socket(&socket[i].socket);
	748
	749	platform_device_unregister(&pcc_device);
	750	if (poll_interval != 0)
	751	del_timer_sync(&poll_timer);
	752
7a192ec3	753	platform_driver_unregister(&pcc_driver);
1da177e4 LT	754	} /* exit_m32r_pcc */
	755
	756	module_init(init_m32r_pcc);
	757	module_exit(exit_m32r_pcc);
	758	MODULE_LICENSE("Dual MPL/GPL");
	759	/====================================================================/