[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / setup-res.c

/*
 *	drivers/pci/setup-res.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Resource sorting
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"


void pci_update_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus_region region;
	bool disable;
	u16 cmd;
	u32 new, check, mask;
	int reg;
	enum pci_bar_type type;
	struct resource *res = dev->resource + resno;

	/*
	 * Ignore resources for unimplemented BARs and unused resource slots
	 * for 64 bit BARs.
	 */
	if (!res->flags)
		return;

	/*
	 * Ignore non-moveable resources.  This might be legacy resources for
	 * which no functional BAR register exists or another important
	 * system resource we shouldn't move around.
	 */
	if (res->flags & IORESOURCE_PCI_FIXED)
		return;

	pcibios_resource_to_bus(dev, &region, res);

	new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
	if (res->flags & IORESOURCE_IO)
		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	else
		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;

	reg = pci_resource_bar(dev, resno, &type);
	if (!reg)
		return;
	if (type != pci_bar_unknown) {
		if (!(res->flags & IORESOURCE_ROM_ENABLE))
			return;
		new |= PCI_ROM_ADDRESS_ENABLE;
	}

	/*
	 * We can't update a 64-bit BAR atomically, so when possible,
	 * disable decoding so that a half-updated BAR won't conflict
	 * with another device.
	 */
	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	if (disable) {
		pci_read_config_word(dev, PCI_COMMAND, &cmd);
		pci_write_config_word(dev, PCI_COMMAND,
				      cmd & ~PCI_COMMAND_MEMORY);
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);

	if ((new ^ check) & mask) {
		dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
			resno, new, check);
	}

	if (res->flags & IORESOURCE_MEM_64) {
		new = region.start >> 16 >> 16;
		pci_write_config_dword(dev, reg + 4, new);
		pci_read_config_dword(dev, reg + 4, &check);
		if (check != new) {
			dev_err(&dev->dev, "BAR %d: error updating "
			       "(high %#08x != %#08x)\n", resno, new, check);
		}
	}

	if (disable)
		pci_write_config_word(dev, PCI_COMMAND, cmd);

	res->flags &= ~IORESOURCE_UNSET;
	dev_dbg(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
		resno, res, (unsigned long long)region.start,
		(unsigned long long)region.end);
}

int pci_claim_resource(struct pci_dev *dev, int resource)
{
	struct resource *res = &dev->resource[resource];
	struct resource *root, *conflict;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		dev_info(&dev->dev, "no compatible bridge window for %pR\n",
			 res);
		return -EINVAL;
	}

	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev,
			 "address space collision: %pR conflicts with %s %pR\n",
			 res, conflict->name, conflict);
		return -EBUSY;
	}

	return 0;
}
EXPORT_SYMBOL(pci_claim_resource);

void pci_disable_bridge_window(struct pci_dev *dev)
{
	dev_info(&dev->dev, "disabling bridge mem windows\n");

	/* MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);

	/* Prefetchable MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
}

/*
 * Generic function that returns a value indicating that the device's
 * original BIOS BAR address was not saved and so is not available for
 * reinstatement.
 *
 * Can be over-ridden by architecture specific code that implements
 * reinstatement functionality rather than leaving it disabled when
 * normal allocation attempts fail.
 */
resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
{
	return 0;
}

static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 
		int resno, resource_size_t size)
{
	struct resource *root, *conflict;
	resource_size_t fw_addr, start, end;
	int ret = 0;

	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
	if (!fw_addr)
		return 1;

	start = res->start;
	end = res->end;
	res->start = fw_addr;
	res->end = res->start + size - 1;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		if (res->flags & IORESOURCE_IO)
			root = &ioport_resource;
		else
			root = &iomem_resource;
	}

	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
		 resno, res);
	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev,
			 "BAR %d: %pR conflicts with %s %pR\n", resno,
			 res, conflict->name, conflict);
		res->start = start;
		res->end = end;
		ret = 1;
	}
	return ret;
}

static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
		int resno, resource_size_t size, resource_size_t align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t min;
	int ret;

	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;

	/* First, try exact prefetching match.. */
	ret = pci_bus_alloc_resource(bus, res, size, align, min,
				     IORESOURCE_PREFETCH,
				     pcibios_align_resource, dev);

	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
		/*
		 * That failed.
		 *
		 * But a prefetching area can handle a non-prefetching
		 * window (it will just not perform as well).
		 */
		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
					     pcibios_align_resource, dev);
	}
	return ret;
}

static int _pci_assign_resource(struct pci_dev *dev, int resno,
				resource_size_t size, resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	struct pci_bus *bus;
	int ret;
	char *type;

	bus = dev->bus;
	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
		if (!bus->parent || !bus->self->transparent)
			break;
		bus = bus->parent;
	}

	if (ret) {
		if (res->flags & IORESOURCE_MEM)
			if (res->flags & IORESOURCE_PREFETCH)
				type = "mem pref";
			else
				type = "mem";
		else if (res->flags & IORESOURCE_IO)
			type = "io";
		else
			type = "unknown";
		dev_info(&dev->dev,
			 "BAR %d: can't assign %s (size %#llx)\n",
			 resno, type, (unsigned long long) resource_size(res));
	}

	return ret;
}

int pci_assign_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t align, size;
	int ret;

	align = pci_resource_alignment(dev, res);
	if (!align) {
		dev_info(&dev->dev, "BAR %d: can't assign %pR "
			 "(bogus alignment)\n", resno, res);
		return -EINVAL;
	}

	size = resource_size(res);
	ret = _pci_assign_resource(dev, resno, size, align);

	/*
	 * If we failed to assign anything, let's try the address
	 * where firmware left it.  That at least has a chance of
	 * working, which is better than just leaving it disabled.
	 */
	if (ret < 0)
		ret = pci_revert_fw_address(res, dev, resno, size);

	if (!ret) {
		res->flags &= ~IORESOURCE_STARTALIGN;
		dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}
	return ret;
}

int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
			resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t new_size;
	int ret;

	if (!res->parent) {
		dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR "
			 "\n", resno, res);
		return -EINVAL;
	}

	/* already aligned with min_align */
	new_size = resource_size(res) + addsize;
	ret = _pci_assign_resource(dev, resno, new_size, min_align);
	if (!ret) {
		res->flags &= ~IORESOURCE_STARTALIGN;
		dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}
	return ret;
}

int pci_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int i;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!(mask & (1 << i)))
			continue;

		r = &dev->resource[i];

		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((i == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;

		if (!r->parent) {
			dev_err(&dev->dev, "device not available "
				"(can't reserve %pR)\n", r);
			return -EINVAL;
		}

		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	if (cmd != old_cmd) {
		dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
			 old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/setup-res.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling (david.rusling@reo.mts.dec.com)
	6	* David Mosberger (davidm@cs.arizona.edu)
	7	* David Miller (davem@redhat.com)
	8	*
	9	* Support routines for initializing a PCI subsystem.
	10	*/
	11
	12	/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
	13
	14	/*
	15	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	16	* Resource sorting
	17	*/
	18
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
363c75db	21	#include <linux/export.h>
1da177e4 LT	22	#include <linux/pci.h>
	23	#include <linux/errno.h>
	24	#include <linux/ioport.h>
	25	#include <linux/cache.h>
	26	#include <linux/slab.h>
	27	#include "pci.h"
	28
	29
14add80b	30	void pci_update_resource(struct pci_dev *dev, int resno)
1da177e4 LT	31	{
1da177e4 LT	32	struct pci_bus_region region;
9aac537e BH	33	bool disable;
9aac537e BH	34	u16 cmd;
1da177e4 LT	35	u32 new, check, mask;
1da177e4 LT	36	int reg;
613e7ed6	37	enum pci_bar_type type;
14add80b	38	struct resource *res = dev->resource + resno;
1da177e4	39
fb0f2b40 RB	40	/*
	41	* Ignore resources for unimplemented BARs and unused resource slots
	42	* for 64 bit BARs.
	43	*/
cf7bee5a IK	44	if (!res->flags)
	45	return;
	46
fb0f2b40 RB	47	/*
	48	* Ignore non-moveable resources. This might be legacy resources for
	49	* which no functional BAR register exists or another important
80ccba11	50	* system resource we shouldn't move around.
fb0f2b40 RB	51	*/
	52	if (res->flags & IORESOURCE_PCI_FIXED)
	53	return;
	54
1da177e4 LT	55	pcibios_resource_to_bus(dev, &region, res);
1da177e4 LT	56
1da177e4 LT	57	new = region.start \| (res->flags & PCI_REGION_FLAG_MASK);
	58	if (res->flags & IORESOURCE_IO)
	59	mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	60	else
	61	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
	62
613e7ed6 YZ	63	reg = pci_resource_bar(dev, resno, &type);
	64	if (!reg)
	65	return;
	66	if (type != pci_bar_unknown) {
755528c8 LT	67	if (!(res->flags & IORESOURCE_ROM_ENABLE))
	68	return;
	69	new \|= PCI_ROM_ADDRESS_ENABLE;
1da177e4 LT	70	}
1da177e4 LT	71
9aac537e BH	72	/*
	73	* We can't update a 64-bit BAR atomically, so when possible,
	74	* disable decoding so that a half-updated BAR won't conflict
	75	* with another device.
	76	*/
	77	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	78	if (disable) {
	79	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	80	pci_write_config_word(dev, PCI_COMMAND,
	81	cmd & ~PCI_COMMAND_MEMORY);
	82	}
	83
1da177e4 LT	84	pci_write_config_dword(dev, reg, new);
	85	pci_read_config_dword(dev, reg, &check);
	86
	87	if ((new ^ check) & mask) {
80ccba11 BH	88	dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
80ccba11 BH	89	resno, new, check);
1da177e4 LT	90	}
1da177e4 LT	91
28c6821a	92	if (res->flags & IORESOURCE_MEM_64) {
cf7bee5a	93	new = region.start >> 16 >> 16;
1da177e4 LT	94	pci_write_config_dword(dev, reg + 4, new);
	95	pci_read_config_dword(dev, reg + 4, &check);
	96	if (check != new) {
80ccba11 BH	97	dev_err(&dev->dev, "BAR %d: error updating "
80ccba11 BH	98	"(high %#08x != %#08x)\n", resno, new, check);
1da177e4 LT	99	}
1da177e4 LT	100	}
9aac537e BH	101
	102	if (disable)
	103	pci_write_config_word(dev, PCI_COMMAND, cmd);
	104
1da177e4	105	res->flags &= ~IORESOURCE_UNSET;
85b8582d VP	106	dev_dbg(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
	107	resno, res, (unsigned long long)region.start,
	108	(unsigned long long)region.end);
1da177e4 LT	109	}
1da177e4 LT	110
96bde06a	111	int pci_claim_resource(struct pci_dev *dev, int resource)
1da177e4 LT	112	{
1da177e4 LT	113	struct resource *res = &dev->resource[resource];
966f3a75	114	struct resource root, conflict;
1da177e4	115
cebd78a8	116	root = pci_find_parent_resource(dev, res);
865df576	117	if (!root) {
f6d440da BH	118	dev_info(&dev->dev, "no compatible bridge window for %pR\n",
f6d440da BH	119	res);
865df576	120	return -EINVAL;
1da177e4 LT	121	}
1da177e4 LT	122
966f3a75 BH	123	conflict = request_resource_conflict(root, res);
966f3a75 BH	124	if (conflict) {
f6d440da BH	125	dev_info(&dev->dev,
	126	"address space collision: %pR conflicts with %s %pR\n",
	127	res, conflict->name, conflict);
966f3a75 BH	128	return -EBUSY;
966f3a75 BH	129	}
865df576	130
966f3a75	131	return 0;
1da177e4	132	}
eaa959df	133	EXPORT_SYMBOL(pci_claim_resource);
1da177e4	134
32a9a682 YS	135	void pci_disable_bridge_window(struct pci_dev *dev)
32a9a682 YS	136	{
865df576	137	dev_info(&dev->dev, "disabling bridge mem windows\n");
32a9a682 YS	138
	139	/* MMIO Base/Limit */
	140	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
	141
	142	/* Prefetchable MMIO Base/Limit */
	143	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	144	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	145	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
	146	}
2bbc6942	147
6535943f MS	148	/*
	149	* Generic function that returns a value indicating that the device's
	150	* original BIOS BAR address was not saved and so is not available for
	151	* reinstatement.
	152	*
	153	* Can be over-ridden by architecture specific code that implements
	154	* reinstatement functionality rather than leaving it disabled when
	155	* normal allocation attempts fail.
	156	*/
	157	resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
	158	{
	159	return 0;
	160	}
	161
2bbc6942 RP	162	static int pci_revert_fw_address(struct resource res, struct pci_dev dev,
	163	int resno, resource_size_t size)
	164	{
	165	struct resource root, conflict;
6535943f	166	resource_size_t fw_addr, start, end;
2bbc6942	167	int ret = 0;
58c84eda	168
6535943f MS	169	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
	170	if (!fw_addr)
	171	return 1;
	172
2bbc6942 RP	173	start = res->start;
2bbc6942 RP	174	end = res->end;
6535943f	175	res->start = fw_addr;
2bbc6942	176	res->end = res->start + size - 1;
351fc6d1 MS	177
	178	root = pci_find_parent_resource(dev, res);
	179	if (!root) {
	180	if (res->flags & IORESOURCE_IO)
	181	root = &ioport_resource;
	182	else
	183	root = &iomem_resource;
	184	}
	185
2bbc6942 RP	186	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
	187	resno, res);
	188	conflict = request_resource_conflict(root, res);
	189	if (conflict) {
	190	dev_info(&dev->dev,
	191	"BAR %d: %pR conflicts with %s %pR\n", resno,
	192	res, conflict->name, conflict);
	193	res->start = start;
	194	res->end = end;
	195	ret = 1;
	196	}
	197	return ret;
	198	}
	199
fe6dacdb BH	200	static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
	201	int resno, resource_size_t size, resource_size_t align)
	202	{
	203	struct resource *res = dev->resource + resno;
	204	resource_size_t min;
	205	int ret;
	206
	207	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
	208
	209	/* First, try exact prefetching match.. */
	210	ret = pci_bus_alloc_resource(bus, res, size, align, min,
	211	IORESOURCE_PREFETCH,
	212	pcibios_align_resource, dev);
	213
	214	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
	215	/*
	216	* That failed.
	217	*
	218	* But a prefetching area can handle a non-prefetching
	219	* window (it will just not perform as well).
	220	*/
	221	ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
	222	pcibios_align_resource, dev);
	223	}
	224	return ret;
	225	}
	226
d6776e6d NR	227	static int _pci_assign_resource(struct pci_dev *dev, int resno,
d6776e6d NR	228	resource_size_t size, resource_size_t min_align)
2bbc6942 RP	229	{
	230	struct resource *res = dev->resource + resno;
	231	struct pci_bus *bus;
	232	int ret;
	233	char *type;
58c84eda	234
2bbc6942 RP	235	bus = dev->bus;
	236	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
	237	if (!bus->parent \|\| !bus->self->transparent)
	238	break;
	239	bus = bus->parent;
	240	}
	241
	242	if (ret) {
	243	if (res->flags & IORESOURCE_MEM)
	244	if (res->flags & IORESOURCE_PREFETCH)
	245	type = "mem pref";
	246	else
	247	type = "mem";
	248	else if (res->flags & IORESOURCE_IO)
	249	type = "io";
58c84eda	250	else
2bbc6942 RP	251	type = "unknown";
	252	dev_info(&dev->dev,
	253	"BAR %d: can't assign %s (size %#llx)\n",
	254	resno, type, (unsigned long long) resource_size(res));
58c84eda BH	255	}
58c84eda BH	256
2bbc6942 RP	257	return ret;
	258	}
	259
d09ee968 YL	260	int pci_assign_resource(struct pci_dev *dev, int resno)
	261	{
	262	struct resource *res = dev->resource + resno;
2bbc6942	263	resource_size_t align, size;
d09ee968 YL	264	int ret;
d09ee968 YL	265
6faf17f6	266	align = pci_resource_alignment(dev, res);
d09ee968	267	if (!align) {
865df576	268	dev_info(&dev->dev, "BAR %d: can't assign %pR "
a369c791	269	"(bogus alignment)\n", resno, res);
d09ee968 YL	270	return -EINVAL;
	271	}
	272
2bbc6942 RP	273	size = resource_size(res);
2bbc6942 RP	274	ret = _pci_assign_resource(dev, resno, size, align);
d09ee968	275
2bbc6942 RP	276	/*
	277	* If we failed to assign anything, let's try the address
	278	* where firmware left it. That at least has a chance of
	279	* working, which is better than just leaving it disabled.
	280	*/
6535943f	281	if (ret < 0)
2bbc6942	282	ret = pci_revert_fw_address(res, dev, resno, size);
d09ee968	283
2bbc6942 RP	284	if (!ret) {
	285	res->flags &= ~IORESOURCE_STARTALIGN;
	286	dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
	287	if (resno < PCI_BRIDGE_RESOURCES)
	288	pci_update_resource(dev, resno);
	289	}
d09ee968 YL	290	return ret;
	291	}
	292
fe6dacdb BH	293	int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
	294	resource_size_t min_align)
	295	{
	296	struct resource *res = dev->resource + resno;
	297	resource_size_t new_size;
	298	int ret;
	299
	300	if (!res->parent) {
	301	dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR "
	302	"\n", resno, res);
	303	return -EINVAL;
	304	}
	305
	306	/* already aligned with min_align */
	307	new_size = resource_size(res) + addsize;
	308	ret = _pci_assign_resource(dev, resno, new_size, min_align);
	309	if (!ret) {
	310	res->flags &= ~IORESOURCE_STARTALIGN;
	311	dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
	312	if (resno < PCI_BRIDGE_RESOURCES)
	313	pci_update_resource(dev, resno);
	314	}
	315	return ret;
	316	}
	317
842de40d BH	318	int pci_enable_resources(struct pci_dev *dev, int mask)
	319	{
	320	u16 cmd, old_cmd;
	321	int i;
	322	struct resource *r;
	323
	324	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	325	old_cmd = cmd;
	326
	327	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	328	if (!(mask & (1 << i)))
	329	continue;
	330
	331	r = &dev->resource[i];
	332
	333	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	334	continue;
	335	if ((i == PCI_ROM_RESOURCE) &&
	336	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	337	continue;
	338
	339	if (!r->parent) {
865df576 BH	340	dev_err(&dev->dev, "device not available "
865df576 BH	341	"(can't reserve %pR)\n", r);
842de40d BH	342	return -EINVAL;
	343	}
	344
	345	if (r->flags & IORESOURCE_IO)
	346	cmd \|= PCI_COMMAND_IO;
	347	if (r->flags & IORESOURCE_MEM)
	348	cmd \|= PCI_COMMAND_MEMORY;
	349	}
	350
	351	if (cmd != old_cmd) {
	352	dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
	353	old_cmd, cmd);
	354	pci_write_config_word(dev, PCI_COMMAND, cmd);
	355	}
	356	return 0;
	357	}