[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / rom.c

/*
 * drivers/pci/rom.c
 *
 * (C) Copyright 2004 Jon Smirl <jonsmirl@yahoo.com>
 * (C) Copyright 2004 Silicon Graphics, Inc. Jesse Barnes <jbarnes@sgi.com>
 *
 * PCI ROM access routines
 */
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/slab.h>

#include "pci.h"

/**
 * pci_enable_rom - enable ROM decoding for a PCI device
 * @pdev: PCI device to enable
 *
 * Enable ROM decoding on @dev.  This involves simply turning on the last
 * bit of the PCI ROM BAR.  Note that some cards may share address decoders
 * between the ROM and other resources, so enabling it may disable access
 * to MMIO registers or other card memory.
 */
int pci_enable_rom(struct pci_dev *pdev)
{
	struct resource *res = pdev->resource + PCI_ROM_RESOURCE;
	struct pci_bus_region region;
	u32 rom_addr;

	if (!res->flags)
		return -1;

	pcibios_resource_to_bus(pdev, &region, res);
	pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
	rom_addr &= ~PCI_ROM_ADDRESS_MASK;
	rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE;
	pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
	return 0;
}

/**
 * pci_disable_rom - disable ROM decoding for a PCI device
 * @pdev: PCI device to disable
 *
 * Disable ROM decoding on a PCI device by turning off the last bit in the
 * ROM BAR.
 */
void pci_disable_rom(struct pci_dev *pdev)
{
	u32 rom_addr;
	pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
	rom_addr &= ~PCI_ROM_ADDRESS_ENABLE;
	pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
}

/**
 * pci_get_rom_size - obtain the actual size of the ROM image
 * @pdev: target PCI device
 * @rom: kernel virtual pointer to image of ROM
 * @size: size of PCI window
 *  return: size of actual ROM image
 *
 * Determine the actual length of the ROM image.
 * The PCI window size could be much larger than the
 * actual image size.
 */
size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)
{
	void __iomem *image;
	int last_image;
	unsigned length;

	image = rom;
	do {
		void __iomem *pds;
		/* Standard PCI ROMs start out with these bytes 55 AA */
		if (readb(image) != 0x55) {
			dev_err(&pdev->dev, "Invalid ROM contents\n");
			break;
		}
		if (readb(image + 1) != 0xAA)
			break;
		/* get the PCI data structure and check its signature */
		pds = image + readw(image + 24);
		if (readb(pds) != 'P')
			break;
		if (readb(pds + 1) != 'C')
			break;
		if (readb(pds + 2) != 'I')
			break;
		if (readb(pds + 3) != 'R')
			break;
		last_image = readb(pds + 21) & 0x80;
		length = readw(pds + 16);
		image += length * 512;
	} while (length && !last_image);

	/* never return a size larger than the PCI resource window */
	/* there are known ROMs that get the size wrong */
	return min((size_t)(image - rom), size);
}

/**
 * pci_map_rom - map a PCI ROM to kernel space
 * @pdev: pointer to pci device struct
 * @size: pointer to receive size of pci window over ROM
 *
 * Return: kernel virtual pointer to image of ROM
 *
 * Map a PCI ROM into kernel space. If ROM is boot video ROM,
 * the shadow BIOS copy will be returned instead of the
 * actual ROM.
 */
void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
{
	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
	loff_t start;
	void __iomem *rom;

	/*
	 * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy
	 * memory map if the VGA enable bit of the Bridge Control register is
	 * set for embedded VGA.
	 */
	if (res->flags & IORESOURCE_ROM_SHADOW) {
		/* primary video rom always starts here */
		start = (loff_t)0xC0000;
		*size = 0x20000; /* cover C000:0 through E000:0 */
	} else {
		if (res->flags &
			(IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {
			*size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
			return (void __iomem *)(unsigned long)
				pci_resource_start(pdev, PCI_ROM_RESOURCE);
		} else {
			/* assign the ROM an address if it doesn't have one */
			if (res->parent == NULL &&
			    pci_assign_resource(pdev,PCI_ROM_RESOURCE))
				return NULL;
			start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
			*size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
			if (*size == 0)
				return NULL;

			/* Enable ROM space decodes */
			if (pci_enable_rom(pdev))
				return NULL;
		}
	}

	rom = ioremap(start, *size);
	if (!rom) {
		/* restore enable if ioremap fails */
		if (!(res->flags & (IORESOURCE_ROM_ENABLE |
				    IORESOURCE_ROM_SHADOW |
				    IORESOURCE_ROM_COPY)))
			pci_disable_rom(pdev);
		return NULL;
	}

	/*
	 * Try to find the true size of the ROM since sometimes the PCI window
	 * size is much larger than the actual size of the ROM.
	 * True size is important if the ROM is going to be copied.
	 */
	*size = pci_get_rom_size(pdev, rom, *size);
	return rom;
}

/**
 * pci_unmap_rom - unmap the ROM from kernel space
 * @pdev: pointer to pci device struct
 * @rom: virtual address of the previous mapping
 *
 * Remove a mapping of a previously mapped ROM
 */
void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
{
	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];

	if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY))
		return;

	iounmap(rom);

	/* Disable again before continuing, leave enabled if pci=rom */
	if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW)))
		pci_disable_rom(pdev);
}

/**
 * pci_cleanup_rom - free the ROM copy created by pci_map_rom_copy
 * @pdev: pointer to pci device struct
 *
 * Free the copied ROM if we allocated one.
 */
void pci_cleanup_rom(struct pci_dev *pdev)
{
	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
	if (res->flags & IORESOURCE_ROM_COPY) {
		kfree((void*)(unsigned long)res->start);
		res->flags &= ~IORESOURCE_ROM_COPY;
		res->start = 0;
		res->end = 0;
	}
}

/**
 * pci_platform_rom - provides a pointer to any ROM image provided by the
 * platform
 * @pdev: pointer to pci device struct
 * @size: pointer to receive size of pci window over ROM
 */
void __iomem *pci_platform_rom(struct pci_dev *pdev, size_t *size)
{
	if (pdev->rom && pdev->romlen) {
		*size = pdev->romlen;
		return phys_to_virt((phys_addr_t)pdev->rom);
	}

	return NULL;
}

EXPORT_SYMBOL(pci_map_rom);
EXPORT_SYMBOL(pci_unmap_rom);
EXPORT_SYMBOL_GPL(pci_enable_rom);
EXPORT_SYMBOL_GPL(pci_disable_rom);
EXPORT_SYMBOL(pci_platform_rom);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/rom.c
	3	*
	4	* (C) Copyright 2004 Jon Smirl <jonsmirl@yahoo.com>
	5	* (C) Copyright 2004 Silicon Graphics, Inc. Jesse Barnes <jbarnes@sgi.com>
	6	*
	7	* PCI ROM access routines
	8	*/
1da177e4	9	#include <linux/kernel.h>
363c75db	10	#include <linux/export.h>
1da177e4	11	#include <linux/pci.h>
4e57b681	12	#include <linux/slab.h>
1da177e4 LT	13
	14	#include "pci.h"
	15
	16	/**
	17	* pci_enable_rom - enable ROM decoding for a PCI device
67be2dd1	18	* @pdev: PCI device to enable
1da177e4 LT	19	*
	20	* Enable ROM decoding on @dev. This involves simply turning on the last
	21	* bit of the PCI ROM BAR. Note that some cards may share address decoders
	22	* between the ROM and other resources, so enabling it may disable access
	23	* to MMIO registers or other card memory.
	24	*/
e416de5e	25	int pci_enable_rom(struct pci_dev *pdev)
1da177e4	26	{
8085ce08 BH	27	struct resource *res = pdev->resource + PCI_ROM_RESOURCE;
8085ce08 BH	28	struct pci_bus_region region;
1da177e4 LT	29	u32 rom_addr;
1da177e4 LT	30
8085ce08 BH	31	if (!res->flags)
	32	return -1;
	33
	34	pcibios_resource_to_bus(pdev, &region, res);
1da177e4	35	pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
8085ce08 BH	36	rom_addr &= ~PCI_ROM_ADDRESS_MASK;
8085ce08 BH	37	rom_addr \|= region.start \| PCI_ROM_ADDRESS_ENABLE;
1da177e4	38	pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
8085ce08	39	return 0;
1da177e4 LT	40	}
	41
	42	/**
	43	* pci_disable_rom - disable ROM decoding for a PCI device
67be2dd1	44	* @pdev: PCI device to disable
1da177e4 LT	45	*
	46	* Disable ROM decoding on a PCI device by turning off the last bit in the
	47	* ROM BAR.
	48	*/
e416de5e	49	void pci_disable_rom(struct pci_dev *pdev)
1da177e4 LT	50	{
	51	u32 rom_addr;
	52	pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
	53	rom_addr &= ~PCI_ROM_ADDRESS_ENABLE;
	54	pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
	55	}
	56
d7ad2254 JK	57	/**
d7ad2254 JK	58	* pci_get_rom_size - obtain the actual size of the ROM image
4cc59c72	59	* @pdev: target PCI device
d7ad2254 JK	60	* @rom: kernel virtual pointer to image of ROM
	61	* @size: size of PCI window
	62	* return: size of actual ROM image
	63	*
	64	* Determine the actual length of the ROM image.
	65	* The PCI window size could be much larger than the
	66	* actual image size.
	67	*/
97c44836	68	size_t pci_get_rom_size(struct pci_dev pdev, void __iomem rom, size_t size)
d7ad2254 JK	69	{
	70	void __iomem *image;
	71	int last_image;
c1b940de	72	unsigned length;
d7ad2254 JK	73
	74	image = rom;
	75	do {
	76	void __iomem *pds;
	77	/* Standard PCI ROMs start out with these bytes 55 AA */
97c44836 TN	78	if (readb(image) != 0x55) {
97c44836 TN	79	dev_err(&pdev->dev, "Invalid ROM contents\n");
d7ad2254	80	break;
97c44836	81	}
d7ad2254 JK	82	if (readb(image + 1) != 0xAA)
	83	break;
	84	/* get the PCI data structure and check its signature */
	85	pds = image + readw(image + 24);
	86	if (readb(pds) != 'P')
	87	break;
	88	if (readb(pds + 1) != 'C')
	89	break;
	90	if (readb(pds + 2) != 'I')
	91	break;
	92	if (readb(pds + 3) != 'R')
	93	break;
	94	last_image = readb(pds + 21) & 0x80;
c1b940de MD	95	length = readw(pds + 16);
	96	image += length * 512;
	97	} while (length && !last_image);
d7ad2254 JK	98
	99	/* never return a size larger than the PCI resource window */
	100	/* there are known ROMs that get the size wrong */
	101	return min((size_t)(image - rom), size);
	102	}
	103
1da177e4 LT	104	/**
1da177e4 LT	105	* pci_map_rom - map a PCI ROM to kernel space
67be2dd1	106	* @pdev: pointer to pci device struct
1da177e4	107	* @size: pointer to receive size of pci window over ROM
f5dafca5 RD	108	*
f5dafca5 RD	109	* Return: kernel virtual pointer to image of ROM
1da177e4 LT	110	*
	111	* Map a PCI ROM into kernel space. If ROM is boot video ROM,
	112	* the shadow BIOS copy will be returned instead of the
	113	* actual ROM.
	114	*/
	115	void __iomem pci_map_rom(struct pci_dev pdev, size_t *size)
	116	{
	117	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
fffe01f7	118	loff_t start;
1da177e4	119	void __iomem *rom;
1da177e4	120
b5e4efe7	121	/*
6b5c76b8 EO	122	* IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy
	123	* memory map if the VGA enable bit of the Bridge Control register is
	124	* set for embedded VGA.
b5e4efe7	125	*/
547b5246	126	if (res->flags & IORESOURCE_ROM_SHADOW) {
1da177e4 LT	127	/* primary video rom always starts here */
	128	start = (loff_t)0xC0000;
	129	size = 0x20000; / cover C000:0 through E000:0 */
	130	} else {
a2302c68 JK	131	if (res->flags &
a2302c68 JK	132	(IORESOURCE_ROM_COPY \| IORESOURCE_ROM_BIOS_COPY)) {
1da177e4	133	*size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
e31dd6e4 GKH	134	return (void __iomem *)(unsigned long)
e31dd6e4 GKH	135	pci_resource_start(pdev, PCI_ROM_RESOURCE);
1da177e4	136	} else {
fffe01f7 MG	137	/* assign the ROM an address if it doesn't have one */
	138	if (res->parent == NULL &&
	139	pci_assign_resource(pdev,PCI_ROM_RESOURCE))
	140	return NULL;
	141	start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
	142	*size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
	143	if (*size == 0)
	144	return NULL;
1da177e4	145
fffe01f7 MG	146	/* Enable ROM space decodes */
	147	if (pci_enable_rom(pdev))
	148	return NULL;
	149	}
547b5246 MG	150	}
547b5246 MG	151
1da177e4 LT	152	rom = ioremap(start, *size);
	153	if (!rom) {
	154	/* restore enable if ioremap fails */
	155	if (!(res->flags & (IORESOURCE_ROM_ENABLE \|
	156	IORESOURCE_ROM_SHADOW \|
	157	IORESOURCE_ROM_COPY)))
	158	pci_disable_rom(pdev);
	159	return NULL;
	160	}
	161
	162	/*
	163	* Try to find the true size of the ROM since sometimes the PCI window
	164	* size is much larger than the actual size of the ROM.
	165	* True size is important if the ROM is going to be copied.
	166	*/
97c44836	167	size = pci_get_rom_size(pdev, rom, size);
1da177e4 LT	168	return rom;
	169	}
	170
1da177e4 LT	171	/**
1da177e4 LT	172	* pci_unmap_rom - unmap the ROM from kernel space
67be2dd1	173	* @pdev: pointer to pci device struct
1da177e4 LT	174	* @rom: virtual address of the previous mapping
	175	*
	176	* Remove a mapping of a previously mapped ROM
	177	*/
	178	void pci_unmap_rom(struct pci_dev pdev, void __iomem rom)
	179	{
	180	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
	181
a2302c68	182	if (res->flags & (IORESOURCE_ROM_COPY \| IORESOURCE_ROM_BIOS_COPY))
1da177e4 LT	183	return;
1da177e4 LT	184
fffe01f7	185	iounmap(rom);
1da177e4 LT	186
	187	/* Disable again before continuing, leave enabled if pci=rom */
	188	if (!(res->flags & (IORESOURCE_ROM_ENABLE \| IORESOURCE_ROM_SHADOW)))
	189	pci_disable_rom(pdev);
	190	}
	191
1da177e4	192	/**
0643245f	193	* pci_cleanup_rom - free the ROM copy created by pci_map_rom_copy
67be2dd1	194	* @pdev: pointer to pci device struct
1da177e4 LT	195	*
	196	* Free the copied ROM if we allocated one.
	197	*/
	198	void pci_cleanup_rom(struct pci_dev *pdev)
	199	{
	200	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
	201	if (res->flags & IORESOURCE_ROM_COPY) {
e31dd6e4	202	kfree((void*)(unsigned long)res->start);
1da177e4 LT	203	res->flags &= ~IORESOURCE_ROM_COPY;
	204	res->start = 0;
	205	res->end = 0;
	206	}
	207	}
	208
fffe01f7 MG	209	/**
	210	* pci_platform_rom - provides a pointer to any ROM image provided by the
	211	* platform
	212	* @pdev: pointer to pci device struct
	213	* @size: pointer to receive size of pci window over ROM
	214	*/
	215	void __iomem pci_platform_rom(struct pci_dev pdev, size_t *size)
	216	{
	217	if (pdev->rom && pdev->romlen) {
	218	*size = pdev->romlen;
	219	return phys_to_virt((phys_addr_t)pdev->rom);
	220	}
	221
	222	return NULL;
	223	}
	224
1da177e4	225	EXPORT_SYMBOL(pci_map_rom);
1da177e4	226	EXPORT_SYMBOL(pci_unmap_rom);
e416de5e AC	227	EXPORT_SYMBOL_GPL(pci_enable_rom);
e416de5e AC	228	EXPORT_SYMBOL_GPL(pci_disable_rom);
fffe01f7	229	EXPORT_SYMBOL(pci_platform_rom);