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PCI: Add new ID for Intel GPU "spurious interrupt" quirk
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
363c75db 20#include <linux/export.h>
1da177e4
LT		 21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/delay.h>
25be5e6c 24#include <linux/acpi.h>
9f23ed3b 25#include <linux/kallsyms.h>
75e07fc3 26#include <linux/dmi.h>
649426ef 27#include <linux/pci-aspm.h>
32a9a682 28#include <linux/ioport.h>
3209874a
AV		 29#include <linux/sched.h>
30#include <linux/ktime.h>
93177a74 31#include <asm/dma.h> /* isa_dma_bridge_buggy */
bc56b9e0 32#include "pci.h"
1da177e4 33
253d2e54
JP		 34/*
35 * Decoding should be disabled for a PCI device during BAR sizing to avoid
36 * conflict. But doing so may cause problems on host bridge and perhaps other
37 * key system devices. For devices that need to have mmio decoding always-on,
38 * we need to set the dev->mmio_always_on bit.
39 */
15856ad5 40static void quirk_mmio_always_on(struct pci_dev *dev)
253d2e54 41{
52d21b5e 42 dev->mmio_always_on = 1;
253d2e54 43}
52d21b5e
YL		 44DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
45 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
253d2e54 46
bd8481e1
DT		 47/* The Mellanox Tavor device gives false positive parity errors
48 * Mark this device with a broken_parity_status, to allow
49 * PCI scanning code to "skip" this now blacklisted device.
50 */
15856ad5 51static void quirk_mellanox_tavor(struct pci_dev *dev)
bd8481e1
DT		 52{
53 dev->broken_parity_status = 1; /* This device gives false positives */
54}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
56DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
57
1da177e4
LT		 58/* Deal with broken BIOS'es that neglect to enable passive release,
59 which can cause problems in combination with the 82441FX/PPro MTRRs */
1597cacb 60static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 61{
62 struct pci_dev *d = NULL;
63 unsigned char dlc;
64
65 /* We have to make sure a particular bit is set in the PIIX3
66 ISA bridge, so we have to go out and find it. */
67 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
68 pci_read_config_byte(d, 0x82, &dlc);
69 if (!(dlc & 1<<1)) {
999da9fd 70 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
1da177e4
LT		 71 dlc |= 1<<1;
72 pci_write_config_byte(d, 0x82, dlc);
73 }
74 }
75}
652c538e
AM		 76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
77DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
1da177e4
LT		 78
79/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
80 but VIA don't answer queries. If you happen to have good contacts at VIA
81 ask them for me please -- Alan
82
83 This appears to be BIOS not version dependent. So presumably there is a
84 chipset level fix */
1da177e4 85
15856ad5 86static void quirk_isa_dma_hangs(struct pci_dev *dev)
1da177e4
LT		 87{
88 if (!isa_dma_bridge_buggy) {
89 isa_dma_bridge_buggy=1;
f0fda801 90 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
1da177e4
LT		 91 }
92}
93 /*
94 * Its not totally clear which chipsets are the problematic ones
95 * We know 82C586 and 82C596 variants are affected.
96 */
652c538e
AM		 97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
103DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
1da177e4 104
4731fdcf
LB		 105/*
106 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
107 * for some HT machines to use C4 w/o hanging.
108 */
15856ad5 109static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
4731fdcf
LB		 110{
111 u32 pmbase;
112 u16 pm1a;
113
114 pci_read_config_dword(dev, 0x40, &pmbase);
115 pmbase = pmbase & 0xff80;
116 pm1a = inw(pmbase);
117
118 if (pm1a & 0x10) {
119 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
120 outw(0x10, pmbase);
121 }
122}
123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
124
1da177e4
LT		 125/*
126 * Chipsets where PCI->PCI transfers vanish or hang
127 */
15856ad5 128static void quirk_nopcipci(struct pci_dev *dev)
1da177e4
LT		 129{
130 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
f0fda801 131 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
1da177e4
LT		 132 pci_pci_problems |= PCIPCI_FAIL;
133 }
134}
652c538e
AM		 135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
236561e5 137
15856ad5 138static void quirk_nopciamd(struct pci_dev *dev)
236561e5
AC		 139{
140 u8 rev;
141 pci_read_config_byte(dev, 0x08, &rev);
142 if (rev == 0x13) {
143 /* Erratum 24 */
f0fda801 144 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
236561e5
AC		 145 pci_pci_problems |= PCIAGP_FAIL;
146 }
147}
652c538e 148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
1da177e4
LT		 149
150/*
151 * Triton requires workarounds to be used by the drivers
152 */
15856ad5 153static void quirk_triton(struct pci_dev *dev)
1da177e4
LT		 154{
155 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
f0fda801 156 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 157 pci_pci_problems |= PCIPCI_TRITON;
158 }
159}
652c538e
AM		 160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
1da177e4
LT		 164
165/*
166 * VIA Apollo KT133 needs PCI latency patch
167 * Made according to a windows driver based patch by George E. Breese
168 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
631dd1a8 169 * and http://www.georgebreese.com/net/software/#PCI
1da177e4
LT		 170 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
171 * the info on which Mr Breese based his work.
172 *
173 * Updated based on further information from the site and also on
174 * information provided by VIA
175 */
1597cacb 176static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 177{
178 struct pci_dev *p;
1da177e4
LT		 179 u8 busarb;
180 /* Ok we have a potential problem chipset here. Now see if we have
181 a buggy southbridge */
182
183 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
184 if (p!=NULL) {
1da177e4
LT		 185 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
186 /* Check for buggy part revisions */
2b1afa87 187 if (p->revision < 0x40 || p->revision > 0x42)
1da177e4
LT		 188 goto exit;
189 } else {
190 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
191 if (p==NULL) /* No problem parts */
192 goto exit;
1da177e4 193 /* Check for buggy part revisions */
2b1afa87 194 if (p->revision < 0x10 || p->revision > 0x12)
1da177e4
LT		 195 goto exit;
196 }
197
198 /*
199 * Ok we have the problem. Now set the PCI master grant to
200 * occur every master grant. The apparent bug is that under high
201 * PCI load (quite common in Linux of course) you can get data
202 * loss when the CPU is held off the bus for 3 bus master requests
203 * This happens to include the IDE controllers....
204 *
205 * VIA only apply this fix when an SB Live! is present but under
25985edc 206 * both Linux and Windows this isn't enough, and we have seen
1da177e4
LT		 207 * corruption without SB Live! but with things like 3 UDMA IDE
208 * controllers. So we ignore that bit of the VIA recommendation..
209 */
210
211 pci_read_config_byte(dev, 0x76, &busarb);
212 /* Set bit 4 and bi 5 of byte 76 to 0x01
213 "Master priority rotation on every PCI master grant */
214 busarb &= ~(1<<5);
215 busarb |= (1<<4);
216 pci_write_config_byte(dev, 0x76, busarb);
f0fda801 217 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
1da177e4
LT		 218exit:
219 pci_dev_put(p);
220}
652c538e
AM		 221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1597cacb 224/* Must restore this on a resume from RAM */
652c538e
AM		 225DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
226DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
227DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1da177e4
LT		 228
229/*
230 * VIA Apollo VP3 needs ETBF on BT848/878
231 */
15856ad5 232static void quirk_viaetbf(struct pci_dev *dev)
1da177e4
LT		 233{
234 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
f0fda801 235 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 236 pci_pci_problems |= PCIPCI_VIAETBF;
237 }
238}
652c538e 239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
1da177e4 240
15856ad5 241static void quirk_vsfx(struct pci_dev *dev)
1da177e4
LT		 242{
243 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
f0fda801 244 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 245 pci_pci_problems |= PCIPCI_VSFX;
246 }
247}
652c538e 248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
1da177e4
LT		 249
250/*
251 * Ali Magik requires workarounds to be used by the drivers
252 * that DMA to AGP space. Latency must be set to 0xA and triton
253 * workaround applied too
254 * [Info kindly provided by ALi]
255 */
15856ad5 256static void quirk_alimagik(struct pci_dev *dev)
1da177e4
LT		 257{
258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
f0fda801 259 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 260 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
261 }
262}
652c538e
AM		 263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
1da177e4
LT		 265
266/*
267 * Natoma has some interesting boundary conditions with Zoran stuff
268 * at least
269 */
15856ad5 270static void quirk_natoma(struct pci_dev *dev)
1da177e4
LT		 271{
272 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
f0fda801 273 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 274 pci_pci_problems |= PCIPCI_NATOMA;
275 }
276}
652c538e
AM		 277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
1da177e4
LT		 283
284/*
285 * This chip can cause PCI parity errors if config register 0xA0 is read
286 * while DMAs are occurring.
287 */
15856ad5 288static void quirk_citrine(struct pci_dev *dev)
1da177e4
LT		 289{
290 dev->cfg_size = 0xA0;
291}
652c538e 292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
1da177e4
LT		 293
294/*
295 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
296 * If it's needed, re-allocate the region.
297 */
15856ad5 298static void quirk_s3_64M(struct pci_dev *dev)
1da177e4
LT		 299{
300 struct resource *r = &dev->resource[0];
301
302 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
303 r->start = 0;
304 r->end = 0x3ffffff;
305 }
306}
652c538e
AM		 307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
1da177e4 309
73d2eaac
AS		 310/*
311 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
312 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
313 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
314 * (which conflicts w/ BAR1's memory range).
315 */
15856ad5 316static void quirk_cs5536_vsa(struct pci_dev *dev)
73d2eaac
AS		 317{
318 if (pci_resource_len(dev, 0) != 8) {
319 struct resource *res = &dev->resource[0];
320 res->end = res->start + 8 - 1;
321 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
322 "(incorrect header); workaround applied.\n");
323 }
324}
325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
326
65195c76
YL		 327static void quirk_io_region(struct pci_dev *dev, int port,
328 unsigned size, int nr, const char *name)
329{
330 u16 region;
331 struct pci_bus_region bus_region;
332 struct resource *res = dev->resource + nr;
333
334 pci_read_config_word(dev, port, &region);
335 region &= ~(size - 1);
336
337 if (!region)
338 return;
339
340 res->name = pci_name(dev);
341 res->flags = IORESOURCE_IO;
342
343 /* Convert from PCI bus to resource space */
344 bus_region.start = region;
345 bus_region.end = region + size - 1;
346 pcibios_bus_to_resource(dev, res, &bus_region);
347
348 if (!pci_claim_resource(dev, nr))
349 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
350}
1da177e4
LT		 351
352/*
353 * ATI Northbridge setups MCE the processor if you even
354 * read somewhere between 0x3b0->0x3bb or read 0x3d3
355 */
15856ad5 356static void quirk_ati_exploding_mce(struct pci_dev *dev)
1da177e4 357{
f0fda801 358 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
1da177e4
LT		 359 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
360 request_region(0x3b0, 0x0C, "RadeonIGP");
361 request_region(0x3d3, 0x01, "RadeonIGP");
362}
652c538e 363DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
1da177e4
LT		 364
365/*
366 * Let's make the southbridge information explicit instead
367 * of having to worry about people probing the ACPI areas,
368 * for example.. (Yes, it happens, and if you read the wrong
369 * ACPI register it will put the machine to sleep with no
370 * way of waking it up again. Bummer).
371 *
372 * ALI M7101: Two IO regions pointed to by words at
373 * 0xE0 (64 bytes of ACPI registers)
374 * 0xE2 (32 bytes of SMB registers)
375 */
15856ad5 376static void quirk_ali7101_acpi(struct pci_dev *dev)
1da177e4 377{
65195c76
YL		 378 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
379 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4 380}
652c538e 381DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
1da177e4 382
6693e74a
LT		 383static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
384{
385 u32 devres;
386 u32 mask, size, base;
387
388 pci_read_config_dword(dev, port, &devres);
389 if ((devres & enable) != enable)
390 return;
391 mask = (devres >> 16) & 15;
392 base = devres & 0xffff;
393 size = 16;
394 for (;;) {
395 unsigned bit = size >> 1;
396 if ((bit & mask) == bit)
397 break;
398 size = bit;
399 }
400 /*
401 * For now we only print it out. Eventually we'll want to
402 * reserve it (at least if it's in the 0x1000+ range), but
403 * let's get enough confirmation reports first.
404 */
405 base &= -size;
f0fda801 406 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 407}
408
409static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
410{
411 u32 devres;
412 u32 mask, size, base;
413
414 pci_read_config_dword(dev, port, &devres);
415 if ((devres & enable) != enable)
416 return;
417 base = devres & 0xffff0000;
418 mask = (devres & 0x3f) << 16;
419 size = 128 << 16;
420 for (;;) {
421 unsigned bit = size >> 1;
422 if ((bit & mask) == bit)
423 break;
424 size = bit;
425 }
426 /*
427 * For now we only print it out. Eventually we'll want to
428 * reserve it, but let's get enough confirmation reports first.
429 */
430 base &= -size;
f0fda801 431 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 432}
433
1da177e4
LT		 434/*
435 * PIIX4 ACPI: Two IO regions pointed to by longwords at
436 * 0x40 (64 bytes of ACPI registers)
08db2a70 437 * 0x90 (16 bytes of SMB registers)
6693e74a 438 * and a few strange programmable PIIX4 device resources.
1da177e4 439 */
15856ad5 440static void quirk_piix4_acpi(struct pci_dev *dev)
1da177e4 441{
65195c76 442 u32 res_a;
1da177e4 443
65195c76
YL		 444 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
445 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 446
447 /* Device resource A has enables for some of the other ones */
448 pci_read_config_dword(dev, 0x5c, &res_a);
449
450 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
451 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
452
453 /* Device resource D is just bitfields for static resources */
454
455 /* Device 12 enabled? */
456 if (res_a & (1 << 29)) {
457 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
458 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
459 }
460 /* Device 13 enabled? */
461 if (res_a & (1 << 30)) {
462 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
463 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
464 }
465 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
466 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4 467}
652c538e
AM		 468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
1da177e4 470
cdb97558
JS		 471#define ICH_PMBASE 0x40
472#define ICH_ACPI_CNTL 0x44
473#define ICH4_ACPI_EN 0x10
474#define ICH6_ACPI_EN 0x80
475#define ICH4_GPIOBASE 0x58
476#define ICH4_GPIO_CNTL 0x5c
477#define ICH4_GPIO_EN 0x10
478#define ICH6_GPIOBASE 0x48
479#define ICH6_GPIO_CNTL 0x4c
480#define ICH6_GPIO_EN 0x10
481
1da177e4
LT		 482/*
483 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
484 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
485 * 0x58 (64 bytes of GPIO I/O space)
486 */
15856ad5 487static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
1da177e4 488{
cdb97558 489 u8 enable;
1da177e4 490
87e3dc38
JS		 491 /*
492 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
493 * with low legacy (and fixed) ports. We don't know the decoding
494 * priority and can't tell whether the legacy device or the one created
495 * here is really at that address. This happens on boards with broken
496 * BIOSes.
497 */
498
cdb97558 499 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
65195c76
YL		 500 if (enable & ICH4_ACPI_EN)
501 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
502 "ICH4 ACPI/GPIO/TCO");
1da177e4 503
cdb97558 504 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
65195c76
YL		 505 if (enable & ICH4_GPIO_EN)
506 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
507 "ICH4 GPIO");
1da177e4 508}
652c538e
AM		 509DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
516DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
517DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
518DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
1da177e4 519
15856ad5 520static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
2cea752f 521{
cdb97558 522 u8 enable;
2cea752f 523
cdb97558 524 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
65195c76
YL		 525 if (enable & ICH6_ACPI_EN)
526 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
527 "ICH6 ACPI/GPIO/TCO");
2cea752f 528
cdb97558 529 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
65195c76
YL		 530 if (enable & ICH6_GPIO_EN)
531 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
532 "ICH6 GPIO");
2cea752f 533}
894886e5 534
15856ad5 535static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
894886e5
LT		 536{
537 u32 val;
538 u32 size, base;
539
540 pci_read_config_dword(dev, reg, &val);
541
542 /* Enabled? */
543 if (!(val & 1))
544 return;
545 base = val & 0xfffc;
546 if (dynsize) {
547 /*
548 * This is not correct. It is 16, 32 or 64 bytes depending on
549 * register D31:F0:ADh bits 5:4.
550 *
551 * But this gets us at least _part_ of it.
552 */
553 size = 16;
554 } else {
555 size = 128;
556 }
557 base &= ~(size-1);
558
559 /* Just print it out for now. We should reserve it after more debugging */
560 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
561}
562
15856ad5 563static void quirk_ich6_lpc(struct pci_dev *dev)
894886e5
LT		 564{
565 /* Shared ACPI/GPIO decode with all ICH6+ */
566 ich6_lpc_acpi_gpio(dev);
567
568 /* ICH6-specific generic IO decode */
569 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
570 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
571}
572DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
573DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
574
15856ad5 575static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
894886e5
LT		 576{
577 u32 val;
578 u32 mask, base;
579
580 pci_read_config_dword(dev, reg, &val);
581
582 /* Enabled? */
583 if (!(val & 1))
584 return;
585
586 /*
587 * IO base in bits 15:2, mask in bits 23:18, both
588 * are dword-based
589 */
590 base = val & 0xfffc;
591 mask = (val >> 16) & 0xfc;
592 mask |= 3;
593
594 /* Just print it out for now. We should reserve it after more debugging */
595 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
596}
597
598/* ICH7-10 has the same common LPC generic IO decode registers */
15856ad5 599static void quirk_ich7_lpc(struct pci_dev *dev)
894886e5 600{
5d9c0a79 601 /* We share the common ACPI/GPIO decode with ICH6 */
894886e5
LT		 602 ich6_lpc_acpi_gpio(dev);
603
604 /* And have 4 ICH7+ generic decodes */
605 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
606 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
607 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
608 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
609}
610DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
611DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
612DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
613DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
614DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
615DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
616DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
617DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
618DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
619DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
620DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
621DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
622DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
2cea752f 623
1da177e4
LT		 624/*
625 * VIA ACPI: One IO region pointed to by longword at
626 * 0x48 or 0x20 (256 bytes of ACPI registers)
627 */
15856ad5 628static void quirk_vt82c586_acpi(struct pci_dev *dev)
1da177e4 629{
65195c76
YL		 630 if (dev->revision & 0x10)
631 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
632 "vt82c586 ACPI");
1da177e4 633}
652c538e 634DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1da177e4
LT		 635
636/*
637 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
638 * 0x48 (256 bytes of ACPI registers)
639 * 0x70 (128 bytes of hardware monitoring register)
640 * 0x90 (16 bytes of SMB registers)
641 */
15856ad5 642static void quirk_vt82c686_acpi(struct pci_dev *dev)
1da177e4 643{
1da177e4
LT		 644 quirk_vt82c586_acpi(dev);
645
65195c76
YL		 646 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
647 "vt82c686 HW-mon");
1da177e4 648
65195c76 649 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
1da177e4 650}
652c538e 651DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1da177e4 652
6d85f29b
IK		 653/*
654 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
655 * 0x88 (128 bytes of power management registers)
656 * 0xd0 (16 bytes of SMB registers)
657 */
15856ad5 658static void quirk_vt8235_acpi(struct pci_dev *dev)
6d85f29b 659{
65195c76
YL		 660 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
661 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
6d85f29b
IK		 662}
663DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
664
1f56f4a2
GB		 665/*
666 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
667 * Disable fast back-to-back on the secondary bus segment
668 */
15856ad5 669static void quirk_xio2000a(struct pci_dev *dev)
1f56f4a2
GB		 670{
671 struct pci_dev *pdev;
672 u16 command;
673
674 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
675 "secondary bus fast back-to-back transfers disabled\n");
676 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
677 pci_read_config_word(pdev, PCI_COMMAND, &command);
678 if (command & PCI_COMMAND_FAST_BACK)
679 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
680 }
681}
682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
683 quirk_xio2000a);
1da177e4
LT		 684
685#ifdef CONFIG_X86_IO_APIC
686
687#include <asm/io_apic.h>
688
689/*
690 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
691 * devices to the external APIC.
692 *
693 * TODO: When we have device-specific interrupt routers,
694 * this code will go away from quirks.
695 */
1597cacb 696static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 697{
698 u8 tmp;
699
700 if (nr_ioapics < 1)
701 tmp = 0; /* nothing routed to external APIC */
702 else
703 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
704
f0fda801 705 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
1da177e4
LT		 706 tmp == 0 ? "Disa" : "Ena");
707
708 /* Offset 0x58: External APIC IRQ output control */
709 pci_write_config_byte (dev, 0x58, tmp);
710}
652c538e 711DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
e1a2a51e 712DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1da177e4 713
a1740913
KW		 714/*
715 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
716 * This leads to doubled level interrupt rates.
717 * Set this bit to get rid of cycle wastage.
718 * Otherwise uncritical.
719 */
1597cacb 720static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 721{
722 u8 misc_control2;
723#define BYPASS_APIC_DEASSERT 8
724
725 pci_read_config_byte(dev, 0x5B, &misc_control2);
726 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
f0fda801 727 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
a1740913
KW		 728 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
729 }
730}
731DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
e1a2a51e 732DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 733
1da177e4
LT		 734/*
735 * The AMD io apic can hang the box when an apic irq is masked.
736 * We check all revs >= B0 (yet not in the pre production!) as the bug
737 * is currently marked NoFix
738 *
739 * We have multiple reports of hangs with this chipset that went away with
236561e5 740 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 741 * of course. However the advice is demonstrably good even if so..
742 */
15856ad5 743static void quirk_amd_ioapic(struct pci_dev *dev)
1da177e4 744{
44c10138 745 if (dev->revision >= 0x02) {
f0fda801 746 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
747 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
1da177e4
LT		 748 }
749}
652c538e 750DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1da177e4 751
15856ad5 752static void quirk_ioapic_rmw(struct pci_dev *dev)
1da177e4
LT		 753{
754 if (dev->devfn == 0 && dev->bus->number == 0)
755 sis_apic_bug = 1;
756}
652c538e 757DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
1da177e4
LT		 758#endif /* CONFIG_X86_IO_APIC */
759
d556ad4b
PO		 760/*
761 * Some settings of MMRBC can lead to data corruption so block changes.
762 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
763 */
15856ad5 764static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
d556ad4b 765{
aa288d4d 766 if (dev->subordinate && dev->revision <= 0x12) {
f0fda801 767 dev_info(&dev->dev, "AMD8131 rev %x detected; "
768 "disabling PCI-X MMRBC\n", dev->revision);
d556ad4b
PO		 769 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
770 }
771}
772DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 773
1da177e4
LT		 774/*
775 * FIXME: it is questionable that quirk_via_acpi
776 * is needed. It shows up as an ISA bridge, and does not
777 * support the PCI_INTERRUPT_LINE register at all. Therefore
778 * it seems like setting the pci_dev's 'irq' to the
779 * value of the ACPI SCI interrupt is only done for convenience.
780 * -jgarzik
781 */
15856ad5 782static void quirk_via_acpi(struct pci_dev *d)
1da177e4
LT		 783{
784 /*
785 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
786 */
787 u8 irq;
788 pci_read_config_byte(d, 0x42, &irq);
789 irq &= 0xf;
790 if (irq && (irq != 2))
791 d->irq = irq;
792}
652c538e
AM		 793DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
794DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1da177e4 795
09d6029f
DD		 796
797/*
1597cacb 798 * VIA bridges which have VLink
09d6029f 799 */
1597cacb 800
c06bb5d4
JD		 801static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
802
803static void quirk_via_bridge(struct pci_dev *dev)
804{
805 /* See what bridge we have and find the device ranges */
806 switch (dev->device) {
807 case PCI_DEVICE_ID_VIA_82C686:
cb7468ef
JD		 808 /* The VT82C686 is special, it attaches to PCI and can have
809 any device number. All its subdevices are functions of
810 that single device. */
811 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
812 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 813 break;
814 case PCI_DEVICE_ID_VIA_8237:
815 case PCI_DEVICE_ID_VIA_8237A:
816 via_vlink_dev_lo = 15;
817 break;
818 case PCI_DEVICE_ID_VIA_8235:
819 via_vlink_dev_lo = 16;
820 break;
821 case PCI_DEVICE_ID_VIA_8231:
822 case PCI_DEVICE_ID_VIA_8233_0:
823 case PCI_DEVICE_ID_VIA_8233A:
824 case PCI_DEVICE_ID_VIA_8233C_0:
825 via_vlink_dev_lo = 17;
826 break;
827 }
828}
829DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
830DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
831DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
832DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
833DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
834DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
835DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
836DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 837
1597cacb
AC		 838/**
839 * quirk_via_vlink - VIA VLink IRQ number update
840 * @dev: PCI device
841 *
842 * If the device we are dealing with is on a PIC IRQ we need to
843 * ensure that the IRQ line register which usually is not relevant
844 * for PCI cards, is actually written so that interrupts get sent
c06bb5d4
JD		 845 * to the right place.
846 * We only do this on systems where a VIA south bridge was detected,
847 * and only for VIA devices on the motherboard (see quirk_via_bridge
848 * above).
1597cacb
AC		 849 */
850
851static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 852{
853 u8 irq, new_irq;
854
c06bb5d4
JD		 855 /* Check if we have VLink at all */
856 if (via_vlink_dev_lo == -1)
09d6029f
DD		 857 return;
858
859 new_irq = dev->irq;
860
861 /* Don't quirk interrupts outside the legacy IRQ range */
862 if (!new_irq || new_irq > 15)
863 return;
864
1597cacb 865 /* Internal device ? */
c06bb5d4
JD		 866 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
867 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 868 return;
869
870 /* This is an internal VLink device on a PIC interrupt. The BIOS
871 ought to have set this but may not have, so we redo it */
872
25be5e6c
LB		 873 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
874 if (new_irq != irq) {
f0fda801 875 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
876 irq, new_irq);
25be5e6c
LB		 877 udelay(15); /* unknown if delay really needed */
878 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
879 }
880}
1597cacb 881DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 882
1da177e4
LT		 883/*
884 * VIA VT82C598 has its device ID settable and many BIOSes
885 * set it to the ID of VT82C597 for backward compatibility.
886 * We need to switch it off to be able to recognize the real
887 * type of the chip.
888 */
15856ad5 889static void quirk_vt82c598_id(struct pci_dev *dev)
1da177e4
LT		 890{
891 pci_write_config_byte(dev, 0xfc, 0);
892 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
893}
652c538e 894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1da177e4
LT		 895
896/*
897 * CardBus controllers have a legacy base address that enables them
898 * to respond as i82365 pcmcia controllers. We don't want them to
899 * do this even if the Linux CardBus driver is not loaded, because
900 * the Linux i82365 driver does not (and should not) handle CardBus.
901 */
1597cacb 902static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4 903{
1da177e4
LT		 904 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
905}
ae9de56b
YL		 906DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
907 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
908DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
909 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1da177e4
LT		 910
911/*
912 * Following the PCI ordering rules is optional on the AMD762. I'm not
913 * sure what the designers were smoking but let's not inhale...
914 *
915 * To be fair to AMD, it follows the spec by default, its BIOS people
916 * who turn it off!
917 */
1597cacb 918static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 919{
920 u32 pcic;
921 pci_read_config_dword(dev, 0x4C, &pcic);
922 if ((pcic&6)!=6) {
923 pcic |= 6;
f0fda801 924 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1da177e4
LT		 925 pci_write_config_dword(dev, 0x4C, pcic);
926 pci_read_config_dword(dev, 0x84, &pcic);
927 pcic |= (1<<23); /* Required in this mode */
928 pci_write_config_dword(dev, 0x84, pcic);
929 }
930}
652c538e 931DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
e1a2a51e 932DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1da177e4
LT		 933
934/*
935 * DreamWorks provided workaround for Dunord I-3000 problem
936 *
937 * This card decodes and responds to addresses not apparently
938 * assigned to it. We force a larger allocation to ensure that
939 * nothing gets put too close to it.
940 */
15856ad5 941static void quirk_dunord(struct pci_dev *dev)
1da177e4
LT		 942{
943 struct resource *r = &dev->resource [1];
944 r->start = 0;
945 r->end = 0xffffff;
946}
652c538e 947DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1da177e4
LT		 948
949/*
950 * i82380FB mobile docking controller: its PCI-to-PCI bridge
951 * is subtractive decoding (transparent), and does indicate this
952 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
953 * instead of 0x01.
954 */
15856ad5 955static void quirk_transparent_bridge(struct pci_dev *dev)
1da177e4
LT		 956{
957 dev->transparent = 1;
958}
652c538e
AM		 959DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
960DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1da177e4
LT		 961
962/*
963 * Common misconfiguration of the MediaGX/Geode PCI master that will
964 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
631dd1a8 965 * datasheets found at http://www.national.com/analog for info on what
1da177e4
LT		 966 * these bits do. <christer@weinigel.se>
967 */
1597cacb 968static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 969{
970 u8 reg;
971 pci_read_config_byte(dev, 0x41, &reg);
972 if (reg & 2) {
973 reg &= ~2;
f0fda801 974 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1da177e4
LT		 975 pci_write_config_byte(dev, 0x41, reg);
976 }
977}
652c538e
AM		 978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
979DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1da177e4 980
1da177e4
LT		 981/*
982 * Ensure C0 rev restreaming is off. This is normally done by
983 * the BIOS but in the odd case it is not the results are corruption
984 * hence the presence of a Linux check
985 */
1597cacb 986static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 987{
988 u16 config;
1da177e4 989
44c10138 990 if (pdev->revision != 0x04) /* Only C0 requires this */
1da177e4
LT		 991 return;
992 pci_read_config_word(pdev, 0x40, &config);
993 if (config & (1<<6)) {
994 config &= ~(1<<6);
995 pci_write_config_word(pdev, 0x40, config);
f0fda801 996 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1da177e4
LT		 997 }
998}
652c538e 999DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
e1a2a51e 1000DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1da177e4 1001
25e742b2 1002static void quirk_amd_ide_mode(struct pci_dev *pdev)
ab17443a 1003{
5deab536 1004 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
05a7d22b 1005 u8 tmp;
ab17443a 1006
05a7d22b
CC		 1007 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1008 if (tmp == 0x01) {
ab17443a
CH		 1009 pci_read_config_byte(pdev, 0x40, &tmp);
1010 pci_write_config_byte(pdev, 0x40, tmp|1);
1011 pci_write_config_byte(pdev, 0x9, 1);
1012 pci_write_config_byte(pdev, 0xa, 6);
1013 pci_write_config_byte(pdev, 0x40, tmp);
1014
c9f89475 1015 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
05a7d22b 1016 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
ab17443a
CH		 1017 }
1018}
05a7d22b 1019DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
e1a2a51e 1020DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
05a7d22b 1021DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
e1a2a51e 1022DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
5deab536
SH		 1023DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1024DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
7d31ea0d
SH		 1025DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1026DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
ab17443a 1027
1da177e4
LT		 1028/*
1029 * Serverworks CSB5 IDE does not fully support native mode
1030 */
15856ad5 1031static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1da177e4
LT		 1032{
1033 u8 prog;
1034 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1035 if (prog & 5) {
1036 prog &= ~5;
1037 pdev->class &= ~5;
1038 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 1039 /* PCI layer will sort out resources */
1da177e4
LT		 1040 }
1041}
652c538e 1042DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1da177e4
LT		 1043
1044/*
1045 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1046 */
15856ad5 1047static void quirk_ide_samemode(struct pci_dev *pdev)
1da177e4
LT		 1048{
1049 u8 prog;
1050
1051 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1052
1053 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
f0fda801 1054 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1da177e4
LT		 1055 prog &= ~5;
1056 pdev->class &= ~5;
1057 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 1058 }
1059}
368c73d4 1060DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4 1061
979b1791
AC		 1062/*
1063 * Some ATA devices break if put into D3
1064 */
1065
15856ad5 1066static void quirk_no_ata_d3(struct pci_dev *pdev)
979b1791 1067{
faa738bb 1068 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
979b1791 1069}
faa738bb
YL		 1070/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1071DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1072 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1073DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1074 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
7a661c6f 1075/* ALi loses some register settings that we cannot then restore */
faa738bb
YL		 1076DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1077 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
7a661c6f
AC		 1078/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1079 occur when mode detecting */
faa738bb
YL		 1080DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1081 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
979b1791 1082
1da177e4
LT		 1083/* This was originally an Alpha specific thing, but it really fits here.
1084 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1085 */
15856ad5 1086static void quirk_eisa_bridge(struct pci_dev *dev)
1da177e4
LT		 1087{
1088 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1089}
652c538e 1090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1da177e4 1091
7daa0c4f 1092
1da177e4
LT		 1093/*
1094 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1095 * is not activated. The myth is that Asus said that they do not want the
1096 * users to be irritated by just another PCI Device in the Win98 device
1097 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1098 * package 2.7.0 for details)
1099 *
1100 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1101 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
d7698edc 1102 * becomes necessary to do this tweak in two steps -- the chosen trigger
1103 * is either the Host bridge (preferred) or on-board VGA controller.
9208ee82
JD		 1104 *
1105 * Note that we used to unhide the SMBus that way on Toshiba laptops
1106 * (Satellite A40 and Tecra M2) but then found that the thermal management
1107 * was done by SMM code, which could cause unsynchronized concurrent
1108 * accesses to the SMBus registers, with potentially bad effects. Thus you
1109 * should be very careful when adding new entries: if SMM is accessing the
1110 * Intel SMBus, this is a very good reason to leave it hidden.
a99acc83
JD		 1111 *
1112 * Likewise, many recent laptops use ACPI for thermal management. If the
1113 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1114 * natively, and keeping the SMBus hidden is the right thing to do. If you
1115 * are about to add an entry in the table below, please first disassemble
1116 * the DSDT and double-check that there is no code accessing the SMBus.
1da177e4 1117 */
9d24a81e 1118static int asus_hides_smbus;
1da177e4 1119
15856ad5 1120static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1da177e4
LT		 1121{
1122 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1123 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1124 switch(dev->subsystem_device) {
a00db371 1125 case 0x8025: /* P4B-LX */
1da177e4
LT		 1126 case 0x8070: /* P4B */
1127 case 0x8088: /* P4B533 */
1128 case 0x1626: /* L3C notebook */
1129 asus_hides_smbus = 1;
1130 }
2f2d39d2 1131 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1da177e4
LT		 1132 switch(dev->subsystem_device) {
1133 case 0x80b1: /* P4GE-V */
1134 case 0x80b2: /* P4PE */
1135 case 0x8093: /* P4B533-V */
1136 asus_hides_smbus = 1;
1137 }
2f2d39d2 1138 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1da177e4
LT		 1139 switch(dev->subsystem_device) {
1140 case 0x8030: /* P4T533 */
1141 asus_hides_smbus = 1;
1142 }
2f2d39d2 1143 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 1144 switch (dev->subsystem_device) {
1145 case 0x8070: /* P4G8X Deluxe */
1146 asus_hides_smbus = 1;
1147 }
2f2d39d2 1148 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 1149 switch (dev->subsystem_device) {
1150 case 0x80c9: /* PU-DLS */
1151 asus_hides_smbus = 1;
1152 }
2f2d39d2 1153 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 1154 switch (dev->subsystem_device) {
1155 case 0x1751: /* M2N notebook */
1156 case 0x1821: /* M5N notebook */
4096ed0f 1157 case 0x1897: /* A6L notebook */
1da177e4
LT		 1158 asus_hides_smbus = 1;
1159 }
2f2d39d2 1160 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 1161 switch (dev->subsystem_device) {
1162 case 0x184b: /* W1N notebook */
1163 case 0x186a: /* M6Ne notebook */
1164 asus_hides_smbus = 1;
1165 }
2f2d39d2 1166 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1167 switch (dev->subsystem_device) {
1168 case 0x80f2: /* P4P800-X */
1169 asus_hides_smbus = 1;
1170 }
2f2d39d2 1171 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
RM		 1172 switch (dev->subsystem_device) {
1173 case 0x1882: /* M6V notebook */
2d1e1c75 1174 case 0x1977: /* A6VA notebook */
acc06632
RM		 1175 asus_hides_smbus = 1;
1176 }
1da177e4
LT		 1177 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1178 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1179 switch(dev->subsystem_device) {
1180 case 0x088C: /* HP Compaq nc8000 */
1181 case 0x0890: /* HP Compaq nc6000 */
1182 asus_hides_smbus = 1;
1183 }
2f2d39d2 1184 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1185 switch (dev->subsystem_device) {
1186 case 0x12bc: /* HP D330L */
e3b1bd57 1187 case 0x12bd: /* HP D530 */
74c57428 1188 case 0x006a: /* HP Compaq nx9500 */
1da177e4
LT		 1189 asus_hides_smbus = 1;
1190 }
677cc644
JD		 1191 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1192 switch (dev->subsystem_device) {
1193 case 0x12bf: /* HP xw4100 */
1194 asus_hides_smbus = 1;
1195 }
1da177e4
LT		 1196 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1197 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1198 switch(dev->subsystem_device) {
1199 case 0xC00C: /* Samsung P35 notebook */
1200 asus_hides_smbus = 1;
1201 }
c87f883e
RIZ		 1202 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1203 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1204 switch(dev->subsystem_device) {
1205 case 0x0058: /* Compaq Evo N620c */
1206 asus_hides_smbus = 1;
1207 }
d7698edc 1208 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1209 switch(dev->subsystem_device) {
1210 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1211 /* Motherboard doesn't have Host bridge
1212 * subvendor/subdevice IDs, therefore checking
1213 * its on-board VGA controller */
1214 asus_hides_smbus = 1;
1215 }
8293b0f6 1216 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
10260d9a
JD		 1217 switch(dev->subsystem_device) {
1218 case 0x00b8: /* Compaq Evo D510 CMT */
1219 case 0x00b9: /* Compaq Evo D510 SFF */
6b5096e4 1220 case 0x00ba: /* Compaq Evo D510 USDT */
8293b0f6
DS		 1221 /* Motherboard doesn't have Host bridge
1222 * subvendor/subdevice IDs and on-board VGA
1223 * controller is disabled if an AGP card is
1224 * inserted, therefore checking USB UHCI
1225 * Controller #1 */
10260d9a
JD		 1226 asus_hides_smbus = 1;
1227 }
27e46859
KH		 1228 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1229 switch (dev->subsystem_device) {
1230 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1231 /* Motherboard doesn't have host bridge
1232 * subvendor/subdevice IDs, therefore checking
1233 * its on-board VGA controller */
1234 asus_hides_smbus = 1;
1235 }
1da177e4
LT		 1236 }
1237}
652c538e
AM		 1238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
677cc644 1242DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
652c538e
AM		 1243DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1244DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1245DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1246DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1247DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1248
1249DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
8293b0f6 1250DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
27e46859 1251DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
d7698edc 1252
1597cacb 1253static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1254{
1255 u16 val;
1256
1257 if (likely(!asus_hides_smbus))
1258 return;
1259
1260 pci_read_config_word(dev, 0xF2, &val);
1261 if (val & 0x8) {
1262 pci_write_config_word(dev, 0xF2, val & (~0x8));
1263 pci_read_config_word(dev, 0xF2, &val);
1264 if (val & 0x8)
f0fda801 1265 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1da177e4 1266 else
f0fda801 1267 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1da177e4
LT		 1268 }
1269}
652c538e
AM		 1270DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1272DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1274DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
e1a2a51e
RW		 1277DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1278DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1279DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1280DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1281DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1282DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1283DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1597cacb 1284
e1a2a51e
RW		 1285/* It appears we just have one such device. If not, we have a warning */
1286static void __iomem *asus_rcba_base;
1287static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
acc06632 1288{
e1a2a51e 1289 u32 rcba;
acc06632
RM		 1290
1291 if (likely(!asus_hides_smbus))
1292 return;
e1a2a51e
RW		 1293 WARN_ON(asus_rcba_base);
1294
acc06632 1295 pci_read_config_dword(dev, 0xF0, &rcba);
e1a2a51e
RW		 1296 /* use bits 31:14, 16 kB aligned */
1297 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1298 if (asus_rcba_base == NULL)
1299 return;
1300}
1301
1302static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1303{
1304 u32 val;
1305
1306 if (likely(!asus_hides_smbus || !asus_rcba_base))
1307 return;
1308 /* read the Function Disable register, dword mode only */
1309 val = readl(asus_rcba_base + 0x3418);
1310 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1311}
1312
1313static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1314{
1315 if (likely(!asus_hides_smbus || !asus_rcba_base))
1316 return;
1317 iounmap(asus_rcba_base);
1318 asus_rcba_base = NULL;
f0fda801 1319 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
acc06632 1320}
e1a2a51e
RW		 1321
1322static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1323{
1324 asus_hides_smbus_lpc_ich6_suspend(dev);
1325 asus_hides_smbus_lpc_ich6_resume_early(dev);
1326 asus_hides_smbus_lpc_ich6_resume(dev);
1327}
652c538e 1328DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
e1a2a51e
RW		 1329DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1330DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1331DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
ce007ea5 1332
1da177e4
LT		 1333/*
1334 * SiS 96x south bridge: BIOS typically hides SMBus device...
1335 */
1597cacb 1336static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1337{
1338 u8 val = 0;
1da177e4 1339 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3 1340 if (val & 0x10) {
f0fda801 1341 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
2f5c33b3
MH		 1342 pci_write_config_byte(dev, 0x77, val & ~0x10);
1343 }
1da177e4 1344}
652c538e
AM		 1345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1347DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1348DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
e1a2a51e
RW		 1349DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1350DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1351DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1352DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1da177e4 1353
1da177e4
LT		 1354/*
1355 * ... This is further complicated by the fact that some SiS96x south
1356 * bridges pretend to be 85C503/5513 instead. In that case see if we
1357 * spotted a compatible north bridge to make sure.
1358 * (pci_find_device doesn't work yet)
1359 *
1360 * We can also enable the sis96x bit in the discovery register..
1361 */
1da177e4
LT		 1362#define SIS_DETECT_REGISTER 0x40
1363
1597cacb 1364static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1365{
1366 u8 reg;
1367 u16 devid;
1368
1369 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1370 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1371 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1372 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1373 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1374 return;
1375 }
1376
1da177e4 1377 /*
2f5c33b3
MH		 1378 * Ok, it now shows up as a 96x.. run the 96x quirk by
1379 * hand in case it has already been processed.
1380 * (depends on link order, which is apparently not guaranteed)
1da177e4
LT		 1381 */
1382 dev->device = devid;
2f5c33b3 1383 quirk_sis_96x_smbus(dev);
1da177e4 1384}
652c538e 1385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
e1a2a51e 1386DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1da177e4 1387
1da177e4 1388
e5548e96
BJD		 1389/*
1390 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1391 * and MC97 modem controller are disabled when a second PCI soundcard is
1392 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1393 * -- bjd
1394 */
1597cacb 1395static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1396{
1397 u8 val;
1398 int asus_hides_ac97 = 0;
1399
1400 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1401 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1402 asus_hides_ac97 = 1;
1403 }
1404
1405 if (!asus_hides_ac97)
1406 return;
1407
1408 pci_read_config_byte(dev, 0x50, &val);
1409 if (val & 0xc0) {
1410 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1411 pci_read_config_byte(dev, 0x50, &val);
1412 if (val & 0xc0)
f0fda801 1413 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
e5548e96 1414 else
f0fda801 1415 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
e5548e96
BJD		 1416 }
1417}
652c538e 1418DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
e1a2a51e 1419DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1597cacb 1420
77967052 1421#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1422
1423/*
1424 * If we are using libata we can drive this chip properly but must
1425 * do this early on to make the additional device appear during
1426 * the PCI scanning.
1427 */
5ee2ae7f 1428static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1429{
e34bb370 1430 u32 conf1, conf5, class;
15e0c694
AC		 1431 u8 hdr;
1432
1433 /* Only poke fn 0 */
1434 if (PCI_FUNC(pdev->devfn))
1435 return;
1436
5ee2ae7f
TH		 1437 pci_read_config_dword(pdev, 0x40, &conf1);
1438 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1439
5ee2ae7f
TH		 1440 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1441 conf5 &= ~(1 << 24); /* Clear bit 24 */
1442
1443 switch (pdev->device) {
4daedcfe
TH		 1444 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1445 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
5b6ae5ba 1446 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
5ee2ae7f
TH		 1447 /* The controller should be in single function ahci mode */
1448 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1449 break;
1450
1451 case PCI_DEVICE_ID_JMICRON_JMB365:
1452 case PCI_DEVICE_ID_JMICRON_JMB366:
1453 /* Redirect IDE second PATA port to the right spot */
1454 conf5 |= (1 << 24);
1455 /* Fall through */
1456 case PCI_DEVICE_ID_JMICRON_JMB361:
1457 case PCI_DEVICE_ID_JMICRON_JMB363:
5b6ae5ba 1458 case PCI_DEVICE_ID_JMICRON_JMB369:
5ee2ae7f
TH		 1459 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1460 /* Set the class codes correctly and then direct IDE 0 */
3a9e3a51 1461 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
5ee2ae7f
TH		 1462 break;
1463
1464 case PCI_DEVICE_ID_JMICRON_JMB368:
1465 /* The controller should be in single function IDE mode */
1466 conf1 |= 0x00C00000; /* Set 22, 23 */
1467 break;
15e0c694 1468 }
5ee2ae7f
TH		 1469
1470 pci_write_config_dword(pdev, 0x40, conf1);
1471 pci_write_config_dword(pdev, 0x80, conf5);
1472
1473 /* Update pdev accordingly */
1474 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1475 pdev->hdr_type = hdr & 0x7f;
1476 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1477
1478 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1479 pdev->class = class >> 8;
15e0c694 1480}
5ee2ae7f
TH		 1481DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1482DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
4daedcfe 1483DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
5ee2ae7f 1484DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
5b6ae5ba 1485DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
5ee2ae7f
TH		 1486DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1487DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1488DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
5b6ae5ba 1489DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
e1a2a51e
RW		 1490DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1491DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
4daedcfe 1492DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
e1a2a51e 1493DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
5b6ae5ba 1494DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
e1a2a51e
RW		 1495DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1496DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1497DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
5b6ae5ba 1498DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
15e0c694
AC		 1499
1500#endif
1501
1da177e4 1502#ifdef CONFIG_X86_IO_APIC
15856ad5 1503static void quirk_alder_ioapic(struct pci_dev *pdev)
1da177e4
LT		 1504{
1505 int i;
1506
1507 if ((pdev->class >> 8) != 0xff00)
1508 return;
1509
1510 /* the first BAR is the location of the IO APIC...we must
1511 * not touch this (and it's already covered by the fixmap), so
1512 * forcibly insert it into the resource tree */
1513 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1514 insert_resource(&iomem_resource, &pdev->resource[0]);
1515
1516 /* The next five BARs all seem to be rubbish, so just clean
1517 * them out */
1518 for (i=1; i < 6; i++) {
1519 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1520 }
1521
1522}
652c538e 1523DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1da177e4
LT		 1524#endif
1525
15856ad5 1526static void quirk_pcie_mch(struct pci_dev *pdev)
1da177e4 1527{
0ba379ec
EB		 1528 pci_msi_off(pdev);
1529 pdev->no_msi = 1;
1da177e4 1530}
652c538e
AM		 1531DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1532DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1533DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1da177e4 1534
4602b88d
KA		 1535
1536/*
1537 * It's possible for the MSI to get corrupted if shpc and acpi
1538 * are used together on certain PXH-based systems.
1539 */
15856ad5 1540static void quirk_pcie_pxh(struct pci_dev *dev)
4602b88d 1541{
f5f2b131 1542 pci_msi_off(dev);
4602b88d 1543 dev->no_msi = 1;
f0fda801 1544 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
4602b88d
KA		 1545}
1546DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1547DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1548DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1549DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1550DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1551
ffadcc2f
KCA		 1552/*
1553 * Some Intel PCI Express chipsets have trouble with downstream
1554 * device power management.
1555 */
1556static void quirk_intel_pcie_pm(struct pci_dev * dev)
1557{
1558 pci_pm_d3_delay = 120;
1559 dev->no_d1d2 = 1;
1560}
1561
1562DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1563DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1564DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1566DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1567DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1572DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1575DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1577DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1579DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1580DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1583
426b3b8d 1584#ifdef CONFIG_X86_IO_APIC
e1d3a908
SA		 1585/*
1586 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1587 * remap the original interrupt in the linux kernel to the boot interrupt, so
1588 * that a PCI device's interrupt handler is installed on the boot interrupt
1589 * line instead.
1590 */
1591static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1592{
41b9eb26 1593 if (noioapicquirk || noioapicreroute)
e1d3a908
SA		 1594 return;
1595
1596 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
fdcdaf6c
BH		 1597 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1598 dev->vendor, dev->device);
e1d3a908 1599}
88d1dce3
OD		 1600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1608DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1609DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1610DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1611DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1612DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1613DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1614DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1615DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
e1d3a908 1616
426b3b8d
SA		 1617/*
1618 * On some chipsets we can disable the generation of legacy INTx boot
1619 * interrupts.
1620 */
1621
1622/*
1623 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1624 * 300641-004US, section 5.7.3.
1625 */
1626#define INTEL_6300_IOAPIC_ABAR 0x40
1627#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1628
1629static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1630{
1631 u16 pci_config_word;
1632
1633 if (noioapicquirk)
1634 return;
1635
1636 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1637 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1638 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1639
fdcdaf6c
BH		 1640 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1641 dev->vendor, dev->device);
426b3b8d 1642}
88d1dce3
OD		 1643DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1644DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
77251188
OD		 1645
1646/*
1647 * disable boot interrupts on HT-1000
1648 */
1649#define BC_HT1000_FEATURE_REG 0x64
1650#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1651#define BC_HT1000_MAP_IDX 0xC00
1652#define BC_HT1000_MAP_DATA 0xC01
1653
1654static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1655{
1656 u32 pci_config_dword;
1657 u8 irq;
1658
1659 if (noioapicquirk)
1660 return;
1661
1662 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1663 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1664 BC_HT1000_PIC_REGS_ENABLE);
1665
1666 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1667 outb(irq, BC_HT1000_MAP_IDX);
1668 outb(0x00, BC_HT1000_MAP_DATA);
1669 }
1670
1671 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1672
fdcdaf6c
BH		 1673 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1674 dev->vendor, dev->device);
77251188 1675}
88d1dce3
OD		 1676DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1677DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
542622da
OD		 1678
1679/*
1680 * disable boot interrupts on AMD and ATI chipsets
1681 */
1682/*
1683 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1684 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1685 * (due to an erratum).
1686 */
1687#define AMD_813X_MISC 0x40
1688#define AMD_813X_NOIOAMODE (1<<0)
4fd8bdc5 1689#define AMD_813X_REV_B1 0x12
bbe19443 1690#define AMD_813X_REV_B2 0x13
542622da
OD		 1691
1692static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1693{
1694 u32 pci_config_dword;
1695
1696 if (noioapicquirk)
1697 return;
4fd8bdc5
SA		 1698 if ((dev->revision == AMD_813X_REV_B1) ||
1699 (dev->revision == AMD_813X_REV_B2))
bbe19443 1700 return;
542622da
OD		 1701
1702 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1703 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1704 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1705
fdcdaf6c
BH		 1706 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1707 dev->vendor, dev->device);
542622da 1708}
4fd8bdc5
SA		 1709DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1710DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1711DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1712DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
542622da
OD		 1713
1714#define AMD_8111_PCI_IRQ_ROUTING 0x56
1715
1716static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1717{
1718 u16 pci_config_word;
1719
1720 if (noioapicquirk)
1721 return;
1722
1723 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1724 if (!pci_config_word) {
fdcdaf6c
BH		 1725 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1726 "already disabled\n", dev->vendor, dev->device);
542622da
OD		 1727 return;
1728 }
1729 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
fdcdaf6c
BH		 1730 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1731 dev->vendor, dev->device);
542622da 1732}
88d1dce3
OD		 1733DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1734DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
426b3b8d
SA		 1735#endif /* CONFIG_X86_IO_APIC */
1736
33dced2e
SS		 1737/*
1738 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1739 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1740 * Re-allocate the region if needed...
1741 */
15856ad5 1742static void quirk_tc86c001_ide(struct pci_dev *dev)
33dced2e
SS		 1743{
1744 struct resource *r = &dev->resource[0];
1745
1746 if (r->start & 0x8) {
1747 r->start = 0;
1748 r->end = 0xf;
1749 }
1750}
1751DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1752 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1753 quirk_tc86c001_ide);
1754
21c5fd97
IA		 1755/*
1756 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1757 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1758 * being read correctly if bit 7 of the base address is set.
1759 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1760 * Re-allocate the regions to a 256-byte boundary if necessary.
1761 */
193c0d68 1762static void quirk_plx_pci9050(struct pci_dev *dev)
21c5fd97
IA		 1763{
1764 unsigned int bar;
1765
1766 /* Fixed in revision 2 (PCI 9052). */
1767 if (dev->revision >= 2)
1768 return;
1769 for (bar = 0; bar <= 1; bar++)
1770 if (pci_resource_len(dev, bar) == 0x80 &&
1771 (pci_resource_start(dev, bar) & 0x80)) {
1772 struct resource *r = &dev->resource[bar];
1773 dev_info(&dev->dev,
1774 "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1775 bar);
1776 r->start = 0;
1777 r->end = 0xff;
1778 }
1779}
1780DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1781 quirk_plx_pci9050);
2794bb28
IA		 1782/*
1783 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1784 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1785 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1786 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1787 *
1788 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1789 * driver.
1790 */
1791DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1792DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
21c5fd97 1793
15856ad5 1794static void quirk_netmos(struct pci_dev *dev)
1da177e4
LT		 1795{
1796 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1797 unsigned int num_serial = dev->subsystem_device & 0xf;
1798
1799 /*
1800 * These Netmos parts are multiport serial devices with optional
1801 * parallel ports. Even when parallel ports are present, they
1802 * are identified as class SERIAL, which means the serial driver
1803 * will claim them. To prevent this, mark them as class OTHER.
1804 * These combo devices should be claimed by parport_serial.
1805 *
1806 * The subdevice ID is of the form 0x00PS, where <P> is the number
1807 * of parallel ports and <S> is the number of serial ports.
1808 */
1809 switch (dev->device) {
4c9c1686
JS		 1810 case PCI_DEVICE_ID_NETMOS_9835:
1811 /* Well, this rule doesn't hold for the following 9835 device */
1812 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1813 dev->subsystem_device == 0x0299)
1814 return;
1da177e4
LT		 1815 case PCI_DEVICE_ID_NETMOS_9735:
1816 case PCI_DEVICE_ID_NETMOS_9745:
1da177e4
LT		 1817 case PCI_DEVICE_ID_NETMOS_9845:
1818 case PCI_DEVICE_ID_NETMOS_9855:
08803efe 1819 if (num_parallel) {
f0fda801 1820 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1da177e4
LT		 1821 "%u serial); changing class SERIAL to OTHER "
1822 "(use parport_serial)\n",
1823 dev->device, num_parallel, num_serial);
1824 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1825 (dev->class & 0xff);
1826 }
1827 }
1828}
08803efe
YL		 1829DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1830 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1da177e4 1831
15856ad5 1832static void quirk_e100_interrupt(struct pci_dev *dev)
16a74744 1833{
e64aeccb 1834 u16 command, pmcsr;
16a74744
BH		 1835 u8 __iomem *csr;
1836 u8 cmd_hi;
e64aeccb 1837 int pm;
16a74744
BH		 1838
1839 switch (dev->device) {
1840 /* PCI IDs taken from drivers/net/e100.c */
1841 case 0x1029:
1842 case 0x1030 ... 0x1034:
1843 case 0x1038 ... 0x103E:
1844 case 0x1050 ... 0x1057:
1845 case 0x1059:
1846 case 0x1064 ... 0x106B:
1847 case 0x1091 ... 0x1095:
1848 case 0x1209:
1849 case 0x1229:
1850 case 0x2449:
1851 case 0x2459:
1852 case 0x245D:
1853 case 0x27DC:
1854 break;
1855 default:
1856 return;
1857 }
1858
1859 /*
1860 * Some firmware hands off the e100 with interrupts enabled,
1861 * which can cause a flood of interrupts if packets are
1862 * received before the driver attaches to the device. So
1863 * disable all e100 interrupts here. The driver will
1864 * re-enable them when it's ready.
1865 */
1866 pci_read_config_word(dev, PCI_COMMAND, &command);
16a74744 1867
1bef7dc0 1868 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
16a74744
BH		 1869 return;
1870
e64aeccb
IK		 1871 /*
1872 * Check that the device is in the D0 power state. If it's not,
1873 * there is no point to look any further.
1874 */
1875 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1876 if (pm) {
1877 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1878 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1879 return;
1880 }
1881
1bef7dc0
BH		 1882 /* Convert from PCI bus to resource space. */
1883 csr = ioremap(pci_resource_start(dev, 0), 8);
16a74744 1884 if (!csr) {
f0fda801 1885 dev_warn(&dev->dev, "Can't map e100 registers\n");
16a74744
BH		 1886 return;
1887 }
1888
1889 cmd_hi = readb(csr + 3);
1890 if (cmd_hi == 0) {
f0fda801 1891 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1892 "disabling\n");
16a74744
BH		 1893 writeb(1, csr + 3);
1894 }
1895
1896 iounmap(csr);
1897}
4c5b28e2
YL		 1898DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1899 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
a5312e28 1900
649426ef
AD		 1901/*
1902 * The 82575 and 82598 may experience data corruption issues when transitioning
1903 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1904 */
15856ad5 1905static void quirk_disable_aspm_l0s(struct pci_dev *dev)
649426ef
AD		 1906{
1907 dev_info(&dev->dev, "Disabling L0s\n");
1908 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1909}
1910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1911DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1912DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1913DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1914DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1915DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1916DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1917DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1918DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1923DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1924
15856ad5 1925static void fixup_rev1_53c810(struct pci_dev *dev)
a5312e28
IK		 1926{
1927 /* rev 1 ncr53c810 chips don't set the class at all which means
1928 * they don't get their resources remapped. Fix that here.
1929 */
1930
1931 if (dev->class == PCI_CLASS_NOT_DEFINED) {
f0fda801 1932 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
a5312e28
IK		 1933 dev->class = PCI_CLASS_STORAGE_SCSI;
1934 }
1935}
1936DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1937
9d265124 1938/* Enable 1k I/O space granularity on the Intel P64H2 */
15856ad5 1939static void quirk_p64h2_1k_io(struct pci_dev *dev)
9d265124
DY		 1940{
1941 u16 en1k;
9d265124
DY		 1942
1943 pci_read_config_word(dev, 0x40, &en1k);
1944
1945 if (en1k & 0x200) {
f0fda801 1946 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2b28ae19 1947 dev->io_window_1k = 1;
9d265124
DY		 1948 }
1949}
1950DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1951
cf34a8e0
BG		 1952/* Under some circumstances, AER is not linked with extended capabilities.
1953 * Force it to be linked by setting the corresponding control bit in the
1954 * config space.
1955 */
1597cacb 1956static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 1957{
1958 uint8_t b;
1959 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1960 if (!(b & 0x20)) {
1961 pci_write_config_byte(dev, 0xf41, b | 0x20);
f0fda801 1962 dev_info(&dev->dev,
1963 "Linking AER extended capability\n");
cf34a8e0
BG		 1964 }
1965 }
1966}
1967DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1968 quirk_nvidia_ck804_pcie_aer_ext_cap);
e1a2a51e 1969DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1597cacb 1970 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 1971
15856ad5 1972static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
53a9bf42
TY		 1973{
1974 /*
1975 * Disable PCI Bus Parking and PCI Master read caching on CX700
1976 * which causes unspecified timing errors with a VT6212L on the PCI
ca846392
TY		 1977 * bus leading to USB2.0 packet loss.
1978 *
1979 * This quirk is only enabled if a second (on the external PCI bus)
1980 * VT6212L is found -- the CX700 core itself also contains a USB
1981 * host controller with the same PCI ID as the VT6212L.
53a9bf42
TY		 1982 */
1983
ca846392
TY		 1984 /* Count VT6212L instances */
1985 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
1986 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
53a9bf42 1987 uint8_t b;
ca846392
TY		 1988
1989 /* p should contain the first (internal) VT6212L -- see if we have
1990 an external one by searching again */
1991 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
1992 if (!p)
1993 return;
1994 pci_dev_put(p);
1995
53a9bf42
TY		 1996 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1997 if (b & 0x40) {
1998 /* Turn off PCI Bus Parking */
1999 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2000
bc043274
TY		 2001 dev_info(&dev->dev,
2002 "Disabling VIA CX700 PCI parking\n");
2003 }
2004 }
2005
2006 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2007 if (b != 0) {
53a9bf42
TY		 2008 /* Turn off PCI Master read caching */
2009 pci_write_config_byte(dev, 0x72, 0x0);
bc043274
TY		 2010
2011 /* Set PCI Master Bus time-out to "1x16 PCLK" */
53a9bf42 2012 pci_write_config_byte(dev, 0x75, 0x1);
bc043274
TY		 2013
2014 /* Disable "Read FIFO Timer" */
53a9bf42
TY		 2015 pci_write_config_byte(dev, 0x77, 0x0);
2016
d6505a52 2017 dev_info(&dev->dev,
bc043274 2018 "Disabling VIA CX700 PCI caching\n");
53a9bf42
TY		 2019 }
2020 }
2021}
ca846392 2022DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
53a9bf42 2023
99cb233d
BL		 2024/*
2025 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2026 * VPD end tag will hang the device. This problem was initially
2027 * observed when a vpd entry was created in sysfs
2028 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2029 * will dump 32k of data. Reading a full 32k will cause an access
2030 * beyond the VPD end tag causing the device to hang. Once the device
2031 * is hung, the bnx2 driver will not be able to reset the device.
2032 * We believe that it is legal to read beyond the end tag and
2033 * therefore the solution is to limit the read/write length.
2034 */
15856ad5 2035static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
99cb233d 2036{
9d82d8ea 2037 /*
35405f25
DH		 2038 * Only disable the VPD capability for 5706, 5706S, 5708,
2039 * 5708S and 5709 rev. A
9d82d8ea 2040 */
99cb233d 2041 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
35405f25 2042 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
99cb233d 2043 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
9d82d8ea 2044 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
99cb233d
BL		 2045 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2046 (dev->revision & 0xf0) == 0x0)) {
2047 if (dev->vpd)
2048 dev->vpd->len = 0x80;
2049 }
2050}
2051
bffadffd
YZ		 2052DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2053 PCI_DEVICE_ID_NX2_5706,
2054 quirk_brcm_570x_limit_vpd);
2055DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2056 PCI_DEVICE_ID_NX2_5706S,
2057 quirk_brcm_570x_limit_vpd);
2058DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2059 PCI_DEVICE_ID_NX2_5708,
2060 quirk_brcm_570x_limit_vpd);
2061DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2062 PCI_DEVICE_ID_NX2_5708S,
2063 quirk_brcm_570x_limit_vpd);
2064DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2065 PCI_DEVICE_ID_NX2_5709,
2066 quirk_brcm_570x_limit_vpd);
2067DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2068 PCI_DEVICE_ID_NX2_5709S,
2069 quirk_brcm_570x_limit_vpd);
99cb233d 2070
25e742b2 2071static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
0b471506
MC		 2072{
2073 u32 rev;
2074
2075 pci_read_config_dword(dev, 0xf4, &rev);
2076
2077 /* Only CAP the MRRS if the device is a 5719 A0 */
2078 if (rev == 0x05719000) {
2079 int readrq = pcie_get_readrq(dev);
2080 if (readrq > 2048)
2081 pcie_set_readrq(dev, 2048);
2082 }
2083}
2084
2085DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2086 PCI_DEVICE_ID_TIGON3_5719,
2087 quirk_brcm_5719_limit_mrrs);
2088
26c56dc0
MM		 2089/* Originally in EDAC sources for i82875P:
2090 * Intel tells BIOS developers to hide device 6 which
2091 * configures the overflow device access containing
2092 * the DRBs - this is where we expose device 6.
2093 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2094 */
15856ad5 2095static void quirk_unhide_mch_dev6(struct pci_dev *dev)
26c56dc0
MM		 2096{
2097 u8 reg;
2098
2099 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2100 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2101 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2102 }
2103}
2104
2105DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2106 quirk_unhide_mch_dev6);
2107DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2108 quirk_unhide_mch_dev6);
2109
12962267 2110#ifdef CONFIG_TILEPRO
f02cbbe6 2111/*
12962267 2112 * The Tilera TILEmpower tilepro platform needs to set the link speed
f02cbbe6
CM		 2113 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2114 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2115 * capability register of the PEX8624 PCIe switch. The switch
2116 * supports link speed auto negotiation, but falsely sets
2117 * the link speed to 5GT/s.
2118 */
15856ad5 2119static void quirk_tile_plx_gen1(struct pci_dev *dev)
f02cbbe6
CM		 2120{
2121 if (tile_plx_gen1) {
2122 pci_write_config_dword(dev, 0x98, 0x1);
2123 mdelay(50);
2124 }
2125}
2126DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
12962267 2127#endif /* CONFIG_TILEPRO */
26c56dc0 2128
3f79e107 2129#ifdef CONFIG_PCI_MSI
ebdf7d39
TH		 2130/* Some chipsets do not support MSI. We cannot easily rely on setting
2131 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2132 * some other busses controlled by the chipset even if Linux is not
2133 * aware of it. Instead of setting the flag on all busses in the
2134 * machine, simply disable MSI globally.
3f79e107 2135 */
15856ad5 2136static void quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 2137{
88187dfa 2138 pci_no_msi();
f0fda801 2139 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
3f79e107 2140}
ebdf7d39
TH		 2141DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2142DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2143DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
66d715c9 2144DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
184b812f 2145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
162dedd3 2146DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
549e1561 2147DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
3f79e107
BG		 2148
2149/* Disable MSI on chipsets that are known to not support it */
15856ad5 2150static void quirk_disable_msi(struct pci_dev *dev)
3f79e107
BG		 2151{
2152 if (dev->subordinate) {
f0fda801 2153 dev_warn(&dev->dev, "MSI quirk detected; "
2154 "subordinate MSI disabled\n");
3f79e107
BG		 2155 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2156 }
2157}
2158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
134b3450 2159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
9313ff45 2160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
6397c75c 2161
aff61369
CL		 2162/*
2163 * The APC bridge device in AMD 780 family northbridges has some random
2164 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2165 * we use the possible vendor/device IDs of the host bridge for the
2166 * declared quirk, and search for the APC bridge by slot number.
2167 */
15856ad5 2168static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
aff61369
CL		 2169{
2170 struct pci_dev *apc_bridge;
2171
2172 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2173 if (apc_bridge) {
2174 if (apc_bridge->device == 0x9602)
2175 quirk_disable_msi(apc_bridge);
2176 pci_dev_put(apc_bridge);
2177 }
2178}
2179DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2180DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2181
6397c75c
BG		 2182/* Go through the list of Hypertransport capabilities and
2183 * return 1 if a HT MSI capability is found and enabled */
25e742b2 2184static int msi_ht_cap_enabled(struct pci_dev *dev)
6397c75c 2185{
7a380507
ME		 2186 int pos, ttl = 48;
2187
2188 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2189 while (pos && ttl--) {
2190 u8 flags;
2191
2192 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2193 &flags) == 0)
2194 {
f0fda801 2195 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
7a380507 2196 flags & HT_MSI_FLAGS_ENABLE ?
f0fda801 2197 "enabled" : "disabled");
7a380507 2198 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 2199 }
7a380507
ME		 2200
2201 pos = pci_find_next_ht_capability(dev, pos,
2202 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 2203 }
2204 return 0;
2205}
2206
2207/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
25e742b2 2208static void quirk_msi_ht_cap(struct pci_dev *dev)
6397c75c
BG		 2209{
2210 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
f0fda801 2211 dev_warn(&dev->dev, "MSI quirk detected; "
2212 "subordinate MSI disabled\n");
6397c75c
BG		 2213 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2214 }
2215}
2216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2217 quirk_msi_ht_cap);
6bae1d96 2218
6397c75c
BG		 2219/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2220 * MSI are supported if the MSI capability set in any of these mappings.
2221 */
25e742b2 2222static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
6397c75c
BG		 2223{
2224 struct pci_dev *pdev;
2225
2226 if (!dev->subordinate)
2227 return;
2228
2229 /* check HT MSI cap on this chipset and the root one.
2230 * a single one having MSI is enough to be sure that MSI are supported.
2231 */
11f242f0 2232 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 2233 if (!pdev)
2234 return;
0c875c28 2235 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
f0fda801 2236 dev_warn(&dev->dev, "MSI quirk detected; "
2237 "subordinate MSI disabled\n");
6397c75c
BG		 2238 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2239 }
11f242f0 2240 pci_dev_put(pdev);
6397c75c
BG		 2241}
2242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2243 quirk_nvidia_ck804_msi_ht_cap);
ba698ad4 2244
415b6d0e 2245/* Force enable MSI mapping capability on HT bridges */
25e742b2 2246static void ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2247{
2248 int pos, ttl = 48;
2249
2250 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2251 while (pos && ttl--) {
2252 u8 flags;
2253
2254 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2255 &flags) == 0) {
2256 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2257
2258 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2259 flags | HT_MSI_FLAGS_ENABLE);
2260 }
2261 pos = pci_find_next_ht_capability(dev, pos,
2262 HT_CAPTYPE_MSI_MAPPING);
2263 }
2264}
415b6d0e
BH		 2265DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2266 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2267 ht_enable_msi_mapping);
9dc625e7 2268
e0ae4f55
YL		 2269DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2270 ht_enable_msi_mapping);
2271
e4146bb9 2272/* The P5N32-SLI motherboards from Asus have a problem with msi
75e07fc3
AP		 2273 * for the MCP55 NIC. It is not yet determined whether the msi problem
2274 * also affects other devices. As for now, turn off msi for this device.
2275 */
15856ad5 2276static void nvenet_msi_disable(struct pci_dev *dev)
75e07fc3 2277{
9251bac9
JD		 2278 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2279
2280 if (board_name &&
2281 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2282 strstr(board_name, "P5N32-E SLI"))) {
75e07fc3 2283 dev_info(&dev->dev,
e4146bb9 2284 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
75e07fc3
AP		 2285 dev->no_msi = 1;
2286 }
2287}
2288DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2289 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2290 nvenet_msi_disable);
2291
66db60ea
NH		 2292/*
2293 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2294 * config register. This register controls the routing of legacy interrupts
2295 * from devices that route through the MCP55. If this register is misprogramed
2296 * interrupts are only sent to the bsp, unlike conventional systems where the
2297 * irq is broadxast to all online cpus. Not having this register set
2298 * properly prevents kdump from booting up properly, so lets make sure that
2299 * we have it set correctly.
2300 * Note this is an undocumented register.
2301 */
15856ad5 2302static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
66db60ea
NH		 2303{
2304 u32 cfg;
2305
49c2fa08
NH		 2306 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2307 return;
2308
66db60ea
NH		 2309 pci_read_config_dword(dev, 0x74, &cfg);
2310
2311 if (cfg & ((1 << 2) | (1 << 15))) {
2312 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2313 cfg &= ~((1 << 2) | (1 << 15));
2314 pci_write_config_dword(dev, 0x74, cfg);
2315 }
2316}
2317
2318DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2319 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2320 nvbridge_check_legacy_irq_routing);
2321
2322DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2323 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2324 nvbridge_check_legacy_irq_routing);
2325
25e742b2 2326static int ht_check_msi_mapping(struct pci_dev *dev)
de745306
YL		 2327{
2328 int pos, ttl = 48;
2329 int found = 0;
2330
2331 /* check if there is HT MSI cap or enabled on this device */
2332 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2333 while (pos && ttl--) {
2334 u8 flags;
2335
2336 if (found < 1)
2337 found = 1;
2338 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2339 &flags) == 0) {
2340 if (flags & HT_MSI_FLAGS_ENABLE) {
2341 if (found < 2) {
2342 found = 2;
2343 break;
2344 }
2345 }
2346 }
2347 pos = pci_find_next_ht_capability(dev, pos,
2348 HT_CAPTYPE_MSI_MAPPING);
2349 }
2350
2351 return found;
2352}
2353
25e742b2 2354static int host_bridge_with_leaf(struct pci_dev *host_bridge)
de745306
YL		 2355{
2356 struct pci_dev *dev;
2357 int pos;
2358 int i, dev_no;
2359 int found = 0;
2360
2361 dev_no = host_bridge->devfn >> 3;
2362 for (i = dev_no + 1; i < 0x20; i++) {
2363 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2364 if (!dev)
2365 continue;
2366
2367 /* found next host bridge ?*/
2368 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2369 if (pos != 0) {
2370 pci_dev_put(dev);
2371 break;
2372 }
2373
2374 if (ht_check_msi_mapping(dev)) {
2375 found = 1;
2376 pci_dev_put(dev);
2377 break;
2378 }
2379 pci_dev_put(dev);
2380 }
2381
2382 return found;
2383}
2384
eeafda70
YL		 2385#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2386#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2387
25e742b2 2388static int is_end_of_ht_chain(struct pci_dev *dev)
eeafda70
YL		 2389{
2390 int pos, ctrl_off;
2391 int end = 0;
2392 u16 flags, ctrl;
2393
2394 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2395
2396 if (!pos)
2397 goto out;
2398
2399 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2400
2401 ctrl_off = ((flags >> 10) & 1) ?
2402 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2403 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2404
2405 if (ctrl & (1 << 6))
2406 end = 1;
2407
2408out:
2409 return end;
2410}
2411
25e742b2 2412static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2413{
2414 struct pci_dev *host_bridge;
1dec6b05
YL		 2415 int pos;
2416 int i, dev_no;
2417 int found = 0;
2418
2419 dev_no = dev->devfn >> 3;
2420 for (i = dev_no; i >= 0; i--) {
2421 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2422 if (!host_bridge)
2423 continue;
2424
2425 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2426 if (pos != 0) {
2427 found = 1;
2428 break;
2429 }
2430 pci_dev_put(host_bridge);
2431 }
2432
2433 if (!found)
2434 return;
2435
eeafda70
YL		 2436 /* don't enable end_device/host_bridge with leaf directly here */
2437 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2438 host_bridge_with_leaf(host_bridge))
de745306
YL		 2439 goto out;
2440
1dec6b05
YL		 2441 /* root did that ! */
2442 if (msi_ht_cap_enabled(host_bridge))
2443 goto out;
2444
2445 ht_enable_msi_mapping(dev);
2446
2447out:
2448 pci_dev_put(host_bridge);
2449}
2450
25e742b2 2451static void ht_disable_msi_mapping(struct pci_dev *dev)
1dec6b05
YL		 2452{
2453 int pos, ttl = 48;
2454
2455 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2456 while (pos && ttl--) {
2457 u8 flags;
2458
2459 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2460 &flags) == 0) {
6a958d5b 2461 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
1dec6b05
YL		 2462
2463 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2464 flags & ~HT_MSI_FLAGS_ENABLE);
2465 }
2466 pos = pci_find_next_ht_capability(dev, pos,
2467 HT_CAPTYPE_MSI_MAPPING);
2468 }
2469}
2470
25e742b2 2471static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
1dec6b05
YL		 2472{
2473 struct pci_dev *host_bridge;
2474 int pos;
2475 int found;
2476
3d2a5318
RW		 2477 if (!pci_msi_enabled())
2478 return;
2479
1dec6b05
YL		 2480 /* check if there is HT MSI cap or enabled on this device */
2481 found = ht_check_msi_mapping(dev);
2482
2483 /* no HT MSI CAP */
2484 if (found == 0)
2485 return;
9dc625e7
PC		 2486
2487 /*
2488 * HT MSI mapping should be disabled on devices that are below
2489 * a non-Hypertransport host bridge. Locate the host bridge...
2490 */
2491 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2492 if (host_bridge == NULL) {
2493 dev_warn(&dev->dev,
2494 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2495 return;
2496 }
2497
2498 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2499 if (pos != 0) {
2500 /* Host bridge is to HT */
1dec6b05
YL		 2501 if (found == 1) {
2502 /* it is not enabled, try to enable it */
de745306
YL		 2503 if (all)
2504 ht_enable_msi_mapping(dev);
2505 else
2506 nv_ht_enable_msi_mapping(dev);
1dec6b05 2507 }
dff3aef7 2508 goto out;
9dc625e7
PC		 2509 }
2510
1dec6b05
YL		 2511 /* HT MSI is not enabled */
2512 if (found == 1)
dff3aef7 2513 goto out;
9dc625e7 2514
1dec6b05
YL		 2515 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2516 ht_disable_msi_mapping(dev);
dff3aef7
MS		 2517
2518out:
2519 pci_dev_put(host_bridge);
9dc625e7 2520}
de745306 2521
25e742b2 2522static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
de745306
YL		 2523{
2524 return __nv_msi_ht_cap_quirk(dev, 1);
2525}
2526
25e742b2 2527static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
de745306
YL		 2528{
2529 return __nv_msi_ht_cap_quirk(dev, 0);
2530}
2531
2532DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
6dab62ee 2533DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
de745306
YL		 2534
2535DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
6dab62ee 2536DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
9dc625e7 2537
15856ad5 2538static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
ba698ad4
DM		 2539{
2540 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2541}
15856ad5 2542static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
4600c9d7
SH		 2543{
2544 struct pci_dev *p;
2545
2546 /* SB700 MSI issue will be fixed at HW level from revision A21,
2547 * we need check PCI REVISION ID of SMBus controller to get SB700
2548 * revision.
2549 */
2550 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2551 NULL);
2552 if (!p)
2553 return;
2554
2555 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2556 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2557 pci_dev_put(p);
2558}
70588818
XH		 2559static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2560{
2561 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2562 if (dev->revision < 0x18) {
2563 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2564 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2565 }
2566}
ba698ad4
DM		 2567DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2568 PCI_DEVICE_ID_TIGON3_5780,
2569 quirk_msi_intx_disable_bug);
2570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2571 PCI_DEVICE_ID_TIGON3_5780S,
2572 quirk_msi_intx_disable_bug);
2573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2574 PCI_DEVICE_ID_TIGON3_5714,
2575 quirk_msi_intx_disable_bug);
2576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2577 PCI_DEVICE_ID_TIGON3_5714S,
2578 quirk_msi_intx_disable_bug);
2579DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2580 PCI_DEVICE_ID_TIGON3_5715,
2581 quirk_msi_intx_disable_bug);
2582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2583 PCI_DEVICE_ID_TIGON3_5715S,
2584 quirk_msi_intx_disable_bug);
2585
bc38b411 2586DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
4600c9d7 2587 quirk_msi_intx_disable_ati_bug);
bc38b411 2588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
4600c9d7 2589 quirk_msi_intx_disable_ati_bug);
bc38b411 2590DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
4600c9d7 2591 quirk_msi_intx_disable_ati_bug);
bc38b411 2592DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
4600c9d7 2593 quirk_msi_intx_disable_ati_bug);
bc38b411 2594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
4600c9d7 2595 quirk_msi_intx_disable_ati_bug);
bc38b411
DM		 2596
2597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2598 quirk_msi_intx_disable_bug);
2599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2600 quirk_msi_intx_disable_bug);
2601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2602 quirk_msi_intx_disable_bug);
2603
7cb6a291
HX		 2604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2605 quirk_msi_intx_disable_bug);
2606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2607 quirk_msi_intx_disable_bug);
2608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2609 quirk_msi_intx_disable_bug);
2610DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2611 quirk_msi_intx_disable_bug);
2612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2613 quirk_msi_intx_disable_bug);
2614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2615 quirk_msi_intx_disable_bug);
70588818
XH		 2616DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2617 quirk_msi_intx_disable_qca_bug);
2618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2619 quirk_msi_intx_disable_qca_bug);
2620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2621 quirk_msi_intx_disable_qca_bug);
2622DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2623 quirk_msi_intx_disable_qca_bug);
2624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2625 quirk_msi_intx_disable_qca_bug);
3f79e107 2626#endif /* CONFIG_PCI_MSI */
3d137310 2627
3322340a
FR		 2628/* Allow manual resource allocation for PCI hotplug bridges
2629 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2630 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2631 * kernel fails to allocate resources when hotplug device is
2632 * inserted and PCI bus is rescanned.
2633 */
15856ad5 2634static void quirk_hotplug_bridge(struct pci_dev *dev)
3322340a
FR		 2635{
2636 dev->is_hotplug_bridge = 1;
2637}
2638
2639DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2640
03cd8f7e
ML		 2641/*
2642 * This is a quirk for the Ricoh MMC controller found as a part of
2643 * some mulifunction chips.
2644
25985edc 2645 * This is very similar and based on the ricoh_mmc driver written by
03cd8f7e
ML		 2646 * Philip Langdale. Thank you for these magic sequences.
2647 *
2648 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2649 * and one or both of cardbus or firewire.
2650 *
2651 * It happens that they implement SD and MMC
2652 * support as separate controllers (and PCI functions). The linux SDHCI
2653 * driver supports MMC cards but the chip detects MMC cards in hardware
2654 * and directs them to the MMC controller - so the SDHCI driver never sees
2655 * them.
2656 *
2657 * To get around this, we must disable the useless MMC controller.
2658 * At that point, the SDHCI controller will start seeing them
2659 * It seems to be the case that the relevant PCI registers to deactivate the
2660 * MMC controller live on PCI function 0, which might be the cardbus controller
2661 * or the firewire controller, depending on the particular chip in question
2662 *
2663 * This has to be done early, because as soon as we disable the MMC controller
2664 * other pci functions shift up one level, e.g. function #2 becomes function
2665 * #1, and this will confuse the pci core.
2666 */
2667
2668#ifdef CONFIG_MMC_RICOH_MMC
2669static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2670{
2671 /* disable via cardbus interface */
2672 u8 write_enable;
2673 u8 write_target;
2674 u8 disable;
2675
2676 /* disable must be done via function #0 */
2677 if (PCI_FUNC(dev->devfn))
2678 return;
2679
2680 pci_read_config_byte(dev, 0xB7, &disable);
2681 if (disable & 0x02)
2682 return;
2683
2684 pci_read_config_byte(dev, 0x8E, &write_enable);
2685 pci_write_config_byte(dev, 0x8E, 0xAA);
2686 pci_read_config_byte(dev, 0x8D, &write_target);
2687 pci_write_config_byte(dev, 0x8D, 0xB7);
2688 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2689 pci_write_config_byte(dev, 0x8E, write_enable);
2690 pci_write_config_byte(dev, 0x8D, write_target);
2691
2692 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2693 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2694}
2695DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2696DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2697
2698static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2699{
2700 /* disable via firewire interface */
2701 u8 write_enable;
2702 u8 disable;
2703
2704 /* disable must be done via function #0 */
2705 if (PCI_FUNC(dev->devfn))
2706 return;
15bed0f2 2707 /*
812089e0 2708 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
15bed0f2
MI		 2709 * certain types of SD/MMC cards. Lowering the SD base
2710 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2711 *
2712 * 0x150 - SD2.0 mode enable for changing base clock
2713 * frequency to 50Mhz
2714 * 0xe1 - Base clock frequency
2715 * 0x32 - 50Mhz new clock frequency
2716 * 0xf9 - Key register for 0x150
2717 * 0xfc - key register for 0xe1
2718 */
812089e0
AL		 2719 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2720 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
15bed0f2
MI		 2721 pci_write_config_byte(dev, 0xf9, 0xfc);
2722 pci_write_config_byte(dev, 0x150, 0x10);
2723 pci_write_config_byte(dev, 0xf9, 0x00);
2724 pci_write_config_byte(dev, 0xfc, 0x01);
2725 pci_write_config_byte(dev, 0xe1, 0x32);
2726 pci_write_config_byte(dev, 0xfc, 0x00);
2727
2728 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2729 }
3e309cdf
JB		 2730
2731 pci_read_config_byte(dev, 0xCB, &disable);
2732
2733 if (disable & 0x02)
2734 return;
2735
2736 pci_read_config_byte(dev, 0xCA, &write_enable);
2737 pci_write_config_byte(dev, 0xCA, 0x57);
2738 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2739 pci_write_config_byte(dev, 0xCA, write_enable);
2740
2741 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2742 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2743
03cd8f7e
ML		 2744}
2745DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2746DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
812089e0
AL		 2747DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2748DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
be98ca65
MI		 2749DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2750DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
03cd8f7e
ML		 2751#endif /*CONFIG_MMC_RICOH_MMC*/
2752
d3f13810 2753#ifdef CONFIG_DMAR_TABLE
254e4200
SS		 2754#define VTUNCERRMSK_REG 0x1ac
2755#define VTD_MSK_SPEC_ERRORS (1 << 31)
2756/*
2757 * This is a quirk for masking vt-d spec defined errors to platform error
2758 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2759 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2760 * on the RAS config settings of the platform) when a vt-d fault happens.
2761 * The resulting SMI caused the system to hang.
2762 *
2763 * VT-d spec related errors are already handled by the VT-d OS code, so no
2764 * need to report the same error through other channels.
2765 */
2766static void vtd_mask_spec_errors(struct pci_dev *dev)
2767{
2768 u32 word;
2769
2770 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2771 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2772}
2773DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2774DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2775#endif
03cd8f7e 2776
15856ad5 2777static void fixup_ti816x_class(struct pci_dev *dev)
63c44080
HP		 2778{
2779 /* TI 816x devices do not have class code set when in PCIe boot mode */
40c96236
YL		 2780 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2781 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
63c44080 2782}
40c96236
YL		 2783DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2784 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
63c44080 2785
a94d072b
BH		 2786/* Some PCIe devices do not work reliably with the claimed maximum
2787 * payload size supported.
2788 */
15856ad5 2789static void fixup_mpss_256(struct pci_dev *dev)
a94d072b
BH		 2790{
2791 dev->pcie_mpss = 1; /* 256 bytes */
2792}
2793DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2794 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2795DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2796 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2797DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2798 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2799
d387a8d6
JM		 2800/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2801 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2802 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2803 * until all of the devices are discovered and buses walked, read completion
2804 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2805 * it is possible to hotplug a device with MPS of 256B.
2806 */
15856ad5 2807static void quirk_intel_mc_errata(struct pci_dev *dev)
d387a8d6
JM		 2808{
2809 int err;
2810 u16 rcc;
2811
2812 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2813 return;
2814
2815 /* Intel errata specifies bits to change but does not say what they are.
2816 * Keeping them magical until such time as the registers and values can
2817 * be explained.
2818 */
2819 err = pci_read_config_word(dev, 0x48, &rcc);
2820 if (err) {
2821 dev_err(&dev->dev, "Error attempting to read the read "
2822 "completion coalescing register.\n");
2823 return;
2824 }
2825
2826 if (!(rcc & (1 << 10)))
2827 return;
2828
2829 rcc &= ~(1 << 10);
2830
2831 err = pci_write_config_word(dev, 0x48, rcc);
2832 if (err) {
2833 dev_err(&dev->dev, "Error attempting to write the read "
2834 "completion coalescing register.\n");
2835 return;
2836 }
2837
2838 pr_info_once("Read completion coalescing disabled due to hardware "
2839 "errata relating to 256B MPS.\n");
2840}
2841/* Intel 5000 series memory controllers and ports 2-7 */
2842DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2843DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2844DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2845DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2846DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2847DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2848DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2849DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2850DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2851DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2852DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2853DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2854DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2855DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2856/* Intel 5100 series memory controllers and ports 2-7 */
2857DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2858DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2859DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2860DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2861DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2862DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2863DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2864DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2865DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2866DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2867DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2868
3209874a 2869
2729d5b1
MS		 2870static ktime_t fixup_debug_start(struct pci_dev *dev,
2871 void (*fn)(struct pci_dev *dev))
3209874a 2872{
2729d5b1
MS		 2873 ktime_t calltime = ktime_set(0, 0);
2874
2875 dev_dbg(&dev->dev, "calling %pF\n", fn);
2876 if (initcall_debug) {
2877 pr_debug("calling %pF @ %i for %s\n",
2878 fn, task_pid_nr(current), dev_name(&dev->dev));
2879 calltime = ktime_get();
2880 }
2881
2882 return calltime;
2883}
2884
2885static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2886 void (*fn)(struct pci_dev *dev))
3209874a 2887{
2729d5b1 2888 ktime_t delta, rettime;
3209874a
AV		 2889 unsigned long long duration;
2890
2729d5b1
MS		 2891 if (initcall_debug) {
2892 rettime = ktime_get();
2893 delta = ktime_sub(rettime, calltime);
2894 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2895 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
2896 fn, duration, dev_name(&dev->dev));
2897 }
3209874a
AV		 2898}
2899
f67fd55f
TJ		 2900/*
2901 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2902 * even though no one is handling them (f.e. i915 driver is never loaded).
2903 * Additionally the interrupt destination is not set up properly
2904 * and the interrupt ends up -somewhere-.
2905 *
2906 * These spurious interrupts are "sticky" and the kernel disables
2907 * the (shared) interrupt line after 100.000+ generated interrupts.
2908 *
2909 * Fix it by disabling the still enabled interrupts.
2910 * This resolves crashes often seen on monitor unplug.
2911 */
2912#define I915_DEIER_REG 0x4400c
15856ad5 2913static void disable_igfx_irq(struct pci_dev *dev)
f67fd55f
TJ		 2914{
2915 void __iomem *regs = pci_iomap(dev, 0, 0);
2916 if (regs == NULL) {
2917 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2918 return;
2919 }
2920
2921 /* Check if any interrupt line is still enabled */
2922 if (readl(regs + I915_DEIER_REG) != 0) {
2923 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2924 "disabling\n");
2925
2926 writel(0, regs + I915_DEIER_REG);
2927 }
2928
2929 pci_iounmap(dev, regs);
2930}
2931DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2932DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
ce914633 2933DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
f67fd55f 2934
fbebb9fd
BH		 2935/*
2936 * Some devices may pass our check in pci_intx_mask_supported if
2937 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
2938 * support this feature.
2939 */
15856ad5 2940static void quirk_broken_intx_masking(struct pci_dev *dev)
fbebb9fd
BH		 2941{
2942 dev->broken_intx_masking = 1;
2943}
de509f9f
JK		 2944DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
2945 quirk_broken_intx_masking);
0bdb3b21
AW		 2946DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
2947 quirk_broken_intx_masking);
fbebb9fd 2948
bfb0f330
JB		 2949static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2950 struct pci_fixup *end)
3d137310 2951{
2729d5b1
MS		 2952 ktime_t calltime;
2953
f4ca5c6a
YL		 2954 for (; f < end; f++)
2955 if ((f->class == (u32) (dev->class >> f->class_shift) ||
2956 f->class == (u32) PCI_ANY_ID) &&
2957 (f->vendor == dev->vendor ||
2958 f->vendor == (u16) PCI_ANY_ID) &&
2959 (f->device == dev->device ||
2960 f->device == (u16) PCI_ANY_ID)) {
2729d5b1
MS		 2961 calltime = fixup_debug_start(dev, f->hook);
2962 f->hook(dev);
2963 fixup_debug_report(dev, calltime, f->hook);
3d137310 2964 }
3d137310
TP		 2965}
2966
2967extern struct pci_fixup __start_pci_fixups_early[];
2968extern struct pci_fixup __end_pci_fixups_early[];
2969extern struct pci_fixup __start_pci_fixups_header[];
2970extern struct pci_fixup __end_pci_fixups_header[];
2971extern struct pci_fixup __start_pci_fixups_final[];
2972extern struct pci_fixup __end_pci_fixups_final[];
2973extern struct pci_fixup __start_pci_fixups_enable[];
2974extern struct pci_fixup __end_pci_fixups_enable[];
2975extern struct pci_fixup __start_pci_fixups_resume[];
2976extern struct pci_fixup __end_pci_fixups_resume[];
2977extern struct pci_fixup __start_pci_fixups_resume_early[];
2978extern struct pci_fixup __end_pci_fixups_resume_early[];
2979extern struct pci_fixup __start_pci_fixups_suspend[];
2980extern struct pci_fixup __end_pci_fixups_suspend[];
2981
95df8b87 2982static bool pci_apply_fixup_final_quirks;
3d137310
TP		 2983
2984void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2985{
2986 struct pci_fixup *start, *end;
2987
2988 switch(pass) {
2989 case pci_fixup_early:
2990 start = __start_pci_fixups_early;
2991 end = __end_pci_fixups_early;
2992 break;
2993
2994 case pci_fixup_header:
2995 start = __start_pci_fixups_header;
2996 end = __end_pci_fixups_header;
2997 break;
2998
2999 case pci_fixup_final:
95df8b87
MS		 3000 if (!pci_apply_fixup_final_quirks)
3001 return;
3d137310
TP		 3002 start = __start_pci_fixups_final;
3003 end = __end_pci_fixups_final;
3004 break;
3005
3006 case pci_fixup_enable:
3007 start = __start_pci_fixups_enable;
3008 end = __end_pci_fixups_enable;
3009 break;
3010
3011 case pci_fixup_resume:
3012 start = __start_pci_fixups_resume;
3013 end = __end_pci_fixups_resume;
3014 break;
3015
3016 case pci_fixup_resume_early:
3017 start = __start_pci_fixups_resume_early;
3018 end = __end_pci_fixups_resume_early;
3019 break;
3020
3021 case pci_fixup_suspend:
3022 start = __start_pci_fixups_suspend;
3023 end = __end_pci_fixups_suspend;
3024 break;
3025
3026 default:
3027 /* stupid compiler warning, you would think with an enum... */
3028 return;
3029 }
3030 pci_do_fixups(dev, start, end);
3031}
93177a74 3032EXPORT_SYMBOL(pci_fixup_device);
8d86fb2c 3033
735bff10 3034
00010268 3035static int __init pci_apply_final_quirks(void)
8d86fb2c
DW		 3036{
3037 struct pci_dev *dev = NULL;
ac1aa47b
JB		 3038 u8 cls = 0;
3039 u8 tmp;
3040
3041 if (pci_cache_line_size)
3042 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3043 pci_cache_line_size << 2);
8d86fb2c 3044
95df8b87 3045 pci_apply_fixup_final_quirks = true;
4e344b1c 3046 for_each_pci_dev(dev) {
8d86fb2c 3047 pci_fixup_device(pci_fixup_final, dev);
ac1aa47b
JB		 3048 /*
3049 * If arch hasn't set it explicitly yet, use the CLS
3050 * value shared by all PCI devices. If there's a
3051 * mismatch, fall back to the default value.
3052 */
3053 if (!pci_cache_line_size) {
3054 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3055 if (!cls)
3056 cls = tmp;
3057 if (!tmp || cls == tmp)
3058 continue;
3059
3060 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3061 "using %u bytes\n", cls << 2, tmp << 2,
3062 pci_dfl_cache_line_size << 2);
3063 pci_cache_line_size = pci_dfl_cache_line_size;
3064 }
3065 }
735bff10 3066
ac1aa47b
JB		 3067 if (!pci_cache_line_size) {
3068 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3069 cls << 2, pci_dfl_cache_line_size << 2);
2820f333 3070 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
8d86fb2c
DW		 3071 }
3072
3073 return 0;
3074}
3075
cf6f3bf7 3076fs_initcall_sync(pci_apply_final_quirks);
b9c3b266
DC		 3077
3078/*
3079 * Followings are device-specific reset methods which can be used to
3080 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3081 * not available.
3082 */
aeb30016
DC		 3083static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3084{
3085 int pos;
3086
3087 /* only implement PCI_CLASS_SERIAL_USB at present */
3088 if (dev->class == PCI_CLASS_SERIAL_USB) {
3089 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3090 if (!pos)
3091 return -ENOTTY;
3092
3093 if (probe)
3094 return 0;
3095
3096 pci_write_config_byte(dev, pos + 0x4, 1);
3097 msleep(100);
3098
3099 return 0;
3100 } else {
3101 return -ENOTTY;
3102 }
3103}
3104
c763e7b5
DC		 3105static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3106{
76b57c67
BH		 3107 int i;
3108 u16 status;
3109
3110 /*
3111 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3112 *
3113 * The 82599 supports FLR on VFs, but FLR support is reported only
3114 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3115 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3116 */
3117
c763e7b5
DC		 3118 if (probe)
3119 return 0;
3120
76b57c67
BH		 3121 /* Wait for Transaction Pending bit clean */
3122 for (i = 0; i < 4; i++) {
3123 if (i)
3124 msleep((1 << (i - 1)) * 100);
3125
3126 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3127 if (!(status & PCI_EXP_DEVSTA_TRPND))
3128 goto clear;
3129 }
3130
3131 dev_err(&dev->dev, "transaction is not cleared; "
3132 "proceeding with reset anyway\n");
3133
3134clear:
3135 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3136
c763e7b5
DC		 3137 msleep(100);
3138
3139 return 0;
3140}
3141
df558de1
XH		 3142#include "../gpu/drm/i915/i915_reg.h"
3143#define MSG_CTL 0x45010
3144#define NSDE_PWR_STATE 0xd0100
3145#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3146
3147static int reset_ivb_igd(struct pci_dev *dev, int probe)
3148{
3149 void __iomem *mmio_base;
3150 unsigned long timeout;
3151 u32 val;
3152
3153 if (probe)
3154 return 0;
3155
3156 mmio_base = pci_iomap(dev, 0, 0);
3157 if (!mmio_base)
3158 return -ENOMEM;
3159
3160 iowrite32(0x00000002, mmio_base + MSG_CTL);
3161
3162 /*
3163 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3164 * driver loaded sets the right bits. However, this's a reset and
3165 * the bits have been set by i915 previously, so we clobber
3166 * SOUTH_CHICKEN2 register directly here.
3167 */
3168 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3169
3170 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3171 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3172
3173 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3174 do {
3175 val = ioread32(mmio_base + PCH_PP_STATUS);
3176 if ((val & 0xb0000000) == 0)
3177 goto reset_complete;
3178 msleep(10);
3179 } while (time_before(jiffies, timeout));
3180 dev_warn(&dev->dev, "timeout during reset\n");
3181
3182reset_complete:
3183 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3184
3185 pci_iounmap(dev, mmio_base);
3186 return 0;
3187}
3188
c763e7b5 3189#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
df558de1
XH		 3190#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3191#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
c763e7b5 3192
5b889bf2 3193static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
c763e7b5
DC		 3194 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3195 reset_intel_82599_sfp_virtfn },
df558de1
XH		 3196 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3197 reset_ivb_igd },
3198 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3199 reset_ivb_igd },
aeb30016
DC		 3200 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3201 reset_intel_generic_dev },
b9c3b266
DC		 3202 { 0 }
3203};
5b889bf2 3204
df558de1
XH		 3205/*
3206 * These device-specific reset methods are here rather than in a driver
3207 * because when a host assigns a device to a guest VM, the host may need
3208 * to reset the device but probably doesn't have a driver for it.
3209 */
5b889bf2
RW		 3210int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3211{
df9d1e8a 3212 const struct pci_dev_reset_methods *i;
5b889bf2
RW		 3213
3214 for (i = pci_dev_reset_methods; i->reset; i++) {
3215 if ((i->vendor == dev->vendor ||
3216 i->vendor == (u16)PCI_ANY_ID) &&
3217 (i->device == dev->device ||
3218 i->device == (u16)PCI_ANY_ID))
3219 return i->reset(dev, probe);
3220 }
3221
3222 return -ENOTTY;
3223}
12ea6cad
AW		 3224
3225static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
3226{
3227 if (!PCI_FUNC(dev->devfn))
3228 return pci_dev_get(dev);
3229
3230 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3231}
3232
3233static const struct pci_dev_dma_source {
3234 u16 vendor;
3235 u16 device;
3236 struct pci_dev *(*dma_source)(struct pci_dev *dev);
3237} pci_dev_dma_source[] = {
3238 /*
3239 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3240 *
3241 * Some Ricoh devices use the function 0 source ID for DMA on
3242 * other functions of a multifunction device. The DMA devices
3243 * is therefore function 0, which will have implications of the
3244 * iommu grouping of these devices.
3245 */
3246 { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
3247 { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
3248 { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
3249 { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
3250 { 0 }
3251};
3252
3253/*
3254 * IOMMUs with isolation capabilities need to be programmed with the
3255 * correct source ID of a device. In most cases, the source ID matches
3256 * the device doing the DMA, but sometimes hardware is broken and will
3257 * tag the DMA as being sourced from a different device. This function
3258 * allows that translation. Note that the reference count of the
3259 * returned device is incremented on all paths.
3260 */
3261struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
3262{
3263 const struct pci_dev_dma_source *i;
3264
3265 for (i = pci_dev_dma_source; i->dma_source; i++) {
3266 if ((i->vendor == dev->vendor ||
3267 i->vendor == (u16)PCI_ANY_ID) &&
3268 (i->device == dev->device ||
3269 i->device == (u16)PCI_ANY_ID))
3270 return i->dma_source(dev);
3271 }
3272
3273 return pci_dev_get(dev);
3274}
ad805758
AW		 3275
3276static const struct pci_dev_acs_enabled {
3277 u16 vendor;
3278 u16 device;
3279 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3280} pci_dev_acs_enabled[] = {
3281 { 0 }
3282};
3283
3284int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3285{
3286 const struct pci_dev_acs_enabled *i;
3287 int ret;
3288
3289 /*
3290 * Allow devices that do not expose standard PCIe ACS capabilities
3291 * or control to indicate their support here. Multi-function express
3292 * devices which do not allow internal peer-to-peer between functions,
3293 * but do not implement PCIe ACS may wish to return true here.
3294 */
3295 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3296 if ((i->vendor == dev->vendor ||
3297 i->vendor == (u16)PCI_ANY_ID) &&
3298 (i->device == dev->device ||
3299 i->device == (u16)PCI_ANY_ID)) {
3300 ret = i->acs_enabled(dev, acs_flags);
3301 if (ret >= 0)
3302 return ret;
3303 }
3304 }
3305
3306 return -ENOTTY;
3307}
kernel source for telekom puls (alcatel/mediatek)