projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'v3.10.76' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
075c1771 14#include <linux/pm.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <linux/module.h>
17#include <linux/spinlock.h>
4e57b681 18#include <linux/string.h>
229f5afd 19#include <linux/log2.h>
7d715a6c 20#include <linux/pci-aspm.h>
c300bd2f 21#include <linux/pm_wakeup.h>
8dd7f803 22#include <linux/interrupt.h>
32a9a682 23#include <linux/device.h>
b67ea761 24#include <linux/pm_runtime.h>
284f5f9d 25#include <asm-generic/pci-bridge.h>
32a9a682 26#include <asm/setup.h>
bc56b9e0 27#include "pci.h"
1da177e4 28
00240c38
AS		 29const char *pci_power_names[] = {
30 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31};
32EXPORT_SYMBOL_GPL(pci_power_names);
33
93177a74
RW		 34int isa_dma_bridge_buggy;
35EXPORT_SYMBOL(isa_dma_bridge_buggy);
36
37int pci_pci_problems;
38EXPORT_SYMBOL(pci_pci_problems);
39
1ae861e6
RW		 40unsigned int pci_pm_d3_delay;
41
df17e62e
MG		 42static void pci_pme_list_scan(struct work_struct *work);
43
44static LIST_HEAD(pci_pme_list);
45static DEFINE_MUTEX(pci_pme_list_mutex);
46static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
47
48struct pci_pme_device {
49 struct list_head list;
50 struct pci_dev *dev;
51};
52
53#define PME_TIMEOUT 1000 /* How long between PME checks */
54
1ae861e6
RW		 55static void pci_dev_d3_sleep(struct pci_dev *dev)
56{
57 unsigned int delay = dev->d3_delay;
58
59 if (delay < pci_pm_d3_delay)
60 delay = pci_pm_d3_delay;
61
62 msleep(delay);
63}
1da177e4 64
32a2eea7
JG		 65#ifdef CONFIG_PCI_DOMAINS
66int pci_domains_supported = 1;
67#endif
68
4516a618
AN		 69#define DEFAULT_CARDBUS_IO_SIZE (256)
70#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
71/* pci=cbmemsize=nnM,cbiosize=nn can override this */
72unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
73unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
74
28760489
EB		 75#define DEFAULT_HOTPLUG_IO_SIZE (256)
76#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
77/* pci=hpmemsize=nnM,hpiosize=nn can override this */
78unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
79unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
80
5f39e670 81enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
b03e7495 82
ac1aa47b
JB		 83/*
84 * The default CLS is used if arch didn't set CLS explicitly and not
85 * all pci devices agree on the same value. Arch can override either
86 * the dfl or actual value as it sees fit. Don't forget this is
87 * measured in 32-bit words, not bytes.
88 */
15856ad5 89u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
ac1aa47b
JB		 90u8 pci_cache_line_size;
91
96c55900
MS		 92/*
93 * If we set up a device for bus mastering, we need to check the latency
94 * timer as certain BIOSes forget to set it properly.
95 */
96unsigned int pcibios_max_latency = 255;
97
6748dcc2
RW		 98/* If set, the PCIe ARI capability will not be used. */
99static bool pcie_ari_disabled;
100
1da177e4
LT		 101/**
102 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
103 * @bus: pointer to PCI bus structure to search
104 *
105 * Given a PCI bus, returns the highest PCI bus number present in the set
106 * including the given PCI bus and its list of child PCI buses.
107 */
96bde06a 108unsigned char pci_bus_max_busnr(struct pci_bus* bus)
1da177e4
LT		 109{
110 struct list_head *tmp;
111 unsigned char max, n;
112
b918c62e 113 max = bus->busn_res.end;
1da177e4
LT		 114 list_for_each(tmp, &bus->children) {
115 n = pci_bus_max_busnr(pci_bus_b(tmp));
116 if(n > max)
117 max = n;
118 }
119 return max;
120}
b82db5ce 121EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
1da177e4 122
1684f5dd
AM		 123#ifdef CONFIG_HAS_IOMEM
124void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
125{
126 /*
127 * Make sure the BAR is actually a memory resource, not an IO resource
128 */
129 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
130 WARN_ON(1);
131 return NULL;
132 }
133 return ioremap_nocache(pci_resource_start(pdev, bar),
134 pci_resource_len(pdev, bar));
135}
136EXPORT_SYMBOL_GPL(pci_ioremap_bar);
137#endif
138
687d5fe3
ME		 139#define PCI_FIND_CAP_TTL 48
140
141static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
142 u8 pos, int cap, int *ttl)
24a4e377
RD		 143{
144 u8 id;
24a4e377 145
687d5fe3 146 while ((*ttl)--) {
24a4e377
RD		 147 pci_bus_read_config_byte(bus, devfn, pos, &pos);
148 if (pos < 0x40)
149 break;
150 pos &= ~3;
151 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
152 &id);
153 if (id == 0xff)
154 break;
155 if (id == cap)
156 return pos;
157 pos += PCI_CAP_LIST_NEXT;
158 }
159 return 0;
160}
161
687d5fe3
ME		 162static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
163 u8 pos, int cap)
164{
165 int ttl = PCI_FIND_CAP_TTL;
166
167 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
168}
169
24a4e377
RD		 170int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
171{
172 return __pci_find_next_cap(dev->bus, dev->devfn,
173 pos + PCI_CAP_LIST_NEXT, cap);
174}
175EXPORT_SYMBOL_GPL(pci_find_next_capability);
176
d3bac118
ME		 177static int __pci_bus_find_cap_start(struct pci_bus *bus,
178 unsigned int devfn, u8 hdr_type)
1da177e4
LT		 179{
180 u16 status;
1da177e4
LT		 181
182 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
183 if (!(status & PCI_STATUS_CAP_LIST))
184 return 0;
185
186 switch (hdr_type) {
187 case PCI_HEADER_TYPE_NORMAL:
188 case PCI_HEADER_TYPE_BRIDGE:
d3bac118 189 return PCI_CAPABILITY_LIST;
1da177e4 190 case PCI_HEADER_TYPE_CARDBUS:
d3bac118 191 return PCI_CB_CAPABILITY_LIST;
1da177e4
LT		 192 default:
193 return 0;
194 }
d3bac118
ME		 195
196 return 0;
1da177e4
LT		 197}
198
199/**
200 * pci_find_capability - query for devices' capabilities
201 * @dev: PCI device to query
202 * @cap: capability code
203 *
204 * Tell if a device supports a given PCI capability.
205 * Returns the address of the requested capability structure within the
206 * device's PCI configuration space or 0 in case the device does not
207 * support it. Possible values for @cap:
208 *
209 * %PCI_CAP_ID_PM Power Management
210 * %PCI_CAP_ID_AGP Accelerated Graphics Port
211 * %PCI_CAP_ID_VPD Vital Product Data
212 * %PCI_CAP_ID_SLOTID Slot Identification
213 * %PCI_CAP_ID_MSI Message Signalled Interrupts
214 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
215 * %PCI_CAP_ID_PCIX PCI-X
216 * %PCI_CAP_ID_EXP PCI Express
217 */
218int pci_find_capability(struct pci_dev *dev, int cap)
219{
d3bac118
ME		 220 int pos;
221
222 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
223 if (pos)
224 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
225
226 return pos;
1da177e4
LT		 227}
228
229/**
230 * pci_bus_find_capability - query for devices' capabilities
231 * @bus: the PCI bus to query
232 * @devfn: PCI device to query
233 * @cap: capability code
234 *
235 * Like pci_find_capability() but works for pci devices that do not have a
236 * pci_dev structure set up yet.
237 *
238 * Returns the address of the requested capability structure within the
239 * device's PCI configuration space or 0 in case the device does not
240 * support it.
241 */
242int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
243{
d3bac118 244 int pos;
1da177e4
LT		 245 u8 hdr_type;
246
247 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
248
d3bac118
ME		 249 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
250 if (pos)
251 pos = __pci_find_next_cap(bus, devfn, pos, cap);
252
253 return pos;
1da177e4
LT		 254}
255
256/**
44a9a36f 257 * pci_find_next_ext_capability - Find an extended capability
1da177e4 258 * @dev: PCI device to query
44a9a36f 259 * @start: address at which to start looking (0 to start at beginning of list)
1da177e4
LT		 260 * @cap: capability code
261 *
44a9a36f 262 * Returns the address of the next matching extended capability structure
1da177e4 263 * within the device's PCI configuration space or 0 if the device does
44a9a36f
BH		 264 * not support it. Some capabilities can occur several times, e.g., the
265 * vendor-specific capability, and this provides a way to find them all.
1da177e4 266 */
44a9a36f 267int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
1da177e4
LT		 268{
269 u32 header;
557848c3
ZY		 270 int ttl;
271 int pos = PCI_CFG_SPACE_SIZE;
1da177e4 272
557848c3
ZY		 273 /* minimum 8 bytes per capability */
274 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
275
276 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
1da177e4
LT		 277 return 0;
278
44a9a36f
BH		 279 if (start)
280 pos = start;
281
1da177e4
LT		 282 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
283 return 0;
284
285 /*
286 * If we have no capabilities, this is indicated by cap ID,
287 * cap version and next pointer all being 0.
288 */
289 if (header == 0)
290 return 0;
291
292 while (ttl-- > 0) {
44a9a36f 293 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
1da177e4
LT		 294 return pos;
295
296 pos = PCI_EXT_CAP_NEXT(header);
557848c3 297 if (pos < PCI_CFG_SPACE_SIZE)
1da177e4
LT		 298 break;
299
300 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
301 break;
302 }
303
304 return 0;
305}
44a9a36f
BH		 306EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
307
308/**
309 * pci_find_ext_capability - Find an extended capability
310 * @dev: PCI device to query
311 * @cap: capability code
312 *
313 * Returns the address of the requested extended capability structure
314 * within the device's PCI configuration space or 0 if the device does
315 * not support it. Possible values for @cap:
316 *
317 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
318 * %PCI_EXT_CAP_ID_VC Virtual Channel
319 * %PCI_EXT_CAP_ID_DSN Device Serial Number
320 * %PCI_EXT_CAP_ID_PWR Power Budgeting
321 */
322int pci_find_ext_capability(struct pci_dev *dev, int cap)
323{
324 return pci_find_next_ext_capability(dev, 0, cap);
325}
3a720d72 326EXPORT_SYMBOL_GPL(pci_find_ext_capability);
1da177e4 327
687d5fe3
ME		 328static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
329{
330 int rc, ttl = PCI_FIND_CAP_TTL;
331 u8 cap, mask;
332
333 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
334 mask = HT_3BIT_CAP_MASK;
335 else
336 mask = HT_5BIT_CAP_MASK;
337
338 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
339 PCI_CAP_ID_HT, &ttl);
340 while (pos) {
341 rc = pci_read_config_byte(dev, pos + 3, &cap);
342 if (rc != PCIBIOS_SUCCESSFUL)
343 return 0;
344
345 if ((cap & mask) == ht_cap)
346 return pos;
347
47a4d5be
BG		 348 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
349 pos + PCI_CAP_LIST_NEXT,
687d5fe3
ME		 350 PCI_CAP_ID_HT, &ttl);
351 }
352
353 return 0;
354}
355/**
356 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
357 * @dev: PCI device to query
358 * @pos: Position from which to continue searching
359 * @ht_cap: Hypertransport capability code
360 *
361 * To be used in conjunction with pci_find_ht_capability() to search for
362 * all capabilities matching @ht_cap. @pos should always be a value returned
363 * from pci_find_ht_capability().
364 *
365 * NB. To be 100% safe against broken PCI devices, the caller should take
366 * steps to avoid an infinite loop.
367 */
368int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
369{
370 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
371}
372EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
373
374/**
375 * pci_find_ht_capability - query a device's Hypertransport capabilities
376 * @dev: PCI device to query
377 * @ht_cap: Hypertransport capability code
378 *
379 * Tell if a device supports a given Hypertransport capability.
380 * Returns an address within the device's PCI configuration space
381 * or 0 in case the device does not support the request capability.
382 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
383 * which has a Hypertransport capability matching @ht_cap.
384 */
385int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
386{
387 int pos;
388
389 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
390 if (pos)
391 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
392
393 return pos;
394}
395EXPORT_SYMBOL_GPL(pci_find_ht_capability);
396
1da177e4
LT		 397/**
398 * pci_find_parent_resource - return resource region of parent bus of given region
399 * @dev: PCI device structure contains resources to be searched
400 * @res: child resource record for which parent is sought
401 *
402 * For given resource region of given device, return the resource
403 * region of parent bus the given region is contained in or where
404 * it should be allocated from.
405 */
406struct resource *
407pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
408{
409 const struct pci_bus *bus = dev->bus;
410 int i;
89a74ecc 411 struct resource *best = NULL, *r;
1da177e4 412
89a74ecc 413 pci_bus_for_each_resource(bus, r, i) {
1da177e4
LT		 414 if (!r)
415 continue;
416 if (res->start && !(res->start >= r->start && res->end <= r->end))
417 continue; /* Not contained */
418 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
419 continue; /* Wrong type */
420 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
421 return r; /* Exact match */
8c8def26
LT		 422 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
423 if (r->flags & IORESOURCE_PREFETCH)
424 continue;
425 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
426 if (!best)
427 best = r;
1da177e4
LT		 428 }
429 return best;
430}
431
064b53db
JL		 432/**
433 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
434 * @dev: PCI device to have its BARs restored
435 *
436 * Restore the BAR values for a given device, so as to make it
437 * accessible by its driver.
438 */
ad668599 439static void
064b53db
JL		 440pci_restore_bars(struct pci_dev *dev)
441{
bc5f5a82 442 int i;
064b53db 443
bc5f5a82 444 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
14add80b 445 pci_update_resource(dev, i);
064b53db
JL		 446}
447
961d9120
RW		 448static struct pci_platform_pm_ops *pci_platform_pm;
449
450int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
451{
eb9d0fe4 452 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
d2e5f0c1 453 || !ops->sleep_wake)
961d9120
RW		 454 return -EINVAL;
455 pci_platform_pm = ops;
456 return 0;
457}
458
459static inline bool platform_pci_power_manageable(struct pci_dev *dev)
460{
461 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
462}
463
464static inline int platform_pci_set_power_state(struct pci_dev *dev,
465 pci_power_t t)
466{
467 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
468}
469
470static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
471{
472 return pci_platform_pm ?
473 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
474}
8f7020d3 475
eb9d0fe4
RW		 476static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
477{
478 return pci_platform_pm ?
479 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
480}
481
b67ea761
RW		 482static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
483{
484 return pci_platform_pm ?
485 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
486}
487
1da177e4 488/**
44e4e66e
RW		 489 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
490 * given PCI device
491 * @dev: PCI device to handle.
44e4e66e 492 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1da177e4 493 *
44e4e66e
RW		 494 * RETURN VALUE:
495 * -EINVAL if the requested state is invalid.
496 * -EIO if device does not support PCI PM or its PM capabilities register has a
497 * wrong version, or device doesn't support the requested state.
498 * 0 if device already is in the requested state.
499 * 0 if device's power state has been successfully changed.
1da177e4 500 */
f00a20ef 501static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1da177e4 502{
337001b6 503 u16 pmcsr;
44e4e66e 504 bool need_restore = false;
1da177e4 505
4a865905
RW		 506 /* Check if we're already there */
507 if (dev->current_state == state)
508 return 0;
509
337001b6 510 if (!dev->pm_cap)
cca03dec
AL		 511 return -EIO;
512
44e4e66e
RW		 513 if (state < PCI_D0 || state > PCI_D3hot)
514 return -EINVAL;
515
1da177e4
LT		 516 /* Validate current state:
517 * Can enter D0 from any state, but if we can only go deeper
518 * to sleep if we're already in a low power state
519 */
4a865905 520 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
44e4e66e 521 && dev->current_state > state) {
80ccba11
BH		 522 dev_err(&dev->dev, "invalid power transition "
523 "(from state %d to %d)\n", dev->current_state, state);
1da177e4 524 return -EINVAL;
44e4e66e 525 }
1da177e4 526
1da177e4 527 /* check if this device supports the desired state */
337001b6
RW		 528 if ((state == PCI_D1 && !dev->d1_support)
529 || (state == PCI_D2 && !dev->d2_support))
3fe9d19f 530 return -EIO;
1da177e4 531
337001b6 532 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
064b53db 533
32a36585 534 /* If we're (effectively) in D3, force entire word to 0.
1da177e4
LT		 535 * This doesn't affect PME_Status, disables PME_En, and
536 * sets PowerState to 0.
537 */
32a36585 538 switch (dev->current_state) {
d3535fbb
JL		 539 case PCI_D0:
540 case PCI_D1:
541 case PCI_D2:
542 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
543 pmcsr |= state;
544 break;
f62795f1
RW		 545 case PCI_D3hot:
546 case PCI_D3cold:
32a36585
JL		 547 case PCI_UNKNOWN: /* Boot-up */
548 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
f00a20ef 549 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
44e4e66e 550 need_restore = true;
32a36585 551 /* Fall-through: force to D0 */
32a36585 552 default:
d3535fbb 553 pmcsr = 0;
32a36585 554 break;
1da177e4
LT		 555 }
556
557 /* enter specified state */
337001b6 558 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1da177e4
LT		 559
560 /* Mandatory power management transition delays */
561 /* see PCI PM 1.1 5.6.1 table 18 */
562 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1ae861e6 563 pci_dev_d3_sleep(dev);
1da177e4 564 else if (state == PCI_D2 || dev->current_state == PCI_D2)
aa8c6c93 565 udelay(PCI_PM_D2_DELAY);
1da177e4 566
e13cdbd7
RW		 567 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
568 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
569 if (dev->current_state != state && printk_ratelimit())
570 dev_info(&dev->dev, "Refused to change power state, "
571 "currently in D%d\n", dev->current_state);
064b53db 572
448bd857
HY		 573 /*
574 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
064b53db
JL		 575 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
576 * from D3hot to D0 _may_ perform an internal reset, thereby
577 * going to "D0 Uninitialized" rather than "D0 Initialized".
578 * For example, at least some versions of the 3c905B and the
579 * 3c556B exhibit this behaviour.
580 *
581 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
582 * devices in a D3hot state at boot. Consequently, we need to
583 * restore at least the BARs so that the device will be
584 * accessible to its driver.
585 */
586 if (need_restore)
587 pci_restore_bars(dev);
588
f00a20ef 589 if (dev->bus->self)
7d715a6c
SL		 590 pcie_aspm_pm_state_change(dev->bus->self);
591
1da177e4
LT		 592 return 0;
593}
594
44e4e66e
RW		 595/**
596 * pci_update_current_state - Read PCI power state of given device from its
597 * PCI PM registers and cache it
598 * @dev: PCI device to handle.
f06fc0b6 599 * @state: State to cache in case the device doesn't have the PM capability
44e4e66e 600 */
73410429 601void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
44e4e66e 602{
337001b6 603 if (dev->pm_cap) {
44e4e66e
RW		 604 u16 pmcsr;
605
448bd857
HY		 606 /*
607 * Configuration space is not accessible for device in
608 * D3cold, so just keep or set D3cold for safety
609 */
610 if (dev->current_state == PCI_D3cold)
611 return;
612 if (state == PCI_D3cold) {
613 dev->current_state = PCI_D3cold;
614 return;
615 }
337001b6 616 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
44e4e66e 617 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
f06fc0b6
RW		 618 } else {
619 dev->current_state = state;
44e4e66e
RW		 620 }
621}
622
db288c9c
RW		 623/**
624 * pci_power_up - Put the given device into D0 forcibly
625 * @dev: PCI device to power up
626 */
627void pci_power_up(struct pci_dev *dev)
628{
629 if (platform_pci_power_manageable(dev))
630 platform_pci_set_power_state(dev, PCI_D0);
631
632 pci_raw_set_power_state(dev, PCI_D0);
633 pci_update_current_state(dev, PCI_D0);
634}
635
0e5dd46b
RW		 636/**
637 * pci_platform_power_transition - Use platform to change device power state
638 * @dev: PCI device to handle.
639 * @state: State to put the device into.
640 */
641static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
642{
643 int error;
644
645 if (platform_pci_power_manageable(dev)) {
646 error = platform_pci_set_power_state(dev, state);
647 if (!error)
648 pci_update_current_state(dev, state);
769ba721 649 } else
0e5dd46b 650 error = -ENODEV;
769ba721
RW		 651
652 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
653 dev->current_state = PCI_D0;
0e5dd46b
RW		 654
655 return error;
656}
657
658/**
659 * __pci_start_power_transition - Start power transition of a PCI device
660 * @dev: PCI device to handle.
661 * @state: State to put the device into.
662 */
663static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
664{
448bd857 665 if (state == PCI_D0) {
0e5dd46b 666 pci_platform_power_transition(dev, PCI_D0);
448bd857
HY		 667 /*
668 * Mandatory power management transition delays, see
669 * PCI Express Base Specification Revision 2.0 Section
670 * 6.6.1: Conventional Reset. Do not delay for
671 * devices powered on/off by corresponding bridge,
672 * because have already delayed for the bridge.
673 */
674 if (dev->runtime_d3cold) {
675 msleep(dev->d3cold_delay);
676 /*
677 * When powering on a bridge from D3cold, the
678 * whole hierarchy may be powered on into
679 * D0uninitialized state, resume them to give
680 * them a chance to suspend again
681 */
682 pci_wakeup_bus(dev->subordinate);
683 }
684 }
685}
686
687/**
688 * __pci_dev_set_current_state - Set current state of a PCI device
689 * @dev: Device to handle
690 * @data: pointer to state to be set
691 */
692static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
693{
694 pci_power_t state = *(pci_power_t *)data;
695
696 dev->current_state = state;
697 return 0;
698}
699
700/**
701 * __pci_bus_set_current_state - Walk given bus and set current state of devices
702 * @bus: Top bus of the subtree to walk.
703 * @state: state to be set
704 */
705static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
706{
707 if (bus)
708 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
0e5dd46b
RW		 709}
710
711/**
712 * __pci_complete_power_transition - Complete power transition of a PCI device
713 * @dev: PCI device to handle.
714 * @state: State to put the device into.
715 *
716 * This function should not be called directly by device drivers.
717 */
718int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
719{
448bd857
HY		 720 int ret;
721
db288c9c 722 if (state <= PCI_D0)
448bd857
HY		 723 return -EINVAL;
724 ret = pci_platform_power_transition(dev, state);
725 /* Power off the bridge may power off the whole hierarchy */
726 if (!ret && state == PCI_D3cold)
727 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
728 return ret;
0e5dd46b
RW		 729}
730EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
731
44e4e66e
RW		 732/**
733 * pci_set_power_state - Set the power state of a PCI device
734 * @dev: PCI device to handle.
735 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
736 *
877d0310 737 * Transition a device to a new power state, using the platform firmware and/or
44e4e66e
RW		 738 * the device's PCI PM registers.
739 *
740 * RETURN VALUE:
741 * -EINVAL if the requested state is invalid.
742 * -EIO if device does not support PCI PM or its PM capabilities register has a
743 * wrong version, or device doesn't support the requested state.
744 * 0 if device already is in the requested state.
745 * 0 if device's power state has been successfully changed.
746 */
747int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
748{
337001b6 749 int error;
44e4e66e
RW		 750
751 /* bound the state we're entering */
448bd857
HY		 752 if (state > PCI_D3cold)
753 state = PCI_D3cold;
44e4e66e
RW		 754 else if (state < PCI_D0)
755 state = PCI_D0;
756 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
757 /*
758 * If the device or the parent bridge do not support PCI PM,
759 * ignore the request if we're doing anything other than putting
760 * it into D0 (which would only happen on boot).
761 */
762 return 0;
763
db288c9c
RW		 764 /* Check if we're already there */
765 if (dev->current_state == state)
766 return 0;
767
0e5dd46b
RW		 768 __pci_start_power_transition(dev, state);
769
979b1791
AC		 770 /* This device is quirked not to be put into D3, so
771 don't put it in D3 */
448bd857 772 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
979b1791 773 return 0;
44e4e66e 774
448bd857
HY		 775 /*
776 * To put device in D3cold, we put device into D3hot in native
777 * way, then put device into D3cold with platform ops
778 */
779 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
780 PCI_D3hot : state);
44e4e66e 781
0e5dd46b
RW		 782 if (!__pci_complete_power_transition(dev, state))
783 error = 0;
1a680b7c
NC		 784 /*
785 * When aspm_policy is "powersave" this call ensures
786 * that ASPM is configured.
787 */
788 if (!error && dev->bus->self)
789 pcie_aspm_powersave_config_link(dev->bus->self);
44e4e66e
RW		 790
791 return error;
792}
793
1da177e4
LT		 794/**
795 * pci_choose_state - Choose the power state of a PCI device
796 * @dev: PCI device to be suspended
797 * @state: target sleep state for the whole system. This is the value
798 * that is passed to suspend() function.
799 *
800 * Returns PCI power state suitable for given device and given system
801 * message.
802 */
803
804pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
805{
ab826ca4 806 pci_power_t ret;
0f64474b 807
1da177e4
LT		 808 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
809 return PCI_D0;
810
961d9120
RW		 811 ret = platform_pci_choose_state(dev);
812 if (ret != PCI_POWER_ERROR)
813 return ret;
ca078bae
PM		 814
815 switch (state.event) {
816 case PM_EVENT_ON:
817 return PCI_D0;
818 case PM_EVENT_FREEZE:
b887d2e6
DB		 819 case PM_EVENT_PRETHAW:
820 /* REVISIT both freeze and pre-thaw "should" use D0 */
ca078bae 821 case PM_EVENT_SUSPEND:
3a2d5b70 822 case PM_EVENT_HIBERNATE:
ca078bae 823 return PCI_D3hot;
1da177e4 824 default:
80ccba11
BH		 825 dev_info(&dev->dev, "unrecognized suspend event %d\n",
826 state.event);
1da177e4
LT		 827 BUG();
828 }
829 return PCI_D0;
830}
831
832EXPORT_SYMBOL(pci_choose_state);
833
89858517
YZ		 834#define PCI_EXP_SAVE_REGS 7
835
1b6b8ce2 836
34a4876e
YL		 837static struct pci_cap_saved_state *pci_find_saved_cap(
838 struct pci_dev *pci_dev, char cap)
839{
840 struct pci_cap_saved_state *tmp;
34a4876e 841
b67bfe0d 842 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
34a4876e
YL		 843 if (tmp->cap.cap_nr == cap)
844 return tmp;
845 }
846 return NULL;
847}
848
b56a5a23
MT		 849static int pci_save_pcie_state(struct pci_dev *dev)
850{
59875ae4 851 int i = 0;
b56a5a23
MT		 852 struct pci_cap_saved_state *save_state;
853 u16 *cap;
854
59875ae4 855 if (!pci_is_pcie(dev))
b56a5a23
MT		 856 return 0;
857
9f35575d 858 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
b56a5a23 859 if (!save_state) {
e496b617 860 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
b56a5a23
MT		 861 return -ENOMEM;
862 }
63f4898a 863
59875ae4
JL		 864 cap = (u16 *)&save_state->cap.data[0];
865 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
866 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
867 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
868 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
869 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
870 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
871 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
9cb604ed 872
b56a5a23
MT		 873 return 0;
874}
875
876static void pci_restore_pcie_state(struct pci_dev *dev)
877{
59875ae4 878 int i = 0;
b56a5a23
MT		 879 struct pci_cap_saved_state *save_state;
880 u16 *cap;
881
882 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
59875ae4 883 if (!save_state)
9cb604ed
MS		 884 return;
885
59875ae4
JL		 886 cap = (u16 *)&save_state->cap.data[0];
887 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
888 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
889 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
890 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
891 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
892 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
893 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
b56a5a23
MT		 894}
895
cc692a5f
SH		 896
897static int pci_save_pcix_state(struct pci_dev *dev)
898{
63f4898a 899 int pos;
cc692a5f 900 struct pci_cap_saved_state *save_state;
cc692a5f
SH		 901
902 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
903 if (pos <= 0)
904 return 0;
905
f34303de 906 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
cc692a5f 907 if (!save_state) {
e496b617 908 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
cc692a5f
SH		 909 return -ENOMEM;
910 }
cc692a5f 911
24a4742f
AW		 912 pci_read_config_word(dev, pos + PCI_X_CMD,
913 (u16 *)save_state->cap.data);
63f4898a 914
cc692a5f
SH		 915 return 0;
916}
917
918static void pci_restore_pcix_state(struct pci_dev *dev)
919{
920 int i = 0, pos;
921 struct pci_cap_saved_state *save_state;
922 u16 *cap;
923
924 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
925 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
926 if (!save_state || pos <= 0)
927 return;
24a4742f 928 cap = (u16 *)&save_state->cap.data[0];
cc692a5f
SH		 929
930 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
cc692a5f
SH		 931}
932
933
1da177e4
LT		 934/**
935 * pci_save_state - save the PCI configuration space of a device before suspending
936 * @dev: - PCI device that we're dealing with
1da177e4
LT		 937 */
938int
939pci_save_state(struct pci_dev *dev)
940{
941 int i;
942 /* XXX: 100% dword access ok here? */
943 for (i = 0; i < 16; i++)
9e0b5b2c 944 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
aa8c6c93 945 dev->state_saved = true;
b56a5a23
MT		 946 if ((i = pci_save_pcie_state(dev)) != 0)
947 return i;
cc692a5f
SH		 948 if ((i = pci_save_pcix_state(dev)) != 0)
949 return i;
1da177e4
LT		 950 return 0;
951}
952
ebfc5b80
RW		 953static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
954 u32 saved_val, int retry)
955{
956 u32 val;
957
958 pci_read_config_dword(pdev, offset, &val);
959 if (val == saved_val)
960 return;
961
962 for (;;) {
963 dev_dbg(&pdev->dev, "restoring config space at offset "
964 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
965 pci_write_config_dword(pdev, offset, saved_val);
966 if (retry-- <= 0)
967 return;
968
969 pci_read_config_dword(pdev, offset, &val);
970 if (val == saved_val)
971 return;
972
973 mdelay(1);
974 }
975}
976
a6cb9ee7
RW		 977static void pci_restore_config_space_range(struct pci_dev *pdev,
978 int start, int end, int retry)
ebfc5b80
RW		 979{
980 int index;
981
982 for (index = end; index >= start; index--)
983 pci_restore_config_dword(pdev, 4 * index,
984 pdev->saved_config_space[index],
985 retry);
986}
987
a6cb9ee7
RW		 988static void pci_restore_config_space(struct pci_dev *pdev)
989{
990 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
991 pci_restore_config_space_range(pdev, 10, 15, 0);
992 /* Restore BARs before the command register. */
993 pci_restore_config_space_range(pdev, 4, 9, 10);
994 pci_restore_config_space_range(pdev, 0, 3, 0);
995 } else {
996 pci_restore_config_space_range(pdev, 0, 15, 0);
997 }
998}
999
1da177e4
LT		 1000/**
1001 * pci_restore_state - Restore the saved state of a PCI device
1002 * @dev: - PCI device that we're dealing with
1da177e4 1003 */
1d3c16a8 1004void pci_restore_state(struct pci_dev *dev)
1da177e4 1005{
c82f63e4 1006 if (!dev->state_saved)
1d3c16a8 1007 return;
4b77b0a2 1008
b56a5a23
MT		 1009 /* PCI Express register must be restored first */
1010 pci_restore_pcie_state(dev);
1900ca13 1011 pci_restore_ats_state(dev);
b56a5a23 1012
a6cb9ee7 1013 pci_restore_config_space(dev);
ebfc5b80 1014
cc692a5f 1015 pci_restore_pcix_state(dev);
41017f0c 1016 pci_restore_msi_state(dev);
8c5cdb6a 1017 pci_restore_iov_state(dev);
8fed4b65 1018
4b77b0a2 1019 dev->state_saved = false;
1da177e4
LT		 1020}
1021
ffbdd3f7
AW		 1022struct pci_saved_state {
1023 u32 config_space[16];
1024 struct pci_cap_saved_data cap[0];
1025};
1026
1027/**
1028 * pci_store_saved_state - Allocate and return an opaque struct containing
1029 * the device saved state.
1030 * @dev: PCI device that we're dealing with
1031 *
1032 * Rerturn NULL if no state or error.
1033 */
1034struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1035{
1036 struct pci_saved_state *state;
1037 struct pci_cap_saved_state *tmp;
1038 struct pci_cap_saved_data *cap;
ffbdd3f7
AW		 1039 size_t size;
1040
1041 if (!dev->state_saved)
1042 return NULL;
1043
1044 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1045
b67bfe0d 1046 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
ffbdd3f7
AW		 1047 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1048
1049 state = kzalloc(size, GFP_KERNEL);
1050 if (!state)
1051 return NULL;
1052
1053 memcpy(state->config_space, dev->saved_config_space,
1054 sizeof(state->config_space));
1055
1056 cap = state->cap;
b67bfe0d 1057 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
ffbdd3f7
AW		 1058 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1059 memcpy(cap, &tmp->cap, len);
1060 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1061 }
1062 /* Empty cap_save terminates list */
1063
1064 return state;
1065}
1066EXPORT_SYMBOL_GPL(pci_store_saved_state);
1067
1068/**
1069 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1070 * @dev: PCI device that we're dealing with
1071 * @state: Saved state returned from pci_store_saved_state()
1072 */
1073int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1074{
1075 struct pci_cap_saved_data *cap;
1076
1077 dev->state_saved = false;
1078
1079 if (!state)
1080 return 0;
1081
1082 memcpy(dev->saved_config_space, state->config_space,
1083 sizeof(state->config_space));
1084
1085 cap = state->cap;
1086 while (cap->size) {
1087 struct pci_cap_saved_state *tmp;
1088
1089 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1090 if (!tmp || tmp->cap.size != cap->size)
1091 return -EINVAL;
1092
1093 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1094 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1095 sizeof(struct pci_cap_saved_data) + cap->size);
1096 }
1097
1098 dev->state_saved = true;
1099 return 0;
1100}
1101EXPORT_SYMBOL_GPL(pci_load_saved_state);
1102
1103/**
1104 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1105 * and free the memory allocated for it.
1106 * @dev: PCI device that we're dealing with
1107 * @state: Pointer to saved state returned from pci_store_saved_state()
1108 */
1109int pci_load_and_free_saved_state(struct pci_dev *dev,
1110 struct pci_saved_state **state)
1111{
1112 int ret = pci_load_saved_state(dev, *state);
1113 kfree(*state);
1114 *state = NULL;
1115 return ret;
1116}
1117EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1118
38cc1302
HS		 1119static int do_pci_enable_device(struct pci_dev *dev, int bars)
1120{
1121 int err;
9942fc02
BH		 1122 u16 cmd;
1123 u8 pin;
38cc1302
HS		 1124
1125 err = pci_set_power_state(dev, PCI_D0);
1126 if (err < 0 && err != -EIO)
1127 return err;
1128 err = pcibios_enable_device(dev, bars);
1129 if (err < 0)
1130 return err;
1131 pci_fixup_device(pci_fixup_enable, dev);
1132
10ff94fa
BH		 1133 if (dev->msi_enabled || dev->msix_enabled)
1134 return 0;
1135
9942fc02
BH		 1136 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1137 if (pin) {
1138 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1139 if (cmd & PCI_COMMAND_INTX_DISABLE)
1140 pci_write_config_word(dev, PCI_COMMAND,
1141 cmd & ~PCI_COMMAND_INTX_DISABLE);
1142 }
1143
38cc1302
HS		 1144 return 0;
1145}
1146
1147/**
0b62e13b 1148 * pci_reenable_device - Resume abandoned device
38cc1302
HS		 1149 * @dev: PCI device to be resumed
1150 *
1151 * Note this function is a backend of pci_default_resume and is not supposed
1152 * to be called by normal code, write proper resume handler and use it instead.
1153 */
0b62e13b 1154int pci_reenable_device(struct pci_dev *dev)
38cc1302 1155{
296ccb08 1156 if (pci_is_enabled(dev))
38cc1302
HS		 1157 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1158 return 0;
1159}
1160
b4b4fbba 1161static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1da177e4
LT		 1162{
1163 int err;
b718989d 1164 int i, bars = 0;
1da177e4 1165
97c145f7
JB		 1166 /*
1167 * Power state could be unknown at this point, either due to a fresh
1168 * boot or a device removal call. So get the current power state
1169 * so that things like MSI message writing will behave as expected
1170 * (e.g. if the device really is in D0 at enable time).
1171 */
1172 if (dev->pm_cap) {
1173 u16 pmcsr;
1174 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1175 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1176 }
1177
cc7ba39b 1178 if (atomic_inc_return(&dev->enable_cnt) > 1)
9fb625c3
HS		 1179 return 0; /* already enabled */
1180
497f16f2
YL		 1181 /* only skip sriov related */
1182 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1183 if (dev->resource[i].flags & flags)
1184 bars |= (1 << i);
1185 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
b718989d
BH		 1186 if (dev->resource[i].flags & flags)
1187 bars |= (1 << i);
1188
38cc1302 1189 err = do_pci_enable_device(dev, bars);
95a62965 1190 if (err < 0)
38cc1302 1191 atomic_dec(&dev->enable_cnt);
9fb625c3 1192 return err;
1da177e4
LT		 1193}
1194
b718989d
BH		 1195/**
1196 * pci_enable_device_io - Initialize a device for use with IO space
1197 * @dev: PCI device to be initialized
1198 *
1199 * Initialize device before it's used by a driver. Ask low-level code
1200 * to enable I/O resources. Wake up the device if it was suspended.
1201 * Beware, this function can fail.
1202 */
1203int pci_enable_device_io(struct pci_dev *dev)
1204{
b4b4fbba 1205 return pci_enable_device_flags(dev, IORESOURCE_IO);
b718989d
BH		 1206}
1207
1208/**
1209 * pci_enable_device_mem - Initialize a device for use with Memory space
1210 * @dev: PCI device to be initialized
1211 *
1212 * Initialize device before it's used by a driver. Ask low-level code
1213 * to enable Memory resources. Wake up the device if it was suspended.
1214 * Beware, this function can fail.
1215 */
1216int pci_enable_device_mem(struct pci_dev *dev)
1217{
b4b4fbba 1218 return pci_enable_device_flags(dev, IORESOURCE_MEM);
b718989d
BH		 1219}
1220
bae94d02
IPG		 1221/**
1222 * pci_enable_device - Initialize device before it's used by a driver.
1223 * @dev: PCI device to be initialized
1224 *
1225 * Initialize device before it's used by a driver. Ask low-level code
1226 * to enable I/O and memory. Wake up the device if it was suspended.
1227 * Beware, this function can fail.
1228 *
1229 * Note we don't actually enable the device many times if we call
1230 * this function repeatedly (we just increment the count).
1231 */
1232int pci_enable_device(struct pci_dev *dev)
1233{
b4b4fbba 1234 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
bae94d02
IPG		 1235}
1236
9ac7849e
TH		 1237/*
1238 * Managed PCI resources. This manages device on/off, intx/msi/msix
1239 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1240 * there's no need to track it separately. pci_devres is initialized
1241 * when a device is enabled using managed PCI device enable interface.
1242 */
1243struct pci_devres {
7f375f32
TH		 1244 unsigned int enabled:1;
1245 unsigned int pinned:1;
9ac7849e
TH		 1246 unsigned int orig_intx:1;
1247 unsigned int restore_intx:1;
1248 u32 region_mask;
1249};
1250
1251static void pcim_release(struct device *gendev, void *res)
1252{
1253 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1254 struct pci_devres *this = res;
1255 int i;
1256
1257 if (dev->msi_enabled)
1258 pci_disable_msi(dev);
1259 if (dev->msix_enabled)
1260 pci_disable_msix(dev);
1261
1262 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1263 if (this->region_mask & (1 << i))
1264 pci_release_region(dev, i);
1265
1266 if (this->restore_intx)
1267 pci_intx(dev, this->orig_intx);
1268
7f375f32 1269 if (this->enabled && !this->pinned)
9ac7849e
TH		 1270 pci_disable_device(dev);
1271}
1272
1273static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1274{
1275 struct pci_devres *dr, *new_dr;
1276
1277 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1278 if (dr)
1279 return dr;
1280
1281 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1282 if (!new_dr)
1283 return NULL;
1284 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1285}
1286
1287static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1288{
1289 if (pci_is_managed(pdev))
1290 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1291 return NULL;
1292}
1293
1294/**
1295 * pcim_enable_device - Managed pci_enable_device()
1296 * @pdev: PCI device to be initialized
1297 *
1298 * Managed pci_enable_device().
1299 */
1300int pcim_enable_device(struct pci_dev *pdev)
1301{
1302 struct pci_devres *dr;
1303 int rc;
1304
1305 dr = get_pci_dr(pdev);
1306 if (unlikely(!dr))
1307 return -ENOMEM;
b95d58ea
TH		 1308 if (dr->enabled)
1309 return 0;
9ac7849e
TH		 1310
1311 rc = pci_enable_device(pdev);
1312 if (!rc) {
1313 pdev->is_managed = 1;
7f375f32 1314 dr->enabled = 1;
9ac7849e
TH		 1315 }
1316 return rc;
1317}
1318
1319/**
1320 * pcim_pin_device - Pin managed PCI device
1321 * @pdev: PCI device to pin
1322 *
1323 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1324 * driver detach. @pdev must have been enabled with
1325 * pcim_enable_device().
1326 */
1327void pcim_pin_device(struct pci_dev *pdev)
1328{
1329 struct pci_devres *dr;
1330
1331 dr = find_pci_dr(pdev);
7f375f32 1332 WARN_ON(!dr || !dr->enabled);
9ac7849e 1333 if (dr)
7f375f32 1334 dr->pinned = 1;
9ac7849e
TH		 1335}
1336
eca0d467
MG		 1337/*
1338 * pcibios_add_device - provide arch specific hooks when adding device dev
1339 * @dev: the PCI device being added
1340 *
1341 * Permits the platform to provide architecture specific functionality when
1342 * devices are added. This is the default implementation. Architecture
1343 * implementations can override this.
1344 */
1345int __weak pcibios_add_device (struct pci_dev *dev)
1346{
1347 return 0;
1348}
1349
1da177e4
LT		 1350/**
1351 * pcibios_disable_device - disable arch specific PCI resources for device dev
1352 * @dev: the PCI device to disable
1353 *
1354 * Disables architecture specific PCI resources for the device. This
1355 * is the default implementation. Architecture implementations can
1356 * override this.
1357 */
d6d88c83 1358void __weak pcibios_disable_device (struct pci_dev *dev) {}
1da177e4 1359
fa58d305
RW		 1360static void do_pci_disable_device(struct pci_dev *dev)
1361{
1362 u16 pci_command;
1363
1364 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1365 if (pci_command & PCI_COMMAND_MASTER) {
1366 pci_command &= ~PCI_COMMAND_MASTER;
1367 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1368 }
1369
1370 pcibios_disable_device(dev);
1371}
1372
1373/**
1374 * pci_disable_enabled_device - Disable device without updating enable_cnt
1375 * @dev: PCI device to disable
1376 *
1377 * NOTE: This function is a backend of PCI power management routines and is
1378 * not supposed to be called drivers.
1379 */
1380void pci_disable_enabled_device(struct pci_dev *dev)
1381{
296ccb08 1382 if (pci_is_enabled(dev))
fa58d305
RW		 1383 do_pci_disable_device(dev);
1384}
1385
1da177e4
LT		 1386/**
1387 * pci_disable_device - Disable PCI device after use
1388 * @dev: PCI device to be disabled
1389 *
1390 * Signal to the system that the PCI device is not in use by the system
1391 * anymore. This only involves disabling PCI bus-mastering, if active.
bae94d02
IPG		 1392 *
1393 * Note we don't actually disable the device until all callers of
ee6583f6 1394 * pci_enable_device() have called pci_disable_device().
1da177e4
LT		 1395 */
1396void
1397pci_disable_device(struct pci_dev *dev)
1398{
9ac7849e 1399 struct pci_devres *dr;
99dc804d 1400
9ac7849e
TH		 1401 dr = find_pci_dr(dev);
1402 if (dr)
7f375f32 1403 dr->enabled = 0;
9ac7849e 1404
fd6dceab
KK		 1405 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1406 "disabling already-disabled device");
1407
cc7ba39b 1408 if (atomic_dec_return(&dev->enable_cnt) != 0)
bae94d02
IPG		 1409 return;
1410
fa58d305 1411 do_pci_disable_device(dev);
1da177e4 1412
fa58d305 1413 dev->is_busmaster = 0;
1da177e4
LT		 1414}
1415
f7bdd12d
BK		 1416/**
1417 * pcibios_set_pcie_reset_state - set reset state for device dev
45e829ea 1418 * @dev: the PCIe device reset
f7bdd12d
BK		 1419 * @state: Reset state to enter into
1420 *
1421 *
45e829ea 1422 * Sets the PCIe reset state for the device. This is the default
f7bdd12d
BK		 1423 * implementation. Architecture implementations can override this.
1424 */
d6d88c83
BH		 1425int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1426 enum pcie_reset_state state)
f7bdd12d
BK		 1427{
1428 return -EINVAL;
1429}
1430
1431/**
1432 * pci_set_pcie_reset_state - set reset state for device dev
45e829ea 1433 * @dev: the PCIe device reset
f7bdd12d
BK		 1434 * @state: Reset state to enter into
1435 *
1436 *
1437 * Sets the PCI reset state for the device.
1438 */
1439int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1440{
1441 return pcibios_set_pcie_reset_state(dev, state);
1442}
1443
58ff4633
RW		 1444/**
1445 * pci_check_pme_status - Check if given device has generated PME.
1446 * @dev: Device to check.
1447 *
1448 * Check the PME status of the device and if set, clear it and clear PME enable
1449 * (if set). Return 'true' if PME status and PME enable were both set or
1450 * 'false' otherwise.
1451 */
1452bool pci_check_pme_status(struct pci_dev *dev)
1453{
1454 int pmcsr_pos;
1455 u16 pmcsr;
1456 bool ret = false;
1457
1458 if (!dev->pm_cap)
1459 return false;
1460
1461 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1462 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1463 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1464 return false;
1465
1466 /* Clear PME status. */
1467 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1468 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1469 /* Disable PME to avoid interrupt flood. */
1470 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1471 ret = true;
1472 }
1473
1474 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1475
1476 return ret;
1477}
1478
b67ea761
RW		 1479/**
1480 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1481 * @dev: Device to handle.
379021d5 1482 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
b67ea761
RW		 1483 *
1484 * Check if @dev has generated PME and queue a resume request for it in that
1485 * case.
1486 */
379021d5 1487static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
b67ea761 1488{
379021d5
RW		 1489 if (pme_poll_reset && dev->pme_poll)
1490 dev->pme_poll = false;
1491
c125e96f 1492 if (pci_check_pme_status(dev)) {
c125e96f 1493 pci_wakeup_event(dev);
0f953bf6 1494 pm_request_resume(&dev->dev);
c125e96f 1495 }
b67ea761
RW		 1496 return 0;
1497}
1498
1499/**
1500 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1501 * @bus: Top bus of the subtree to walk.
1502 */
1503void pci_pme_wakeup_bus(struct pci_bus *bus)
1504{
1505 if (bus)
379021d5 1506 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
b67ea761
RW		 1507}
1508
448bd857
HY		 1509/**
1510 * pci_wakeup - Wake up a PCI device
ceaf5b5f 1511 * @pci_dev: Device to handle.
448bd857
HY		 1512 * @ign: ignored parameter
1513 */
1514static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1515{
1516 pci_wakeup_event(pci_dev);
1517 pm_request_resume(&pci_dev->dev);
1518 return 0;
1519}
1520
1521/**
1522 * pci_wakeup_bus - Walk given bus and wake up devices on it
1523 * @bus: Top bus of the subtree to walk.
1524 */
1525void pci_wakeup_bus(struct pci_bus *bus)
1526{
1527 if (bus)
1528 pci_walk_bus(bus, pci_wakeup, NULL);
1529}
1530
eb9d0fe4
RW		 1531/**
1532 * pci_pme_capable - check the capability of PCI device to generate PME#
1533 * @dev: PCI device to handle.
eb9d0fe4
RW		 1534 * @state: PCI state from which device will issue PME#.
1535 */
e5899e1b 1536bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
eb9d0fe4 1537{
337001b6 1538 if (!dev->pm_cap)
eb9d0fe4
RW		 1539 return false;
1540
337001b6 1541 return !!(dev->pme_support & (1 << state));
eb9d0fe4
RW		 1542}
1543
df17e62e
MG		 1544static void pci_pme_list_scan(struct work_struct *work)
1545{
379021d5 1546 struct pci_pme_device *pme_dev, *n;
df17e62e
MG		 1547
1548 mutex_lock(&pci_pme_list_mutex);
1549 if (!list_empty(&pci_pme_list)) {
379021d5
RW		 1550 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1551 if (pme_dev->dev->pme_poll) {
71a83bd7
ZY		 1552 struct pci_dev *bridge;
1553
1554 bridge = pme_dev->dev->bus->self;
1555 /*
1556 * If bridge is in low power state, the
1557 * configuration space of subordinate devices
1558 * may be not accessible
1559 */
1560 if (bridge && bridge->current_state != PCI_D0)
1561 continue;
379021d5
RW		 1562 pci_pme_wakeup(pme_dev->dev, NULL);
1563 } else {
1564 list_del(&pme_dev->list);
1565 kfree(pme_dev);
1566 }
1567 }
1568 if (!list_empty(&pci_pme_list))
1569 schedule_delayed_work(&pci_pme_work,
1570 msecs_to_jiffies(PME_TIMEOUT));
df17e62e
MG		 1571 }
1572 mutex_unlock(&pci_pme_list_mutex);
1573}
1574
eb9d0fe4
RW		 1575/**
1576 * pci_pme_active - enable or disable PCI device's PME# function
1577 * @dev: PCI device to handle.
eb9d0fe4
RW		 1578 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1579 *
1580 * The caller must verify that the device is capable of generating PME# before
1581 * calling this function with @enable equal to 'true'.
1582 */
5a6c9b60 1583void pci_pme_active(struct pci_dev *dev, bool enable)
eb9d0fe4
RW		 1584{
1585 u16 pmcsr;
1586
ffaddbe8 1587 if (!dev->pme_support)
eb9d0fe4
RW		 1588 return;
1589
337001b6 1590 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
eb9d0fe4
RW		 1591 /* Clear PME_Status by writing 1 to it and enable PME# */
1592 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1593 if (!enable)
1594 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1595
337001b6 1596 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
eb9d0fe4 1597
6e965e0d
HY		 1598 /*
1599 * PCI (as opposed to PCIe) PME requires that the device have
1600 * its PME# line hooked up correctly. Not all hardware vendors
1601 * do this, so the PME never gets delivered and the device
1602 * remains asleep. The easiest way around this is to
1603 * periodically walk the list of suspended devices and check
1604 * whether any have their PME flag set. The assumption is that
1605 * we'll wake up often enough anyway that this won't be a huge
1606 * hit, and the power savings from the devices will still be a
1607 * win.
1608 *
1609 * Although PCIe uses in-band PME message instead of PME# line
1610 * to report PME, PME does not work for some PCIe devices in
1611 * reality. For example, there are devices that set their PME
1612 * status bits, but don't really bother to send a PME message;
1613 * there are PCI Express Root Ports that don't bother to
1614 * trigger interrupts when they receive PME messages from the
1615 * devices below. So PME poll is used for PCIe devices too.
1616 */
df17e62e 1617
379021d5 1618 if (dev->pme_poll) {
df17e62e
MG		 1619 struct pci_pme_device *pme_dev;
1620 if (enable) {
1621 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1622 GFP_KERNEL);
1623 if (!pme_dev)
1624 goto out;
1625 pme_dev->dev = dev;
1626 mutex_lock(&pci_pme_list_mutex);
1627 list_add(&pme_dev->list, &pci_pme_list);
1628 if (list_is_singular(&pci_pme_list))
1629 schedule_delayed_work(&pci_pme_work,
1630 msecs_to_jiffies(PME_TIMEOUT));
1631 mutex_unlock(&pci_pme_list_mutex);
1632 } else {
1633 mutex_lock(&pci_pme_list_mutex);
1634 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1635 if (pme_dev->dev == dev) {
1636 list_del(&pme_dev->list);
1637 kfree(pme_dev);
1638 break;
1639 }
1640 }
1641 mutex_unlock(&pci_pme_list_mutex);
1642 }
1643 }
1644
1645out:
85b8582d 1646 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
eb9d0fe4
RW		 1647}
1648
1da177e4 1649/**
6cbf8214 1650 * __pci_enable_wake - enable PCI device as wakeup event source
075c1771
DB		 1651 * @dev: PCI device affected
1652 * @state: PCI state from which device will issue wakeup events
6cbf8214 1653 * @runtime: True if the events are to be generated at run time
075c1771
DB		 1654 * @enable: True to enable event generation; false to disable
1655 *
1656 * This enables the device as a wakeup event source, or disables it.
1657 * When such events involves platform-specific hooks, those hooks are
1658 * called automatically by this routine.
1659 *
1660 * Devices with legacy power management (no standard PCI PM capabilities)
eb9d0fe4 1661 * always require such platform hooks.
075c1771 1662 *
eb9d0fe4
RW		 1663 * RETURN VALUE:
1664 * 0 is returned on success
1665 * -EINVAL is returned if device is not supposed to wake up the system
1666 * Error code depending on the platform is returned if both the platform and
1667 * the native mechanism fail to enable the generation of wake-up events
1da177e4 1668 */
6cbf8214
RW		 1669int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1670 bool runtime, bool enable)
1da177e4 1671{
5bcc2fb4 1672 int ret = 0;
075c1771 1673
6cbf8214 1674 if (enable && !runtime && !device_may_wakeup(&dev->dev))
eb9d0fe4 1675 return -EINVAL;
1da177e4 1676
e80bb09d
RW		 1677 /* Don't do the same thing twice in a row for one device. */
1678 if (!!enable == !!dev->wakeup_prepared)
1679 return 0;
1680
eb9d0fe4
RW		 1681 /*
1682 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1683 * Anderson we should be doing PME# wake enable followed by ACPI wake
1684 * enable. To disable wake-up we call the platform first, for symmetry.
075c1771 1685 */
1da177e4 1686
5bcc2fb4
RW		 1687 if (enable) {
1688 int error;
1da177e4 1689
5bcc2fb4
RW		 1690 if (pci_pme_capable(dev, state))
1691 pci_pme_active(dev, true);
1692 else
1693 ret = 1;
6cbf8214
RW		 1694 error = runtime ? platform_pci_run_wake(dev, true) :
1695 platform_pci_sleep_wake(dev, true);
5bcc2fb4
RW		 1696 if (ret)
1697 ret = error;
e80bb09d
RW		 1698 if (!ret)
1699 dev->wakeup_prepared = true;
5bcc2fb4 1700 } else {
6cbf8214
RW		 1701 if (runtime)
1702 platform_pci_run_wake(dev, false);
1703 else
1704 platform_pci_sleep_wake(dev, false);
5bcc2fb4 1705 pci_pme_active(dev, false);
e80bb09d 1706 dev->wakeup_prepared = false;
5bcc2fb4 1707 }
1da177e4 1708
5bcc2fb4 1709 return ret;
eb9d0fe4 1710}
6cbf8214 1711EXPORT_SYMBOL(__pci_enable_wake);
1da177e4 1712
0235c4fc
RW		 1713/**
1714 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1715 * @dev: PCI device to prepare
1716 * @enable: True to enable wake-up event generation; false to disable
1717 *
1718 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1719 * and this function allows them to set that up cleanly - pci_enable_wake()
1720 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1721 * ordering constraints.
1722 *
1723 * This function only returns error code if the device is not capable of
1724 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1725 * enable wake-up power for it.
1726 */
1727int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1728{
1729 return pci_pme_capable(dev, PCI_D3cold) ?
1730 pci_enable_wake(dev, PCI_D3cold, enable) :
1731 pci_enable_wake(dev, PCI_D3hot, enable);
1732}
1733
404cc2d8 1734/**
37139074
JB		 1735 * pci_target_state - find an appropriate low power state for a given PCI dev
1736 * @dev: PCI device
1737 *
1738 * Use underlying platform code to find a supported low power state for @dev.
1739 * If the platform can't manage @dev, return the deepest state from which it
1740 * can generate wake events, based on any available PME info.
404cc2d8 1741 */
e5899e1b 1742pci_power_t pci_target_state(struct pci_dev *dev)
404cc2d8
RW		 1743{
1744 pci_power_t target_state = PCI_D3hot;
404cc2d8
RW		 1745
1746 if (platform_pci_power_manageable(dev)) {
1747 /*
1748 * Call the platform to choose the target state of the device
1749 * and enable wake-up from this state if supported.
1750 */
1751 pci_power_t state = platform_pci_choose_state(dev);
1752
1753 switch (state) {
1754 case PCI_POWER_ERROR:
1755 case PCI_UNKNOWN:
1756 break;
1757 case PCI_D1:
1758 case PCI_D2:
1759 if (pci_no_d1d2(dev))
1760 break;
1761 default:
1762 target_state = state;
404cc2d8 1763 }
d2abdf62
RW		 1764 } else if (!dev->pm_cap) {
1765 target_state = PCI_D0;
404cc2d8
RW		 1766 } else if (device_may_wakeup(&dev->dev)) {
1767 /*
1768 * Find the deepest state from which the device can generate
1769 * wake-up events, make it the target state and enable device
1770 * to generate PME#.
1771 */
337001b6
RW		 1772 if (dev->pme_support) {
1773 while (target_state
1774 && !(dev->pme_support & (1 << target_state)))
1775 target_state--;
404cc2d8
RW		 1776 }
1777 }
1778
e5899e1b
RW		 1779 return target_state;
1780}
1781
1782/**
1783 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1784 * @dev: Device to handle.
1785 *
1786 * Choose the power state appropriate for the device depending on whether
1787 * it can wake up the system and/or is power manageable by the platform
1788 * (PCI_D3hot is the default) and put the device into that state.
1789 */
1790int pci_prepare_to_sleep(struct pci_dev *dev)
1791{
1792 pci_power_t target_state = pci_target_state(dev);
1793 int error;
1794
1795 if (target_state == PCI_POWER_ERROR)
1796 return -EIO;
1797
448bd857
HY		 1798 /* D3cold during system suspend/hibernate is not supported */
1799 if (target_state > PCI_D3hot)
1800 target_state = PCI_D3hot;
1801
8efb8c76 1802 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
c157dfa3 1803
404cc2d8
RW		 1804 error = pci_set_power_state(dev, target_state);
1805
1806 if (error)
1807 pci_enable_wake(dev, target_state, false);
1808
1809 return error;
1810}
1811
1812/**
443bd1c4 1813 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
404cc2d8
RW		 1814 * @dev: Device to handle.
1815 *
88393161 1816 * Disable device's system wake-up capability and put it into D0.
404cc2d8
RW		 1817 */
1818int pci_back_from_sleep(struct pci_dev *dev)
1819{
1820 pci_enable_wake(dev, PCI_D0, false);
1821 return pci_set_power_state(dev, PCI_D0);
1822}
1823
6cbf8214
RW		 1824/**
1825 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1826 * @dev: PCI device being suspended.
1827 *
1828 * Prepare @dev to generate wake-up events at run time and put it into a low
1829 * power state.
1830 */
1831int pci_finish_runtime_suspend(struct pci_dev *dev)
1832{
1833 pci_power_t target_state = pci_target_state(dev);
1834 int error;
1835
1836 if (target_state == PCI_POWER_ERROR)
1837 return -EIO;
1838
448bd857
HY		 1839 dev->runtime_d3cold = target_state == PCI_D3cold;
1840
6cbf8214
RW		 1841 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1842
1843 error = pci_set_power_state(dev, target_state);
1844
448bd857 1845 if (error) {
6cbf8214 1846 __pci_enable_wake(dev, target_state, true, false);
448bd857
HY		 1847 dev->runtime_d3cold = false;
1848 }
6cbf8214
RW		 1849
1850 return error;
1851}
1852
b67ea761
RW		 1853/**
1854 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1855 * @dev: Device to check.
1856 *
1857 * Return true if the device itself is cabable of generating wake-up events
1858 * (through the platform or using the native PCIe PME) or if the device supports
1859 * PME and one of its upstream bridges can generate wake-up events.
1860 */
1861bool pci_dev_run_wake(struct pci_dev *dev)
1862{
1863 struct pci_bus *bus = dev->bus;
1864
1865 if (device_run_wake(&dev->dev))
1866 return true;
1867
1868 if (!dev->pme_support)
1869 return false;
1870
1871 while (bus->parent) {
1872 struct pci_dev *bridge = bus->self;
1873
1874 if (device_run_wake(&bridge->dev))
1875 return true;
1876
1877 bus = bus->parent;
1878 }
1879
1880 /* We have reached the root bus. */
1881 if (bus->bridge)
1882 return device_run_wake(bus->bridge);
1883
1884 return false;
1885}
1886EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1887
b3c32c4f
HY		 1888void pci_config_pm_runtime_get(struct pci_dev *pdev)
1889{
1890 struct device *dev = &pdev->dev;
1891 struct device *parent = dev->parent;
1892
1893 if (parent)
1894 pm_runtime_get_sync(parent);
1895 pm_runtime_get_noresume(dev);
1896 /*
1897 * pdev->current_state is set to PCI_D3cold during suspending,
1898 * so wait until suspending completes
1899 */
1900 pm_runtime_barrier(dev);
1901 /*
1902 * Only need to resume devices in D3cold, because config
1903 * registers are still accessible for devices suspended but
1904 * not in D3cold.
1905 */
1906 if (pdev->current_state == PCI_D3cold)
1907 pm_runtime_resume(dev);
1908}
1909
1910void pci_config_pm_runtime_put(struct pci_dev *pdev)
1911{
1912 struct device *dev = &pdev->dev;
1913 struct device *parent = dev->parent;
1914
1915 pm_runtime_put(dev);
1916 if (parent)
1917 pm_runtime_put_sync(parent);
1918}
1919
eb9d0fe4
RW		 1920/**
1921 * pci_pm_init - Initialize PM functions of given PCI device
1922 * @dev: PCI device to handle.
1923 */
1924void pci_pm_init(struct pci_dev *dev)
1925{
1926 int pm;
1927 u16 pmc;
1da177e4 1928
bb910a70 1929 pm_runtime_forbid(&dev->dev);
967577b0
HY		 1930 pm_runtime_set_active(&dev->dev);
1931 pm_runtime_enable(&dev->dev);
a1e4d72c 1932 device_enable_async_suspend(&dev->dev);
e80bb09d 1933 dev->wakeup_prepared = false;
bb910a70 1934
337001b6 1935 dev->pm_cap = 0;
ffaddbe8 1936 dev->pme_support = 0;
337001b6 1937
eb9d0fe4
RW		 1938 /* find PCI PM capability in list */
1939 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1940 if (!pm)
50246dd4 1941 return;
eb9d0fe4
RW		 1942 /* Check device's ability to generate PME# */
1943 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
075c1771 1944
eb9d0fe4
RW		 1945 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1946 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1947 pmc & PCI_PM_CAP_VER_MASK);
50246dd4 1948 return;
eb9d0fe4
RW		 1949 }
1950
337001b6 1951 dev->pm_cap = pm;
1ae861e6 1952 dev->d3_delay = PCI_PM_D3_WAIT;
448bd857 1953 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
4f9c1397 1954 dev->d3cold_allowed = true;
337001b6
RW		 1955
1956 dev->d1_support = false;
1957 dev->d2_support = false;
1958 if (!pci_no_d1d2(dev)) {
c9ed77ee 1959 if (pmc & PCI_PM_CAP_D1)
337001b6 1960 dev->d1_support = true;
c9ed77ee 1961 if (pmc & PCI_PM_CAP_D2)
337001b6 1962 dev->d2_support = true;
c9ed77ee
BH		 1963
1964 if (dev->d1_support || dev->d2_support)
1965 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
ec84f126
JB		 1966 dev->d1_support ? " D1" : "",
1967 dev->d2_support ? " D2" : "");
337001b6
RW		 1968 }
1969
1970 pmc &= PCI_PM_CAP_PME_MASK;
1971 if (pmc) {
10c3d71d
BH		 1972 dev_printk(KERN_DEBUG, &dev->dev,
1973 "PME# supported from%s%s%s%s%s\n",
c9ed77ee
BH		 1974 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1975 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1976 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1977 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1978 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
337001b6 1979 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
379021d5 1980 dev->pme_poll = true;
eb9d0fe4
RW		 1981 /*
1982 * Make device's PM flags reflect the wake-up capability, but
1983 * let the user space enable it to wake up the system as needed.
1984 */
1985 device_set_wakeup_capable(&dev->dev, true);
eb9d0fe4 1986 /* Disable the PME# generation functionality */
337001b6 1987 pci_pme_active(dev, false);
eb9d0fe4 1988 }
1da177e4
LT		 1989}
1990
34a4876e
YL		 1991static void pci_add_saved_cap(struct pci_dev *pci_dev,
1992 struct pci_cap_saved_state *new_cap)
1993{
1994 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
1995}
1996
63f4898a
RW		 1997/**
1998 * pci_add_save_buffer - allocate buffer for saving given capability registers
1999 * @dev: the PCI device
2000 * @cap: the capability to allocate the buffer for
2001 * @size: requested size of the buffer
2002 */
2003static int pci_add_cap_save_buffer(
2004 struct pci_dev *dev, char cap, unsigned int size)
2005{
2006 int pos;
2007 struct pci_cap_saved_state *save_state;
2008
2009 pos = pci_find_capability(dev, cap);
2010 if (pos <= 0)
2011 return 0;
2012
2013 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2014 if (!save_state)
2015 return -ENOMEM;
2016
24a4742f
AW		 2017 save_state->cap.cap_nr = cap;
2018 save_state->cap.size = size;
63f4898a
RW		 2019 pci_add_saved_cap(dev, save_state);
2020
2021 return 0;
2022}
2023
2024/**
2025 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2026 * @dev: the PCI device
2027 */
2028void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2029{
2030 int error;
2031
89858517
YZ		 2032 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2033 PCI_EXP_SAVE_REGS * sizeof(u16));
63f4898a
RW		 2034 if (error)
2035 dev_err(&dev->dev,
2036 "unable to preallocate PCI Express save buffer\n");
2037
2038 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2039 if (error)
2040 dev_err(&dev->dev,
2041 "unable to preallocate PCI-X save buffer\n");
2042}
2043
f796841e
YL		 2044void pci_free_cap_save_buffers(struct pci_dev *dev)
2045{
2046 struct pci_cap_saved_state *tmp;
b67bfe0d 2047 struct hlist_node *n;
f796841e 2048
b67bfe0d 2049 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
f796841e
YL		 2050 kfree(tmp);
2051}
2052
58c3a727 2053/**
31ab2476 2054 * pci_configure_ari - enable or disable ARI forwarding
58c3a727 2055 * @dev: the PCI device
b0cc6020
YW		 2056 *
2057 * If @dev and its upstream bridge both support ARI, enable ARI in the
2058 * bridge. Otherwise, disable ARI in the bridge.
58c3a727 2059 */
31ab2476 2060void pci_configure_ari(struct pci_dev *dev)
58c3a727 2061{
58c3a727 2062 u32 cap;
8113587c 2063 struct pci_dev *bridge;
58c3a727 2064
6748dcc2 2065 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
58c3a727
YZ		 2066 return;
2067
8113587c 2068 bridge = dev->bus->self;
cb97ae34 2069 if (!bridge)
8113587c
ZY		 2070 return;
2071
59875ae4 2072 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
58c3a727
YZ		 2073 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2074 return;
2075
b0cc6020
YW		 2076 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2077 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2078 PCI_EXP_DEVCTL2_ARI);
2079 bridge->ari_enabled = 1;
2080 } else {
2081 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2082 PCI_EXP_DEVCTL2_ARI);
2083 bridge->ari_enabled = 0;
2084 }
58c3a727
YZ		 2085}
2086
b48d4425 2087/**
c463b8cb 2088 * pci_enable_ido - enable ID-based Ordering on a device
b48d4425
JB		 2089 * @dev: the PCI device
2090 * @type: which types of IDO to enable
2091 *
2092 * Enable ID-based ordering on @dev. @type can contain the bits
2093 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
2094 * which types of transactions are allowed to be re-ordered.
2095 */
2096void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2097{
59875ae4 2098 u16 ctrl = 0;
b48d4425 2099
b48d4425
JB		 2100 if (type & PCI_EXP_IDO_REQUEST)
2101 ctrl |= PCI_EXP_IDO_REQ_EN;
2102 if (type & PCI_EXP_IDO_COMPLETION)
2103 ctrl |= PCI_EXP_IDO_CMP_EN;
59875ae4
JL		 2104 if (ctrl)
2105 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
b48d4425
JB		 2106}
2107EXPORT_SYMBOL(pci_enable_ido);
2108
2109/**
2110 * pci_disable_ido - disable ID-based ordering on a device
2111 * @dev: the PCI device
2112 * @type: which types of IDO to disable
2113 */
2114void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2115{
59875ae4 2116 u16 ctrl = 0;
b48d4425 2117
b48d4425 2118 if (type & PCI_EXP_IDO_REQUEST)
59875ae4 2119 ctrl |= PCI_EXP_IDO_REQ_EN;
b48d4425 2120 if (type & PCI_EXP_IDO_COMPLETION)
59875ae4
JL		 2121 ctrl |= PCI_EXP_IDO_CMP_EN;
2122 if (ctrl)
2123 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
b48d4425
JB		 2124}
2125EXPORT_SYMBOL(pci_disable_ido);
2126
48a92a81
JB		 2127/**
2128 * pci_enable_obff - enable optimized buffer flush/fill
2129 * @dev: PCI device
2130 * @type: type of signaling to use
2131 *
2132 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2133 * signaling if possible, falling back to message signaling only if
2134 * WAKE# isn't supported. @type should indicate whether the PCIe link
2135 * be brought out of L0s or L1 to send the message. It should be either
2136 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2137 *
2138 * If your device can benefit from receiving all messages, even at the
2139 * power cost of bringing the link back up from a low power state, use
2140 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2141 * preferred type).
2142 *
2143 * RETURNS:
2144 * Zero on success, appropriate error number on failure.
2145 */
2146int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2147{
48a92a81
JB		 2148 u32 cap;
2149 u16 ctrl;
2150 int ret;
2151
59875ae4 2152 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
48a92a81
JB		 2153 if (!(cap & PCI_EXP_OBFF_MASK))
2154 return -ENOTSUPP; /* no OBFF support at all */
2155
2156 /* Make sure the topology supports OBFF as well */
8291550f 2157 if (dev->bus->self) {
48a92a81
JB		 2158 ret = pci_enable_obff(dev->bus->self, type);
2159 if (ret)
2160 return ret;
2161 }
2162
59875ae4 2163 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
48a92a81
JB		 2164 if (cap & PCI_EXP_OBFF_WAKE)
2165 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2166 else {
2167 switch (type) {
2168 case PCI_EXP_OBFF_SIGNAL_L0:
2169 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2170 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2171 break;
2172 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2173 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2174 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2175 break;
2176 default:
2177 WARN(1, "bad OBFF signal type\n");
2178 return -ENOTSUPP;
2179 }
2180 }
59875ae4 2181 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
48a92a81
JB		 2182
2183 return 0;
2184}
2185EXPORT_SYMBOL(pci_enable_obff);
2186
2187/**
2188 * pci_disable_obff - disable optimized buffer flush/fill
2189 * @dev: PCI device
2190 *
2191 * Disable OBFF on @dev.
2192 */
2193void pci_disable_obff(struct pci_dev *dev)
2194{
59875ae4 2195 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
48a92a81
JB		 2196}
2197EXPORT_SYMBOL(pci_disable_obff);
2198
51c2e0a7
JB		 2199/**
2200 * pci_ltr_supported - check whether a device supports LTR
2201 * @dev: PCI device
2202 *
2203 * RETURNS:
2204 * True if @dev supports latency tolerance reporting, false otherwise.
2205 */
c32823f8 2206static bool pci_ltr_supported(struct pci_dev *dev)
51c2e0a7 2207{
51c2e0a7
JB		 2208 u32 cap;
2209
59875ae4 2210 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
51c2e0a7
JB		 2211
2212 return cap & PCI_EXP_DEVCAP2_LTR;
2213}
51c2e0a7
JB		 2214
2215/**
2216 * pci_enable_ltr - enable latency tolerance reporting
2217 * @dev: PCI device
2218 *
2219 * Enable LTR on @dev if possible, which means enabling it first on
2220 * upstream ports.
2221 *
2222 * RETURNS:
2223 * Zero on success, errno on failure.
2224 */
2225int pci_enable_ltr(struct pci_dev *dev)
2226{
51c2e0a7
JB		 2227 int ret;
2228
51c2e0a7
JB		 2229 /* Only primary function can enable/disable LTR */
2230 if (PCI_FUNC(dev->devfn) != 0)
2231 return -EINVAL;
2232
59875ae4
JL		 2233 if (!pci_ltr_supported(dev))
2234 return -ENOTSUPP;
2235
51c2e0a7 2236 /* Enable upstream ports first */
8291550f 2237 if (dev->bus->self) {
51c2e0a7
JB		 2238 ret = pci_enable_ltr(dev->bus->self);
2239 if (ret)
2240 return ret;
2241 }
2242
59875ae4 2243 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
51c2e0a7
JB		 2244}
2245EXPORT_SYMBOL(pci_enable_ltr);
2246
2247/**
2248 * pci_disable_ltr - disable latency tolerance reporting
2249 * @dev: PCI device
2250 */
2251void pci_disable_ltr(struct pci_dev *dev)
2252{
51c2e0a7
JB		 2253 /* Only primary function can enable/disable LTR */
2254 if (PCI_FUNC(dev->devfn) != 0)
2255 return;
2256
59875ae4
JL		 2257 if (!pci_ltr_supported(dev))
2258 return;
2259
2260 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
51c2e0a7
JB		 2261}
2262EXPORT_SYMBOL(pci_disable_ltr);
2263
2264static int __pci_ltr_scale(int *val)
2265{
2266 int scale = 0;
2267
2268 while (*val > 1023) {
2269 *val = (*val + 31) / 32;
2270 scale++;
2271 }
2272 return scale;
2273}
2274
2275/**
2276 * pci_set_ltr - set LTR latency values
2277 * @dev: PCI device
2278 * @snoop_lat_ns: snoop latency in nanoseconds
2279 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2280 *
2281 * Figure out the scale and set the LTR values accordingly.
2282 */
2283int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2284{
2285 int pos, ret, snoop_scale, nosnoop_scale;
2286 u16 val;
2287
2288 if (!pci_ltr_supported(dev))
2289 return -ENOTSUPP;
2290
2291 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2292 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2293
2294 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2295 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2296 return -EINVAL;
2297
2298 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2299 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2300 return -EINVAL;
2301
2302 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2303 if (!pos)
2304 return -ENOTSUPP;
2305
2306 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2307 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2308 if (ret != 4)
2309 return -EIO;
2310
2311 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2312 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2313 if (ret != 4)
2314 return -EIO;
2315
2316 return 0;
2317}
2318EXPORT_SYMBOL(pci_set_ltr);
2319
5d990b62
CW		 2320static int pci_acs_enable;
2321
2322/**
2323 * pci_request_acs - ask for ACS to be enabled if supported
2324 */
2325void pci_request_acs(void)
2326{
2327 pci_acs_enable = 1;
2328}
2329
ae21ee65
AK		 2330/**
2331 * pci_enable_acs - enable ACS if hardware support it
2332 * @dev: the PCI device
2333 */
2334void pci_enable_acs(struct pci_dev *dev)
2335{
2336 int pos;
2337 u16 cap;
2338 u16 ctrl;
2339
5d990b62
CW		 2340 if (!pci_acs_enable)
2341 return;
2342
ae21ee65
AK		 2343 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2344 if (!pos)
2345 return;
2346
2347 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2348 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2349
2350 /* Source Validation */
2351 ctrl |= (cap & PCI_ACS_SV);
2352
2353 /* P2P Request Redirect */
2354 ctrl |= (cap & PCI_ACS_RR);
2355
2356 /* P2P Completion Redirect */
2357 ctrl |= (cap & PCI_ACS_CR);
2358
2359 /* Upstream Forwarding */
2360 ctrl |= (cap & PCI_ACS_UF);
2361
2362 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2363}
2364
ad805758
AW		 2365/**
2366 * pci_acs_enabled - test ACS against required flags for a given device
2367 * @pdev: device to test
2368 * @acs_flags: required PCI ACS flags
2369 *
2370 * Return true if the device supports the provided flags. Automatically
2371 * filters out flags that are not implemented on multifunction devices.
2372 */
2373bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2374{
2375 int pos, ret;
2376 u16 ctrl;
2377
2378 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2379 if (ret >= 0)
2380 return ret > 0;
2381
2382 if (!pci_is_pcie(pdev))
2383 return false;
2384
2385 /* Filter out flags not applicable to multifunction */
2386 if (pdev->multifunction)
2387 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
2388 PCI_ACS_EC | PCI_ACS_DT);
2389
62f87c0e
YW		 2390 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM ||
2391 pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
ad805758
AW		 2392 pdev->multifunction) {
2393 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2394 if (!pos)
2395 return false;
2396
2397 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2398 if ((ctrl & acs_flags) != acs_flags)
2399 return false;
2400 }
2401
2402 return true;
2403}
2404
2405/**
2406 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2407 * @start: starting downstream device
2408 * @end: ending upstream device or NULL to search to the root bus
2409 * @acs_flags: required flags
2410 *
2411 * Walk up a device tree from start to end testing PCI ACS support. If
2412 * any step along the way does not support the required flags, return false.
2413 */
2414bool pci_acs_path_enabled(struct pci_dev *start,
2415 struct pci_dev *end, u16 acs_flags)
2416{
2417 struct pci_dev *pdev, *parent = start;
2418
2419 do {
2420 pdev = parent;
2421
2422 if (!pci_acs_enabled(pdev, acs_flags))
2423 return false;
2424
2425 if (pci_is_root_bus(pdev->bus))
2426 return (end == NULL);
2427
2428 parent = pdev->bus->self;
2429 } while (pdev != end);
2430
2431 return true;
2432}
2433
57c2cf71
BH		 2434/**
2435 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2436 * @dev: the PCI device
2437 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2438 *
2439 * Perform INTx swizzling for a device behind one level of bridge. This is
2440 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
46b952a3
MW		 2441 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2442 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2443 * the PCI Express Base Specification, Revision 2.1)
57c2cf71 2444 */
3df425f3 2445u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
57c2cf71 2446{
46b952a3
MW		 2447 int slot;
2448
2449 if (pci_ari_enabled(dev->bus))
2450 slot = 0;
2451 else
2452 slot = PCI_SLOT(dev->devfn);
2453
2454 return (((pin - 1) + slot) % 4) + 1;
57c2cf71
BH		 2455}
2456
1da177e4
LT		 2457int
2458pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2459{
2460 u8 pin;
2461
514d207d 2462 pin = dev->pin;
1da177e4
LT		 2463 if (!pin)
2464 return -1;
878f2e50 2465
8784fd4d 2466 while (!pci_is_root_bus(dev->bus)) {
57c2cf71 2467 pin = pci_swizzle_interrupt_pin(dev, pin);
1da177e4
LT		 2468 dev = dev->bus->self;
2469 }
2470 *bridge = dev;
2471 return pin;
2472}
2473
68feac87
BH		 2474/**
2475 * pci_common_swizzle - swizzle INTx all the way to root bridge
2476 * @dev: the PCI device
2477 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2478 *
2479 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2480 * bridges all the way up to a PCI root bus.
2481 */
2482u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2483{
2484 u8 pin = *pinp;
2485
1eb39487 2486 while (!pci_is_root_bus(dev->bus)) {
68feac87
BH		 2487 pin = pci_swizzle_interrupt_pin(dev, pin);
2488 dev = dev->bus->self;
2489 }
2490 *pinp = pin;
2491 return PCI_SLOT(dev->devfn);
2492}
2493
1da177e4
LT		 2494/**
2495 * pci_release_region - Release a PCI bar
2496 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2497 * @bar: BAR to release
2498 *
2499 * Releases the PCI I/O and memory resources previously reserved by a
2500 * successful call to pci_request_region. Call this function only
2501 * after all use of the PCI regions has ceased.
2502 */
2503void pci_release_region(struct pci_dev *pdev, int bar)
2504{
9ac7849e
TH		 2505 struct pci_devres *dr;
2506
1da177e4
LT		 2507 if (pci_resource_len(pdev, bar) == 0)
2508 return;
2509 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2510 release_region(pci_resource_start(pdev, bar),
2511 pci_resource_len(pdev, bar));
2512 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2513 release_mem_region(pci_resource_start(pdev, bar),
2514 pci_resource_len(pdev, bar));
9ac7849e
TH		 2515
2516 dr = find_pci_dr(pdev);
2517 if (dr)
2518 dr->region_mask &= ~(1 << bar);
1da177e4
LT		 2519}
2520
2521/**
f5ddcac4 2522 * __pci_request_region - Reserved PCI I/O and memory resource
1da177e4
LT		 2523 * @pdev: PCI device whose resources are to be reserved
2524 * @bar: BAR to be reserved
2525 * @res_name: Name to be associated with resource.
f5ddcac4 2526 * @exclusive: whether the region access is exclusive or not
1da177e4
LT		 2527 *
2528 * Mark the PCI region associated with PCI device @pdev BR @bar as
2529 * being reserved by owner @res_name. Do not access any
2530 * address inside the PCI regions unless this call returns
2531 * successfully.
2532 *
f5ddcac4
RD		 2533 * If @exclusive is set, then the region is marked so that userspace
2534 * is explicitly not allowed to map the resource via /dev/mem or
2535 * sysfs MMIO access.
2536 *
1da177e4
LT		 2537 * Returns 0 on success, or %EBUSY on error. A warning
2538 * message is also printed on failure.
2539 */
e8de1481
AV		 2540static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2541 int exclusive)
1da177e4 2542{
9ac7849e
TH		 2543 struct pci_devres *dr;
2544
1da177e4
LT		 2545 if (pci_resource_len(pdev, bar) == 0)
2546 return 0;
2547
2548 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2549 if (!request_region(pci_resource_start(pdev, bar),
2550 pci_resource_len(pdev, bar), res_name))
2551 goto err_out;
2552 }
2553 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
e8de1481
AV		 2554 if (!__request_mem_region(pci_resource_start(pdev, bar),
2555 pci_resource_len(pdev, bar), res_name,
2556 exclusive))
1da177e4
LT		 2557 goto err_out;
2558 }
9ac7849e
TH		 2559
2560 dr = find_pci_dr(pdev);
2561 if (dr)
2562 dr->region_mask |= 1 << bar;
2563
1da177e4
LT		 2564 return 0;
2565
2566err_out:
c7dabef8 2567 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
096e6f67 2568 &pdev->resource[bar]);
1da177e4
LT		 2569 return -EBUSY;
2570}
2571
e8de1481 2572/**
f5ddcac4 2573 * pci_request_region - Reserve PCI I/O and memory resource
e8de1481
AV		 2574 * @pdev: PCI device whose resources are to be reserved
2575 * @bar: BAR to be reserved
f5ddcac4 2576 * @res_name: Name to be associated with resource
e8de1481 2577 *
f5ddcac4 2578 * Mark the PCI region associated with PCI device @pdev BAR @bar as
e8de1481
AV		 2579 * being reserved by owner @res_name. Do not access any
2580 * address inside the PCI regions unless this call returns
2581 * successfully.
2582 *
2583 * Returns 0 on success, or %EBUSY on error. A warning
2584 * message is also printed on failure.
2585 */
2586int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2587{
2588 return __pci_request_region(pdev, bar, res_name, 0);
2589}
2590
2591/**
2592 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2593 * @pdev: PCI device whose resources are to be reserved
2594 * @bar: BAR to be reserved
2595 * @res_name: Name to be associated with resource.
2596 *
2597 * Mark the PCI region associated with PCI device @pdev BR @bar as
2598 * being reserved by owner @res_name. Do not access any
2599 * address inside the PCI regions unless this call returns
2600 * successfully.
2601 *
2602 * Returns 0 on success, or %EBUSY on error. A warning
2603 * message is also printed on failure.
2604 *
2605 * The key difference that _exclusive makes it that userspace is
2606 * explicitly not allowed to map the resource via /dev/mem or
2607 * sysfs.
2608 */
2609int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2610{
2611 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2612}
c87deff7
HS		 2613/**
2614 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2615 * @pdev: PCI device whose resources were previously reserved
2616 * @bars: Bitmask of BARs to be released
2617 *
2618 * Release selected PCI I/O and memory resources previously reserved.
2619 * Call this function only after all use of the PCI regions has ceased.
2620 */
2621void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2622{
2623 int i;
2624
2625 for (i = 0; i < 6; i++)
2626 if (bars & (1 << i))
2627 pci_release_region(pdev, i);
2628}
2629
9738abed 2630static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
e8de1481 2631 const char *res_name, int excl)
c87deff7
HS		 2632{
2633 int i;
2634
2635 for (i = 0; i < 6; i++)
2636 if (bars & (1 << i))
e8de1481 2637 if (__pci_request_region(pdev, i, res_name, excl))
c87deff7
HS		 2638 goto err_out;
2639 return 0;
2640
2641err_out:
2642 while(--i >= 0)
2643 if (bars & (1 << i))
2644 pci_release_region(pdev, i);
2645
2646 return -EBUSY;
2647}
1da177e4 2648
e8de1481
AV		 2649
2650/**
2651 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2652 * @pdev: PCI device whose resources are to be reserved
2653 * @bars: Bitmask of BARs to be requested
2654 * @res_name: Name to be associated with resource
2655 */
2656int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2657 const char *res_name)
2658{
2659 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2660}
2661
2662int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2663 int bars, const char *res_name)
2664{
2665 return __pci_request_selected_regions(pdev, bars, res_name,
2666 IORESOURCE_EXCLUSIVE);
2667}
2668
1da177e4
LT		 2669/**
2670 * pci_release_regions - Release reserved PCI I/O and memory resources
2671 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2672 *
2673 * Releases all PCI I/O and memory resources previously reserved by a
2674 * successful call to pci_request_regions. Call this function only
2675 * after all use of the PCI regions has ceased.
2676 */
2677
2678void pci_release_regions(struct pci_dev *pdev)
2679{
c87deff7 2680 pci_release_selected_regions(pdev, (1 << 6) - 1);
1da177e4
LT		 2681}
2682
2683/**
2684 * pci_request_regions - Reserved PCI I/O and memory resources
2685 * @pdev: PCI device whose resources are to be reserved
2686 * @res_name: Name to be associated with resource.
2687 *
2688 * Mark all PCI regions associated with PCI device @pdev as
2689 * being reserved by owner @res_name. Do not access any
2690 * address inside the PCI regions unless this call returns
2691 * successfully.
2692 *
2693 * Returns 0 on success, or %EBUSY on error. A warning
2694 * message is also printed on failure.
2695 */
3c990e92 2696int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1da177e4 2697{
c87deff7 2698 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1da177e4
LT		 2699}
2700
e8de1481
AV		 2701/**
2702 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2703 * @pdev: PCI device whose resources are to be reserved
2704 * @res_name: Name to be associated with resource.
2705 *
2706 * Mark all PCI regions associated with PCI device @pdev as
2707 * being reserved by owner @res_name. Do not access any
2708 * address inside the PCI regions unless this call returns
2709 * successfully.
2710 *
2711 * pci_request_regions_exclusive() will mark the region so that
2712 * /dev/mem and the sysfs MMIO access will not be allowed.
2713 *
2714 * Returns 0 on success, or %EBUSY on error. A warning
2715 * message is also printed on failure.
2716 */
2717int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2718{
2719 return pci_request_selected_regions_exclusive(pdev,
2720 ((1 << 6) - 1), res_name);
2721}
2722
6a479079
BH		 2723static void __pci_set_master(struct pci_dev *dev, bool enable)
2724{
2725 u16 old_cmd, cmd;
2726
2727 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2728 if (enable)
2729 cmd = old_cmd | PCI_COMMAND_MASTER;
2730 else
2731 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2732 if (cmd != old_cmd) {
2733 dev_dbg(&dev->dev, "%s bus mastering\n",
2734 enable ? "enabling" : "disabling");
2735 pci_write_config_word(dev, PCI_COMMAND, cmd);
2736 }
2737 dev->is_busmaster = enable;
2738}
e8de1481 2739
2b6f2c35
MS		 2740/**
2741 * pcibios_setup - process "pci=" kernel boot arguments
2742 * @str: string used to pass in "pci=" kernel boot arguments
2743 *
2744 * Process kernel boot arguments. This is the default implementation.
2745 * Architecture specific implementations can override this as necessary.
2746 */
2747char * __weak __init pcibios_setup(char *str)
2748{
2749 return str;
2750}
2751
96c55900
MS		 2752/**
2753 * pcibios_set_master - enable PCI bus-mastering for device dev
2754 * @dev: the PCI device to enable
2755 *
2756 * Enables PCI bus-mastering for the device. This is the default
2757 * implementation. Architecture specific implementations can override
2758 * this if necessary.
2759 */
2760void __weak pcibios_set_master(struct pci_dev *dev)
2761{
2762 u8 lat;
2763
f676678f
MS		 2764 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2765 if (pci_is_pcie(dev))
2766 return;
2767
96c55900
MS		 2768 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2769 if (lat < 16)
2770 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2771 else if (lat > pcibios_max_latency)
2772 lat = pcibios_max_latency;
2773 else
2774 return;
2775 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
2776 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2777}
2778
1da177e4
LT		 2779/**
2780 * pci_set_master - enables bus-mastering for device dev
2781 * @dev: the PCI device to enable
2782 *
2783 * Enables bus-mastering on the device and calls pcibios_set_master()
2784 * to do the needed arch specific settings.
2785 */
6a479079 2786void pci_set_master(struct pci_dev *dev)
1da177e4 2787{
6a479079 2788 __pci_set_master(dev, true);
1da177e4
LT		 2789 pcibios_set_master(dev);
2790}
2791
6a479079
BH		 2792/**
2793 * pci_clear_master - disables bus-mastering for device dev
2794 * @dev: the PCI device to disable
2795 */
2796void pci_clear_master(struct pci_dev *dev)
2797{
2798 __pci_set_master(dev, false);
2799}
2800
1da177e4 2801/**
edb2d97e
MW		 2802 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2803 * @dev: the PCI device for which MWI is to be enabled
1da177e4 2804 *
edb2d97e
MW		 2805 * Helper function for pci_set_mwi.
2806 * Originally copied from drivers/net/acenic.c.
1da177e4
LT		 2807 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2808 *
2809 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2810 */
15ea76d4 2811int pci_set_cacheline_size(struct pci_dev *dev)
1da177e4
LT		 2812{
2813 u8 cacheline_size;
2814
2815 if (!pci_cache_line_size)
15ea76d4 2816 return -EINVAL;
1da177e4
LT		 2817
2818 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2819 equal to or multiple of the right value. */
2820 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2821 if (cacheline_size >= pci_cache_line_size &&
2822 (cacheline_size % pci_cache_line_size) == 0)
2823 return 0;
2824
2825 /* Write the correct value. */
2826 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2827 /* Read it back. */
2828 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2829 if (cacheline_size == pci_cache_line_size)
2830 return 0;
2831
80ccba11
BH		 2832 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2833 "supported\n", pci_cache_line_size << 2);
1da177e4
LT		 2834
2835 return -EINVAL;
2836}
15ea76d4
TH		 2837EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2838
2839#ifdef PCI_DISABLE_MWI
2840int pci_set_mwi(struct pci_dev *dev)
2841{
2842 return 0;
2843}
2844
2845int pci_try_set_mwi(struct pci_dev *dev)
2846{
2847 return 0;
2848}
2849
2850void pci_clear_mwi(struct pci_dev *dev)
2851{
2852}
2853
2854#else
1da177e4
LT		 2855
2856/**
2857 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2858 * @dev: the PCI device for which MWI is enabled
2859 *
694625c0 2860 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1da177e4
LT		 2861 *
2862 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2863 */
2864int
2865pci_set_mwi(struct pci_dev *dev)
2866{
2867 int rc;
2868 u16 cmd;
2869
edb2d97e 2870 rc = pci_set_cacheline_size(dev);
1da177e4
LT		 2871 if (rc)
2872 return rc;
2873
2874 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2875 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
80ccba11 2876 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1da177e4
LT		 2877 cmd |= PCI_COMMAND_INVALIDATE;
2878 pci_write_config_word(dev, PCI_COMMAND, cmd);
2879 }
2880
2881 return 0;
2882}
2883
694625c0
RD		 2884/**
2885 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2886 * @dev: the PCI device for which MWI is enabled
2887 *
2888 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2889 * Callers are not required to check the return value.
2890 *
2891 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2892 */
2893int pci_try_set_mwi(struct pci_dev *dev)
2894{
2895 int rc = pci_set_mwi(dev);
2896 return rc;
2897}
2898
1da177e4
LT		 2899/**
2900 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2901 * @dev: the PCI device to disable
2902 *
2903 * Disables PCI Memory-Write-Invalidate transaction on the device
2904 */
2905void
2906pci_clear_mwi(struct pci_dev *dev)
2907{
2908 u16 cmd;
2909
2910 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2911 if (cmd & PCI_COMMAND_INVALIDATE) {
2912 cmd &= ~PCI_COMMAND_INVALIDATE;
2913 pci_write_config_word(dev, PCI_COMMAND, cmd);
2914 }
2915}
edb2d97e 2916#endif /* ! PCI_DISABLE_MWI */
1da177e4 2917
a04ce0ff
BR		 2918/**
2919 * pci_intx - enables/disables PCI INTx for device dev
8f7020d3
RD		 2920 * @pdev: the PCI device to operate on
2921 * @enable: boolean: whether to enable or disable PCI INTx
a04ce0ff
BR		 2922 *
2923 * Enables/disables PCI INTx for device dev
2924 */
2925void
2926pci_intx(struct pci_dev *pdev, int enable)
2927{
2928 u16 pci_command, new;
2929
2930 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2931
2932 if (enable) {
2933 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2934 } else {
2935 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2936 }
2937
2938 if (new != pci_command) {
9ac7849e
TH		 2939 struct pci_devres *dr;
2940
2fd9d74b 2941 pci_write_config_word(pdev, PCI_COMMAND, new);
9ac7849e
TH		 2942
2943 dr = find_pci_dr(pdev);
2944 if (dr && !dr->restore_intx) {
2945 dr->restore_intx = 1;
2946 dr->orig_intx = !enable;
2947 }
a04ce0ff
BR		 2948 }
2949}
2950
a2e27787
JK		 2951/**
2952 * pci_intx_mask_supported - probe for INTx masking support
6e9292c5 2953 * @dev: the PCI device to operate on
a2e27787
JK		 2954 *
2955 * Check if the device dev support INTx masking via the config space
2956 * command word.
2957 */
2958bool pci_intx_mask_supported(struct pci_dev *dev)
2959{
2960 bool mask_supported = false;
2961 u16 orig, new;
2962
fbebb9fd
BH		 2963 if (dev->broken_intx_masking)
2964 return false;
2965
a2e27787
JK		 2966 pci_cfg_access_lock(dev);
2967
2968 pci_read_config_word(dev, PCI_COMMAND, &orig);
2969 pci_write_config_word(dev, PCI_COMMAND,
2970 orig ^ PCI_COMMAND_INTX_DISABLE);
2971 pci_read_config_word(dev, PCI_COMMAND, &new);
2972
2973 /*
2974 * There's no way to protect against hardware bugs or detect them
2975 * reliably, but as long as we know what the value should be, let's
2976 * go ahead and check it.
2977 */
2978 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2979 dev_err(&dev->dev, "Command register changed from "
2980 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2981 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2982 mask_supported = true;
2983 pci_write_config_word(dev, PCI_COMMAND, orig);
2984 }
2985
2986 pci_cfg_access_unlock(dev);
2987 return mask_supported;
2988}
2989EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2990
2991static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2992{
2993 struct pci_bus *bus = dev->bus;
2994 bool mask_updated = true;
2995 u32 cmd_status_dword;
2996 u16 origcmd, newcmd;
2997 unsigned long flags;
2998 bool irq_pending;
2999
3000 /*
3001 * We do a single dword read to retrieve both command and status.
3002 * Document assumptions that make this possible.
3003 */
3004 BUILD_BUG_ON(PCI_COMMAND % 4);
3005 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3006
3007 raw_spin_lock_irqsave(&pci_lock, flags);
3008
3009 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3010
3011 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3012
3013 /*
3014 * Check interrupt status register to see whether our device
3015 * triggered the interrupt (when masking) or the next IRQ is
3016 * already pending (when unmasking).
3017 */
3018 if (mask != irq_pending) {
3019 mask_updated = false;
3020 goto done;
3021 }
3022
3023 origcmd = cmd_status_dword;
3024 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3025 if (mask)
3026 newcmd |= PCI_COMMAND_INTX_DISABLE;
3027 if (newcmd != origcmd)
3028 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3029
3030done:
3031 raw_spin_unlock_irqrestore(&pci_lock, flags);
3032
3033 return mask_updated;
3034}
3035
3036/**
3037 * pci_check_and_mask_intx - mask INTx on pending interrupt
6e9292c5 3038 * @dev: the PCI device to operate on
a2e27787
JK		 3039 *
3040 * Check if the device dev has its INTx line asserted, mask it and
3041 * return true in that case. False is returned if not interrupt was
3042 * pending.
3043 */
3044bool pci_check_and_mask_intx(struct pci_dev *dev)
3045{
3046 return pci_check_and_set_intx_mask(dev, true);
3047}
3048EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3049
3050/**
3051 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
6e9292c5 3052 * @dev: the PCI device to operate on
a2e27787
JK		 3053 *
3054 * Check if the device dev has its INTx line asserted, unmask it if not
3055 * and return true. False is returned and the mask remains active if
3056 * there was still an interrupt pending.
3057 */
3058bool pci_check_and_unmask_intx(struct pci_dev *dev)
3059{
3060 return pci_check_and_set_intx_mask(dev, false);
3061}
3062EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3063
f5f2b131
EB		 3064/**
3065 * pci_msi_off - disables any msi or msix capabilities
8d7d86e9 3066 * @dev: the PCI device to operate on
f5f2b131
EB		 3067 *
3068 * If you want to use msi see pci_enable_msi and friends.
3069 * This is a lower level primitive that allows us to disable
3070 * msi operation at the device level.
3071 */
3072void pci_msi_off(struct pci_dev *dev)
3073{
3074 int pos;
3075 u16 control;
3076
3077 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3078 if (pos) {
3079 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3080 control &= ~PCI_MSI_FLAGS_ENABLE;
3081 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3082 }
3083 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3084 if (pos) {
3085 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3086 control &= ~PCI_MSIX_FLAGS_ENABLE;
3087 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3088 }
3089}
b03214d5 3090EXPORT_SYMBOL_GPL(pci_msi_off);
f5f2b131 3091
4d57cdfa
FT		 3092int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3093{
3094 return dma_set_max_seg_size(&dev->dev, size);
3095}
3096EXPORT_SYMBOL(pci_set_dma_max_seg_size);
4d57cdfa 3097
59fc67de
FT		 3098int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3099{
3100 return dma_set_seg_boundary(&dev->dev, mask);
3101}
3102EXPORT_SYMBOL(pci_set_dma_seg_boundary);
59fc67de 3103
8c1c699f 3104static int pcie_flr(struct pci_dev *dev, int probe)
8dd7f803 3105{
8c1c699f 3106 int i;
8dd7f803 3107 u32 cap;
59875ae4 3108 u16 status;
8c1c699f 3109
59875ae4 3110 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
8dd7f803
SY		 3111 if (!(cap & PCI_EXP_DEVCAP_FLR))
3112 return -ENOTTY;
3113
d91cdc74
SY		 3114 if (probe)
3115 return 0;
3116
8dd7f803 3117 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 3118 for (i = 0; i < 4; i++) {
3119 if (i)
3120 msleep((1 << (i - 1)) * 100);
5fe5db05 3121
59875ae4 3122 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
8c1c699f
YZ		 3123 if (!(status & PCI_EXP_DEVSTA_TRPND))
3124 goto clear;
3125 }
3126
3127 dev_err(&dev->dev, "transaction is not cleared; "
3128 "proceeding with reset anyway\n");
3129
3130clear:
59875ae4 3131 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
04b55c47 3132
8c1c699f 3133 msleep(100);
8dd7f803 3134
8dd7f803
SY		 3135 return 0;
3136}
d91cdc74 3137
8c1c699f 3138static int pci_af_flr(struct pci_dev *dev, int probe)
1ca88797 3139{
8c1c699f
YZ		 3140 int i;
3141 int pos;
1ca88797 3142 u8 cap;
8c1c699f 3143 u8 status;
1ca88797 3144
8c1c699f
YZ		 3145 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3146 if (!pos)
1ca88797 3147 return -ENOTTY;
8c1c699f
YZ		 3148
3149 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
1ca88797
SY		 3150 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3151 return -ENOTTY;
3152
3153 if (probe)
3154 return 0;
3155
1ca88797 3156 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 3157 for (i = 0; i < 4; i++) {
3158 if (i)
3159 msleep((1 << (i - 1)) * 100);
3160
3161 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3162 if (!(status & PCI_AF_STATUS_TP))
3163 goto clear;
3164 }
5fe5db05 3165
8c1c699f
YZ		 3166 dev_err(&dev->dev, "transaction is not cleared; "
3167 "proceeding with reset anyway\n");
5fe5db05 3168
8c1c699f
YZ		 3169clear:
3170 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
1ca88797 3171 msleep(100);
8c1c699f 3172
1ca88797
SY		 3173 return 0;
3174}
3175
83d74e03
RW		 3176/**
3177 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3178 * @dev: Device to reset.
3179 * @probe: If set, only check if the device can be reset this way.
3180 *
3181 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3182 * unset, it will be reinitialized internally when going from PCI_D3hot to
3183 * PCI_D0. If that's the case and the device is not in a low-power state
3184 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3185 *
3186 * NOTE: This causes the caller to sleep for twice the device power transition
3187 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3188 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3189 * Moreover, only devices in D0 can be reset by this function.
3190 */
f85876ba 3191static int pci_pm_reset(struct pci_dev *dev, int probe)
d91cdc74 3192{
f85876ba
YZ		 3193 u16 csr;
3194
3195 if (!dev->pm_cap)
3196 return -ENOTTY;
d91cdc74 3197
f85876ba
YZ		 3198 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3199 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3200 return -ENOTTY;
d91cdc74 3201
f85876ba
YZ		 3202 if (probe)
3203 return 0;
1ca88797 3204
f85876ba
YZ		 3205 if (dev->current_state != PCI_D0)
3206 return -EINVAL;
3207
3208 csr &= ~PCI_PM_CTRL_STATE_MASK;
3209 csr |= PCI_D3hot;
3210 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 3211 pci_dev_d3_sleep(dev);
f85876ba
YZ		 3212
3213 csr &= ~PCI_PM_CTRL_STATE_MASK;
3214 csr |= PCI_D0;
3215 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 3216 pci_dev_d3_sleep(dev);
f85876ba
YZ		 3217
3218 return 0;
3219}
3220
c12ff1df
YZ		 3221static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3222{
3223 u16 ctrl;
3224 struct pci_dev *pdev;
3225
654b75e0 3226 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
c12ff1df
YZ		 3227 return -ENOTTY;
3228
3229 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3230 if (pdev != dev)
3231 return -ENOTTY;
3232
3233 if (probe)
3234 return 0;
3235
3236 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
3237 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3238 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3239 msleep(100);
3240
3241 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3242 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3243 msleep(100);
3244
3245 return 0;
3246}
3247
977f857c 3248static int __pci_dev_reset(struct pci_dev *dev, int probe)
d91cdc74 3249{
8c1c699f
YZ		 3250 int rc;
3251
3252 might_sleep();
3253
b9c3b266
DC		 3254 rc = pci_dev_specific_reset(dev, probe);
3255 if (rc != -ENOTTY)
3256 goto done;
3257
8c1c699f
YZ		 3258 rc = pcie_flr(dev, probe);
3259 if (rc != -ENOTTY)
3260 goto done;
d91cdc74 3261
8c1c699f 3262 rc = pci_af_flr(dev, probe);
f85876ba
YZ		 3263 if (rc != -ENOTTY)
3264 goto done;
3265
3266 rc = pci_pm_reset(dev, probe);
c12ff1df
YZ		 3267 if (rc != -ENOTTY)
3268 goto done;
3269
3270 rc = pci_parent_bus_reset(dev, probe);
8c1c699f 3271done:
977f857c
KRW		 3272 return rc;
3273}
3274
3275static int pci_dev_reset(struct pci_dev *dev, int probe)
3276{
3277 int rc;
3278
3279 if (!probe) {
3280 pci_cfg_access_lock(dev);
3281 /* block PM suspend, driver probe, etc. */
3282 device_lock(&dev->dev);
3283 }
3284
3285 rc = __pci_dev_reset(dev, probe);
3286
8c1c699f 3287 if (!probe) {
8e9394ce 3288 device_unlock(&dev->dev);
fb51ccbf 3289 pci_cfg_access_unlock(dev);
8c1c699f 3290 }
8c1c699f 3291 return rc;
d91cdc74 3292}
d91cdc74 3293/**
8c1c699f
YZ		 3294 * __pci_reset_function - reset a PCI device function
3295 * @dev: PCI device to reset
d91cdc74
SY		 3296 *
3297 * Some devices allow an individual function to be reset without affecting
3298 * other functions in the same device. The PCI device must be responsive
3299 * to PCI config space in order to use this function.
3300 *
3301 * The device function is presumed to be unused when this function is called.
3302 * Resetting the device will make the contents of PCI configuration space
3303 * random, so any caller of this must be prepared to reinitialise the
3304 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3305 * etc.
3306 *
8c1c699f 3307 * Returns 0 if the device function was successfully reset or negative if the
d91cdc74
SY		 3308 * device doesn't support resetting a single function.
3309 */
8c1c699f 3310int __pci_reset_function(struct pci_dev *dev)
d91cdc74 3311{
8c1c699f 3312 return pci_dev_reset(dev, 0);
d91cdc74 3313}
8c1c699f 3314EXPORT_SYMBOL_GPL(__pci_reset_function);
8dd7f803 3315
6fbf9e7a
KRW		 3316/**
3317 * __pci_reset_function_locked - reset a PCI device function while holding
3318 * the @dev mutex lock.
3319 * @dev: PCI device to reset
3320 *
3321 * Some devices allow an individual function to be reset without affecting
3322 * other functions in the same device. The PCI device must be responsive
3323 * to PCI config space in order to use this function.
3324 *
3325 * The device function is presumed to be unused and the caller is holding
3326 * the device mutex lock when this function is called.
3327 * Resetting the device will make the contents of PCI configuration space
3328 * random, so any caller of this must be prepared to reinitialise the
3329 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3330 * etc.
3331 *
3332 * Returns 0 if the device function was successfully reset or negative if the
3333 * device doesn't support resetting a single function.
3334 */
3335int __pci_reset_function_locked(struct pci_dev *dev)
3336{
977f857c 3337 return __pci_dev_reset(dev, 0);
6fbf9e7a
KRW		 3338}
3339EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3340
711d5779
MT		 3341/**
3342 * pci_probe_reset_function - check whether the device can be safely reset
3343 * @dev: PCI device to reset
3344 *
3345 * Some devices allow an individual function to be reset without affecting
3346 * other functions in the same device. The PCI device must be responsive
3347 * to PCI config space in order to use this function.
3348 *
3349 * Returns 0 if the device function can be reset or negative if the
3350 * device doesn't support resetting a single function.
3351 */
3352int pci_probe_reset_function(struct pci_dev *dev)
3353{
3354 return pci_dev_reset(dev, 1);
3355}
3356
8dd7f803 3357/**
8c1c699f
YZ		 3358 * pci_reset_function - quiesce and reset a PCI device function
3359 * @dev: PCI device to reset
8dd7f803
SY		 3360 *
3361 * Some devices allow an individual function to be reset without affecting
3362 * other functions in the same device. The PCI device must be responsive
3363 * to PCI config space in order to use this function.
3364 *
3365 * This function does not just reset the PCI portion of a device, but
3366 * clears all the state associated with the device. This function differs
8c1c699f 3367 * from __pci_reset_function in that it saves and restores device state
8dd7f803
SY		 3368 * over the reset.
3369 *
8c1c699f 3370 * Returns 0 if the device function was successfully reset or negative if the
8dd7f803
SY		 3371 * device doesn't support resetting a single function.
3372 */
3373int pci_reset_function(struct pci_dev *dev)
3374{
8c1c699f 3375 int rc;
8dd7f803 3376
8c1c699f
YZ		 3377 rc = pci_dev_reset(dev, 1);
3378 if (rc)
3379 return rc;
8dd7f803 3380
8dd7f803
SY		 3381 pci_save_state(dev);
3382
8c1c699f
YZ		 3383 /*
3384 * both INTx and MSI are disabled after the Interrupt Disable bit
3385 * is set and the Bus Master bit is cleared.
3386 */
8dd7f803
SY		 3387 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3388
8c1c699f 3389 rc = pci_dev_reset(dev, 0);
8dd7f803
SY		 3390
3391 pci_restore_state(dev);
8dd7f803 3392
8c1c699f 3393 return rc;
8dd7f803
SY		 3394}
3395EXPORT_SYMBOL_GPL(pci_reset_function);
3396
d556ad4b
PO		 3397/**
3398 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3399 * @dev: PCI device to query
3400 *
3401 * Returns mmrbc: maximum designed memory read count in bytes
3402 * or appropriate error value.
3403 */
3404int pcix_get_max_mmrbc(struct pci_dev *dev)
3405{
7c9e2b1c 3406 int cap;
d556ad4b
PO		 3407 u32 stat;
3408
3409 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3410 if (!cap)
3411 return -EINVAL;
3412
7c9e2b1c 3413 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
d556ad4b
PO		 3414 return -EINVAL;
3415
25daeb55 3416 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
d556ad4b
PO		 3417}
3418EXPORT_SYMBOL(pcix_get_max_mmrbc);
3419
3420/**
3421 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3422 * @dev: PCI device to query
3423 *
3424 * Returns mmrbc: maximum memory read count in bytes
3425 * or appropriate error value.
3426 */
3427int pcix_get_mmrbc(struct pci_dev *dev)
3428{
7c9e2b1c 3429 int cap;
bdc2bda7 3430 u16 cmd;
d556ad4b
PO		 3431
3432 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3433 if (!cap)
3434 return -EINVAL;
3435
7c9e2b1c
DN		 3436 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3437 return -EINVAL;
d556ad4b 3438
7c9e2b1c 3439 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
d556ad4b
PO		 3440}
3441EXPORT_SYMBOL(pcix_get_mmrbc);
3442
3443/**
3444 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3445 * @dev: PCI device to query
3446 * @mmrbc: maximum memory read count in bytes
3447 * valid values are 512, 1024, 2048, 4096
3448 *
3449 * If possible sets maximum memory read byte count, some bridges have erratas
3450 * that prevent this.
3451 */
3452int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3453{
7c9e2b1c 3454 int cap;
bdc2bda7
DN		 3455 u32 stat, v, o;
3456 u16 cmd;
d556ad4b 3457
229f5afd 3458 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
7c9e2b1c 3459 return -EINVAL;
d556ad4b
PO		 3460
3461 v = ffs(mmrbc) - 10;
3462
3463 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3464 if (!cap)
7c9e2b1c 3465 return -EINVAL;
d556ad4b 3466
7c9e2b1c
DN		 3467 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3468 return -EINVAL;
d556ad4b
PO		 3469
3470 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3471 return -E2BIG;
3472
7c9e2b1c
DN		 3473 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3474 return -EINVAL;
d556ad4b
PO		 3475
3476 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3477 if (o != v) {
809a3bf9 3478 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
d556ad4b
PO		 3479 return -EIO;
3480
3481 cmd &= ~PCI_X_CMD_MAX_READ;
3482 cmd |= v << 2;
7c9e2b1c
DN		 3483 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3484 return -EIO;
d556ad4b 3485 }
7c9e2b1c 3486 return 0;
d556ad4b
PO		 3487}
3488EXPORT_SYMBOL(pcix_set_mmrbc);
3489
3490/**
3491 * pcie_get_readrq - get PCI Express read request size
3492 * @dev: PCI device to query
3493 *
3494 * Returns maximum memory read request in bytes
3495 * or appropriate error value.
3496 */
3497int pcie_get_readrq(struct pci_dev *dev)
3498{
d556ad4b
PO		 3499 u16 ctl;
3500
59875ae4 3501 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
d556ad4b 3502
59875ae4 3503 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
d556ad4b
PO		 3504}
3505EXPORT_SYMBOL(pcie_get_readrq);
3506
3507/**
3508 * pcie_set_readrq - set PCI Express maximum memory read request
3509 * @dev: PCI device to query
42e61f4a 3510 * @rq: maximum memory read count in bytes
d556ad4b
PO		 3511 * valid values are 128, 256, 512, 1024, 2048, 4096
3512 *
c9b378c7 3513 * If possible sets maximum memory read request in bytes
d556ad4b
PO		 3514 */
3515int pcie_set_readrq(struct pci_dev *dev, int rq)
3516{
59875ae4 3517 u16 v;
d556ad4b 3518
229f5afd 3519 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
59875ae4 3520 return -EINVAL;
d556ad4b 3521
a1c473aa
BH		 3522 /*
3523 * If using the "performance" PCIe config, we clamp the
3524 * read rq size to the max packet size to prevent the
3525 * host bridge generating requests larger than we can
3526 * cope with
3527 */
3528 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3529 int mps = pcie_get_mps(dev);
3530
3531 if (mps < 0)
3532 return mps;
3533 if (mps < rq)
3534 rq = mps;
3535 }
3536
3537 v = (ffs(rq) - 8) << 12;
d556ad4b 3538
59875ae4
JL		 3539 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3540 PCI_EXP_DEVCTL_READRQ, v);
d556ad4b
PO		 3541}
3542EXPORT_SYMBOL(pcie_set_readrq);
3543
b03e7495
JM		 3544/**
3545 * pcie_get_mps - get PCI Express maximum payload size
3546 * @dev: PCI device to query
3547 *
3548 * Returns maximum payload size in bytes
3549 * or appropriate error value.
3550 */
3551int pcie_get_mps(struct pci_dev *dev)
3552{
b03e7495
JM		 3553 u16 ctl;
3554
59875ae4 3555 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
b03e7495 3556
59875ae4 3557 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
b03e7495
JM		 3558}
3559
3560/**
3561 * pcie_set_mps - set PCI Express maximum payload size
3562 * @dev: PCI device to query
47c08f31 3563 * @mps: maximum payload size in bytes
b03e7495
JM		 3564 * valid values are 128, 256, 512, 1024, 2048, 4096
3565 *
3566 * If possible sets maximum payload size
3567 */
3568int pcie_set_mps(struct pci_dev *dev, int mps)
3569{
59875ae4 3570 u16 v;
b03e7495
JM		 3571
3572 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
59875ae4 3573 return -EINVAL;
b03e7495
JM		 3574
3575 v = ffs(mps) - 8;
3576 if (v > dev->pcie_mpss)
59875ae4 3577 return -EINVAL;
b03e7495
JM		 3578 v <<= 5;
3579
59875ae4
JL		 3580 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3581 PCI_EXP_DEVCTL_PAYLOAD, v);
b03e7495
JM		 3582}
3583
c87deff7
HS		 3584/**
3585 * pci_select_bars - Make BAR mask from the type of resource
f95d882d 3586 * @dev: the PCI device for which BAR mask is made
c87deff7
HS		 3587 * @flags: resource type mask to be selected
3588 *
3589 * This helper routine makes bar mask from the type of resource.
3590 */
3591int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3592{
3593 int i, bars = 0;
3594 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3595 if (pci_resource_flags(dev, i) & flags)
3596 bars |= (1 << i);
3597 return bars;
3598}
3599
613e7ed6
YZ		 3600/**
3601 * pci_resource_bar - get position of the BAR associated with a resource
3602 * @dev: the PCI device
3603 * @resno: the resource number
3604 * @type: the BAR type to be filled in
3605 *
3606 * Returns BAR position in config space, or 0 if the BAR is invalid.
3607 */
3608int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3609{
d1b054da
YZ		 3610 int reg;
3611
613e7ed6
YZ		 3612 if (resno < PCI_ROM_RESOURCE) {
3613 *type = pci_bar_unknown;
3614 return PCI_BASE_ADDRESS_0 + 4 * resno;
3615 } else if (resno == PCI_ROM_RESOURCE) {
3616 *type = pci_bar_mem32;
3617 return dev->rom_base_reg;
d1b054da
YZ		 3618 } else if (resno < PCI_BRIDGE_RESOURCES) {
3619 /* device specific resource */
3620 reg = pci_iov_resource_bar(dev, resno, type);
3621 if (reg)
3622 return reg;
613e7ed6
YZ		 3623 }
3624
865df576 3625 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
613e7ed6
YZ		 3626 return 0;
3627}
3628
95a8b6ef
MT		 3629/* Some architectures require additional programming to enable VGA */
3630static arch_set_vga_state_t arch_set_vga_state;
3631
3632void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3633{
3634 arch_set_vga_state = func; /* NULL disables */
3635}
3636
3637static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
7ad35cf2 3638 unsigned int command_bits, u32 flags)
95a8b6ef
MT		 3639{
3640 if (arch_set_vga_state)
3641 return arch_set_vga_state(dev, decode, command_bits,
7ad35cf2 3642 flags);
95a8b6ef
MT		 3643 return 0;
3644}
3645
deb2d2ec
BH		 3646/**
3647 * pci_set_vga_state - set VGA decode state on device and parents if requested
19eea630
RD		 3648 * @dev: the PCI device
3649 * @decode: true = enable decoding, false = disable decoding
3650 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3f37d622 3651 * @flags: traverse ancestors and change bridges
3448a19d 3652 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
deb2d2ec
BH		 3653 */
3654int pci_set_vga_state(struct pci_dev *dev, bool decode,
3448a19d 3655 unsigned int command_bits, u32 flags)
deb2d2ec
BH		 3656{
3657 struct pci_bus *bus;
3658 struct pci_dev *bridge;
3659 u16 cmd;
95a8b6ef 3660 int rc;
deb2d2ec 3661
b7291c36 3662 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
deb2d2ec 3663
95a8b6ef 3664 /* ARCH specific VGA enables */
3448a19d 3665 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
95a8b6ef
MT		 3666 if (rc)
3667 return rc;
3668
3448a19d
DA		 3669 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3670 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3671 if (decode == true)
3672 cmd |= command_bits;
3673 else
3674 cmd &= ~command_bits;
3675 pci_write_config_word(dev, PCI_COMMAND, cmd);
3676 }
deb2d2ec 3677
3448a19d 3678 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
deb2d2ec
BH		 3679 return 0;
3680
3681 bus = dev->bus;
3682 while (bus) {
3683 bridge = bus->self;
3684 if (bridge) {
3685 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3686 &cmd);
3687 if (decode == true)
3688 cmd |= PCI_BRIDGE_CTL_VGA;
3689 else
3690 cmd &= ~PCI_BRIDGE_CTL_VGA;
3691 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3692 cmd);
3693 }
3694 bus = bus->parent;
3695 }
3696 return 0;
3697}
3698
32a9a682
YS		 3699#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3700static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
e9d1e492 3701static DEFINE_SPINLOCK(resource_alignment_lock);
32a9a682
YS		 3702
3703/**
3704 * pci_specified_resource_alignment - get resource alignment specified by user.
3705 * @dev: the PCI device to get
3706 *
3707 * RETURNS: Resource alignment if it is specified.
3708 * Zero if it is not specified.
3709 */
9738abed 3710static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
32a9a682
YS		 3711{
3712 int seg, bus, slot, func, align_order, count;
3713 resource_size_t align = 0;
3714 char *p;
3715
3716 spin_lock(&resource_alignment_lock);
3717 p = resource_alignment_param;
3718 while (*p) {
3719 count = 0;
3720 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3721 p[count] == '@') {
3722 p += count + 1;
3723 } else {
3724 align_order = -1;
3725 }
3726 if (sscanf(p, "%x:%x:%x.%x%n",
3727 &seg, &bus, &slot, &func, &count) != 4) {
3728 seg = 0;
3729 if (sscanf(p, "%x:%x.%x%n",
3730 &bus, &slot, &func, &count) != 3) {
3731 /* Invalid format */
3732 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3733 p);
3734 break;
3735 }
3736 }
3737 p += count;
3738 if (seg == pci_domain_nr(dev->bus) &&
3739 bus == dev->bus->number &&
3740 slot == PCI_SLOT(dev->devfn) &&
3741 func == PCI_FUNC(dev->devfn)) {
3742 if (align_order == -1) {
3743 align = PAGE_SIZE;
3744 } else {
3745 align = 1 << align_order;
3746 }
3747 /* Found */
3748 break;
3749 }
3750 if (*p != ';' && *p != ',') {
3751 /* End of param or invalid format */
3752 break;
3753 }
3754 p++;
3755 }
3756 spin_unlock(&resource_alignment_lock);
3757 return align;
3758}
3759
2069ecfb
YL		 3760/*
3761 * This function disables memory decoding and releases memory resources
3762 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
3763 * It also rounds up size to specified alignment.
3764 * Later on, the kernel will assign page-aligned memory resource back
3765 * to the device.
3766 */
3767void pci_reassigndev_resource_alignment(struct pci_dev *dev)
3768{
3769 int i;
3770 struct resource *r;
3771 resource_size_t align, size;
3772 u16 command;
3773
10c463a7
YL		 3774 /* check if specified PCI is target device to reassign */
3775 align = pci_specified_resource_alignment(dev);
3776 if (!align)
2069ecfb
YL		 3777 return;
3778
3779 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
3780 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
3781 dev_warn(&dev->dev,
3782 "Can't reassign resources to host bridge.\n");
3783 return;
3784 }
3785
3786 dev_info(&dev->dev,
3787 "Disabling memory decoding and releasing memory resources.\n");
3788 pci_read_config_word(dev, PCI_COMMAND, &command);
3789 command &= ~PCI_COMMAND_MEMORY;
3790 pci_write_config_word(dev, PCI_COMMAND, command);
3791
2069ecfb
YL		 3792 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
3793 r = &dev->resource[i];
3794 if (!(r->flags & IORESOURCE_MEM))
3795 continue;
3796 size = resource_size(r);
3797 if (size < align) {
3798 size = align;
3799 dev_info(&dev->dev,
3800 "Rounding up size of resource #%d to %#llx.\n",
3801 i, (unsigned long long)size);
3802 }
3803 r->end = size - 1;
3804 r->start = 0;
3805 }
3806 /* Need to disable bridge's resource window,
3807 * to enable the kernel to reassign new resource
3808 * window later on.
3809 */
3810 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3811 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
3812 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
3813 r = &dev->resource[i];
3814 if (!(r->flags & IORESOURCE_MEM))
3815 continue;
3816 r->end = resource_size(r) - 1;
3817 r->start = 0;
3818 }
3819 pci_disable_bridge_window(dev);
3820 }
3821}
3822
9738abed 3823static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
32a9a682
YS		 3824{
3825 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3826 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3827 spin_lock(&resource_alignment_lock);
3828 strncpy(resource_alignment_param, buf, count);
3829 resource_alignment_param[count] = '\0';
3830 spin_unlock(&resource_alignment_lock);
3831 return count;
3832}
3833
9738abed 3834static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
32a9a682
YS		 3835{
3836 size_t count;
3837 spin_lock(&resource_alignment_lock);
3838 count = snprintf(buf, size, "%s", resource_alignment_param);
3839 spin_unlock(&resource_alignment_lock);
3840 return count;
3841}
3842
3843static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3844{
3845 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3846}
3847
3848static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3849 const char *buf, size_t count)
3850{
3851 return pci_set_resource_alignment_param(buf, count);
3852}
3853
3854BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3855 pci_resource_alignment_store);
3856
3857static int __init pci_resource_alignment_sysfs_init(void)
3858{
3859 return bus_create_file(&pci_bus_type,
3860 &bus_attr_resource_alignment);
3861}
3862
3863late_initcall(pci_resource_alignment_sysfs_init);
3864
15856ad5 3865static void pci_no_domains(void)
32a2eea7
JG		 3866{
3867#ifdef CONFIG_PCI_DOMAINS
3868 pci_domains_supported = 0;
3869#endif
3870}
3871
0ef5f8f6 3872/**
642c92da 3873 * pci_ext_cfg_avail - can we access extended PCI config space?
0ef5f8f6
AP		 3874 *
3875 * Returns 1 if we can access PCI extended config space (offsets
3876 * greater than 0xff). This is the default implementation. Architecture
3877 * implementations can override this.
3878 */
642c92da 3879int __weak pci_ext_cfg_avail(void)
0ef5f8f6
AP		 3880{
3881 return 1;
3882}
3883
2d1c8618
BH		 3884void __weak pci_fixup_cardbus(struct pci_bus *bus)
3885{
3886}
3887EXPORT_SYMBOL(pci_fixup_cardbus);
3888
ad04d31e 3889static int __init pci_setup(char *str)
1da177e4
LT		 3890{
3891 while (str) {
3892 char *k = strchr(str, ',');
3893 if (k)
3894 *k++ = 0;
3895 if (*str && (str = pcibios_setup(str)) && *str) {
309e57df
MW		 3896 if (!strcmp(str, "nomsi")) {
3897 pci_no_msi();
7f785763
RD		 3898 } else if (!strcmp(str, "noaer")) {
3899 pci_no_aer();
b55438fd
YL		 3900 } else if (!strncmp(str, "realloc=", 8)) {
3901 pci_realloc_get_opt(str + 8);
f483d392 3902 } else if (!strncmp(str, "realloc", 7)) {
b55438fd 3903 pci_realloc_get_opt("on");
32a2eea7
JG		 3904 } else if (!strcmp(str, "nodomains")) {
3905 pci_no_domains();
6748dcc2
RW		 3906 } else if (!strncmp(str, "noari", 5)) {
3907 pcie_ari_disabled = true;
4516a618
AN		 3908 } else if (!strncmp(str, "cbiosize=", 9)) {
3909 pci_cardbus_io_size = memparse(str + 9, &str);
3910 } else if (!strncmp(str, "cbmemsize=", 10)) {
3911 pci_cardbus_mem_size = memparse(str + 10, &str);
32a9a682
YS		 3912 } else if (!strncmp(str, "resource_alignment=", 19)) {
3913 pci_set_resource_alignment_param(str + 19,
3914 strlen(str + 19));
43c16408
AP		 3915 } else if (!strncmp(str, "ecrc=", 5)) {
3916 pcie_ecrc_get_policy(str + 5);
28760489
EB		 3917 } else if (!strncmp(str, "hpiosize=", 9)) {
3918 pci_hotplug_io_size = memparse(str + 9, &str);
3919 } else if (!strncmp(str, "hpmemsize=", 10)) {
3920 pci_hotplug_mem_size = memparse(str + 10, &str);
5f39e670
JM		 3921 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3922 pcie_bus_config = PCIE_BUS_TUNE_OFF;
b03e7495
JM		 3923 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3924 pcie_bus_config = PCIE_BUS_SAFE;
3925 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3926 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5f39e670
JM		 3927 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3928 pcie_bus_config = PCIE_BUS_PEER2PEER;
284f5f9d
BH		 3929 } else if (!strncmp(str, "pcie_scan_all", 13)) {
3930 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
309e57df
MW		 3931 } else {
3932 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3933 str);
3934 }
1da177e4
LT		 3935 }
3936 str = k;
3937 }
0637a70a 3938 return 0;
1da177e4 3939}
0637a70a 3940early_param("pci", pci_setup);
1da177e4 3941
0b62e13b 3942EXPORT_SYMBOL(pci_reenable_device);
b718989d
BH		 3943EXPORT_SYMBOL(pci_enable_device_io);
3944EXPORT_SYMBOL(pci_enable_device_mem);
1da177e4 3945EXPORT_SYMBOL(pci_enable_device);
9ac7849e
TH		 3946EXPORT_SYMBOL(pcim_enable_device);
3947EXPORT_SYMBOL(pcim_pin_device);
1da177e4 3948EXPORT_SYMBOL(pci_disable_device);
1da177e4
LT		 3949EXPORT_SYMBOL(pci_find_capability);
3950EXPORT_SYMBOL(pci_bus_find_capability);
3951EXPORT_SYMBOL(pci_release_regions);
3952EXPORT_SYMBOL(pci_request_regions);
e8de1481 3953EXPORT_SYMBOL(pci_request_regions_exclusive);
1da177e4
LT		 3954EXPORT_SYMBOL(pci_release_region);
3955EXPORT_SYMBOL(pci_request_region);
e8de1481 3956EXPORT_SYMBOL(pci_request_region_exclusive);
c87deff7
HS		 3957EXPORT_SYMBOL(pci_release_selected_regions);
3958EXPORT_SYMBOL(pci_request_selected_regions);
e8de1481 3959EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
1da177e4 3960EXPORT_SYMBOL(pci_set_master);
6a479079 3961EXPORT_SYMBOL(pci_clear_master);
1da177e4 3962EXPORT_SYMBOL(pci_set_mwi);
694625c0 3963EXPORT_SYMBOL(pci_try_set_mwi);
1da177e4 3964EXPORT_SYMBOL(pci_clear_mwi);
a04ce0ff 3965EXPORT_SYMBOL_GPL(pci_intx);
1da177e4
LT		 3966EXPORT_SYMBOL(pci_assign_resource);
3967EXPORT_SYMBOL(pci_find_parent_resource);
c87deff7 3968EXPORT_SYMBOL(pci_select_bars);
1da177e4
LT		 3969
3970EXPORT_SYMBOL(pci_set_power_state);
3971EXPORT_SYMBOL(pci_save_state);
3972EXPORT_SYMBOL(pci_restore_state);
e5899e1b 3973EXPORT_SYMBOL(pci_pme_capable);
5a6c9b60 3974EXPORT_SYMBOL(pci_pme_active);
0235c4fc 3975EXPORT_SYMBOL(pci_wake_from_d3);
e5899e1b 3976EXPORT_SYMBOL(pci_target_state);
404cc2d8
RW		 3977EXPORT_SYMBOL(pci_prepare_to_sleep);
3978EXPORT_SYMBOL(pci_back_from_sleep);
f7bdd12d 3979EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
kernel source for telekom puls (alcatel/mediatek)