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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / parport / parport_pc.c
CommitLineData
1da177e4 1/* Low-level parallel-port routines for 8255-based PC-style hardware.
3aeda9bc 2 *
1da177e4
LT		 3 * Authors: Phil Blundell <philb@gnu.org>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
bdca3f20 6 * David Campbell
1da177e4
LT		 7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
3aeda9bc 14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
1da177e4
LT		 15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
17 */
18
19/* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
22 * layout is:
23 *
24 * base+0 data
25 * base+1 status
26 * base+2 control
27 *
28 * In addition, there are some optional registers:
29 *
30 * base+3 EPP address
31 * base+4 EPP data
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
35 *
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
39 * accommodate this.
40 *
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
43 */
44
1da177e4
LT		 45#include <linux/module.h>
46#include <linux/init.h>
47#include <linux/sched.h>
48#include <linux/delay.h>
49#include <linux/errno.h>
50#include <linux/interrupt.h>
51#include <linux/ioport.h>
52#include <linux/kernel.h>
53#include <linux/slab.h>
8382d2b9 54#include <linux/dma-mapping.h>
1da177e4
LT		 55#include <linux/pci.h>
56#include <linux/pnp.h>
a7d801af 57#include <linux/platform_device.h>
1da177e4 58#include <linux/sysctl.h>
3aeda9bc
AC		 59#include <linux/io.h>
60#include <linux/uaccess.h>
1da177e4 61
1da177e4 62#include <asm/dma.h>
1da177e4
LT		 63
64#include <linux/parport.h>
65#include <linux/parport_pc.h>
66#include <linux/via.h>
67#include <asm/parport.h>
68
69#define PARPORT_PC_MAX_PORTS PARPORT_MAX
70
7fbacd52
AV		 71#ifdef CONFIG_ISA_DMA_API
72#define HAS_DMA
73#endif
74
1da177e4
LT		 75/* ECR modes */
76#define ECR_SPP 00
77#define ECR_PS2 01
78#define ECR_PPF 02
79#define ECR_ECP 03
80#define ECR_EPP 04
81#define ECR_VND 05
82#define ECR_TST 06
83#define ECR_CNF 07
84#define ECR_MODE_MASK 0xe0
3aeda9bc 85#define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
1da177e4
LT		 86
87#undef DEBUG
88
89#ifdef DEBUG
90#define DPRINTK printk
91#else
92#define DPRINTK(stuff...)
93#endif
94
95
96#define NR_SUPERIOS 3
97static struct superio_struct { /* For Super-IO chips autodetection */
98 int io;
99 int irq;
100 int dma;
96766a3c 101} superios[NR_SUPERIOS] = { {0,},};
1da177e4
LT		 102
103static int user_specified;
104#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
105 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
106static int verbose_probing;
107#endif
108static int pci_registered_parport;
109static int pnp_registered_parport;
110
111/* frob_control, but for ECR */
3aeda9bc 112static void frob_econtrol(struct parport *pb, unsigned char m,
1da177e4
LT		 113 unsigned char v)
114{
115 unsigned char ectr = 0;
116
117 if (m != 0xff)
3aeda9bc 118 ectr = inb(ECONTROL(pb));
1da177e4 119
3aeda9bc 120 DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
1da177e4
LT		 121 m, v, ectr, (ectr & ~m) ^ v);
122
3aeda9bc 123 outb((ectr & ~m) ^ v, ECONTROL(pb));
1da177e4
LT		 124}
125
3aeda9bc 126static inline void frob_set_mode(struct parport *p, int mode)
1da177e4 127{
3aeda9bc 128 frob_econtrol(p, ECR_MODE_MASK, mode << 5);
1da177e4
LT		 129}
130
131#ifdef CONFIG_PARPORT_PC_FIFO
3aeda9bc 132/* Safely change the mode bits in the ECR
1da177e4
LT		 133 Returns:
134 0 : Success
135 -EBUSY: Could not drain FIFO in some finite amount of time,
136 mode not changed!
137 */
138static int change_mode(struct parport *p, int m)
139{
140 const struct parport_pc_private *priv = p->physport->private_data;
141 unsigned char oecr;
142 int mode;
143
3aeda9bc 144 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m);
1da177e4
LT		 145
146 if (!priv->ecr) {
3aeda9bc 147 printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
1da177e4
LT		 148 return 0;
149 }
150
151 /* Bits <7:5> contain the mode. */
3aeda9bc 152 oecr = inb(ECONTROL(p));
1da177e4 153 mode = (oecr >> 5) & 0x7;
3aeda9bc
AC		 154 if (mode == m)
155 return 0;
1da177e4
LT		 156
157 if (mode >= 2 && !(priv->ctr & 0x20)) {
158 /* This mode resets the FIFO, so we may
159 * have to wait for it to drain first. */
160 unsigned long expire = jiffies + p->physport->cad->timeout;
161 int counter;
162 switch (mode) {
163 case ECR_PPF: /* Parallel Port FIFO mode */
164 case ECR_ECP: /* ECP Parallel Port mode */
165 /* Busy wait for 200us */
166 for (counter = 0; counter < 40; counter++) {
3aeda9bc 167 if (inb(ECONTROL(p)) & 0x01)
1da177e4 168 break;
3aeda9bc
AC		 169 if (signal_pending(current))
170 break;
171 udelay(5);
1da177e4
LT		 172 }
173
174 /* Poll slowly. */
3aeda9bc
AC		 175 while (!(inb(ECONTROL(p)) & 0x01)) {
176 if (time_after_eq(jiffies, expire))
1da177e4
LT		 177 /* The FIFO is stuck. */
178 return -EBUSY;
3aeda9bc
AC		 179 schedule_timeout_interruptible(
180 msecs_to_jiffies(10));
181 if (signal_pending(current))
1da177e4
LT		 182 break;
183 }
184 }
185 }
186
187 if (mode >= 2 && m >= 2) {
188 /* We have to go through mode 001 */
189 oecr &= ~(7 << 5);
190 oecr |= ECR_PS2 << 5;
3aeda9bc 191 ECR_WRITE(p, oecr);
1da177e4
LT		 192 }
193
194 /* Set the mode. */
195 oecr &= ~(7 << 5);
196 oecr |= m << 5;
3aeda9bc 197 ECR_WRITE(p, oecr);
1da177e4
LT		 198 return 0;
199}
1da177e4
LT		 200#endif /* FIFO support */
201
202/*
203 * Clear TIMEOUT BIT in EPP MODE
204 *
205 * This is also used in SPP detection.
206 */
207static int clear_epp_timeout(struct parport *pb)
208{
209 unsigned char r;
210
211 if (!(parport_pc_read_status(pb) & 0x01))
212 return 1;
213
214 /* To clear timeout some chips require double read */
215 parport_pc_read_status(pb);
216 r = parport_pc_read_status(pb);
3aeda9bc
AC		 217 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
218 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
1da177e4
LT		 219 r = parport_pc_read_status(pb);
220
221 return !(r & 0x01);
222}
223
224/*
225 * Access functions.
226 *
227 * Most of these aren't static because they may be used by the
228 * parport_xxx_yyy macros. extern __inline__ versions of several
229 * of these are in parport_pc.h.
230 */
231
3aeda9bc
AC		 232static void parport_pc_init_state(struct pardevice *dev,
233 struct parport_state *s)
1da177e4
LT		 234{
235 s->u.pc.ctr = 0xc;
236 if (dev->irq_func &&
237 dev->port->irq != PARPORT_IRQ_NONE)
238 /* Set ackIntEn */
239 s->u.pc.ctr |= 0x10;
240
241 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
242 * D.Gruszka VScom */
243}
244
245static void parport_pc_save_state(struct parport *p, struct parport_state *s)
246{
247 const struct parport_pc_private *priv = p->physport->private_data;
248 s->u.pc.ctr = priv->ctr;
249 if (priv->ecr)
3aeda9bc 250 s->u.pc.ecr = inb(ECONTROL(p));
1da177e4
LT		 251}
252
3aeda9bc
AC		 253static void parport_pc_restore_state(struct parport *p,
254 struct parport_state *s)
1da177e4
LT		 255{
256 struct parport_pc_private *priv = p->physport->private_data;
257 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
3aeda9bc 258 outb(c, CONTROL(p));
1da177e4
LT		 259 priv->ctr = c;
260 if (priv->ecr)
3aeda9bc 261 ECR_WRITE(p, s->u.pc.ecr);
1da177e4
LT		 262}
263
264#ifdef CONFIG_PARPORT_1284
3aeda9bc
AC		 265static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
266 size_t length, int flags)
1da177e4
LT		 267{
268 size_t got = 0;
269
270 if (flags & PARPORT_W91284PIC) {
271 unsigned char status;
272 size_t left = length;
273
274 /* use knowledge about data lines..:
275 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
276 * pError is 1 if there are 16 bytes in the Warp's FIFO
277 */
3aeda9bc 278 status = inb(STATUS(port));
1da177e4 279
3aeda9bc
AC		 280 while (!(status & 0x08) && got < length) {
281 if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
1da177e4 282 /* can grab 16 bytes from warp fifo */
3aeda9bc
AC		 283 if (!((long)buf & 0x03))
284 insl(EPPDATA(port), buf, 4);
285 else
286 insb(EPPDATA(port), buf, 16);
1da177e4
LT		 287 buf += 16;
288 got += 16;
289 left -= 16;
290 } else {
291 /* grab single byte from the warp fifo */
3aeda9bc 292 *((char *)buf) = inb(EPPDATA(port));
1da177e4
LT		 293 buf++;
294 got++;
295 left--;
296 }
3aeda9bc 297 status = inb(STATUS(port));
1da177e4
LT		 298 if (status & 0x01) {
299 /* EPP timeout should never occur... */
3aeda9bc
AC		 300 printk(KERN_DEBUG
301"%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name);
302 clear_epp_timeout(port);
1da177e4
LT		 303 }
304 }
305 return got;
306 }
307 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
3aeda9bc
AC		 308 if (!(((long)buf | length) & 0x03))
309 insl(EPPDATA(port), buf, (length >> 2));
310 else
311 insb(EPPDATA(port), buf, length);
312 if (inb(STATUS(port)) & 0x01) {
313 clear_epp_timeout(port);
1da177e4
LT		 314 return -EIO;
315 }
316 return length;
317 }
318 for (; got < length; got++) {
3aeda9bc 319 *((char *)buf) = inb(EPPDATA(port));
1da177e4 320 buf++;
3aeda9bc 321 if (inb(STATUS(port)) & 0x01) {
1da177e4 322 /* EPP timeout */
3aeda9bc 323 clear_epp_timeout(port);
1da177e4
LT		 324 break;
325 }
326 }
327
328 return got;
329}
330
3aeda9bc
AC		 331static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
332 size_t length, int flags)
1da177e4
LT		 333{
334 size_t written = 0;
335
336 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
3aeda9bc
AC		 337 if (!(((long)buf | length) & 0x03))
338 outsl(EPPDATA(port), buf, (length >> 2));
339 else
340 outsb(EPPDATA(port), buf, length);
341 if (inb(STATUS(port)) & 0x01) {
342 clear_epp_timeout(port);
1da177e4
LT		 343 return -EIO;
344 }
345 return length;
346 }
347 for (; written < length; written++) {
3aeda9bc 348 outb(*((char *)buf), EPPDATA(port));
1da177e4 349 buf++;
3aeda9bc
AC		 350 if (inb(STATUS(port)) & 0x01) {
351 clear_epp_timeout(port);
1da177e4
LT		 352 break;
353 }
354 }
355
356 return written;
357}
358
3aeda9bc 359static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
1da177e4
LT		 360 size_t length, int flags)
361{
362 size_t got = 0;
363
364 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
3aeda9bc
AC		 365 insb(EPPADDR(port), buf, length);
366 if (inb(STATUS(port)) & 0x01) {
367 clear_epp_timeout(port);
1da177e4
LT		 368 return -EIO;
369 }
370 return length;
371 }
372 for (; got < length; got++) {
3aeda9bc 373 *((char *)buf) = inb(EPPADDR(port));
1da177e4 374 buf++;
3aeda9bc
AC		 375 if (inb(STATUS(port)) & 0x01) {
376 clear_epp_timeout(port);
1da177e4
LT		 377 break;
378 }
379 }
380
381 return got;
382}
383
3aeda9bc 384static size_t parport_pc_epp_write_addr(struct parport *port,
1da177e4
LT		 385 const void *buf, size_t length,
386 int flags)
387{
388 size_t written = 0;
389
390 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
3aeda9bc
AC		 391 outsb(EPPADDR(port), buf, length);
392 if (inb(STATUS(port)) & 0x01) {
393 clear_epp_timeout(port);
1da177e4
LT		 394 return -EIO;
395 }
396 return length;
397 }
398 for (; written < length; written++) {
3aeda9bc 399 outb(*((char *)buf), EPPADDR(port));
1da177e4 400 buf++;
3aeda9bc
AC		 401 if (inb(STATUS(port)) & 0x01) {
402 clear_epp_timeout(port);
1da177e4
LT		 403 break;
404 }
405 }
406
407 return written;
408}
409
3aeda9bc
AC		 410static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
411 size_t length, int flags)
1da177e4
LT		 412{
413 size_t got;
414
3aeda9bc
AC		 415 frob_set_mode(port, ECR_EPP);
416 parport_pc_data_reverse(port);
417 parport_pc_write_control(port, 0x4);
418 got = parport_pc_epp_read_data(port, buf, length, flags);
419 frob_set_mode(port, ECR_PS2);
1da177e4
LT		 420
421 return got;
422}
423
3aeda9bc
AC		 424static size_t parport_pc_ecpepp_write_data(struct parport *port,
425 const void *buf, size_t length,
426 int flags)
1da177e4
LT		 427{
428 size_t written;
429
3aeda9bc
AC		 430 frob_set_mode(port, ECR_EPP);
431 parport_pc_write_control(port, 0x4);
432 parport_pc_data_forward(port);
433 written = parport_pc_epp_write_data(port, buf, length, flags);
434 frob_set_mode(port, ECR_PS2);
1da177e4
LT		 435
436 return written;
437}
438
3aeda9bc
AC		 439static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
440 size_t length, int flags)
1da177e4
LT		 441{
442 size_t got;
443
3aeda9bc
AC		 444 frob_set_mode(port, ECR_EPP);
445 parport_pc_data_reverse(port);
446 parport_pc_write_control(port, 0x4);
447 got = parport_pc_epp_read_addr(port, buf, length, flags);
448 frob_set_mode(port, ECR_PS2);
1da177e4
LT		 449
450 return got;
451}
452
3aeda9bc 453static size_t parport_pc_ecpepp_write_addr(struct parport *port,
1da177e4
LT		 454 const void *buf, size_t length,
455 int flags)
456{
457 size_t written;
458
3aeda9bc
AC		 459 frob_set_mode(port, ECR_EPP);
460 parport_pc_write_control(port, 0x4);
461 parport_pc_data_forward(port);
462 written = parport_pc_epp_write_addr(port, buf, length, flags);
463 frob_set_mode(port, ECR_PS2);
1da177e4
LT		 464
465 return written;
466}
467#endif /* IEEE 1284 support */
468
469#ifdef CONFIG_PARPORT_PC_FIFO
3aeda9bc 470static size_t parport_pc_fifo_write_block_pio(struct parport *port,
1da177e4
LT		 471 const void *buf, size_t length)
472{
473 int ret = 0;
474 const unsigned char *bufp = buf;
475 size_t left = length;
476 unsigned long expire = jiffies + port->physport->cad->timeout;
3aeda9bc 477 const int fifo = FIFO(port);
1da177e4
LT		 478 int poll_for = 8; /* 80 usecs */
479 const struct parport_pc_private *priv = port->physport->private_data;
480 const int fifo_depth = priv->fifo_depth;
481
482 port = port->physport;
483
484 /* We don't want to be interrupted every character. */
3aeda9bc 485 parport_pc_disable_irq(port);
1da177e4 486 /* set nErrIntrEn and serviceIntr */
3aeda9bc 487 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
1da177e4
LT		 488
489 /* Forward mode. */
3aeda9bc 490 parport_pc_data_forward(port); /* Must be in PS2 mode */
1da177e4
LT		 491
492 while (left) {
493 unsigned char byte;
3aeda9bc 494 unsigned char ecrval = inb(ECONTROL(port));
1da177e4
LT		 495 int i = 0;
496
3aeda9bc 497 if (need_resched() && time_before(jiffies, expire))
1da177e4 498 /* Can't yield the port. */
3aeda9bc 499 schedule();
1da177e4
LT		 500
501 /* Anyone else waiting for the port? */
502 if (port->waithead) {
3aeda9bc 503 printk(KERN_DEBUG "Somebody wants the port\n");
1da177e4
LT		 504 break;
505 }
506
507 if (ecrval & 0x02) {
508 /* FIFO is full. Wait for interrupt. */
509
510 /* Clear serviceIntr */
3aeda9bc
AC		 511 ECR_WRITE(port, ecrval & ~(1<<2));
512false_alarm:
513 ret = parport_wait_event(port, HZ);
514 if (ret < 0)
515 break;
1da177e4 516 ret = 0;
3aeda9bc 517 if (!time_before(jiffies, expire)) {
1da177e4 518 /* Timed out. */
3aeda9bc 519 printk(KERN_DEBUG "FIFO write timed out\n");
1da177e4
LT		 520 break;
521 }
3aeda9bc 522 ecrval = inb(ECONTROL(port));
1da177e4
LT		 523 if (!(ecrval & (1<<2))) {
524 if (need_resched() &&
3aeda9bc
AC		 525 time_before(jiffies, expire))
526 schedule();
1da177e4
LT		 527
528 goto false_alarm;
529 }
530
531 continue;
532 }
533
534 /* Can't fail now. */
535 expire = jiffies + port->cad->timeout;
536
3aeda9bc
AC		 537poll:
538 if (signal_pending(current))
1da177e4
LT		 539 break;
540
541 if (ecrval & 0x01) {
542 /* FIFO is empty. Blast it full. */
543 const int n = left < fifo_depth ? left : fifo_depth;
3aeda9bc 544 outsb(fifo, bufp, n);
1da177e4
LT		 545 bufp += n;
546 left -= n;
547
548 /* Adjust the poll time. */
3aeda9bc
AC		 549 if (i < (poll_for - 2))
550 poll_for--;
1da177e4
LT		 551 continue;
552 } else if (i++ < poll_for) {
3aeda9bc
AC		 553 udelay(10);
554 ecrval = inb(ECONTROL(port));
1da177e4
LT		 555 goto poll;
556 }
557
3aeda9bc 558 /* Half-full(call me an optimist) */
1da177e4 559 byte = *bufp++;
3aeda9bc 560 outb(byte, fifo);
1da177e4 561 left--;
3aeda9bc
AC		 562 }
563 dump_parport_state("leave fifo_write_block_pio", port);
1da177e4
LT		 564 return length - left;
565}
566
7fbacd52 567#ifdef HAS_DMA
3aeda9bc 568static size_t parport_pc_fifo_write_block_dma(struct parport *port,
1da177e4
LT		 569 const void *buf, size_t length)
570{
571 int ret = 0;
572 unsigned long dmaflag;
573 size_t left = length;
574 const struct parport_pc_private *priv = port->physport->private_data;
c15a3837 575 struct device *dev = port->physport->dev;
1da177e4
LT		 576 dma_addr_t dma_addr, dma_handle;
577 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
578 unsigned long start = (unsigned long) buf;
579 unsigned long end = (unsigned long) buf + length - 1;
580
181bf1e8 581 dump_parport_state("enter fifo_write_block_dma", port);
1da177e4
LT		 582 if (end < MAX_DMA_ADDRESS) {
583 /* If it would cross a 64k boundary, cap it at the end. */
584 if ((start ^ end) & ~0xffffUL)
585 maxlen = 0x10000 - (start & 0xffff);
586
c15a3837
DB		 587 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
588 DMA_TO_DEVICE);
3aeda9bc
AC		 589 } else {
590 /* above 16 MB we use a bounce buffer as ISA-DMA
591 is not possible */
1da177e4
LT		 592 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
593 dma_addr = priv->dma_handle;
594 dma_handle = 0;
595 }
596
597 port = port->physport;
598
599 /* We don't want to be interrupted every character. */
3aeda9bc 600 parport_pc_disable_irq(port);
1da177e4 601 /* set nErrIntrEn and serviceIntr */
3aeda9bc 602 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
1da177e4
LT		 603
604 /* Forward mode. */
3aeda9bc 605 parport_pc_data_forward(port); /* Must be in PS2 mode */
1da177e4
LT		 606
607 while (left) {
608 unsigned long expire = jiffies + port->physport->cad->timeout;
609
610 size_t count = left;
611
612 if (count > maxlen)
613 count = maxlen;
614
615 if (!dma_handle) /* bounce buffer ! */
616 memcpy(priv->dma_buf, buf, count);
617
618 dmaflag = claim_dma_lock();
619 disable_dma(port->dma);
620 clear_dma_ff(port->dma);
621 set_dma_mode(port->dma, DMA_MODE_WRITE);
622 set_dma_addr(port->dma, dma_addr);
623 set_dma_count(port->dma, count);
624
625 /* Set DMA mode */
3aeda9bc 626 frob_econtrol(port, 1<<3, 1<<3);
1da177e4
LT		 627
628 /* Clear serviceIntr */
3aeda9bc 629 frob_econtrol(port, 1<<2, 0);
1da177e4
LT		 630
631 enable_dma(port->dma);
632 release_dma_lock(dmaflag);
633
634 /* assume DMA will be successful */
635 left -= count;
636 buf += count;
3aeda9bc
AC		 637 if (dma_handle)
638 dma_addr += count;
1da177e4
LT		 639
640 /* Wait for interrupt. */
3aeda9bc
AC		 641false_alarm:
642 ret = parport_wait_event(port, HZ);
643 if (ret < 0)
644 break;
1da177e4 645 ret = 0;
3aeda9bc 646 if (!time_before(jiffies, expire)) {
1da177e4 647 /* Timed out. */
3aeda9bc 648 printk(KERN_DEBUG "DMA write timed out\n");
1da177e4
LT		 649 break;
650 }
651 /* Is serviceIntr set? */
3aeda9bc 652 if (!(inb(ECONTROL(port)) & (1<<2))) {
1da177e4
LT		 653 cond_resched();
654
655 goto false_alarm;
656 }
657
658 dmaflag = claim_dma_lock();
659 disable_dma(port->dma);
660 clear_dma_ff(port->dma);
661 count = get_dma_residue(port->dma);
662 release_dma_lock(dmaflag);
663
664 cond_resched(); /* Can't yield the port. */
665
666 /* Anyone else waiting for the port? */
667 if (port->waithead) {
3aeda9bc 668 printk(KERN_DEBUG "Somebody wants the port\n");
1da177e4
LT		 669 break;
670 }
671
672 /* update for possible DMA residue ! */
673 buf -= count;
674 left += count;
3aeda9bc
AC		 675 if (dma_handle)
676 dma_addr -= count;
1da177e4
LT		 677 }
678
679 /* Maybe got here through break, so adjust for DMA residue! */
680 dmaflag = claim_dma_lock();
681 disable_dma(port->dma);
682 clear_dma_ff(port->dma);
683 left += get_dma_residue(port->dma);
684 release_dma_lock(dmaflag);
685
686 /* Turn off DMA mode */
3aeda9bc 687 frob_econtrol(port, 1<<3, 0);
c15a3837 688
1da177e4 689 if (dma_handle)
c15a3837 690 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
1da177e4 691
181bf1e8 692 dump_parport_state("leave fifo_write_block_dma", port);
1da177e4
LT		 693 return length - left;
694}
7fbacd52
AV		 695#endif
696
697static inline size_t parport_pc_fifo_write_block(struct parport *port,
698 const void *buf, size_t length)
699{
700#ifdef HAS_DMA
701 if (port->dma != PARPORT_DMA_NONE)
3aeda9bc 702 return parport_pc_fifo_write_block_dma(port, buf, length);
7fbacd52 703#endif
3aeda9bc 704 return parport_pc_fifo_write_block_pio(port, buf, length);
7fbacd52 705}
1da177e4
LT		 706
707/* Parallel Port FIFO mode (ECP chipsets) */
3aeda9bc 708static size_t parport_pc_compat_write_block_pio(struct parport *port,
1da177e4
LT		 709 const void *buf, size_t length,
710 int flags)
711{
712 size_t written;
713 int r;
714 unsigned long expire;
715 const struct parport_pc_private *priv = port->physport->private_data;
716
717 /* Special case: a timeout of zero means we cannot call schedule().
718 * Also if O_NONBLOCK is set then use the default implementation. */
719 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
3aeda9bc 720 return parport_ieee1284_write_compat(port, buf,
1da177e4
LT		 721 length, flags);
722
723 /* Set up parallel port FIFO mode.*/
3aeda9bc
AC		 724 parport_pc_data_forward(port); /* Must be in PS2 mode */
725 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
726 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
727 if (r)
728 printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
729 port->name);
1da177e4
LT		 730
731 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
732
733 /* Write the data to the FIFO. */
7fbacd52 734 written = parport_pc_fifo_write_block(port, buf, length);
1da177e4
LT		 735
736 /* Finish up. */
737 /* For some hardware we don't want to touch the mode until
738 * the FIFO is empty, so allow 4 seconds for each position
739 * in the fifo.
740 */
3aeda9bc 741 expire = jiffies + (priv->fifo_depth * HZ * 4);
1da177e4
LT		 742 do {
743 /* Wait for the FIFO to empty */
3aeda9bc
AC		 744 r = change_mode(port, ECR_PS2);
745 if (r != -EBUSY)
1da177e4 746 break;
3aeda9bc 747 } while (time_before(jiffies, expire));
1da177e4
LT		 748 if (r == -EBUSY) {
749
3aeda9bc 750 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
1da177e4
LT		 751
752 /* Prevent further data transfer. */
3aeda9bc 753 frob_set_mode(port, ECR_TST);
1da177e4
LT		 754
755 /* Adjust for the contents of the FIFO. */
756 for (written -= priv->fifo_depth; ; written++) {
3aeda9bc 757 if (inb(ECONTROL(port)) & 0x2) {
1da177e4
LT		 758 /* Full up. */
759 break;
760 }
3aeda9bc 761 outb(0, FIFO(port));
1da177e4
LT		 762 }
763
764 /* Reset the FIFO and return to PS2 mode. */
3aeda9bc 765 frob_set_mode(port, ECR_PS2);
1da177e4
LT		 766 }
767
3aeda9bc 768 r = parport_wait_peripheral(port,
1da177e4
LT		 769 PARPORT_STATUS_BUSY,
770 PARPORT_STATUS_BUSY);
771 if (r)
3aeda9bc
AC		 772 printk(KERN_DEBUG
773 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
1da177e4
LT		 774 port->name, r);
775
776 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
777
778 return written;
779}
780
781/* ECP */
782#ifdef CONFIG_PARPORT_1284
3aeda9bc 783static size_t parport_pc_ecp_write_block_pio(struct parport *port,
1da177e4
LT		 784 const void *buf, size_t length,
785 int flags)
786{
787 size_t written;
788 int r;
789 unsigned long expire;
790 const struct parport_pc_private *priv = port->physport->private_data;
791
792 /* Special case: a timeout of zero means we cannot call schedule().
793 * Also if O_NONBLOCK is set then use the default implementation. */
794 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
3aeda9bc 795 return parport_ieee1284_ecp_write_data(port, buf,
1da177e4
LT		 796 length, flags);
797
798 /* Switch to forward mode if necessary. */
799 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
800 /* Event 47: Set nInit high. */
3aeda9bc 801 parport_frob_control(port,
1da177e4
LT		 802 PARPORT_CONTROL_INIT
803 | PARPORT_CONTROL_AUTOFD,
804 PARPORT_CONTROL_INIT
805 | PARPORT_CONTROL_AUTOFD);
806
807 /* Event 49: PError goes high. */
3aeda9bc 808 r = parport_wait_peripheral(port,
1da177e4
LT		 809 PARPORT_STATUS_PAPEROUT,
810 PARPORT_STATUS_PAPEROUT);
811 if (r) {
3aeda9bc 812 printk(KERN_DEBUG "%s: PError timeout (%d) "
1da177e4
LT		 813 "in ecp_write_block_pio\n", port->name, r);
814 }
815 }
816
817 /* Set up ECP parallel port mode.*/
3aeda9bc
AC		 818 parport_pc_data_forward(port); /* Must be in PS2 mode */
819 parport_pc_frob_control(port,
1da177e4
LT		 820 PARPORT_CONTROL_STROBE |
821 PARPORT_CONTROL_AUTOFD,
822 0);
3aeda9bc
AC		 823 r = change_mode(port, ECR_ECP); /* ECP FIFO */
824 if (r)
825 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
826 port->name);
1da177e4
LT		 827 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
828
829 /* Write the data to the FIFO. */
7fbacd52 830 written = parport_pc_fifo_write_block(port, buf, length);
1da177e4
LT		 831
832 /* Finish up. */
833 /* For some hardware we don't want to touch the mode until
834 * the FIFO is empty, so allow 4 seconds for each position
835 * in the fifo.
836 */
837 expire = jiffies + (priv->fifo_depth * (HZ * 4));
838 do {
839 /* Wait for the FIFO to empty */
3aeda9bc
AC		 840 r = change_mode(port, ECR_PS2);
841 if (r != -EBUSY)
1da177e4 842 break;
3aeda9bc 843 } while (time_before(jiffies, expire));
1da177e4
LT		 844 if (r == -EBUSY) {
845
3aeda9bc 846 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
1da177e4
LT		 847
848 /* Prevent further data transfer. */
3aeda9bc 849 frob_set_mode(port, ECR_TST);
1da177e4
LT		 850
851 /* Adjust for the contents of the FIFO. */
852 for (written -= priv->fifo_depth; ; written++) {
3aeda9bc 853 if (inb(ECONTROL(port)) & 0x2) {
1da177e4
LT		 854 /* Full up. */
855 break;
856 }
3aeda9bc 857 outb(0, FIFO(port));
1da177e4
LT		 858 }
859
860 /* Reset the FIFO and return to PS2 mode. */
3aeda9bc 861 frob_set_mode(port, ECR_PS2);
1da177e4
LT		 862
863 /* Host transfer recovery. */
3aeda9bc
AC		 864 parport_pc_data_reverse(port); /* Must be in PS2 mode */
865 udelay(5);
866 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
867 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
1da177e4 868 if (r)
3aeda9bc 869 printk(KERN_DEBUG "%s: PE,1 timeout (%d) "
1da177e4
LT		 870 "in ecp_write_block_pio\n", port->name, r);
871
3aeda9bc 872 parport_frob_control(port,
1da177e4
LT		 873 PARPORT_CONTROL_INIT,
874 PARPORT_CONTROL_INIT);
3aeda9bc 875 r = parport_wait_peripheral(port,
1da177e4
LT		 876 PARPORT_STATUS_PAPEROUT,
877 PARPORT_STATUS_PAPEROUT);
3aeda9bc
AC		 878 if (r)
879 printk(KERN_DEBUG "%s: PE,2 timeout (%d) "
1da177e4
LT		 880 "in ecp_write_block_pio\n", port->name, r);
881 }
882
3aeda9bc
AC		 883 r = parport_wait_peripheral(port,
884 PARPORT_STATUS_BUSY,
1da177e4 885 PARPORT_STATUS_BUSY);
3aeda9bc
AC		 886 if (r)
887 printk(KERN_DEBUG
1da177e4
LT		 888 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
889 port->name, r);
890
891 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
892
893 return written;
894}
1da177e4
LT		 895#endif /* IEEE 1284 support */
896#endif /* Allowed to use FIFO/DMA */
897
898
899/*
900 * ******************************************
901 * INITIALISATION AND MODULE STUFF BELOW HERE
902 * ******************************************
903 */
904
905/* GCC is not inlining extern inline function later overwriten to non-inline,
906 so we use outlined_ variants here. */
3aeda9bc 907static const struct parport_operations parport_pc_ops = {
1da177e4
LT		 908 .write_data = parport_pc_write_data,
909 .read_data = parport_pc_read_data,
910
911 .write_control = parport_pc_write_control,
912 .read_control = parport_pc_read_control,
913 .frob_control = parport_pc_frob_control,
914
915 .read_status = parport_pc_read_status,
916
917 .enable_irq = parport_pc_enable_irq,
918 .disable_irq = parport_pc_disable_irq,
919
920 .data_forward = parport_pc_data_forward,
921 .data_reverse = parport_pc_data_reverse,
922
923 .init_state = parport_pc_init_state,
924 .save_state = parport_pc_save_state,
925 .restore_state = parport_pc_restore_state,
926
927 .epp_write_data = parport_ieee1284_epp_write_data,
928 .epp_read_data = parport_ieee1284_epp_read_data,
929 .epp_write_addr = parport_ieee1284_epp_write_addr,
930 .epp_read_addr = parport_ieee1284_epp_read_addr,
931
932 .ecp_write_data = parport_ieee1284_ecp_write_data,
933 .ecp_read_data = parport_ieee1284_ecp_read_data,
934 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
935
936 .compat_write_data = parport_ieee1284_write_compat,
937 .nibble_read_data = parport_ieee1284_read_nibble,
938 .byte_read_data = parport_ieee1284_read_byte,
939
940 .owner = THIS_MODULE,
941};
942
943#ifdef CONFIG_PARPORT_PC_SUPERIO
181bf1e8
AC		 944
945static struct superio_struct *find_free_superio(void)
946{
947 int i;
948 for (i = 0; i < NR_SUPERIOS; i++)
949 if (superios[i].io == 0)
950 return &superios[i];
951 return NULL;
952}
953
954
1da177e4 955/* Super-IO chipset detection, Winbond, SMSC */
312facaf 956static void show_parconfig_smsc37c669(int io, int key)
1da177e4 957{
181bf1e8
AC		 958 int cr1, cr4, cra, cr23, cr26, cr27;
959 struct superio_struct *s;
960
3aeda9bc 961 static const char *const modes[] = {
a6767b7c
MK		 962 "SPP and Bidirectional (PS/2)",
963 "EPP and SPP",
964 "ECP",
965 "ECP and EPP" };
1da177e4 966
3aeda9bc
AC		 967 outb(key, io);
968 outb(key, io);
969 outb(1, io);
970 cr1 = inb(io + 1);
971 outb(4, io);
972 cr4 = inb(io + 1);
973 outb(0x0a, io);
974 cra = inb(io + 1);
975 outb(0x23, io);
976 cr23 = inb(io + 1);
977 outb(0x26, io);
978 cr26 = inb(io + 1);
979 outb(0x27, io);
980 cr27 = inb(io + 1);
981 outb(0xaa, io);
1da177e4
LT		 982
983 if (verbose_probing) {
3aeda9bc
AC		 984 printk(KERN_INFO
985 "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1da177e4 986 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
3aeda9bc
AC		 987 cr1, cr4, cra, cr23, cr26, cr27);
988
1da177e4
LT		 989 /* The documentation calls DMA and IRQ-Lines by letters, so
990 the board maker can/will wire them
991 appropriately/randomly... G=reserved H=IDE-irq, */
3aeda9bc
AC		 992 printk(KERN_INFO
993 "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
994 cr23 * 4,
995 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
996 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
997 cra & 0x0f);
1da177e4 998 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
3aeda9bc
AC		 999 (cr23 * 4 >= 0x100) ? "yes" : "no",
1000 (cr1 & 4) ? "yes" : "no");
1001 printk(KERN_INFO
1002 "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1003 (cr1 & 0x08) ? "Standard mode only (SPP)"
1004 : modes[cr4 & 0x03],
1005 (cr4 & 0x40) ? "1.7" : "1.9");
1da177e4 1006 }
73e0d48b 1007
1da177e4
LT		 1008 /* Heuristics ! BIOS setup for this mainboard device limits
1009 the choices to standard settings, i.e. io-address and IRQ
1010 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1011 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
73e0d48b 1012 if (cr23 * 4 >= 0x100) { /* if active */
181bf1e8
AC		 1013 s = find_free_superio();
1014 if (s == NULL)
1da177e4 1015 printk(KERN_INFO "Super-IO: too many chips!\n");
181bf1e8 1016 else {
1da177e4 1017 int d;
3aeda9bc
AC		 1018 switch (cr23 * 4) {
1019 case 0x3bc:
181bf1e8
AC		 1020 s->io = 0x3bc;
1021 s->irq = 7;
3aeda9bc
AC		 1022 break;
1023 case 0x378:
181bf1e8
AC		 1024 s->io = 0x378;
1025 s->irq = 7;
3aeda9bc
AC		 1026 break;
1027 case 0x278:
181bf1e8
AC		 1028 s->io = 0x278;
1029 s->irq = 5;
1da177e4 1030 }
3aeda9bc
AC		 1031 d = (cr26 & 0x0f);
1032 if (d == 1 || d == 3)
181bf1e8 1033 s->dma = d;
1da177e4 1034 else
181bf1e8 1035 s->dma = PARPORT_DMA_NONE;
1da177e4 1036 }
3aeda9bc 1037 }
1da177e4
LT		 1038}
1039
1040
312facaf 1041static void show_parconfig_winbond(int io, int key)
1da177e4 1042{
181bf1e8
AC		 1043 int cr30, cr60, cr61, cr70, cr74, crf0;
1044 struct superio_struct *s;
a6767b7c 1045 static const char *const modes[] = {
1da177e4
LT		 1046 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1047 "EPP-1.9 and SPP",
1048 "ECP",
1049 "ECP and EPP-1.9",
1050 "Standard (SPP)",
1051 "EPP-1.7 and SPP", /* 5 */
1052 "undefined!",
1053 "ECP and EPP-1.7" };
a6767b7c
MK		 1054 static char *const irqtypes[] = {
1055 "pulsed low, high-Z",
1056 "follows nACK" };
3aeda9bc 1057
1da177e4 1058 /* The registers are called compatible-PnP because the
3aeda9bc
AC		 1059 register layout is modelled after ISA-PnP, the access
1060 method is just another ... */
1061 outb(key, io);
1062 outb(key, io);
1063 outb(0x07, io); /* Register 7: Select Logical Device */
1064 outb(0x01, io + 1); /* LD1 is Parallel Port */
1065 outb(0x30, io);
1066 cr30 = inb(io + 1);
1067 outb(0x60, io);
1068 cr60 = inb(io + 1);
1069 outb(0x61, io);
1070 cr61 = inb(io + 1);
1071 outb(0x70, io);
1072 cr70 = inb(io + 1);
1073 outb(0x74, io);
1074 cr74 = inb(io + 1);
1075 outb(0xf0, io);
1076 crf0 = inb(io + 1);
1077 outb(0xaa, io);
1da177e4
LT		 1078
1079 if (verbose_probing) {
3aeda9bc
AC		 1080 printk(KERN_INFO
1081 "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1082 cr30, cr60, cr61, cr70, cr74, crf0);
1083 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1084 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1da177e4
LT		 1085 if ((cr74 & 0x07) > 3)
1086 printk("dma=none\n");
1087 else
3aeda9bc
AC		 1088 printk("dma=%d\n", cr74 & 0x07);
1089 printk(KERN_INFO
1090 "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1091 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1092 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n",
1093 modes[crf0 & 0x07]);
1da177e4
LT		 1094 }
1095
73e0d48b 1096 if (cr30 & 0x01) { /* the settings can be interrogated later ... */
181bf1e8
AC		 1097 s = find_free_superio();
1098 if (s == NULL)
1da177e4 1099 printk(KERN_INFO "Super-IO: too many chips!\n");
181bf1e8
AC		 1100 else {
1101 s->io = (cr60 << 8) | cr61;
1102 s->irq = cr70 & 0x0f;
1103 s->dma = (((cr74 & 0x07) > 3) ?
1da177e4
LT		 1104 PARPORT_DMA_NONE : (cr74 & 0x07));
1105 }
1106 }
1107}
1108
312facaf 1109static void decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1da177e4
LT		 1110{
1111 const char *type = "unknown";
3aeda9bc 1112 int id, progif = 2;
1da177e4
LT		 1113
1114 if (devid == devrev)
1115 /* simple heuristics, we happened to read some
3aeda9bc 1116 non-winbond register */
1da177e4
LT		 1117 return;
1118
3aeda9bc 1119 id = (devid << 8) | devrev;
1da177e4
LT		 1120
1121 /* Values are from public data sheets pdf files, I can just
3aeda9bc
AC		 1122 confirm 83977TF is correct :-) */
1123 if (id == 0x9771)
1124 type = "83977F/AF";
1125 else if (id == 0x9773)
1126 type = "83977TF / SMSC 97w33x/97w34x";
1127 else if (id == 0x9774)
1128 type = "83977ATF";
1129 else if ((id & ~0x0f) == 0x5270)
1130 type = "83977CTF / SMSC 97w36x";
1131 else if ((id & ~0x0f) == 0x52f0)
1132 type = "83977EF / SMSC 97w35x";
1133 else if ((id & ~0x0f) == 0x5210)
1134 type = "83627";
1135 else if ((id & ~0x0f) == 0x6010)
1136 type = "83697HF";
1137 else if ((oldid & 0x0f) == 0x0a) {
1138 type = "83877F";
1139 progif = 1;
1140 } else if ((oldid & 0x0f) == 0x0b) {
1141 type = "83877AF";
1142 progif = 1;
1143 } else if ((oldid & 0x0f) == 0x0c) {
1144 type = "83877TF";
1145 progif = 1;
1146 } else if ((oldid & 0x0f) == 0x0d) {
1147 type = "83877ATF";
1148 progif = 1;
1149 } else
1150 progif = 0;
1da177e4
LT		 1151
1152 if (verbose_probing)
1153 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
3aeda9bc 1154 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1da177e4
LT		 1155 efer, key, devid, devrev, oldid, type);
1156
1157 if (progif == 2)
3aeda9bc 1158 show_parconfig_winbond(efer, key);
1da177e4
LT		 1159}
1160
312facaf 1161static void decode_smsc(int efer, int key, int devid, int devrev)
1da177e4 1162{
3aeda9bc 1163 const char *type = "unknown";
1da177e4 1164 void (*func)(int io, int key);
3aeda9bc 1165 int id;
1da177e4 1166
3aeda9bc 1167 if (devid == devrev)
1da177e4 1168 /* simple heuristics, we happened to read some
3aeda9bc 1169 non-smsc register */
1da177e4
LT		 1170 return;
1171
3aeda9bc
AC		 1172 func = NULL;
1173 id = (devid << 8) | devrev;
1da177e4 1174
3aeda9bc
AC		 1175 if (id == 0x0302) {
1176 type = "37c669";
1177 func = show_parconfig_smsc37c669;
1178 } else if (id == 0x6582)
1179 type = "37c665IR";
1180 else if (devid == 0x65)
1181 type = "37c665GT";
1182 else if (devid == 0x66)
1183 type = "37c666GT";
1da177e4
LT		 1184
1185 if (verbose_probing)
1186 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1187 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1188 efer, key, devid, devrev, type);
1189
1190 if (func)
3aeda9bc 1191 func(efer, key);
1da177e4
LT		 1192}
1193
1194
312facaf 1195static void winbond_check(int io, int key)
1da177e4 1196{
e2434dc1 1197 int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1da177e4 1198
145980a0 1199 if (!request_region(io, 3, __func__))
1da177e4
LT		 1200 return;
1201
e2434dc1
JR		 1202 origval = inb(io); /* Save original value */
1203
1da177e4 1204 /* First probe without key */
3aeda9bc
AC		 1205 outb(0x20, io);
1206 x_devid = inb(io + 1);
1207 outb(0x21, io);
1208 x_devrev = inb(io + 1);
1209 outb(0x09, io);
1210 x_oldid = inb(io + 1);
1211
1212 outb(key, io);
1213 outb(key, io); /* Write Magic Sequence to EFER, extended
25985edc 1214 function enable register */
3aeda9bc
AC		 1215 outb(0x20, io); /* Write EFIR, extended function index register */
1216 devid = inb(io + 1); /* Read EFDR, extended function data register */
1217 outb(0x21, io);
1218 devrev = inb(io + 1);
1219 outb(0x09, io);
1220 oldid = inb(io + 1);
1221 outb(0xaa, io); /* Magic Seal */
1da177e4 1222
e2434dc1
JR		 1223 outb(origval, io); /* in case we poked some entirely different hardware */
1224
1da177e4
LT		 1225 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1226 goto out; /* protection against false positives */
1227
3aeda9bc 1228 decode_winbond(io, key, devid, devrev, oldid);
1da177e4
LT		 1229out:
1230 release_region(io, 3);
1231}
1232
312facaf 1233static void winbond_check2(int io, int key)
1da177e4 1234{
e2434dc1 1235 int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1da177e4 1236
145980a0 1237 if (!request_region(io, 3, __func__))
1da177e4
LT		 1238 return;
1239
e2434dc1
JR		 1240 origval[0] = inb(io); /* Save original values */
1241 origval[1] = inb(io + 1);
1242 origval[2] = inb(io + 2);
1243
1da177e4 1244 /* First probe without the key */
3aeda9bc
AC		 1245 outb(0x20, io + 2);
1246 x_devid = inb(io + 2);
1247 outb(0x21, io + 1);
1248 x_devrev = inb(io + 2);
1249 outb(0x09, io + 1);
1250 x_oldid = inb(io + 2);
1251
1252 outb(key, io); /* Write Magic Byte to EFER, extended
25985edc 1253 function enable register */
3aeda9bc
AC		 1254 outb(0x20, io + 2); /* Write EFIR, extended function index register */
1255 devid = inb(io + 2); /* Read EFDR, extended function data register */
1256 outb(0x21, io + 1);
1257 devrev = inb(io + 2);
1258 outb(0x09, io + 1);
1259 oldid = inb(io + 2);
1260 outb(0xaa, io); /* Magic Seal */
1261
e2434dc1
JR		 1262 outb(origval[0], io); /* in case we poked some entirely different hardware */
1263 outb(origval[1], io + 1);
1264 outb(origval[2], io + 2);
1265
3aeda9bc 1266 if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1da177e4
LT		 1267 goto out; /* protection against false positives */
1268
3aeda9bc 1269 decode_winbond(io, key, devid, devrev, oldid);
1da177e4
LT		 1270out:
1271 release_region(io, 3);
1272}
1273
312facaf 1274static void smsc_check(int io, int key)
1da177e4 1275{
e2434dc1 1276 int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1da177e4 1277
145980a0 1278 if (!request_region(io, 3, __func__))
1da177e4
LT		 1279 return;
1280
e2434dc1
JR		 1281 origval = inb(io); /* Save original value */
1282
1da177e4 1283 /* First probe without the key */
3aeda9bc
AC		 1284 outb(0x0d, io);
1285 x_oldid = inb(io + 1);
1286 outb(0x0e, io);
1287 x_oldrev = inb(io + 1);
1288 outb(0x20, io);
1289 x_id = inb(io + 1);
1290 outb(0x21, io);
1291 x_rev = inb(io + 1);
1292
1293 outb(key, io);
1294 outb(key, io); /* Write Magic Sequence to EFER, extended
25985edc 1295 function enable register */
3aeda9bc
AC		 1296 outb(0x0d, io); /* Write EFIR, extended function index register */
1297 oldid = inb(io + 1); /* Read EFDR, extended function data register */
1298 outb(0x0e, io);
1299 oldrev = inb(io + 1);
1300 outb(0x20, io);
1301 id = inb(io + 1);
1302 outb(0x21, io);
1303 rev = inb(io + 1);
1304 outb(0xaa, io); /* Magic Seal */
1305
e2434dc1
JR		 1306 outb(origval, io); /* in case we poked some entirely different hardware */
1307
3aeda9bc
AC		 1308 if (x_id == id && x_oldrev == oldrev &&
1309 x_oldid == oldid && x_rev == rev)
1da177e4
LT		 1310 goto out; /* protection against false positives */
1311
3aeda9bc 1312 decode_smsc(io, key, oldid, oldrev);
1da177e4
LT		 1313out:
1314 release_region(io, 3);
1315}
1316
1317
312facaf 1318static void detect_and_report_winbond(void)
3aeda9bc 1319{
1da177e4
LT		 1320 if (verbose_probing)
1321 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
3aeda9bc
AC		 1322 winbond_check(0x3f0, 0x87);
1323 winbond_check(0x370, 0x87);
1324 winbond_check(0x2e , 0x87);
1325 winbond_check(0x4e , 0x87);
1326 winbond_check(0x3f0, 0x86);
1327 winbond_check2(0x250, 0x88);
1328 winbond_check2(0x250, 0x89);
1da177e4
LT		 1329}
1330
312facaf 1331static void detect_and_report_smsc(void)
1da177e4
LT		 1332{
1333 if (verbose_probing)
1334 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
3aeda9bc
AC		 1335 smsc_check(0x3f0, 0x55);
1336 smsc_check(0x370, 0x55);
1337 smsc_check(0x3f0, 0x44);
1338 smsc_check(0x370, 0x44);
1da177e4 1339}
f63fd7e2 1340
312facaf 1341static void detect_and_report_it87(void)
f63fd7e2
PC		 1342{
1343 u16 dev;
e2434dc1 1344 u8 origval, r;
f63fd7e2
PC		 1345 if (verbose_probing)
1346 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
868d1721 1347 if (!request_muxed_region(0x2e, 2, __func__))
f63fd7e2 1348 return;
e2434dc1 1349 origval = inb(0x2e); /* Save original value */
f63fd7e2
PC		 1350 outb(0x87, 0x2e);
1351 outb(0x01, 0x2e);
1352 outb(0x55, 0x2e);
1353 outb(0x55, 0x2e);
1354 outb(0x20, 0x2e);
1355 dev = inb(0x2f) << 8;
1356 outb(0x21, 0x2e);
1357 dev |= inb(0x2f);
1358 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1359 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1360 printk(KERN_INFO "IT%04X SuperIO detected.\n", dev);
1361 outb(0x07, 0x2E); /* Parallel Port */
1362 outb(0x03, 0x2F);
1363 outb(0xF0, 0x2E); /* BOOT 0x80 off */
1364 r = inb(0x2f);
1365 outb(0xF0, 0x2E);
1366 outb(r | 8, 0x2F);
1367 outb(0x02, 0x2E); /* Lock */
1368 outb(0x02, 0x2F);
e2434dc1
JR		 1369 } else {
1370 outb(origval, 0x2e); /* Oops, sorry to disturb */
f63fd7e2 1371 }
e2434dc1 1372 release_region(0x2e, 2);
f63fd7e2 1373}
1da177e4
LT		 1374#endif /* CONFIG_PARPORT_PC_SUPERIO */
1375
181bf1e8 1376static struct superio_struct *find_superio(struct parport *p)
1da177e4 1377{
181bf1e8
AC		 1378 int i;
1379 for (i = 0; i < NR_SUPERIOS; i++)
1380 if (superios[i].io != p->base)
1381 return &superios[i];
1382 return NULL;
1383}
73e0d48b 1384
181bf1e8
AC		 1385static int get_superio_dma(struct parport *p)
1386{
1387 struct superio_struct *s = find_superio(p);
1388 if (s)
1389 return s->dma;
1da177e4
LT		 1390 return PARPORT_DMA_NONE;
1391}
1392
3aeda9bc 1393static int get_superio_irq(struct parport *p)
1da177e4 1394{
181bf1e8
AC		 1395 struct superio_struct *s = find_superio(p);
1396 if (s)
1397 return s->irq;
3aeda9bc 1398 return PARPORT_IRQ_NONE;
1da177e4 1399}
73e0d48b 1400
1da177e4
LT		 1401
1402/* --- Mode detection ------------------------------------- */
1403
1404/*
1405 * Checks for port existence, all ports support SPP MODE
3aeda9bc 1406 * Returns:
1da177e4 1407 * 0 : No parallel port at this address
3aeda9bc 1408 * PARPORT_MODE_PCSPP : SPP port detected
1da177e4
LT		 1409 * (if the user specified an ioport himself,
1410 * this shall always be the case!)
1411 *
1412 */
96766a3c 1413static int parport_SPP_supported(struct parport *pb)
1da177e4
LT		 1414{
1415 unsigned char r, w;
1416
1417 /*
3aeda9bc 1418 * first clear an eventually pending EPP timeout
1da177e4
LT		 1419 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1420 * that does not even respond to SPP cycles if an EPP
1421 * timeout is pending
1422 */
1423 clear_epp_timeout(pb);
1424
1425 /* Do a simple read-write test to make sure the port exists. */
1426 w = 0xc;
3aeda9bc 1427 outb(w, CONTROL(pb));
1da177e4
LT		 1428
1429 /* Is there a control register that we can read from? Some
1430 * ports don't allow reads, so read_control just returns a
1431 * software copy. Some ports _do_ allow reads, so bypass the
1432 * software copy here. In addition, some bits aren't
1433 * writable. */
3aeda9bc 1434 r = inb(CONTROL(pb));
1da177e4
LT		 1435 if ((r & 0xf) == w) {
1436 w = 0xe;
3aeda9bc
AC		 1437 outb(w, CONTROL(pb));
1438 r = inb(CONTROL(pb));
1439 outb(0xc, CONTROL(pb));
1da177e4
LT		 1440 if ((r & 0xf) == w)
1441 return PARPORT_MODE_PCSPP;
1442 }
1443
1444 if (user_specified)
1445 /* That didn't work, but the user thinks there's a
1446 * port here. */
3aeda9bc 1447 printk(KERN_INFO "parport 0x%lx (WARNING): CTR: "
1da177e4
LT		 1448 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1449
1450 /* Try the data register. The data lines aren't tri-stated at
1451 * this stage, so we expect back what we wrote. */
1452 w = 0xaa;
3aeda9bc
AC		 1453 parport_pc_write_data(pb, w);
1454 r = parport_pc_read_data(pb);
1da177e4
LT		 1455 if (r == w) {
1456 w = 0x55;
3aeda9bc
AC		 1457 parport_pc_write_data(pb, w);
1458 r = parport_pc_read_data(pb);
1da177e4
LT		 1459 if (r == w)
1460 return PARPORT_MODE_PCSPP;
1461 }
1462
1463 if (user_specified) {
1464 /* Didn't work, but the user is convinced this is the
1465 * place. */
3aeda9bc 1466 printk(KERN_INFO "parport 0x%lx (WARNING): DATA: "
1da177e4 1467 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
3aeda9bc 1468 printk(KERN_INFO "parport 0x%lx: You gave this address, "
1da177e4
LT		 1469 "but there is probably no parallel port there!\n",
1470 pb->base);
1471 }
1472
1473 /* It's possible that we can't read the control register or
1474 * the data register. In that case just believe the user. */
1475 if (user_specified)
1476 return PARPORT_MODE_PCSPP;
1477
1478 return 0;
1479}
1480
1481/* Check for ECR
1482 *
1483 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1484 * on these cards actually accesses the CTR.
1485 *
1486 * Modern cards don't do this but reading from ECR will return 0xff
1487 * regardless of what is written here if the card does NOT support
1488 * ECP.
1489 *
1490 * We first check to see if ECR is the same as CTR. If not, the low
1491 * two bits of ECR aren't writable, so we check by writing ECR and
1492 * reading it back to see if it's what we expect.
1493 */
96766a3c 1494static int parport_ECR_present(struct parport *pb)
1da177e4
LT		 1495{
1496 struct parport_pc_private *priv = pb->private_data;
1497 unsigned char r = 0xc;
1498
3aeda9bc
AC		 1499 outb(r, CONTROL(pb));
1500 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1501 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1da177e4 1502
3aeda9bc
AC		 1503 r = inb(CONTROL(pb));
1504 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1da177e4
LT		 1505 goto no_reg; /* Sure that no ECR register exists */
1506 }
3aeda9bc
AC		 1507
1508 if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1da177e4
LT		 1509 goto no_reg;
1510
3aeda9bc
AC		 1511 ECR_WRITE(pb, 0x34);
1512 if (inb(ECONTROL(pb)) != 0x35)
1da177e4
LT		 1513 goto no_reg;
1514
1515 priv->ecr = 1;
3aeda9bc
AC		 1516 outb(0xc, CONTROL(pb));
1517
1da177e4 1518 /* Go to mode 000 */
3aeda9bc 1519 frob_set_mode(pb, ECR_SPP);
1da177e4
LT		 1520
1521 return 1;
1522
1523 no_reg:
3aeda9bc
AC		 1524 outb(0xc, CONTROL(pb));
1525 return 0;
1da177e4
LT		 1526}
1527
1528#ifdef CONFIG_PARPORT_1284
1529/* Detect PS/2 support.
1530 *
1531 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1532 * allows us to read data from the data lines. In theory we would get back
1533 * 0xff but any peripheral attached to the port may drag some or all of the
1534 * lines down to zero. So if we get back anything that isn't the contents
3aeda9bc 1535 * of the data register we deem PS/2 support to be present.
1da177e4
LT		 1536 *
1537 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1538 * drivers, but an external peripheral with sufficiently beefy drivers of
1539 * its own can overpower them and assert its own levels onto the bus, from
1540 * where they can then be read back as normal. Ports with this property
1541 * and the right type of device attached are likely to fail the SPP test,
1542 * (as they will appear to have stuck bits) and so the fact that they might
3aeda9bc 1543 * be misdetected here is rather academic.
1da177e4
LT		 1544 */
1545
96766a3c 1546static int parport_PS2_supported(struct parport *pb)
1da177e4
LT		 1547{
1548 int ok = 0;
3aeda9bc 1549
1da177e4
LT		 1550 clear_epp_timeout(pb);
1551
1552 /* try to tri-state the buffer */
3aeda9bc
AC		 1553 parport_pc_data_reverse(pb);
1554
1da177e4 1555 parport_pc_write_data(pb, 0x55);
3aeda9bc
AC		 1556 if (parport_pc_read_data(pb) != 0x55)
1557 ok++;
1da177e4
LT		 1558
1559 parport_pc_write_data(pb, 0xaa);
3aeda9bc
AC		 1560 if (parport_pc_read_data(pb) != 0xaa)
1561 ok++;
1da177e4
LT		 1562
1563 /* cancel input mode */
3aeda9bc 1564 parport_pc_data_forward(pb);
1da177e4
LT		 1565
1566 if (ok) {
1567 pb->modes |= PARPORT_MODE_TRISTATE;
1568 } else {
1569 struct parport_pc_private *priv = pb->private_data;
1570 priv->ctr_writable &= ~0x20;
1571 }
1572
1573 return ok;
1574}
1575
1576#ifdef CONFIG_PARPORT_PC_FIFO
55265b00 1577static int parport_ECP_supported(struct parport *pb)
1da177e4
LT		 1578{
1579 int i;
1580 int config, configb;
1581 int pword;
1582 struct parport_pc_private *priv = pb->private_data;
3aeda9bc
AC		 1583 /* Translate ECP intrLine to ISA irq value */
1584 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1da177e4
LT		 1585
1586 /* If there is no ECR, we have no hope of supporting ECP. */
1587 if (!priv->ecr)
1588 return 0;
1589
1590 /* Find out FIFO depth */
3aeda9bc
AC		 1591 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1592 ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1593 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1594 outb(0xaa, FIFO(pb));
1da177e4
LT		 1595
1596 /*
1597 * Using LGS chipset it uses ECR register, but
1598 * it doesn't support ECP or FIFO MODE
1599 */
1600 if (i == 1024) {
3aeda9bc 1601 ECR_WRITE(pb, ECR_SPP << 5);
1da177e4
LT		 1602 return 0;
1603 }
1604
1605 priv->fifo_depth = i;
1606 if (verbose_probing)
3aeda9bc 1607 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1da177e4
LT		 1608
1609 /* Find out writeIntrThreshold */
3aeda9bc
AC		 1610 frob_econtrol(pb, 1<<2, 1<<2);
1611 frob_econtrol(pb, 1<<2, 0);
1da177e4 1612 for (i = 1; i <= priv->fifo_depth; i++) {
3aeda9bc
AC		 1613 inb(FIFO(pb));
1614 udelay(50);
1615 if (inb(ECONTROL(pb)) & (1<<2))
1da177e4
LT		 1616 break;
1617 }
1618
1619 if (i <= priv->fifo_depth) {
1620 if (verbose_probing)
3aeda9bc 1621 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1da177e4
LT		 1622 pb->base, i);
1623 } else
1624 /* Number of bytes we know we can write if we get an
3aeda9bc 1625 interrupt. */
1da177e4
LT		 1626 i = 0;
1627
1628 priv->writeIntrThreshold = i;
1629
1630 /* Find out readIntrThreshold */
3aeda9bc
AC		 1631 frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1632 parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1633 frob_set_mode(pb, ECR_TST); /* Test FIFO */
1634 frob_econtrol(pb, 1<<2, 1<<2);
1635 frob_econtrol(pb, 1<<2, 0);
1da177e4 1636 for (i = 1; i <= priv->fifo_depth; i++) {
3aeda9bc
AC		 1637 outb(0xaa, FIFO(pb));
1638 if (inb(ECONTROL(pb)) & (1<<2))
1da177e4
LT		 1639 break;
1640 }
1641
1642 if (i <= priv->fifo_depth) {
1643 if (verbose_probing)
3aeda9bc 1644 printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1da177e4
LT		 1645 pb->base, i);
1646 } else
1647 /* Number of bytes we can read if we get an interrupt. */
1648 i = 0;
1649
1650 priv->readIntrThreshold = i;
1651
3aeda9bc
AC		 1652 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1653 ECR_WRITE(pb, 0xf4); /* Configuration mode */
1654 config = inb(CONFIGA(pb));
1da177e4
LT		 1655 pword = (config >> 4) & 0x7;
1656 switch (pword) {
1657 case 0:
1658 pword = 2;
3aeda9bc 1659 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1da177e4
LT		 1660 pb->base);
1661 break;
1662 case 2:
1663 pword = 4;
3aeda9bc 1664 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1da177e4
LT		 1665 pb->base);
1666 break;
1667 default:
3aeda9bc 1668 printk(KERN_WARNING "0x%lx: Unknown implementation ID\n",
1da177e4
LT		 1669 pb->base);
1670 /* Assume 1 */
1671 case 1:
1672 pword = 1;
1673 }
1674 priv->pword = pword;
1675
1676 if (verbose_probing) {
3aeda9bc
AC		 1677 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1678 pb->base, 8 * pword);
1679
1680 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1da177e4
LT		 1681 config & 0x80 ? "Level" : "Pulses");
1682
3aeda9bc
AC		 1683 configb = inb(CONFIGB(pb));
1684 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1da177e4 1685 pb->base, config, configb);
3aeda9bc
AC		 1686 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1687 if ((configb >> 3) & 0x07)
1688 printk("%d", intrline[(configb >> 3) & 0x07]);
1da177e4
LT		 1689 else
1690 printk("<none or set by other means>");
3aeda9bc
AC		 1691 printk(" dma=");
1692 if ((configb & 0x03) == 0x00)
1da177e4
LT		 1693 printk("<none or set by other means>\n");
1694 else
3aeda9bc 1695 printk("%d\n", configb & 0x07);
1da177e4
LT		 1696 }
1697
1698 /* Go back to mode 000 */
3aeda9bc 1699 frob_set_mode(pb, ECR_SPP);
1da177e4
LT		 1700
1701 return 1;
1702}
1703#endif
1704
96766a3c 1705static int parport_ECPPS2_supported(struct parport *pb)
1da177e4
LT		 1706{
1707 const struct parport_pc_private *priv = pb->private_data;
1708 int result;
1709 unsigned char oecr;
1710
1711 if (!priv->ecr)
1712 return 0;
1713
3aeda9bc
AC		 1714 oecr = inb(ECONTROL(pb));
1715 ECR_WRITE(pb, ECR_PS2 << 5);
1da177e4 1716 result = parport_PS2_supported(pb);
3aeda9bc 1717 ECR_WRITE(pb, oecr);
1da177e4
LT		 1718 return result;
1719}
1720
1721/* EPP mode detection */
1722
96766a3c 1723static int parport_EPP_supported(struct parport *pb)
1da177e4
LT		 1724{
1725 const struct parport_pc_private *priv = pb->private_data;
1726
1727 /*
1728 * Theory:
1729 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1730 * when EPP is possible and is set high when an EPP timeout
1731 * occurs (EPP uses the HALT line to stop the CPU while it does
1732 * the byte transfer, an EPP timeout occurs if the attached
1733 * device fails to respond after 10 micro seconds).
1734 *
1735 * This bit is cleared by either reading it (National Semi)
1736 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1737 * This bit is always high in non EPP modes.
1738 */
1739
1740 /* If EPP timeout bit clear then EPP available */
3aeda9bc 1741 if (!clear_epp_timeout(pb))
1da177e4 1742 return 0; /* No way to clear timeout */
1da177e4
LT		 1743
1744 /* Check for Intel bug. */
1745 if (priv->ecr) {
1746 unsigned char i;
1747 for (i = 0x00; i < 0x80; i += 0x20) {
3aeda9bc
AC		 1748 ECR_WRITE(pb, i);
1749 if (clear_epp_timeout(pb)) {
1da177e4
LT		 1750 /* Phony EPP in ECP. */
1751 return 0;
1752 }
1753 }
1754 }
1755
1756 pb->modes |= PARPORT_MODE_EPP;
1757
1758 /* Set up access functions to use EPP hardware. */
1759 pb->ops->epp_read_data = parport_pc_epp_read_data;
1760 pb->ops->epp_write_data = parport_pc_epp_write_data;
1761 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1762 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1763
1764 return 1;
1765}
1766
96766a3c 1767static int parport_ECPEPP_supported(struct parport *pb)
1da177e4
LT		 1768{
1769 struct parport_pc_private *priv = pb->private_data;
1770 int result;
1771 unsigned char oecr;
1772
3aeda9bc 1773 if (!priv->ecr)
1da177e4 1774 return 0;
1da177e4 1775
3aeda9bc 1776 oecr = inb(ECONTROL(pb));
1da177e4 1777 /* Search for SMC style EPP+ECP mode */
3aeda9bc
AC		 1778 ECR_WRITE(pb, 0x80);
1779 outb(0x04, CONTROL(pb));
1da177e4
LT		 1780 result = parport_EPP_supported(pb);
1781
3aeda9bc 1782 ECR_WRITE(pb, oecr);
1da177e4
LT		 1783
1784 if (result) {
1785 /* Set up access functions to use ECP+EPP hardware. */
1786 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1787 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1788 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1789 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1790 }
1791
1792 return result;
1793}
1794
1795#else /* No IEEE 1284 support */
1796
1797/* Don't bother probing for modes we know we won't use. */
312facaf 1798static int parport_PS2_supported(struct parport *pb) { return 0; }
1da177e4 1799#ifdef CONFIG_PARPORT_PC_FIFO
3aeda9bc
AC		 1800static int parport_ECP_supported(struct parport *pb)
1801{
1802 return 0;
1803}
1da177e4 1804#endif
312facaf 1805static int parport_EPP_supported(struct parport *pb)
3aeda9bc
AC		 1806{
1807 return 0;
1808}
1809
312facaf 1810static int parport_ECPEPP_supported(struct parport *pb)
3aeda9bc
AC		 1811{
1812 return 0;
1813}
1814
312facaf 1815static int parport_ECPPS2_supported(struct parport *pb)
3aeda9bc
AC		 1816{
1817 return 0;
1818}
1da177e4
LT		 1819
1820#endif /* No IEEE 1284 support */
1821
1822/* --- IRQ detection -------------------------------------- */
1823
1824/* Only if supports ECP mode */
4438982f 1825static int programmable_irq_support(struct parport *pb)
1da177e4
LT		 1826{
1827 int irq, intrLine;
3aeda9bc 1828 unsigned char oecr = inb(ECONTROL(pb));
1da177e4
LT		 1829 static const int lookup[8] = {
1830 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1831 };
1832
3aeda9bc 1833 ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
1da177e4 1834
3aeda9bc 1835 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
1da177e4
LT		 1836 irq = lookup[intrLine];
1837
3aeda9bc 1838 ECR_WRITE(pb, oecr);
1da177e4
LT		 1839 return irq;
1840}
1841
4438982f 1842static int irq_probe_ECP(struct parport *pb)
1da177e4
LT		 1843{
1844 int i;
1845 unsigned long irqs;
1846
1847 irqs = probe_irq_on();
3aeda9bc
AC		 1848
1849 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1850 ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
1851 ECR_WRITE(pb, ECR_TST << 5);
1da177e4
LT		 1852
1853 /* If Full FIFO sure that writeIntrThreshold is generated */
3aeda9bc
AC		 1854 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
1855 outb(0xaa, FIFO(pb));
1856
1da177e4 1857 pb->irq = probe_irq_off(irqs);
3aeda9bc 1858 ECR_WRITE(pb, ECR_SPP << 5);
1da177e4
LT		 1859
1860 if (pb->irq <= 0)
1861 pb->irq = PARPORT_IRQ_NONE;
1862
1863 return pb->irq;
1864}
1865
1866/*
1867 * This detection seems that only works in National Semiconductors
3aeda9bc 1868 * This doesn't work in SMC, LGS, and Winbond
1da177e4 1869 */
4438982f 1870static int irq_probe_EPP(struct parport *pb)
1da177e4
LT		 1871{
1872#ifndef ADVANCED_DETECT
1873 return PARPORT_IRQ_NONE;
1874#else
1875 int irqs;
1876 unsigned char oecr;
1877
1878 if (pb->modes & PARPORT_MODE_PCECR)
3aeda9bc 1879 oecr = inb(ECONTROL(pb));
1da177e4
LT		 1880
1881 irqs = probe_irq_on();
1882
1883 if (pb->modes & PARPORT_MODE_PCECR)
3aeda9bc
AC		 1884 frob_econtrol(pb, 0x10, 0x10);
1885
1da177e4 1886 clear_epp_timeout(pb);
3aeda9bc
AC		 1887 parport_pc_frob_control(pb, 0x20, 0x20);
1888 parport_pc_frob_control(pb, 0x10, 0x10);
1da177e4
LT		 1889 clear_epp_timeout(pb);
1890
1891 /* Device isn't expecting an EPP read
1892 * and generates an IRQ.
1893 */
1894 parport_pc_read_epp(pb);
1895 udelay(20);
1896
3aeda9bc 1897 pb->irq = probe_irq_off(irqs);
1da177e4 1898 if (pb->modes & PARPORT_MODE_PCECR)
3aeda9bc 1899 ECR_WRITE(pb, oecr);
1da177e4
LT		 1900 parport_pc_write_control(pb, 0xc);
1901
1902 if (pb->irq <= 0)
1903 pb->irq = PARPORT_IRQ_NONE;
1904
1905 return pb->irq;
1906#endif /* Advanced detection */
1907}
1908
4438982f 1909static int irq_probe_SPP(struct parport *pb)
1da177e4
LT		 1910{
1911 /* Don't even try to do this. */
1912 return PARPORT_IRQ_NONE;
1913}
1914
1915/* We will attempt to share interrupt requests since other devices
1916 * such as sound cards and network cards seem to like using the
1917 * printer IRQs.
1918 *
1919 * When ECP is available we can autoprobe for IRQs.
1920 * NOTE: If we can autoprobe it, we can register the IRQ.
1921 */
96766a3c 1922static int parport_irq_probe(struct parport *pb)
1da177e4
LT		 1923{
1924 struct parport_pc_private *priv = pb->private_data;
1925
1926 if (priv->ecr) {
1927 pb->irq = programmable_irq_support(pb);
1928
1929 if (pb->irq == PARPORT_IRQ_NONE)
1930 pb->irq = irq_probe_ECP(pb);
1931 }
1932
1933 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
1934 (pb->modes & PARPORT_MODE_EPP))
1935 pb->irq = irq_probe_EPP(pb);
1936
1937 clear_epp_timeout(pb);
1938
1939 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
1940 pb->irq = irq_probe_EPP(pb);
1941
1942 clear_epp_timeout(pb);
1943
1944 if (pb->irq == PARPORT_IRQ_NONE)
1945 pb->irq = irq_probe_SPP(pb);
1946
1947 if (pb->irq == PARPORT_IRQ_NONE)
1948 pb->irq = get_superio_irq(pb);
1949
1950 return pb->irq;
1951}
1952
1953/* --- DMA detection -------------------------------------- */
1954
1955/* Only if chipset conforms to ECP ISA Interface Standard */
3aeda9bc 1956static int programmable_dma_support(struct parport *p)
1da177e4 1957{
3aeda9bc 1958 unsigned char oecr = inb(ECONTROL(p));
1da177e4
LT		 1959 int dma;
1960
3aeda9bc
AC		 1961 frob_set_mode(p, ECR_CNF);
1962
1963 dma = inb(CONFIGB(p)) & 0x07;
1da177e4
LT		 1964 /* 000: Indicates jumpered 8-bit DMA if read-only.
1965 100: Indicates jumpered 16-bit DMA if read-only. */
1966 if ((dma & 0x03) == 0)
1967 dma = PARPORT_DMA_NONE;
1968
3aeda9bc 1969 ECR_WRITE(p, oecr);
1da177e4
LT		 1970 return dma;
1971}
1972
3aeda9bc 1973static int parport_dma_probe(struct parport *p)
1da177e4
LT		 1974{
1975 const struct parport_pc_private *priv = p->private_data;
3aeda9bc
AC		 1976 if (priv->ecr) /* ask ECP chipset first */
1977 p->dma = programmable_dma_support(p);
1da177e4
LT		 1978 if (p->dma == PARPORT_DMA_NONE) {
1979 /* ask known Super-IO chips proper, although these
1980 claim ECP compatible, some don't report their DMA
1981 conforming to ECP standards */
1982 p->dma = get_superio_dma(p);
1983 }
1984
1985 return p->dma;
1986}
1987
1988/* --- Initialisation code -------------------------------- */
1989
1990static LIST_HEAD(ports_list);
1991static DEFINE_SPINLOCK(ports_lock);
1992
51dcdfec
AC		 1993struct parport *parport_pc_probe_port(unsigned long int base,
1994 unsigned long int base_hi,
1995 int irq, int dma,
1996 struct device *dev,
1997 int irqflags)
1da177e4
LT		 1998{
1999 struct parport_pc_private *priv;
2000 struct parport_operations *ops;
2001 struct parport *p;
2002 int probedirq = PARPORT_IRQ_NONE;
2003 struct resource *base_res;
2004 struct resource *ECR_res = NULL;
2005 struct resource *EPP_res = NULL;
a7d801af
JD		 2006 struct platform_device *pdev = NULL;
2007
2008 if (!dev) {
2009 /* We need a physical device to attach to, but none was
2010 * provided. Create our own. */
2011 pdev = platform_device_register_simple("parport_pc",
2012 base, NULL, 0);
2013 if (IS_ERR(pdev))
2014 return NULL;
2015 dev = &pdev->dev;
dfa7c4d8
FT		 2016
2017 dev->coherent_dma_mask = DMA_BIT_MASK(24);
2018 dev->dma_mask = &dev->coherent_dma_mask;
a7d801af 2019 }
1da177e4 2020
51dcdfec 2021 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
1da177e4
LT		 2022 if (!ops)
2023 goto out1;
2024
51dcdfec 2025 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
1da177e4
LT		 2026 if (!priv)
2027 goto out2;
2028
2029 /* a misnomer, actually - it's allocate and reserve parport number */
2030 p = parport_register_port(base, irq, dma, ops);
2031 if (!p)
2032 goto out3;
2033
2034 base_res = request_region(base, 3, p->name);
2035 if (!base_res)
2036 goto out4;
2037
3aeda9bc 2038 memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
1da177e4
LT		 2039 priv->ctr = 0xc;
2040 priv->ctr_writable = ~0x10;
2041 priv->ecr = 0;
2042 priv->fifo_depth = 0;
2043 priv->dma_buf = NULL;
2044 priv->dma_handle = 0;
1da177e4
LT		 2045 INIT_LIST_HEAD(&priv->list);
2046 priv->port = p;
c15a3837
DB		 2047
2048 p->dev = dev;
1da177e4
LT		 2049 p->base_hi = base_hi;
2050 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2051 p->private_data = priv;
2052
2053 if (base_hi) {
2054 ECR_res = request_region(base_hi, 3, p->name);
2055 if (ECR_res)
2056 parport_ECR_present(p);
2057 }
2058
2059 if (base != 0x3bc) {
2060 EPP_res = request_region(base+0x3, 5, p->name);
2061 if (EPP_res)
2062 if (!parport_EPP_supported(p))
2063 parport_ECPEPP_supported(p);
2064 }
3aeda9bc 2065 if (!parport_SPP_supported(p))
1da177e4
LT		 2066 /* No port. */
2067 goto out5;
2068 if (priv->ecr)
2069 parport_ECPPS2_supported(p);
2070 else
2071 parport_PS2_supported(p);
2072
3aeda9bc 2073 p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
1da177e4
LT		 2074
2075 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2076 if (p->base_hi && priv->ecr)
2c03ead6 2077 printk(KERN_CONT " (0x%lx)", p->base_hi);
1da177e4
LT		 2078 if (p->irq == PARPORT_IRQ_AUTO) {
2079 p->irq = PARPORT_IRQ_NONE;
2080 parport_irq_probe(p);
2081 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2082 p->irq = PARPORT_IRQ_NONE;
2083 parport_irq_probe(p);
2084 probedirq = p->irq;
2085 p->irq = PARPORT_IRQ_NONE;
2086 }
2087 if (p->irq != PARPORT_IRQ_NONE) {
2c03ead6 2088 printk(KERN_CONT ", irq %d", p->irq);
1da177e4
LT		 2089 priv->ctr_writable |= 0x10;
2090
2091 if (p->dma == PARPORT_DMA_AUTO) {
2092 p->dma = PARPORT_DMA_NONE;
2093 parport_dma_probe(p);
2094 }
2095 }
2096 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
3aeda9bc 2097 is mandatory (see above) */
1da177e4
LT		 2098 p->dma = PARPORT_DMA_NONE;
2099
2100#ifdef CONFIG_PARPORT_PC_FIFO
2101 if (parport_ECP_supported(p) &&
2102 p->dma != PARPORT_DMA_NOFIFO &&
2103 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2104 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2105 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2106#ifdef CONFIG_PARPORT_1284
2107 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2108 /* currently broken, but working on it.. (FB) */
2109 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2110#endif /* IEEE 1284 support */
2111 if (p->dma != PARPORT_DMA_NONE) {
2c03ead6 2112 printk(KERN_CONT ", dma %d", p->dma);
1da177e4 2113 p->modes |= PARPORT_MODE_DMA;
3aeda9bc 2114 } else
2c03ead6 2115 printk(KERN_CONT ", using FIFO");
3aeda9bc 2116 } else
1da177e4
LT		 2117 /* We can't use the DMA channel after all. */
2118 p->dma = PARPORT_DMA_NONE;
2119#endif /* Allowed to use FIFO/DMA */
2120
2c03ead6 2121 printk(KERN_CONT " [");
3aeda9bc
AC		 2122
2123#define printmode(x) \
2124 {\
2125 if (p->modes & PARPORT_MODE_##x) {\
2c03ead6 2126 printk(KERN_CONT "%s%s", f ? "," : "", #x);\
3aeda9bc
AC		 2127 f++;\
2128 } \
2129 }
2130
1da177e4
LT		 2131 {
2132 int f = 0;
2133 printmode(PCSPP);
2134 printmode(TRISTATE);
2135 printmode(COMPAT)
2136 printmode(EPP);
2137 printmode(ECP);
2138 printmode(DMA);
2139 }
2140#undef printmode
2141#ifndef CONFIG_PARPORT_1284
2c03ead6 2142 printk(KERN_CONT "(,...)");
1da177e4 2143#endif /* CONFIG_PARPORT_1284 */
2c03ead6 2144 printk(KERN_CONT "]\n");
3aeda9bc 2145 if (probedirq != PARPORT_IRQ_NONE)
1da177e4
LT		 2146 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2147
2148 /* If No ECP release the ports grabbed above. */
2149 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2150 release_region(base_hi, 3);
2151 ECR_res = NULL;
2152 }
2153 /* Likewise for EEP ports */
2154 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2155 release_region(base+3, 5);
2156 EPP_res = NULL;
2157 }
2158 if (p->irq != PARPORT_IRQ_NONE) {
51dcdfec
AC		 2159 if (request_irq(p->irq, parport_irq_handler,
2160 irqflags, p->name, p)) {
3aeda9bc 2161 printk(KERN_WARNING "%s: irq %d in use, "
1da177e4
LT		 2162 "resorting to polled operation\n",
2163 p->name, p->irq);
2164 p->irq = PARPORT_IRQ_NONE;
2165 p->dma = PARPORT_DMA_NONE;
2166 }
2167
2168#ifdef CONFIG_PARPORT_PC_FIFO
7fbacd52 2169#ifdef HAS_DMA
1da177e4 2170 if (p->dma != PARPORT_DMA_NONE) {
3aeda9bc
AC		 2171 if (request_dma(p->dma, p->name)) {
2172 printk(KERN_WARNING "%s: dma %d in use, "
1da177e4
LT		 2173 "resorting to PIO operation\n",
2174 p->name, p->dma);
2175 p->dma = PARPORT_DMA_NONE;
2176 } else {
2177 priv->dma_buf =
c15a3837 2178 dma_alloc_coherent(dev,
1da177e4 2179 PAGE_SIZE,
c15a3837
DB		 2180 &priv->dma_handle,
2181 GFP_KERNEL);
3aeda9bc
AC		 2182 if (!priv->dma_buf) {
2183 printk(KERN_WARNING "%s: "
1da177e4
LT		 2184 "cannot get buffer for DMA, "
2185 "resorting to PIO operation\n",
2186 p->name);
2187 free_dma(p->dma);
2188 p->dma = PARPORT_DMA_NONE;
2189 }
2190 }
2191 }
7fbacd52
AV		 2192#endif
2193#endif
1da177e4
LT		 2194 }
2195
2196 /* Done probing. Now put the port into a sensible start-up state. */
2197 if (priv->ecr)
2198 /*
2199 * Put the ECP detected port in PS2 mode.
2200 * Do this also for ports that have ECR but don't do ECP.
2201 */
3aeda9bc 2202 ECR_WRITE(p, 0x34);
1da177e4
LT		 2203
2204 parport_pc_write_data(p, 0);
3aeda9bc 2205 parport_pc_data_forward(p);
1da177e4
LT		 2206
2207 /* Now that we've told the sharing engine about the port, and
2208 found out its characteristics, let the high-level drivers
2209 know about it. */
2210 spin_lock(&ports_lock);
2211 list_add(&priv->list, &ports_list);
2212 spin_unlock(&ports_lock);
3aeda9bc 2213 parport_announce_port(p);
1da177e4
LT		 2214
2215 return p;
2216
2217out5:
2218 if (ECR_res)
2219 release_region(base_hi, 3);
2220 if (EPP_res)
2221 release_region(base+0x3, 5);
2222 release_region(base, 3);
2223out4:
2224 parport_put_port(p);
2225out3:
3aeda9bc 2226 kfree(priv);
1da177e4 2227out2:
3aeda9bc 2228 kfree(ops);
1da177e4 2229out1:
a7d801af
JD		 2230 if (pdev)
2231 platform_device_unregister(pdev);
1da177e4
LT		 2232 return NULL;
2233}
3aeda9bc 2234EXPORT_SYMBOL(parport_pc_probe_port);
1da177e4 2235
3aeda9bc 2236void parport_pc_unregister_port(struct parport *p)
1da177e4
LT		 2237{
2238 struct parport_pc_private *priv = p->private_data;
2239 struct parport_operations *ops = p->ops;
2240
2241 parport_remove_port(p);
2242 spin_lock(&ports_lock);
2243 list_del_init(&priv->list);
2244 spin_unlock(&ports_lock);
d1c4ac40 2245#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
1da177e4
LT		 2246 if (p->dma != PARPORT_DMA_NONE)
2247 free_dma(p->dma);
d1c4ac40 2248#endif
1da177e4
LT		 2249 if (p->irq != PARPORT_IRQ_NONE)
2250 free_irq(p->irq, p);
2251 release_region(p->base, 3);
2252 if (p->size > 3)
2253 release_region(p->base + 3, p->size - 3);
2254 if (p->modes & PARPORT_MODE_ECP)
2255 release_region(p->base_hi, 3);
d1c4ac40 2256#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
1da177e4 2257 if (priv->dma_buf)
c15a3837 2258 dma_free_coherent(p->physport->dev, PAGE_SIZE,
1da177e4
LT		 2259 priv->dma_buf,
2260 priv->dma_handle);
7fbacd52 2261#endif
3aeda9bc 2262 kfree(p->private_data);
1da177e4 2263 parport_put_port(p);
3aeda9bc 2264 kfree(ops); /* hope no-one cached it */
1da177e4 2265}
3aeda9bc 2266EXPORT_SYMBOL(parport_pc_unregister_port);
1da177e4
LT		 2267
2268#ifdef CONFIG_PCI
2269
2270/* ITE support maintained by Rich Liu <richliu@poorman.org> */
312facaf
GKH		 2271static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma,
2272 const struct parport_pc_via_data *via)
1da177e4
LT		 2273{
2274 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
1da177e4
LT		 2275 u32 ite8872set;
2276 u32 ite8872_lpt, ite8872_lpthi;
2277 u8 ite8872_irq, type;
1da177e4
LT		 2278 int irq;
2279 int i;
2280
3aeda9bc
AC		 2281 DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n");
2282
2283 /* make sure which one chip */
2284 for (i = 0; i < 5; i++) {
0f6db217 2285 if (request_region(inta_addr[i], 32, "it887x")) {
1da177e4 2286 int test;
3aeda9bc 2287 pci_write_config_dword(pdev, 0x60,
e7c310c3 2288 0xe5000000 | inta_addr[i]);
3aeda9bc 2289 pci_write_config_dword(pdev, 0x78,
1da177e4 2290 0x00000000 | inta_addr[i]);
3aeda9bc
AC		 2291 test = inb(inta_addr[i]);
2292 if (test != 0xff)
2293 break;
0f6db217 2294 release_region(inta_addr[i], 32);
1da177e4
LT		 2295 }
2296 }
3aeda9bc
AC		 2297 if (i >= 5) {
2298 printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
1da177e4
LT		 2299 return 0;
2300 }
2301
3aeda9bc 2302 type = inb(inta_addr[i] + 0x18);
1da177e4
LT		 2303 type &= 0x0f;
2304
2305 switch (type) {
2306 case 0x2:
3aeda9bc 2307 printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n");
1da177e4
LT		 2308 ite8872set = 0x64200000;
2309 break;
2310 case 0xa:
3aeda9bc 2311 printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n");
1da177e4
LT		 2312 ite8872set = 0x64200000;
2313 break;
2314 case 0xe:
3aeda9bc 2315 printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
1da177e4
LT		 2316 ite8872set = 0x64e00000;
2317 break;
2318 case 0x6:
3aeda9bc 2319 printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n");
9fdbdd06 2320 release_region(inta_addr[i], 32);
1da177e4
LT		 2321 return 0;
2322 case 0x8:
6c8e4c92 2323 printk(KERN_INFO "parport_pc: ITE8874 found (2S)\n");
9fdbdd06 2324 release_region(inta_addr[i], 32);
1da177e4
LT		 2325 return 0;
2326 default:
3aeda9bc
AC		 2327 printk(KERN_INFO "parport_pc: unknown ITE887x\n");
2328 printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' "
1da177e4 2329 "output to Rich.Liu@ite.com.tw\n");
9fdbdd06 2330 release_region(inta_addr[i], 32);
1da177e4
LT		 2331 return 0;
2332 }
2333
3aeda9bc
AC		 2334 pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2335 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
1da177e4 2336 ite8872_lpt &= 0x0000ff00;
3aeda9bc 2337 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
1da177e4 2338 ite8872_lpthi &= 0x0000ff00;
3aeda9bc
AC		 2339 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2340 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2341 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2342 /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2343 /* SET Parallel IRQ */
2344 pci_write_config_dword(pdev, 0x9c,
1da177e4
LT		 2345 ite8872set | (ite8872_irq * 0x11111));
2346
3aeda9bc
AC		 2347 DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2348 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
1da177e4 2349 ite8872_lpt);
3aeda9bc 2350 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
1da177e4
LT		 2351 ite8872_lpthi);
2352
2353 /* Let the user (or defaults) steer us away from interrupts */
2354 irq = ite8872_irq;
2355 if (autoirq != PARPORT_IRQ_AUTO)
2356 irq = PARPORT_IRQ_NONE;
2357
2358 /*
2359 * Release the resource so that parport_pc_probe_port can get it.
2360 */
0f6db217 2361 release_region(inta_addr[i], 32);
3aeda9bc 2362 if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
51dcdfec 2363 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
3aeda9bc 2364 printk(KERN_INFO
1da177e4 2365 "parport_pc: ITE 8872 parallel port: io=0x%X",
3aeda9bc 2366 ite8872_lpt);
1da177e4 2367 if (irq != PARPORT_IRQ_NONE)
3aeda9bc
AC		 2368 printk(", irq=%d", irq);
2369 printk("\n");
1da177e4
LT		 2370 return 1;
2371 }
2372
2373 return 0;
2374}
2375
2376/* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2377 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
312facaf 2378static int parport_init_mode;
1da177e4
LT		 2379
2380/* Data for two known VIA chips */
312facaf 2381static struct parport_pc_via_data via_686a_data = {
1da177e4
LT		 2382 0x51,
2383 0x50,
2384 0x85,
2385 0x02,
2386 0xE2,
2387 0xF0,
2388 0xE6
2389};
312facaf 2390static struct parport_pc_via_data via_8231_data = {
1da177e4
LT		 2391 0x45,
2392 0x44,
2393 0x50,
2394 0x04,
2395 0xF2,
2396 0xFA,
2397 0xF6
2398};
2399
312facaf
GKH		 2400static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma,
2401 const struct parport_pc_via_data *via)
1da177e4
LT		 2402{
2403 u8 tmp, tmp2, siofunc;
2404 u8 ppcontrol = 0;
2405 int dma, irq;
2406 unsigned port1, port2;
2407 unsigned have_epp = 0;
2408
2409 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2410
3aeda9bc 2411 switch (parport_init_mode) {
1da177e4 2412 case 1:
3aeda9bc
AC		 2413 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2414 siofunc = VIA_FUNCTION_PARPORT_SPP;
2415 break;
1da177e4 2416 case 2:
3aeda9bc
AC		 2417 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2418 siofunc = VIA_FUNCTION_PARPORT_SPP;
2419 ppcontrol = VIA_PARPORT_BIDIR;
2420 break;
1da177e4 2421 case 3:
3aeda9bc
AC		 2422 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2423 siofunc = VIA_FUNCTION_PARPORT_EPP;
2424 ppcontrol = VIA_PARPORT_BIDIR;
2425 have_epp = 1;
2426 break;
1da177e4 2427 case 4:
3aeda9bc
AC		 2428 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2429 siofunc = VIA_FUNCTION_PARPORT_ECP;
2430 ppcontrol = VIA_PARPORT_BIDIR;
2431 break;
1da177e4 2432 case 5:
3aeda9bc
AC		 2433 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2434 siofunc = VIA_FUNCTION_PARPORT_ECP;
2435 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2436 have_epp = 1;
2437 break;
2438 default:
2439 printk(KERN_DEBUG
2440 "parport_pc: probing current configuration\n");
2441 siofunc = VIA_FUNCTION_PROBE;
2442 break;
1da177e4
LT		 2443 }
2444 /*
2445 * unlock super i/o configuration
2446 */
2447 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2448 tmp |= via->via_pci_superio_config_data;
2449 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2450
2451 /* Bits 1-0: Parallel Port Mode / Enable */
2452 outb(via->viacfg_function, VIA_CONFIG_INDEX);
3aeda9bc 2453 tmp = inb(VIA_CONFIG_DATA);
1da177e4
LT		 2454 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2455 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
3aeda9bc
AC		 2456 tmp2 = inb(VIA_CONFIG_DATA);
2457 if (siofunc == VIA_FUNCTION_PROBE) {
2458 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2459 ppcontrol = tmp2;
2460 } else {
2461 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2462 tmp |= siofunc;
2463 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2464 outb(tmp, VIA_CONFIG_DATA);
2465 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2466 tmp2 |= ppcontrol;
2467 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2468 outb(tmp2, VIA_CONFIG_DATA);
1da177e4 2469 }
3aeda9bc 2470
1da177e4
LT		 2471 /* Parallel Port I/O Base Address, bits 9-2 */
2472 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2473 port1 = inb(VIA_CONFIG_DATA) << 2;
3aeda9bc
AC		 2474
2475 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2476 port1);
2477 if (port1 == 0x3BC && have_epp) {
2478 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2479 outb((0x378 >> 2), VIA_CONFIG_DATA);
2480 printk(KERN_DEBUG
2481 "parport_pc: Parallel port base changed to 0x378\n");
2482 port1 = 0x378;
1da177e4
LT		 2483 }
2484
2485 /*
2486 * lock super i/o configuration
2487 */
2488 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2489 tmp &= ~via->via_pci_superio_config_data;
2490 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2491
2492 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2493 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2494 return 0;
2495 }
3aeda9bc 2496
1da177e4
LT		 2497 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2498 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2499 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2500
3aeda9bc
AC		 2501 if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2502 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2503 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2504 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2505 } else
2506 /* if ECP not enabled, DMA is not enabled, assumed
2507 bogus 'dma' value */
2508 dma = PARPORT_DMA_NONE;
1da177e4
LT		 2509
2510 /* Let the user (or defaults) steer us away from interrupts and DMA */
2511 if (autoirq == PARPORT_IRQ_NONE) {
3aeda9bc
AC		 2512 irq = PARPORT_IRQ_NONE;
2513 dma = PARPORT_DMA_NONE;
1da177e4
LT		 2514 }
2515 if (autodma == PARPORT_DMA_NONE)
3aeda9bc 2516 dma = PARPORT_DMA_NONE;
1da177e4
LT		 2517
2518 switch (port1) {
3aeda9bc
AC		 2519 case 0x3bc:
2520 port2 = 0x7bc; break;
2521 case 0x378:
2522 port2 = 0x778; break;
2523 case 0x278:
2524 port2 = 0x678; break;
1da177e4 2525 default:
3aeda9bc
AC		 2526 printk(KERN_INFO
2527 "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2528 port1);
1da177e4
LT		 2529 return 0;
2530 }
2531
2532 /* filter bogus IRQs */
2533 switch (irq) {
2534 case 0:
2535 case 2:
2536 case 8:
2537 case 13:
2538 irq = PARPORT_IRQ_NONE;
2539 break;
2540
2541 default: /* do nothing */
2542 break;
2543 }
2544
2545 /* finally, do the probe with values obtained */
3aeda9bc
AC		 2546 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2547 printk(KERN_INFO
1da177e4
LT		 2548 "parport_pc: VIA parallel port: io=0x%X", port1);
2549 if (irq != PARPORT_IRQ_NONE)
3aeda9bc 2550 printk(", irq=%d", irq);
1da177e4 2551 if (dma != PARPORT_DMA_NONE)
3aeda9bc
AC		 2552 printk(", dma=%d", dma);
2553 printk("\n");
1da177e4
LT		 2554 return 1;
2555 }
3aeda9bc 2556
1da177e4
LT		 2557 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2558 port1, irq, dma);
2559 return 0;
2560}
2561
2562
2563enum parport_pc_sio_types {
3aeda9bc
AC		 2564 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2565 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
1da177e4
LT		 2566 sio_ite_8872,
2567 last_sio
2568};
2569
2570/* each element directly indexed from enum list, above */
2571static struct parport_pc_superio {
a6767b7c
MK		 2572 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2573 const struct parport_pc_via_data *via);
2574 const struct parport_pc_via_data *via;
312facaf 2575} parport_pc_superio_info[] = {
1da177e4
LT		 2576 { sio_via_probe, &via_686a_data, },
2577 { sio_via_probe, &via_8231_data, },
2578 { sio_ite_8872_probe, NULL, },
2579};
2580
2581enum parport_pc_pci_cards {
2582 siig_1p_10x = last_sio,
2583 siig_2p_10x,
2584 siig_1p_20x,
2585 siig_2p_20x,
2586 lava_parallel,
2587 lava_parallel_dual_a,
2588 lava_parallel_dual_b,
2589 boca_ioppar,
2590 plx_9050,
1da177e4
LT		 2591 timedia_4006a,
2592 timedia_4014,
2593 timedia_4008a,
2594 timedia_4018,
2595 timedia_9018a,
2596 syba_2p_epp,
2597 syba_1p_ecp,
2598 titan_010l,
1da177e4
LT		 2599 avlab_1p,
2600 avlab_2p,
c140e110 2601 oxsemi_952,
1da177e4
LT		 2602 oxsemi_954,
2603 oxsemi_840,
7106b4e3 2604 oxsemi_pcie_pport,
1da177e4
LT		 2605 aks_0100,
2606 mobility_pp,
2607 netmos_9705,
2608 netmos_9715,
2609 netmos_9755,
2610 netmos_9805,
2611 netmos_9815,
c4285b47 2612 netmos_9901,
ac6ec5b1 2613 netmos_9865,
dc999159 2614 quatech_sppxp100,
1da177e4
LT		 2615};
2616
2617
3aeda9bc 2618/* each element directly indexed from enum list, above
1da177e4
LT		 2619 * (but offset by last_sio) */
2620static struct parport_pc_pci {
2621 int numports;
2622 struct { /* BAR (base address registers) numbers in the config
3aeda9bc 2623 space header */
1da177e4 2624 int lo;
3aeda9bc
AC		 2625 int hi;
2626 /* -1 if not there, >6 for offset-method (max BAR is 6) */
1da177e4
LT		 2627 } addr[4];
2628
2629 /* If set, this is called immediately after pci_enable_device.
2630 * If it returns non-zero, no probing will take place and the
2631 * ports will not be used. */
2632 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2633
2634 /* If set, this is called after probing for ports. If 'failed'
2635 * is non-zero we couldn't use any of the ports. */
2636 void (*postinit_hook) (struct pci_dev *pdev, int failed);
96766a3c 2637} cards[] = {
1da177e4
LT		 2638 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2639 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2640 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2641 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2642 /* lava_parallel */ { 1, { { 0, -1 }, } },
2643 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2644 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2645 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2646 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
1da177e4
LT		 2647 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2648 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2649 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2650 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2651 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2652 /* SYBA uses fixed offsets in
3aeda9bc 2653 a 1K io window */
1da177e4
LT		 2654 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2655 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2656 /* titan_010l */ { 1, { { 3, -1 }, } },
1da177e4
LT		 2657 /* avlab_1p */ { 1, { { 0, 1}, } },
2658 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2659 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2660 * and 840 locks up if you write 1 to bit 2! */
c140e110 2661 /* oxsemi_952 */ { 1, { { 0, 1 }, } },
1da177e4 2662 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
adbd321a 2663 /* oxsemi_840 */ { 1, { { 0, 1 }, } },
7106b4e3 2664 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
1da177e4
LT		 2665 /* aks_0100 */ { 1, { { 0, -1 }, } },
2666 /* mobility_pp */ { 1, { { 0, 1 }, } },
3aeda9bc
AC		 2667
2668 /* The netmos entries below are untested */
2669 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2670 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2671 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
d35b93d0
SAS		 2672 /* netmos_9805 */ { 1, { { 0, 1 }, } },
2673 /* netmos_9815 */ { 2, { { 0, 1 }, { 2, 3 }, } },
c4285b47 2674 /* netmos_9901 */ { 1, { { 0, -1 }, } },
ac6ec5b1 2675 /* netmos_9865 */ { 1, { { 0, -1 }, } },
dc999159 2676 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
1da177e4
LT		 2677};
2678
a6767b7c 2679static const struct pci_device_id parport_pc_pci_tbl[] = {
1da177e4
LT		 2680 /* Super-IO onboard chips */
2681 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2682 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2683 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2684 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2685
2686 /* PCI cards */
2687 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2688 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2689 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2690 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2691 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2693 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2695 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2696 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2697 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2699 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2701 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2702 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2703 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3aeda9bc 2704 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
1da177e4 2705 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
1da177e4
LT		 2706 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2707 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2708 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2709 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2710 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
1da177e4
LT		 2711 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2712 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2713 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2714 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2715 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2716 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
1da177e4 2717 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
3aeda9bc
AC		 2718 /* AFAVLAB_TK9902 */
2719 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
1da177e4 2720 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
c140e110
RU		 2721 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
2722 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
1da177e4
LT		 2723 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2725 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
7106b4e3
LH		 2727 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
2728 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2729 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
2730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2731 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
2732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2733 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
2734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2735 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
2736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2737 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
2738 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2739 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
2740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2741 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
2742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
1da177e4
LT		 2743 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2744 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
7106b4e3 2745 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
1da177e4
LT		 2746 /* NetMos communication controllers */
2747 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2749 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2750 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2751 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2752 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2753 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2754 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2755 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2756 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
c4285b47
MB		 2757 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
2758 0xA000, 0x2000, 0, 0, netmos_9901 },
ac6ec5b1
IS		 2759 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2760 0xA000, 0x1000, 0, 0, netmos_9865 },
2761 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2762 0xA000, 0x2000, 0, 0, netmos_9865 },
dc999159
LM		 2763 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2764 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
2765 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
1da177e4
LT		 2766 { 0, } /* terminate list */
2767};
3aeda9bc 2768MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
1da177e4
LT		 2769
2770struct pci_parport_data {
2771 int num;
2772 struct parport *ports[2];
2773};
2774
3aeda9bc 2775static int parport_pc_pci_probe(struct pci_dev *dev,
1da177e4
LT		 2776 const struct pci_device_id *id)
2777{
2778 int err, count, n, i = id->driver_data;
2779 struct pci_parport_data *data;
2780
2781 if (i < last_sio)
2782 /* This is an onboard Super-IO and has already been probed */
2783 return 0;
2784
2785 /* This is a PCI card */
2786 i -= last_sio;
2787 count = 0;
3aeda9bc
AC		 2788 err = pci_enable_device(dev);
2789 if (err)
1da177e4
LT		 2790 return err;
2791
2792 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2793 if (!data)
2794 return -ENOMEM;
2795
2796 if (cards[i].preinit_hook &&
3aeda9bc 2797 cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
1da177e4
LT		 2798 kfree(data);
2799 return -ENODEV;
2800 }
2801
2802 for (n = 0; n < cards[i].numports; n++) {
2803 int lo = cards[i].addr[n].lo;
2804 int hi = cards[i].addr[n].hi;
51dcdfec 2805 int irq;
1da177e4 2806 unsigned long io_lo, io_hi;
3aeda9bc 2807 io_lo = pci_resource_start(dev, lo);
1da177e4
LT		 2808 io_hi = 0;
2809 if ((hi >= 0) && (hi <= 6))
3aeda9bc 2810 io_hi = pci_resource_start(dev, hi);
1da177e4
LT		 2811 else if (hi > 6)
2812 io_lo += hi; /* Reinterpret the meaning of
3aeda9bc
AC		 2813 "hi" as an offset (see SYBA
2814 def.) */
1da177e4 2815 /* TODO: test if sharing interrupts works */
51dcdfec
AC		 2816 irq = dev->irq;
2817 if (irq == IRQ_NONE) {
3aeda9bc 2818 printk(KERN_DEBUG
51dcdfec
AC		 2819 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
2820 parport_pc_pci_tbl[i + last_sio].vendor,
2821 parport_pc_pci_tbl[i + last_sio].device,
2822 io_lo, io_hi);
2823 irq = PARPORT_IRQ_NONE;
2824 } else {
3aeda9bc 2825 printk(KERN_DEBUG
51dcdfec
AC		 2826 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
2827 parport_pc_pci_tbl[i + last_sio].vendor,
2828 parport_pc_pci_tbl[i + last_sio].device,
2829 io_lo, io_hi, irq);
2830 }
1da177e4 2831 data->ports[count] =
51dcdfec
AC		 2832 parport_pc_probe_port(io_lo, io_hi, irq,
2833 PARPORT_DMA_NONE, &dev->dev,
2834 IRQF_SHARED);
1da177e4
LT		 2835 if (data->ports[count])
2836 count++;
2837 }
2838
2839 data->num = count;
2840
2841 if (cards[i].postinit_hook)
3aeda9bc 2842 cards[i].postinit_hook(dev, count == 0);
1da177e4
LT		 2843
2844 if (count) {
2845 pci_set_drvdata(dev, data);
2846 return 0;
2847 }
2848
2849 kfree(data);
2850
2851 return -ENODEV;
2852}
2853
312facaf 2854static void parport_pc_pci_remove(struct pci_dev *dev)
1da177e4
LT		 2855{
2856 struct pci_parport_data *data = pci_get_drvdata(dev);
2857 int i;
2858
2859 pci_set_drvdata(dev, NULL);
2860
2861 if (data) {
2862 for (i = data->num - 1; i >= 0; i--)
2863 parport_pc_unregister_port(data->ports[i]);
2864
2865 kfree(data);
2866 }
2867}
2868
2869static struct pci_driver parport_pc_pci_driver = {
2870 .name = "parport_pc",
2871 .id_table = parport_pc_pci_tbl,
2872 .probe = parport_pc_pci_probe,
312facaf 2873 .remove = parport_pc_pci_remove,
1da177e4
LT		 2874};
2875
3aeda9bc 2876static int __init parport_pc_init_superio(int autoirq, int autodma)
1da177e4
LT		 2877{
2878 const struct pci_device_id *id;
2879 struct pci_dev *pdev = NULL;
2880 int ret = 0;
2881
c9d8073f 2882 for_each_pci_dev(pdev) {
75865858 2883 id = pci_match_id(parport_pc_pci_tbl, pdev);
1da177e4
LT		 2884 if (id == NULL || id->driver_data >= last_sio)
2885 continue;
2886
3aeda9bc
AC		 2887 if (parport_pc_superio_info[id->driver_data].probe(
2888 pdev, autoirq, autodma,
2889 parport_pc_superio_info[id->driver_data].via)) {
1da177e4
LT		 2890 ret++;
2891 }
2892 }
2893
2894 return ret; /* number of devices found */
2895}
2896#else
2897static struct pci_driver parport_pc_pci_driver;
3aeda9bc
AC		 2898static int __init parport_pc_init_superio(int autoirq, int autodma)
2899{
2900 return 0;
2901}
1da177e4
LT		 2902#endif /* CONFIG_PCI */
2903
f2b9a396 2904#ifdef CONFIG_PNP
1da177e4
LT		 2905
2906static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2907 /* Standard LPT Printer Port */
2908 {.id = "PNP0400", .driver_data = 0},
2909 /* ECP Printer Port */
2910 {.id = "PNP0401", .driver_data = 0},
2911 { }
2912};
2913
3aeda9bc 2914MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
1da177e4 2915
3aeda9bc
AC		 2916static int parport_pc_pnp_probe(struct pnp_dev *dev,
2917 const struct pnp_device_id *id)
1da177e4
LT		 2918{
2919 struct parport *pdata;
2920 unsigned long io_lo, io_hi;
2921 int dma, irq;
2922
3aeda9bc
AC		 2923 if (pnp_port_valid(dev, 0) &&
2924 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
2925 io_lo = pnp_port_start(dev, 0);
1da177e4
LT		 2926 } else
2927 return -EINVAL;
2928
3aeda9bc
AC		 2929 if (pnp_port_valid(dev, 1) &&
2930 !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
2931 io_hi = pnp_port_start(dev, 1);
1da177e4
LT		 2932 } else
2933 io_hi = 0;
2934
3aeda9bc
AC		 2935 if (pnp_irq_valid(dev, 0) &&
2936 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
2937 irq = pnp_irq(dev, 0);
1da177e4
LT		 2938 } else
2939 irq = PARPORT_IRQ_NONE;
2940
3aeda9bc
AC		 2941 if (pnp_dma_valid(dev, 0) &&
2942 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
2943 dma = pnp_dma(dev, 0);
1da177e4
LT		 2944 } else
2945 dma = PARPORT_DMA_NONE;
2946
c15a3837 2947 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
3aeda9bc
AC		 2948 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
2949 if (pdata == NULL)
1da177e4
LT		 2950 return -ENODEV;
2951
3aeda9bc 2952 pnp_set_drvdata(dev, pdata);
1da177e4
LT		 2953 return 0;
2954}
2955
2956static void parport_pc_pnp_remove(struct pnp_dev *dev)
2957{
2958 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
2959 if (!pdata)
2960 return;
2961
2962 parport_pc_unregister_port(pdata);
2963}
2964
2965/* we only need the pnp layer to activate the device, at least for now */
2966static struct pnp_driver parport_pc_pnp_driver = {
2967 .name = "parport_pc",
2968 .id_table = parport_pc_pnp_tbl,
2969 .probe = parport_pc_pnp_probe,
2970 .remove = parport_pc_pnp_remove,
2971};
2972
f2b9a396
BH		 2973#else
2974static struct pnp_driver parport_pc_pnp_driver;
2975#endif /* CONFIG_PNP */
1da177e4 2976
312facaf 2977static int parport_pc_platform_probe(struct platform_device *pdev)
a7d801af
JD		 2978{
2979 /* Always succeed, the actual probing is done in
2980 * parport_pc_probe_port(). */
2981 return 0;
2982}
2983
2984static struct platform_driver parport_pc_platform_driver = {
2985 .driver = {
2986 .owner = THIS_MODULE,
2987 .name = "parport_pc",
2988 },
2989 .probe = parport_pc_platform_probe,
2990};
2991
1da177e4 2992/* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
312facaf 2993static int __attribute__((unused))
3aeda9bc 2994parport_pc_find_isa_ports(int autoirq, int autodma)
1da177e4
LT		 2995{
2996 int count = 0;
2997
51dcdfec 2998 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
1da177e4 2999 count++;
51dcdfec 3000 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
1da177e4 3001 count++;
51dcdfec 3002 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
1da177e4
LT		 3003 count++;
3004
3005 return count;
3006}
3007
3008/* This function is called by parport_pc_init if the user didn't
3009 * specify any ports to probe. Its job is to find some ports. Order
3010 * is important here -- we want ISA ports to be registered first,
3011 * followed by PCI cards (for least surprise), but before that we want
3012 * to do chipset-specific tests for some onboard ports that we know
3013 * about.
3014 *
3015 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3016 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3017 */
3aeda9bc 3018static void __init parport_pc_find_ports(int autoirq, int autodma)
1da177e4 3019{
7597fee3 3020 int count = 0, err;
1da177e4
LT		 3021
3022#ifdef CONFIG_PARPORT_PC_SUPERIO
f63fd7e2
PC		 3023 detect_and_report_it87();
3024 detect_and_report_winbond();
3025 detect_and_report_smsc();
1da177e4
LT		 3026#endif
3027
3028 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
f63fd7e2 3029 count += parport_pc_init_superio(autoirq, autodma);
1da177e4
LT		 3030
3031 /* PnP ports, skip detection if SuperIO already found them */
3032 if (!count) {
f63fd7e2 3033 err = pnp_register_driver(&parport_pc_pnp_driver);
7597fee3 3034 if (!err)
1da177e4 3035 pnp_registered_parport = 1;
1da177e4
LT		 3036 }
3037
3038 /* ISA ports and whatever (see asm/parport.h). */
f63fd7e2 3039 parport_pc_find_nonpci_ports(autoirq, autodma);
1da177e4 3040
f63fd7e2 3041 err = pci_register_driver(&parport_pc_pci_driver);
7597fee3
BH		 3042 if (!err)
3043 pci_registered_parport = 1;
1da177e4
LT		 3044}
3045
3046/*
3047 * Piles of crap below pretend to be a parser for module and kernel
3048 * parameters. Say "thank you" to whoever had come up with that
3049 * syntax and keep in mind that code below is a cleaned up version.
3050 */
3051
3aeda9bc
AC		 3052static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3053 [0 ... PARPORT_PC_MAX_PORTS] = 0
3054};
3055static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3056 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3057};
3058static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3059 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3060};
3061static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3062 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3063};
1da177e4
LT		 3064
3065static int __init parport_parse_param(const char *s, int *val,
3066 int automatic, int none, int nofifo)
3067{
3068 if (!s)
3069 return 0;
3070 if (!strncmp(s, "auto", 4))
3071 *val = automatic;
3072 else if (!strncmp(s, "none", 4))
3073 *val = none;
1f2c19f8 3074 else if (nofifo && !strncmp(s, "nofifo", 6))
1da177e4
LT		 3075 *val = nofifo;
3076 else {
3077 char *ep;
3078 unsigned long r = simple_strtoul(s, &ep, 0);
3079 if (ep != s)
3080 *val = r;
3081 else {
3082 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3083 return -1;
3084 }
3085 }
3086 return 0;
3087}
3088
3089static int __init parport_parse_irq(const char *irqstr, int *val)
3090{
3091 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3092 PARPORT_IRQ_NONE, 0);
3093}
3094
3095static int __init parport_parse_dma(const char *dmastr, int *val)
3096{
3097 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3098 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3099}
3100
3101#ifdef CONFIG_PCI
3102static int __init parport_init_mode_setup(char *str)
3103{
3aeda9bc
AC		 3104 printk(KERN_DEBUG
3105 "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3106
3107 if (!strcmp(str, "spp"))
3108 parport_init_mode = 1;
3109 if (!strcmp(str, "ps2"))
3110 parport_init_mode = 2;
3111 if (!strcmp(str, "epp"))
3112 parport_init_mode = 3;
3113 if (!strcmp(str, "ecp"))
3114 parport_init_mode = 4;
3115 if (!strcmp(str, "ecpepp"))
3116 parport_init_mode = 5;
1da177e4
LT		 3117 return 1;
3118}
3119#endif
3120
3121#ifdef MODULE
45dac90f
AM		 3122static char *irq[PARPORT_PC_MAX_PORTS];
3123static char *dma[PARPORT_PC_MAX_PORTS];
1da177e4
LT		 3124
3125MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3126module_param_array(io, int, NULL, 0);
3127MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3128module_param_array(io_hi, int, NULL, 0);
3129MODULE_PARM_DESC(irq, "IRQ line");
3130module_param_array(irq, charp, NULL, 0);
3131MODULE_PARM_DESC(dma, "DMA channel");
3132module_param_array(dma, charp, NULL, 0);
3133#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3134 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3135MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3136module_param(verbose_probing, int, 0644);
3137#endif
3138#ifdef CONFIG_PCI
3139static char *init_mode;
3aeda9bc
AC		 3140MODULE_PARM_DESC(init_mode,
3141 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
1da177e4
LT		 3142module_param(init_mode, charp, 0);
3143#endif
3144
3145static int __init parse_parport_params(void)
3146{
3147 unsigned int i;
3148 int val;
3149
3150#ifdef CONFIG_PCI
3151 if (init_mode)
3152 parport_init_mode_setup(init_mode);
3153#endif
3154
3155 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3156 if (parport_parse_irq(irq[i], &val))
3157 return 1;
3158 irqval[i] = val;
3159 if (parport_parse_dma(dma[i], &val))
3160 return 1;
3161 dmaval[i] = val;
3162 }
3163 if (!io[0]) {
3164 /* The user can make us use any IRQs or DMAs we find. */
3165 if (irq[0] && !parport_parse_irq(irq[0], &val))
3166 switch (val) {
3167 case PARPORT_IRQ_NONE:
3168 case PARPORT_IRQ_AUTO:
3169 irqval[0] = val;
3170 break;
3171 default:
3aeda9bc 3172 printk(KERN_WARNING
1da177e4
LT		 3173 "parport_pc: irq specified "
3174 "without base address. Use 'io=' "
3175 "to specify one\n");
3176 }
3177
3178 if (dma[0] && !parport_parse_dma(dma[0], &val))
3179 switch (val) {
3180 case PARPORT_DMA_NONE:
3181 case PARPORT_DMA_AUTO:
3182 dmaval[0] = val;
3183 break;
3184 default:
3aeda9bc 3185 printk(KERN_WARNING
1da177e4
LT		 3186 "parport_pc: dma specified "
3187 "without base address. Use 'io=' "
3188 "to specify one\n");
3189 }
3190 }
3191 return 0;
3192}
3193
3194#else
3195
3aeda9bc 3196static int parport_setup_ptr __initdata;
1da177e4
LT		 3197
3198/*
3199 * Acceptable parameters:
3200 *
3201 * parport=0
3202 * parport=auto
3203 * parport=0xBASE[,IRQ[,DMA]]
3204 *
3205 * IRQ/DMA may be numeric or 'auto' or 'none'
3206 */
3aeda9bc 3207static int __init parport_setup(char *str)
1da177e4
LT		 3208{
3209 char *endptr;
3210 char *sep;
3211 int val;
3212
3213 if (!str || !*str || (*str == '0' && !*(str+1))) {
3214 /* Disable parport if "parport=0" in cmdline */
3215 io[0] = PARPORT_DISABLE;
3216 return 1;
3217 }
3218
3aeda9bc 3219 if (!strncmp(str, "auto", 4)) {
1da177e4
LT		 3220 irqval[0] = PARPORT_IRQ_AUTO;
3221 dmaval[0] = PARPORT_DMA_AUTO;
3222 return 1;
3223 }
3224
3aeda9bc 3225 val = simple_strtoul(str, &endptr, 0);
1da177e4 3226 if (endptr == str) {
3aeda9bc 3227 printk(KERN_WARNING "parport=%s not understood\n", str);
1da177e4
LT		 3228 return 1;
3229 }
3230
3231 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3232 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3233 return 1;
3234 }
3235
3236 io[parport_setup_ptr] = val;
3237 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3238 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3239
3240 sep = strchr(str, ',');
3241 if (sep++) {
3242 if (parport_parse_irq(sep, &val))
3243 return 1;
3244 irqval[parport_setup_ptr] = val;
3245 sep = strchr(sep, ',');
3246 if (sep++) {
3247 if (parport_parse_dma(sep, &val))
3248 return 1;
3249 dmaval[parport_setup_ptr] = val;
3250 }
3251 }
3252 parport_setup_ptr++;
3253 return 1;
3254}
3255
3256static int __init parse_parport_params(void)
3257{
3258 return io[0] == PARPORT_DISABLE;
3259}
3260
3aeda9bc 3261__setup("parport=", parport_setup);
1da177e4
LT		 3262
3263/*
3264 * Acceptable parameters:
3265 *
3266 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3267 */
3268#ifdef CONFIG_PCI
3aeda9bc 3269__setup("parport_init_mode=", parport_init_mode_setup);
1da177e4
LT		 3270#endif
3271#endif
3272
3273/* "Parser" ends here */
3274
3275static int __init parport_pc_init(void)
3276{
a7d801af
JD		 3277 int err;
3278
1da177e4
LT		 3279 if (parse_parport_params())
3280 return -EINVAL;
3281
a7d801af
JD		 3282 err = platform_driver_register(&parport_pc_platform_driver);
3283 if (err)
3284 return err;
3285
1da177e4
LT		 3286 if (io[0]) {
3287 int i;
3288 /* Only probe the ports we were given. */
3289 user_specified = 1;
3290 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3291 if (!io[i])
3292 break;
3aeda9bc
AC		 3293 if (io_hi[i] == PARPORT_IOHI_AUTO)
3294 io_hi[i] = 0x400 + io[i];
7597fee3 3295 parport_pc_probe_port(io[i], io_hi[i],
3aeda9bc 3296 irqval[i], dmaval[i], NULL, 0);
1da177e4
LT		 3297 }
3298 } else
3aeda9bc 3299 parport_pc_find_ports(irqval[0], dmaval[0]);
1da177e4
LT		 3300
3301 return 0;
3302}
3303
3304static void __exit parport_pc_exit(void)
3305{
3306 if (pci_registered_parport)
3aeda9bc 3307 pci_unregister_driver(&parport_pc_pci_driver);
1da177e4 3308 if (pnp_registered_parport)
3aeda9bc 3309 pnp_unregister_driver(&parport_pc_pnp_driver);
a7d801af 3310 platform_driver_unregister(&parport_pc_platform_driver);
1da177e4 3311
1da177e4
LT		 3312 while (!list_empty(&ports_list)) {
3313 struct parport_pc_private *priv;
3314 struct parport *port;
3315 priv = list_entry(ports_list.next,
3316 struct parport_pc_private, list);
3317 port = priv->port;
a7d801af
JD		 3318 if (port->dev && port->dev->bus == &platform_bus_type)
3319 platform_device_unregister(
3320 to_platform_device(port->dev));
1da177e4 3321 parport_pc_unregister_port(port);
1da177e4 3322 }
1da177e4
LT		 3323}
3324
3325MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3326MODULE_DESCRIPTION("PC-style parallel port driver");
3327MODULE_LICENSE("GPL");
3328module_init(parport_pc_init)
3329module_exit(parport_pc_exit)
kernel source for telekom puls (alcatel/mediatek)