[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / b43 / phy_common.c

/*

  Broadcom B43 wireless driver
  Common PHY routines

  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
  Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
  Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
  Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>

  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; see the file COPYING.  If not, write to
  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  Boston, MA 02110-1301, USA.

*/

#include "phy_common.h"
#include "phy_g.h"
#include "phy_a.h"
#include "phy_n.h"
#include "phy_lp.h"
#include "b43.h"
#include "main.h"


int b43_phy_allocate(struct b43_wldev *dev)
{
	struct b43_phy *phy = &(dev->phy);
	int err;

	phy->ops = NULL;

	switch (phy->type) {
	case B43_PHYTYPE_A:
		phy->ops = &b43_phyops_a;
		break;
	case B43_PHYTYPE_G:
		phy->ops = &b43_phyops_g;
		break;
	case B43_PHYTYPE_N:
#ifdef CONFIG_B43_PHY_N
		phy->ops = &b43_phyops_n;
#endif
		break;
	case B43_PHYTYPE_LP:
#ifdef CONFIG_B43_PHY_LP
		phy->ops = &b43_phyops_lp;
#endif
		break;
	}
	if (B43_WARN_ON(!phy->ops))
		return -ENODEV;

	err = phy->ops->allocate(dev);
	if (err)
		phy->ops = NULL;

	return err;
}

void b43_phy_free(struct b43_wldev *dev)
{
	dev->phy.ops->free(dev);
	dev->phy.ops = NULL;
}

int b43_phy_init(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	const struct b43_phy_operations *ops = phy->ops;
	int err;

	phy->channel = ops->get_default_chan(dev);

	ops->software_rfkill(dev, false);
	err = ops->init(dev);
	if (err) {
		b43err(dev->wl, "PHY init failed\n");
		goto err_block_rf;
	}
	/* Make sure to switch hardware and firmware (SHM) to
	 * the default channel. */
	err = b43_switch_channel(dev, ops->get_default_chan(dev));
	if (err) {
		b43err(dev->wl, "PHY init: Channel switch to default failed\n");
		goto err_phy_exit;
	}

	return 0;

err_phy_exit:
	if (ops->exit)
		ops->exit(dev);
err_block_rf:
	ops->software_rfkill(dev, true);

	return err;
}

void b43_phy_exit(struct b43_wldev *dev)
{
	const struct b43_phy_operations *ops = dev->phy.ops;

	ops->software_rfkill(dev, true);
	if (ops->exit)
		ops->exit(dev);
}

bool b43_has_hardware_pctl(struct b43_wldev *dev)
{
	if (!dev->phy.hardware_power_control)
		return 0;
	if (!dev->phy.ops->supports_hwpctl)
		return 0;
	return dev->phy.ops->supports_hwpctl(dev);
}

void b43_radio_lock(struct b43_wldev *dev)
{
	u32 macctl;

#if B43_DEBUG
	B43_WARN_ON(dev->phy.radio_locked);
	dev->phy.radio_locked = 1;
#endif

	macctl = b43_read32(dev, B43_MMIO_MACCTL);
	macctl |= B43_MACCTL_RADIOLOCK;
	b43_write32(dev, B43_MMIO_MACCTL, macctl);
	/* Commit the write and wait for the firmware
	 * to finish any radio register access. */
	b43_read32(dev, B43_MMIO_MACCTL);
	udelay(10);
}

void b43_radio_unlock(struct b43_wldev *dev)
{
	u32 macctl;

#if B43_DEBUG
	B43_WARN_ON(!dev->phy.radio_locked);
	dev->phy.radio_locked = 0;
#endif

	/* Commit any write */
	b43_read16(dev, B43_MMIO_PHY_VER);
	/* unlock */
	macctl = b43_read32(dev, B43_MMIO_MACCTL);
	macctl &= ~B43_MACCTL_RADIOLOCK;
	b43_write32(dev, B43_MMIO_MACCTL, macctl);
}

void b43_phy_lock(struct b43_wldev *dev)
{
#if B43_DEBUG
	B43_WARN_ON(dev->phy.phy_locked);
	dev->phy.phy_locked = 1;
#endif
	B43_WARN_ON(dev->sdev->id.revision < 3);

	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
		b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
}

void b43_phy_unlock(struct b43_wldev *dev)
{
#if B43_DEBUG
	B43_WARN_ON(!dev->phy.phy_locked);
	dev->phy.phy_locked = 0;
#endif
	B43_WARN_ON(dev->sdev->id.revision < 3);

	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
		b43_power_saving_ctl_bits(dev, 0);
}

static inline void assert_mac_suspended(struct b43_wldev *dev)
{
	if (!B43_DEBUG)
		return;
	if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
	    (dev->mac_suspended <= 0)) {
		b43dbg(dev->wl, "PHY/RADIO register access with "
		       "enabled MAC.\n");
		dump_stack();
	}
}

u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
{
	assert_mac_suspended(dev);
	return dev->phy.ops->radio_read(dev, reg);
}

void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	assert_mac_suspended(dev);
	dev->phy.ops->radio_write(dev, reg, value);
}

void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
{
	b43_radio_write16(dev, offset,
			  b43_radio_read16(dev, offset) & mask);
}

void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
{
	b43_radio_write16(dev, offset,
			  b43_radio_read16(dev, offset) | set);
}

void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
{
	b43_radio_write16(dev, offset,
			  (b43_radio_read16(dev, offset) & mask) | set);
}

u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
{
	assert_mac_suspended(dev);
	dev->phy.writes_counter = 0;
	return dev->phy.ops->phy_read(dev, reg);
}

void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	assert_mac_suspended(dev);
	dev->phy.ops->phy_write(dev, reg, value);
	if (++dev->phy.writes_counter == B43_MAX_WRITES_IN_ROW) {
		b43_read16(dev, B43_MMIO_PHY_VER);
		dev->phy.writes_counter = 0;
	}
}

void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
{
	assert_mac_suspended(dev);
	dev->phy.ops->phy_write(dev, destreg,
		dev->phy.ops->phy_read(dev, srcreg));
}

void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
{
	if (dev->phy.ops->phy_maskset) {
		assert_mac_suspended(dev);
		dev->phy.ops->phy_maskset(dev, offset, mask, 0);
	} else {
		b43_phy_write(dev, offset,
			      b43_phy_read(dev, offset) & mask);
	}
}

void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
{
	if (dev->phy.ops->phy_maskset) {
		assert_mac_suspended(dev);
		dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
	} else {
		b43_phy_write(dev, offset,
			      b43_phy_read(dev, offset) | set);
	}
}

void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
{
	if (dev->phy.ops->phy_maskset) {
		assert_mac_suspended(dev);
		dev->phy.ops->phy_maskset(dev, offset, mask, set);
	} else {
		b43_phy_write(dev, offset,
			      (b43_phy_read(dev, offset) & mask) | set);
	}
}

int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
{
	struct b43_phy *phy = &(dev->phy);
	u16 channelcookie, savedcookie;
	int err;

	if (new_channel == B43_DEFAULT_CHANNEL)
		new_channel = phy->ops->get_default_chan(dev);

	/* First we set the channel radio code to prevent the
	 * firmware from sending ghost packets.
	 */
	channelcookie = new_channel;
	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
		channelcookie |= B43_SHM_SH_CHAN_5GHZ;
	/* FIXME: set 40Mhz flag if required */
	if (0)
		channelcookie |= B43_SHM_SH_CHAN_40MHZ;
	savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);

	/* Now try to switch the PHY hardware channel. */
	err = phy->ops->switch_channel(dev, new_channel);
	if (err)
		goto err_restore_cookie;

	dev->phy.channel = new_channel;
	/* Wait for the radio to tune to the channel and stabilize. */
	msleep(8);

	return 0;

err_restore_cookie:
	b43_shm_write16(dev, B43_SHM_SHARED,
			B43_SHM_SH_CHAN, savedcookie);

	return err;
}

void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
{
	struct b43_phy *phy = &dev->phy;

	b43_mac_suspend(dev);
	phy->ops->software_rfkill(dev, blocked);
	phy->radio_on = !blocked;
	b43_mac_enable(dev);
}

/**
 * b43_phy_txpower_adjust_work - TX power workqueue.
 *
 * Workqueue for updating the TX power parameters in hardware.
 */
void b43_phy_txpower_adjust_work(struct work_struct *work)
{
	struct b43_wl *wl = container_of(work, struct b43_wl,
					 txpower_adjust_work);
	struct b43_wldev *dev;

	mutex_lock(&wl->mutex);
	dev = wl->current_dev;

	if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
		dev->phy.ops->adjust_txpower(dev);

	mutex_unlock(&wl->mutex);
}

void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
{
	struct b43_phy *phy = &dev->phy;
	unsigned long now = jiffies;
	enum b43_txpwr_result result;

	if (!(flags & B43_TXPWR_IGNORE_TIME)) {
		/* Check if it's time for a TXpower check. */
		if (time_before(now, phy->next_txpwr_check_time))
			return; /* Not yet */
	}
	/* The next check will be needed in two seconds, or later. */
	phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));

	if ((dev->sdev->bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
	    (dev->sdev->bus->boardinfo.type == SSB_BOARD_BU4306))
		return; /* No software txpower adjustment needed */

	result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
	if (result == B43_TXPWR_RES_DONE)
		return; /* We are done. */
	B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
	B43_WARN_ON(phy->ops->adjust_txpower == NULL);

	/* We must adjust the transmission power in hardware.
	 * Schedule b43_phy_txpower_adjust_work(). */
	ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
}

int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
{
	const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
	unsigned int a, b, c, d;
	unsigned int average;
	u32 tmp;

	tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
	a = tmp & 0xFF;
	b = (tmp >> 8) & 0xFF;
	c = (tmp >> 16) & 0xFF;
	d = (tmp >> 24) & 0xFF;
	if (a == 0 || a == B43_TSSI_MAX ||
	    b == 0 || b == B43_TSSI_MAX ||
	    c == 0 || c == B43_TSSI_MAX ||
	    d == 0 || d == B43_TSSI_MAX)
		return -ENOENT;
	/* The values are OK. Clear them. */
	tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
	      (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
	b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);

	if (is_ofdm) {
		a = (a + 32) & 0x3F;
		b = (b + 32) & 0x3F;
		c = (c + 32) & 0x3F;
		d = (d + 32) & 0x3F;
	}

	/* Get the average of the values with 0.5 added to each value. */
	average = (a + b + c + d + 2) / 4;
	if (is_ofdm) {
		/* Adjust for CCK-boost */
		if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO)
		    & B43_HF_CCKBOOST)
			average = (average >= 13) ? (average - 13) : 0;
	}

	return average;
}

void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
{
	b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
}


bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type)
{
	return (channel_type == NL80211_CHAN_HT40MINUS ||
		channel_type == NL80211_CHAN_HT40PLUS);
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
struct b43_c32 b43_cordic(int theta)
{
	static const u32 arctg[] = {
		2949120, 1740967, 919879, 466945, 234379, 117304,
		  58666,   29335,  14668,   7334,   3667,   1833,
		    917,     458,    229,    115,     57,     29,
	};
	u8 i;
	s32 tmp;
	s8 signx = 1;
	u32 angle = 0;
	struct b43_c32 ret = { .i = 39797, .q = 0, };

	while (theta > (180 << 16))
		theta -= (360 << 16);
	while (theta < -(180 << 16))
		theta += (360 << 16);

	if (theta > (90 << 16)) {
		theta -= (180 << 16);
		signx = -1;
	} else if (theta < -(90 << 16)) {
		theta += (180 << 16);
		signx = -1;
	}

	for (i = 0; i <= 17; i++) {
		if (theta > angle) {
			tmp = ret.i - (ret.q >> i);
			ret.q += ret.i >> i;
			ret.i = tmp;
			angle += arctg[i];
		} else {
			tmp = ret.i + (ret.q >> i);
			ret.q -= ret.i >> i;
			ret.i = tmp;
			angle -= arctg[i];
		}
	}

	ret.i *= signx;
	ret.q *= signx;

	return ret;
}
Commit	Line	Data
ef1a628d MB	1	/*
	2
	3	Broadcom B43 wireless driver
	4	Common PHY routines
	5
	6	Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
	7	Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98	8	Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
ef1a628d MB	9	Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
	10	Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
	11
	12	This program is free software; you can redistribute it and/or modify
	13	it under the terms of the GNU General Public License as published by
	14	the Free Software Foundation; either version 2 of the License, or
	15	(at your option) any later version.
	16
	17	This program is distributed in the hope that it will be useful,
	18	but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	GNU General Public License for more details.
	21
	22	You should have received a copy of the GNU General Public License
	23	along with this program; see the file COPYING. If not, write to
	24	the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
	25	Boston, MA 02110-1301, USA.
	26
	27	*/
	28
	29	#include "phy_common.h"
	30	#include "phy_g.h"
	31	#include "phy_a.h"
3d0da751	32	#include "phy_n.h"
e63e4363	33	#include "phy_lp.h"
ef1a628d MB	34	#include "b43.h"
	35	#include "main.h"
	36
	37
fb11137a	38	int b43_phy_allocate(struct b43_wldev *dev)
ef1a628d MB	39	{
	40	struct b43_phy *phy = &(dev->phy);
	41	int err;
	42
	43	phy->ops = NULL;
	44
	45	switch (phy->type) {
	46	case B43_PHYTYPE_A:
	47	phy->ops = &b43_phyops_a;
	48	break;
	49	case B43_PHYTYPE_G:
	50	phy->ops = &b43_phyops_g;
	51	break;
	52	case B43_PHYTYPE_N:
692d2c0f	53	#ifdef CONFIG_B43_PHY_N
ef1a628d MB	54	phy->ops = &b43_phyops_n;
	55	#endif
	56	break;
	57	case B43_PHYTYPE_LP:
e63e4363 MB	58	#ifdef CONFIG_B43_PHY_LP
	59	phy->ops = &b43_phyops_lp;
	60	#endif
ef1a628d MB	61	break;
	62	}
	63	if (B43_WARN_ON(!phy->ops))
	64	return -ENODEV;
	65
	66	err = phy->ops->allocate(dev);
	67	if (err)
	68	phy->ops = NULL;
	69
	70	return err;
	71	}
	72
fb11137a MB	73	void b43_phy_free(struct b43_wldev *dev)
	74	{
	75	dev->phy.ops->free(dev);
	76	dev->phy.ops = NULL;
	77	}
	78
ef1a628d MB	79	int b43_phy_init(struct b43_wldev *dev)
	80	{
	81	struct b43_phy *phy = &dev->phy;
	82	const struct b43_phy_operations *ops = phy->ops;
	83	int err;
	84
	85	phy->channel = ops->get_default_chan(dev);
	86
19d337df	87	ops->software_rfkill(dev, false);
ef1a628d MB	88	err = ops->init(dev);
	89	if (err) {
	90	b43err(dev->wl, "PHY init failed\n");
	91	goto err_block_rf;
	92	}
	93	/* Make sure to switch hardware and firmware (SHM) to
	94	* the default channel. */
	95	err = b43_switch_channel(dev, ops->get_default_chan(dev));
	96	if (err) {
	97	b43err(dev->wl, "PHY init: Channel switch to default failed\n");
	98	goto err_phy_exit;
	99	}
	100
	101	return 0;
	102
	103	err_phy_exit:
	104	if (ops->exit)
	105	ops->exit(dev);
	106	err_block_rf:
19d337df	107	ops->software_rfkill(dev, true);
ef1a628d MB	108
	109	return err;
	110	}
	111
	112	void b43_phy_exit(struct b43_wldev *dev)
	113	{
	114	const struct b43_phy_operations *ops = dev->phy.ops;
	115
19d337df	116	ops->software_rfkill(dev, true);
ef1a628d MB	117	if (ops->exit)
	118	ops->exit(dev);
	119	}
	120
	121	bool b43_has_hardware_pctl(struct b43_wldev *dev)
	122	{
	123	if (!dev->phy.hardware_power_control)
	124	return 0;
	125	if (!dev->phy.ops->supports_hwpctl)
	126	return 0;
	127	return dev->phy.ops->supports_hwpctl(dev);
	128	}
	129
	130	void b43_radio_lock(struct b43_wldev *dev)
	131	{
	132	u32 macctl;
	133
591f3dc2 MB	134	#if B43_DEBUG
	135	B43_WARN_ON(dev->phy.radio_locked);
	136	dev->phy.radio_locked = 1;
	137	#endif
	138
ef1a628d	139	macctl = b43_read32(dev, B43_MMIO_MACCTL);
ef1a628d MB	140	macctl \|= B43_MACCTL_RADIOLOCK;
ef1a628d MB	141	b43_write32(dev, B43_MMIO_MACCTL, macctl);
591f3dc2 MB	142	/* Commit the write and wait for the firmware
591f3dc2 MB	143	* to finish any radio register access. */
ef1a628d MB	144	b43_read32(dev, B43_MMIO_MACCTL);
	145	udelay(10);
	146	}
	147
	148	void b43_radio_unlock(struct b43_wldev *dev)
	149	{
	150	u32 macctl;
	151
591f3dc2 MB	152	#if B43_DEBUG
	153	B43_WARN_ON(!dev->phy.radio_locked);
	154	dev->phy.radio_locked = 0;
	155	#endif
	156
ef1a628d MB	157	/* Commit any write */
	158	b43_read16(dev, B43_MMIO_PHY_VER);
	159	/* unlock */
	160	macctl = b43_read32(dev, B43_MMIO_MACCTL);
ef1a628d MB	161	macctl &= ~B43_MACCTL_RADIOLOCK;
	162	b43_write32(dev, B43_MMIO_MACCTL, macctl);
	163	}
	164
	165	void b43_phy_lock(struct b43_wldev *dev)
	166	{
	167	#if B43_DEBUG
	168	B43_WARN_ON(dev->phy.phy_locked);
	169	dev->phy.phy_locked = 1;
	170	#endif
dedb1eb9	171	B43_WARN_ON(dev->sdev->id.revision < 3);
ef1a628d	172
05c914fe	173	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
ef1a628d MB	174	b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
	175	}
	176
	177	void b43_phy_unlock(struct b43_wldev *dev)
	178	{
	179	#if B43_DEBUG
	180	B43_WARN_ON(!dev->phy.phy_locked);
	181	dev->phy.phy_locked = 0;
	182	#endif
dedb1eb9	183	B43_WARN_ON(dev->sdev->id.revision < 3);
ef1a628d	184
05c914fe	185	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
ef1a628d MB	186	b43_power_saving_ctl_bits(dev, 0);
	187	}
	188
d10d0e57 MB	189	static inline void assert_mac_suspended(struct b43_wldev *dev)
	190	{
	191	if (!B43_DEBUG)
	192	return;
	193	if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
	194	(dev->mac_suspended <= 0)) {
	195	b43dbg(dev->wl, "PHY/RADIO register access with "
	196	"enabled MAC.\n");
	197	dump_stack();
	198	}
	199	}
	200
ef1a628d MB	201	u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
ef1a628d MB	202	{
d10d0e57	203	assert_mac_suspended(dev);
ef1a628d MB	204	return dev->phy.ops->radio_read(dev, reg);
	205	}
	206
	207	void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
	208	{
d10d0e57	209	assert_mac_suspended(dev);
ef1a628d MB	210	dev->phy.ops->radio_write(dev, reg, value);
	211	}
	212
	213	void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
	214	{
	215	b43_radio_write16(dev, offset,
	216	b43_radio_read16(dev, offset) & mask);
	217	}
	218
	219	void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
	220	{
	221	b43_radio_write16(dev, offset,
	222	b43_radio_read16(dev, offset) \| set);
	223	}
	224
	225	void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
	226	{
	227	b43_radio_write16(dev, offset,
	228	(b43_radio_read16(dev, offset) & mask) \| set);
	229	}
	230
	231	u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
	232	{
d10d0e57	233	assert_mac_suspended(dev);
15518080	234	dev->phy.writes_counter = 0;
ef1a628d MB	235	return dev->phy.ops->phy_read(dev, reg);
	236	}
	237
	238	void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
	239	{
d10d0e57	240	assert_mac_suspended(dev);
ef1a628d	241	dev->phy.ops->phy_write(dev, reg, value);
15518080 RM	242	if (++dev->phy.writes_counter == B43_MAX_WRITES_IN_ROW) {
	243	b43_read16(dev, B43_MMIO_PHY_VER);
	244	dev->phy.writes_counter = 0;
	245	}
ef1a628d MB	246	}
ef1a628d MB	247
738f0f43 GS	248	void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
	249	{
	250	assert_mac_suspended(dev);
	251	dev->phy.ops->phy_write(dev, destreg,
	252	dev->phy.ops->phy_read(dev, srcreg));
	253	}
	254
ef1a628d MB	255	void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
ef1a628d MB	256	{
68ec5329 GS	257	if (dev->phy.ops->phy_maskset) {
	258	assert_mac_suspended(dev);
	259	dev->phy.ops->phy_maskset(dev, offset, mask, 0);
	260	} else {
	261	b43_phy_write(dev, offset,
	262	b43_phy_read(dev, offset) & mask);
	263	}
ef1a628d MB	264	}
	265
	266	void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
	267	{
68ec5329 GS	268	if (dev->phy.ops->phy_maskset) {
	269	assert_mac_suspended(dev);
	270	dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
	271	} else {
	272	b43_phy_write(dev, offset,
	273	b43_phy_read(dev, offset) \| set);
	274	}
ef1a628d MB	275	}
	276
	277	void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
	278	{
68ec5329 GS	279	if (dev->phy.ops->phy_maskset) {
	280	assert_mac_suspended(dev);
	281	dev->phy.ops->phy_maskset(dev, offset, mask, set);
	282	} else {
	283	b43_phy_write(dev, offset,
	284	(b43_phy_read(dev, offset) & mask) \| set);
	285	}
ef1a628d MB	286	}
	287
	288	int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
	289	{
	290	struct b43_phy *phy = &(dev->phy);
	291	u16 channelcookie, savedcookie;
	292	int err;
	293
	294	if (new_channel == B43_DEFAULT_CHANNEL)
	295	new_channel = phy->ops->get_default_chan(dev);
	296
	297	/* First we set the channel radio code to prevent the
	298	* firmware from sending ghost packets.
	299	*/
	300	channelcookie = new_channel;
	301	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
106cb09a RM	302	channelcookie \|= B43_SHM_SH_CHAN_5GHZ;
	303	/* FIXME: set 40Mhz flag if required */
	304	if (0)
	305	channelcookie \|= B43_SHM_SH_CHAN_40MHZ;
ef1a628d MB	306	savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
	307	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
	308
	309	/* Now try to switch the PHY hardware channel. */
	310	err = phy->ops->switch_channel(dev, new_channel);
	311	if (err)
	312	goto err_restore_cookie;
	313
	314	dev->phy.channel = new_channel;
	315	/* Wait for the radio to tune to the channel and stabilize. */
	316	msleep(8);
	317
	318	return 0;
	319
	320	err_restore_cookie:
	321	b43_shm_write16(dev, B43_SHM_SHARED,
	322	B43_SHM_SH_CHAN, savedcookie);
	323
	324	return err;
	325	}
	326
19d337df	327	void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
ef1a628d MB	328	{
	329	struct b43_phy *phy = &dev->phy;
	330
b929ecf7	331	b43_mac_suspend(dev);
19d337df JB	332	phy->ops->software_rfkill(dev, blocked);
19d337df JB	333	phy->radio_on = !blocked;
b929ecf7	334	b43_mac_enable(dev);
ef1a628d	335	}
18c8adeb MB	336
	337	/**
	338	* b43_phy_txpower_adjust_work - TX power workqueue.
	339	*
	340	* Workqueue for updating the TX power parameters in hardware.
	341	*/
	342	void b43_phy_txpower_adjust_work(struct work_struct *work)
	343	{
	344	struct b43_wl *wl = container_of(work, struct b43_wl,
	345	txpower_adjust_work);
	346	struct b43_wldev *dev;
	347
	348	mutex_lock(&wl->mutex);
	349	dev = wl->current_dev;
	350
	351	if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
	352	dev->phy.ops->adjust_txpower(dev);
	353
	354	mutex_unlock(&wl->mutex);
	355	}
	356
18c8adeb MB	357	void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
	358	{
	359	struct b43_phy *phy = &dev->phy;
	360	unsigned long now = jiffies;
	361	enum b43_txpwr_result result;
	362
	363	if (!(flags & B43_TXPWR_IGNORE_TIME)) {
	364	/* Check if it's time for a TXpower check. */
	365	if (time_before(now, phy->next_txpwr_check_time))
	366	return; /* Not yet */
	367	}
	368	/* The next check will be needed in two seconds, or later. */
	369	phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
	370
dedb1eb9 RM	371	if ((dev->sdev->bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
dedb1eb9 RM	372	(dev->sdev->bus->boardinfo.type == SSB_BOARD_BU4306))
18c8adeb MB	373	return; /* No software txpower adjustment needed */
	374
	375	result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
	376	if (result == B43_TXPWR_RES_DONE)
	377	return; /* We are done. */
	378	B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
	379	B43_WARN_ON(phy->ops->adjust_txpower == NULL);
	380
	381	/* We must adjust the transmission power in hardware.
	382	* Schedule b43_phy_txpower_adjust_work(). */
42935eca	383	ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
18c8adeb MB	384	}
	385
	386	int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
	387	{
	388	const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
	389	unsigned int a, b, c, d;
	390	unsigned int average;
	391	u32 tmp;
	392
	393	tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
	394	a = tmp & 0xFF;
	395	b = (tmp >> 8) & 0xFF;
	396	c = (tmp >> 16) & 0xFF;
	397	d = (tmp >> 24) & 0xFF;
	398	if (a == 0 \|\| a == B43_TSSI_MAX \|\|
	399	b == 0 \|\| b == B43_TSSI_MAX \|\|
	400	c == 0 \|\| c == B43_TSSI_MAX \|\|
	401	d == 0 \|\| d == B43_TSSI_MAX)
	402	return -ENOENT;
	403	/* The values are OK. Clear them. */
	404	tmp = B43_TSSI_MAX \| (B43_TSSI_MAX << 8) \|
	405	(B43_TSSI_MAX << 16) \| (B43_TSSI_MAX << 24);
	406	b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
	407
	408	if (is_ofdm) {
	409	a = (a + 32) & 0x3F;
	410	b = (b + 32) & 0x3F;
	411	c = (c + 32) & 0x3F;
	412	d = (d + 32) & 0x3F;
	413	}
	414
	415	/* Get the average of the values with 0.5 added to each value. */
	416	average = (a + b + c + d + 2) / 4;
	417	if (is_ofdm) {
	418	/* Adjust for CCK-boost */
	419	if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO)
	420	& B43_HF_CCKBOOST)
	421	average = (average >= 13) ? (average - 13) : 0;
	422	}
	423
	424	return average;
	425	}
cb24f57f MB	426
	427	void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
	428	{
	429	b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
	430	}
98650454	431
abc1f7cd RM	432
	433	bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type)
	434	{
	435	return (channel_type == NL80211_CHAN_HT40MINUS \|\|
	436	channel_type == NL80211_CHAN_HT40PLUS);
	437	}
	438
6f98e62a	439	/* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
98650454 RM	440	struct b43_c32 b43_cordic(int theta)
98650454 RM	441	{
5b4bc649 JP	442	static const u32 arctg[] = {
	443	2949120, 1740967, 919879, 466945, 234379, 117304,
	444	58666, 29335, 14668, 7334, 3667, 1833,
	445	917, 458, 229, 115, 57, 29,
	446	};
6f98e62a RM	447	u8 i;
	448	s32 tmp;
	449	s8 signx = 1;
	450	u32 angle = 0;
98650454 RM	451	struct b43_c32 ret = { .i = 39797, .q = 0, };
98650454 RM	452
6f98e62a RM	453	while (theta > (180 << 16))
	454	theta -= (360 << 16);
	455	while (theta < -(180 << 16))
	456	theta += (360 << 16);
98650454	457
6f98e62a RM	458	if (theta > (90 << 16)) {
6f98e62a RM	459	theta -= (180 << 16);
98650454	460	signx = -1;
6f98e62a RM	461	} else if (theta < -(90 << 16)) {
6f98e62a RM	462	theta += (180 << 16);
98650454 RM	463	signx = -1;
	464	}
	465
	466	for (i = 0; i <= 17; i++) {
	467	if (theta > angle) {
	468	tmp = ret.i - (ret.q >> i);
	469	ret.q += ret.i >> i;
	470	ret.i = tmp;
	471	angle += arctg[i];
	472	} else {
	473	tmp = ret.i + (ret.q >> i);
	474	ret.q -= ret.i >> i;
	475	ret.i = tmp;
	476	angle -= arctg[i];
	477	}
	478	}
	479
	480	ret.i *= signx;
	481	ret.q *= signx;
	482
	483	return ret;
	484	}