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Fix typo in printed messages
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98 7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
108f4f3c 10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
e4d6b795 11
3dbba8e2
AH		 12 SDIO support
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
e4d6b795
MB		 15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
32
33*/
34
35#include <linux/delay.h>
36#include <linux/init.h>
ac5c24e9 37#include <linux/module.h>
e4d6b795
MB		 38#include <linux/if_arp.h>
39#include <linux/etherdevice.h>
e4d6b795 40#include <linux/firmware.h>
e4d6b795
MB		 41#include <linux/workqueue.h>
42#include <linux/skbuff.h>
96cf49a2 43#include <linux/io.h>
e4d6b795 44#include <linux/dma-mapping.h>
5a0e3ad6 45#include <linux/slab.h>
e4d6b795
MB		 46#include <asm/unaligned.h>
47
48#include "b43.h"
49#include "main.h"
50#include "debugfs.h"
ef1a628d
MB		 51#include "phy_common.h"
52#include "phy_g.h"
3d0da751 53#include "phy_n.h"
e4d6b795 54#include "dma.h"
5100d5ac 55#include "pio.h"
e4d6b795
MB		 56#include "sysfs.h"
57#include "xmit.h"
e4d6b795
MB		 58#include "lo.h"
59#include "pcmcia.h"
3dbba8e2
AH		 60#include "sdio.h"
61#include <linux/mmc/sdio_func.h>
e4d6b795
MB		 62
63MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64MODULE_AUTHOR("Martin Langer");
65MODULE_AUTHOR("Stefano Brivio");
66MODULE_AUTHOR("Michael Buesch");
0136e51e 67MODULE_AUTHOR("Gábor Stefanik");
108f4f3c 68MODULE_AUTHOR("Rafał Miłecki");
e4d6b795
MB		 69MODULE_LICENSE("GPL");
70
6021e08d
TG		 71MODULE_FIRMWARE("b43/ucode11.fw");
72MODULE_FIRMWARE("b43/ucode13.fw");
73MODULE_FIRMWARE("b43/ucode14.fw");
74MODULE_FIRMWARE("b43/ucode15.fw");
f6158394 75MODULE_FIRMWARE("b43/ucode16_mimo.fw");
6021e08d
TG		 76MODULE_FIRMWARE("b43/ucode5.fw");
77MODULE_FIRMWARE("b43/ucode9.fw");
e4d6b795
MB		 78
79static int modparam_bad_frames_preempt;
80module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
83
e4d6b795
MB		 84static char modparam_fwpostfix[16];
85module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87
e4d6b795
MB		 88static int modparam_hwpctl;
89module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91
92static int modparam_nohwcrypt;
93module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95
035d0243 96static int modparam_hwtkip;
97module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99
403a3a13
MB		 100static int modparam_qos = 1;
101module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 102MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103
1855ba78
MB		 104static int modparam_btcoex = 1;
105module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 106MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 107
060210f9
MB		 108int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109module_param_named(verbose, b43_modparam_verbose, int, 0644);
110MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111
df766267 112static int b43_modparam_pio = 0;
9e3bd919
LT		 113module_param_named(pio, b43_modparam_pio, int, 0644);
114MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
e6f5b934 115
3c65ab62
RM		 116#ifdef CONFIG_B43_BCMA
117static const struct bcma_device_id b43_bcma_tbl[] = {
c027ed4c 118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
4f3d09de 119#ifdef CONFIG_B43_BCMA_EXTRA
3c65ab62
RM		 120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
4f3d09de 122#endif
3c65ab62
RM		 123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
124 BCMA_CORETABLE_END
125};
126MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
127#endif
128
aec7ffdf 129#ifdef CONFIG_B43_SSB
e4d6b795
MB		 130static const struct ssb_device_id b43_ssb_tbl[] = {
131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
003d6d27 137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
013978b6 138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 141 SSB_DEVTABLE_END
142};
e4d6b795 143MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
aec7ffdf 144#endif
e4d6b795
MB		 145
146/* Channel and ratetables are shared for all devices.
147 * They can't be const, because ieee80211 puts some precalculated
148 * data in there. This data is the same for all devices, so we don't
149 * get concurrency issues */
150#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 151 { \
152 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
153 .hw_value = (_rateid), \
154 .flags = (_flags), \
e4d6b795 155 }
8318d78a
JB		 156
157/*
158 * NOTE: When changing this, sync with xmit.c's
159 * b43_plcp_get_bitrate_idx_* functions!
160 */
e4d6b795 161static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 162 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
163 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
164 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
165 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
166 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
167 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
168 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
171 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
172 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 174};
175
176#define b43_a_ratetable (__b43_ratetable + 4)
177#define b43_a_ratetable_size 8
178#define b43_b_ratetable (__b43_ratetable + 0)
179#define b43_b_ratetable_size 4
180#define b43_g_ratetable (__b43_ratetable + 0)
181#define b43_g_ratetable_size 12
182
bb1eeff1
MB		 183#define CHAN4G(_channel, _freq, _flags) { \
184 .band = IEEE80211_BAND_2GHZ, \
185 .center_freq = (_freq), \
186 .hw_value = (_channel), \
187 .flags = (_flags), \
188 .max_antenna_gain = 0, \
189 .max_power = 30, \
190}
96c755a3 191static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 192 CHAN4G(1, 2412, 0),
193 CHAN4G(2, 2417, 0),
194 CHAN4G(3, 2422, 0),
195 CHAN4G(4, 2427, 0),
196 CHAN4G(5, 2432, 0),
197 CHAN4G(6, 2437, 0),
198 CHAN4G(7, 2442, 0),
199 CHAN4G(8, 2447, 0),
200 CHAN4G(9, 2452, 0),
201 CHAN4G(10, 2457, 0),
202 CHAN4G(11, 2462, 0),
203 CHAN4G(12, 2467, 0),
204 CHAN4G(13, 2472, 0),
205 CHAN4G(14, 2484, 0),
206};
207#undef CHAN4G
208
209#define CHAN5G(_channel, _flags) { \
210 .band = IEEE80211_BAND_5GHZ, \
211 .center_freq = 5000 + (5 * (_channel)), \
212 .hw_value = (_channel), \
213 .flags = (_flags), \
214 .max_antenna_gain = 0, \
215 .max_power = 30, \
216}
217static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
218 CHAN5G(32, 0), CHAN5G(34, 0),
219 CHAN5G(36, 0), CHAN5G(38, 0),
220 CHAN5G(40, 0), CHAN5G(42, 0),
221 CHAN5G(44, 0), CHAN5G(46, 0),
222 CHAN5G(48, 0), CHAN5G(50, 0),
223 CHAN5G(52, 0), CHAN5G(54, 0),
224 CHAN5G(56, 0), CHAN5G(58, 0),
225 CHAN5G(60, 0), CHAN5G(62, 0),
226 CHAN5G(64, 0), CHAN5G(66, 0),
227 CHAN5G(68, 0), CHAN5G(70, 0),
228 CHAN5G(72, 0), CHAN5G(74, 0),
229 CHAN5G(76, 0), CHAN5G(78, 0),
230 CHAN5G(80, 0), CHAN5G(82, 0),
231 CHAN5G(84, 0), CHAN5G(86, 0),
232 CHAN5G(88, 0), CHAN5G(90, 0),
233 CHAN5G(92, 0), CHAN5G(94, 0),
234 CHAN5G(96, 0), CHAN5G(98, 0),
235 CHAN5G(100, 0), CHAN5G(102, 0),
236 CHAN5G(104, 0), CHAN5G(106, 0),
237 CHAN5G(108, 0), CHAN5G(110, 0),
238 CHAN5G(112, 0), CHAN5G(114, 0),
239 CHAN5G(116, 0), CHAN5G(118, 0),
240 CHAN5G(120, 0), CHAN5G(122, 0),
241 CHAN5G(124, 0), CHAN5G(126, 0),
242 CHAN5G(128, 0), CHAN5G(130, 0),
243 CHAN5G(132, 0), CHAN5G(134, 0),
244 CHAN5G(136, 0), CHAN5G(138, 0),
245 CHAN5G(140, 0), CHAN5G(142, 0),
246 CHAN5G(144, 0), CHAN5G(145, 0),
247 CHAN5G(146, 0), CHAN5G(147, 0),
248 CHAN5G(148, 0), CHAN5G(149, 0),
249 CHAN5G(150, 0), CHAN5G(151, 0),
250 CHAN5G(152, 0), CHAN5G(153, 0),
251 CHAN5G(154, 0), CHAN5G(155, 0),
252 CHAN5G(156, 0), CHAN5G(157, 0),
253 CHAN5G(158, 0), CHAN5G(159, 0),
254 CHAN5G(160, 0), CHAN5G(161, 0),
255 CHAN5G(162, 0), CHAN5G(163, 0),
256 CHAN5G(164, 0), CHAN5G(165, 0),
257 CHAN5G(166, 0), CHAN5G(168, 0),
258 CHAN5G(170, 0), CHAN5G(172, 0),
259 CHAN5G(174, 0), CHAN5G(176, 0),
260 CHAN5G(178, 0), CHAN5G(180, 0),
261 CHAN5G(182, 0), CHAN5G(184, 0),
262 CHAN5G(186, 0), CHAN5G(188, 0),
263 CHAN5G(190, 0), CHAN5G(192, 0),
264 CHAN5G(194, 0), CHAN5G(196, 0),
265 CHAN5G(198, 0), CHAN5G(200, 0),
266 CHAN5G(202, 0), CHAN5G(204, 0),
267 CHAN5G(206, 0), CHAN5G(208, 0),
268 CHAN5G(210, 0), CHAN5G(212, 0),
269 CHAN5G(214, 0), CHAN5G(216, 0),
270 CHAN5G(218, 0), CHAN5G(220, 0),
271 CHAN5G(222, 0), CHAN5G(224, 0),
272 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 273};
274
bb1eeff1
MB		 275static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
276 CHAN5G(34, 0), CHAN5G(36, 0),
277 CHAN5G(38, 0), CHAN5G(40, 0),
278 CHAN5G(42, 0), CHAN5G(44, 0),
279 CHAN5G(46, 0), CHAN5G(48, 0),
280 CHAN5G(52, 0), CHAN5G(56, 0),
281 CHAN5G(60, 0), CHAN5G(64, 0),
282 CHAN5G(100, 0), CHAN5G(104, 0),
283 CHAN5G(108, 0), CHAN5G(112, 0),
284 CHAN5G(116, 0), CHAN5G(120, 0),
285 CHAN5G(124, 0), CHAN5G(128, 0),
286 CHAN5G(132, 0), CHAN5G(136, 0),
287 CHAN5G(140, 0), CHAN5G(149, 0),
288 CHAN5G(153, 0), CHAN5G(157, 0),
289 CHAN5G(161, 0), CHAN5G(165, 0),
290 CHAN5G(184, 0), CHAN5G(188, 0),
291 CHAN5G(192, 0), CHAN5G(196, 0),
292 CHAN5G(200, 0), CHAN5G(204, 0),
293 CHAN5G(208, 0), CHAN5G(212, 0),
294 CHAN5G(216, 0),
295};
296#undef CHAN5G
297
298static struct ieee80211_supported_band b43_band_5GHz_nphy = {
299 .band = IEEE80211_BAND_5GHZ,
300 .channels = b43_5ghz_nphy_chantable,
301 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
302 .bitrates = b43_a_ratetable,
303 .n_bitrates = b43_a_ratetable_size,
e4d6b795 304};
8318d78a 305
bb1eeff1
MB		 306static struct ieee80211_supported_band b43_band_5GHz_aphy = {
307 .band = IEEE80211_BAND_5GHZ,
308 .channels = b43_5ghz_aphy_chantable,
309 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
310 .bitrates = b43_a_ratetable,
311 .n_bitrates = b43_a_ratetable_size,
8318d78a 312};
e4d6b795 313
8318d78a 314static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 315 .band = IEEE80211_BAND_2GHZ,
316 .channels = b43_2ghz_chantable,
317 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
318 .bitrates = b43_g_ratetable,
319 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 320};
321
e4d6b795
MB		 322static void b43_wireless_core_exit(struct b43_wldev *dev);
323static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 324static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795 325static int b43_wireless_core_start(struct b43_wldev *dev);
2a190322
FF		 326static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
327 struct ieee80211_vif *vif,
328 struct ieee80211_bss_conf *conf,
329 u32 changed);
e4d6b795
MB		 330
331static int b43_ratelimit(struct b43_wl *wl)
332{
333 if (!wl || !wl->current_dev)
334 return 1;
335 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
336 return 1;
337 /* We are up and running.
338 * Ratelimit the messages to avoid DoS over the net. */
339 return net_ratelimit();
340}
341
342void b43info(struct b43_wl *wl, const char *fmt, ...)
343{
5b736d42 344 struct va_format vaf;
e4d6b795
MB		 345 va_list args;
346
060210f9
MB		 347 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
348 return;
e4d6b795
MB		 349 if (!b43_ratelimit(wl))
350 return;
5b736d42 351
e4d6b795 352 va_start(args, fmt);
5b736d42
JP		 353
354 vaf.fmt = fmt;
355 vaf.va = &args;
356
357 printk(KERN_INFO "b43-%s: %pV",
358 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
359
e4d6b795
MB		 360 va_end(args);
361}
362
363void b43err(struct b43_wl *wl, const char *fmt, ...)
364{
5b736d42 365 struct va_format vaf;
e4d6b795
MB		 366 va_list args;
367
060210f9
MB		 368 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
369 return;
e4d6b795
MB		 370 if (!b43_ratelimit(wl))
371 return;
5b736d42 372
e4d6b795 373 va_start(args, fmt);
5b736d42
JP		 374
375 vaf.fmt = fmt;
376 vaf.va = &args;
377
378 printk(KERN_ERR "b43-%s ERROR: %pV",
379 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
380
e4d6b795
MB		 381 va_end(args);
382}
383
384void b43warn(struct b43_wl *wl, const char *fmt, ...)
385{
5b736d42 386 struct va_format vaf;
e4d6b795
MB		 387 va_list args;
388
060210f9
MB		 389 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
390 return;
e4d6b795
MB		 391 if (!b43_ratelimit(wl))
392 return;
5b736d42 393
e4d6b795 394 va_start(args, fmt);
5b736d42
JP		 395
396 vaf.fmt = fmt;
397 vaf.va = &args;
398
399 printk(KERN_WARNING "b43-%s warning: %pV",
400 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
401
e4d6b795
MB		 402 va_end(args);
403}
404
e4d6b795
MB		 405void b43dbg(struct b43_wl *wl, const char *fmt, ...)
406{
5b736d42 407 struct va_format vaf;
e4d6b795
MB		 408 va_list args;
409
060210f9
MB		 410 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
411 return;
5b736d42 412
e4d6b795 413 va_start(args, fmt);
5b736d42
JP		 414
415 vaf.fmt = fmt;
416 vaf.va = &args;
417
418 printk(KERN_DEBUG "b43-%s debug: %pV",
419 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
420
e4d6b795
MB		 421 va_end(args);
422}
e4d6b795
MB		 423
424static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
425{
426 u32 macctl;
427
428 B43_WARN_ON(offset % 4 != 0);
429
430 macctl = b43_read32(dev, B43_MMIO_MACCTL);
431 if (macctl & B43_MACCTL_BE)
432 val = swab32(val);
433
434 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
435 mmiowb();
436 b43_write32(dev, B43_MMIO_RAM_DATA, val);
437}
438
280d0e16
MB		 439static inline void b43_shm_control_word(struct b43_wldev *dev,
440 u16 routing, u16 offset)
e4d6b795
MB		 441{
442 u32 control;
443
444 /* "offset" is the WORD offset. */
e4d6b795
MB		 445 control = routing;
446 control <<= 16;
447 control |= offset;
448 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
449}
450
69eddc8a 451u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 452{
453 u32 ret;
454
455 if (routing == B43_SHM_SHARED) {
456 B43_WARN_ON(offset & 0x0001);
457 if (offset & 0x0003) {
458 /* Unaligned access */
459 b43_shm_control_word(dev, routing, offset >> 2);
460 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 461 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 462 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 463
280d0e16 464 goto out;
e4d6b795
MB		 465 }
466 offset >>= 2;
467 }
468 b43_shm_control_word(dev, routing, offset);
469 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 470out:
e4d6b795
MB		 471 return ret;
472}
473
69eddc8a 474u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 475{
476 u16 ret;
477
e4d6b795
MB		 478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
483 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
484
280d0e16 485 goto out;
e4d6b795
MB		 486 }
487 offset >>= 2;
488 }
489 b43_shm_control_word(dev, routing, offset);
490 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 491out:
e4d6b795
MB		 492 return ret;
493}
494
69eddc8a 495void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 496{
e4d6b795
MB		 497 if (routing == B43_SHM_SHARED) {
498 B43_WARN_ON(offset & 0x0001);
499 if (offset & 0x0003) {
500 /* Unaligned access */
501 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 502 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 503 value & 0xFFFF);
e4d6b795 504 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 505 b43_write16(dev, B43_MMIO_SHM_DATA,
506 (value >> 16) & 0xFFFF);
6bbc321a 507 return;
e4d6b795
MB		 508 }
509 offset >>= 2;
510 }
511 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 512 b43_write32(dev, B43_MMIO_SHM_DATA, value);
513}
514
69eddc8a 515void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 516{
e4d6b795
MB		 517 if (routing == B43_SHM_SHARED) {
518 B43_WARN_ON(offset & 0x0001);
519 if (offset & 0x0003) {
520 /* Unaligned access */
521 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 522 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 523 return;
e4d6b795
MB		 524 }
525 offset >>= 2;
526 }
527 b43_shm_control_word(dev, routing, offset);
e4d6b795 528 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 529}
530
e4d6b795 531/* Read HostFlags */
99da185a 532u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 533{
35f0d354 534 u64 ret;
e4d6b795
MB		 535
536 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
537 ret <<= 16;
35f0d354
MB		 538 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
539 ret <<= 16;
e4d6b795
MB		 540 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
541
542 return ret;
543}
544
545/* Write HostFlags */
35f0d354 546void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 547{
35f0d354
MB		 548 u16 lo, mi, hi;
549
550 lo = (value & 0x00000000FFFFULL);
551 mi = (value & 0x0000FFFF0000ULL) >> 16;
552 hi = (value & 0xFFFF00000000ULL) >> 32;
553 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
554 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
555 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 556}
557
403a3a13
MB		 558/* Read the firmware capabilities bitmask (Opensource firmware only) */
559static u16 b43_fwcapa_read(struct b43_wldev *dev)
560{
561 B43_WARN_ON(!dev->fw.opensource);
562 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
563}
564
3ebbbb56 565void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 566{
3ebbbb56
MB		 567 u32 low, high;
568
21d889d4 569 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 570
571 /* The hardware guarantees us an atomic read, if we
572 * read the low register first. */
573 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
574 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
575
576 *tsf = high;
577 *tsf <<= 32;
578 *tsf |= low;
e4d6b795
MB		 579}
580
581static void b43_time_lock(struct b43_wldev *dev)
582{
5056635c 583 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
e4d6b795
MB		 584 /* Commit the write */
585 b43_read32(dev, B43_MMIO_MACCTL);
586}
587
588static void b43_time_unlock(struct b43_wldev *dev)
589{
5056635c 590 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
e4d6b795
MB		 591 /* Commit the write */
592 b43_read32(dev, B43_MMIO_MACCTL);
593}
594
595static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
596{
3ebbbb56
MB		 597 u32 low, high;
598
21d889d4 599 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 600
601 low = tsf;
602 high = (tsf >> 32);
603 /* The hardware guarantees us an atomic write, if we
604 * write the low register first. */
605 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
606 mmiowb();
607 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
608 mmiowb();
e4d6b795
MB		 609}
610
611void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
612{
613 b43_time_lock(dev);
614 b43_tsf_write_locked(dev, tsf);
615 b43_time_unlock(dev);
616}
617
618static
99da185a 619void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 620{
621 static const u8 zero_addr[ETH_ALEN] = { 0 };
622 u16 data;
623
624 if (!mac)
625 mac = zero_addr;
626
627 offset |= 0x0020;
628 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
629
630 data = mac[0];
631 data |= mac[1] << 8;
632 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
633 data = mac[2];
634 data |= mac[3] << 8;
635 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
636 data = mac[4];
637 data |= mac[5] << 8;
638 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
639}
640
641static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
642{
643 const u8 *mac;
644 const u8 *bssid;
645 u8 mac_bssid[ETH_ALEN * 2];
646 int i;
647 u32 tmp;
648
649 bssid = dev->wl->bssid;
650 mac = dev->wl->mac_addr;
651
652 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
653
654 memcpy(mac_bssid, mac, ETH_ALEN);
655 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
656
657 /* Write our MAC address and BSSID to template ram */
658 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
659 tmp = (u32) (mac_bssid[i + 0]);
660 tmp |= (u32) (mac_bssid[i + 1]) << 8;
661 tmp |= (u32) (mac_bssid[i + 2]) << 16;
662 tmp |= (u32) (mac_bssid[i + 3]) << 24;
663 b43_ram_write(dev, 0x20 + i, tmp);
664 }
665}
666
4150c572 667static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 668{
e4d6b795 669 b43_write_mac_bssid_templates(dev);
4150c572 670 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 671}
672
673static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
674{
675 /* slot_time is in usec. */
b6c3f5be
LF		 676 /* This test used to exit for all but a G PHY. */
677 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
e4d6b795 678 return;
b6c3f5be
LF		 679 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
680 /* Shared memory location 0x0010 is the slot time and should be
681 * set to slot_time; however, this register is initially 0 and changing
682 * the value adversely affects the transmit rate for BCM4311
683 * devices. Until this behavior is unterstood, delete this step
684 *
685 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
686 */
e4d6b795
MB		 687}
688
689static void b43_short_slot_timing_enable(struct b43_wldev *dev)
690{
691 b43_set_slot_time(dev, 9);
e4d6b795
MB		 692}
693
694static void b43_short_slot_timing_disable(struct b43_wldev *dev)
695{
696 b43_set_slot_time(dev, 20);
e4d6b795
MB		 697}
698
e4d6b795 699/* DummyTransmission function, as documented on
2f19c287 700 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 701 */
2f19c287 702void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 703{
704 struct b43_phy *phy = &dev->phy;
705 unsigned int i, max_loop;
706 u16 value;
707 u32 buffer[5] = {
708 0x00000000,
709 0x00D40000,
710 0x00000000,
711 0x01000000,
712 0x00000000,
713 };
714
2f19c287 715 if (ofdm) {
e4d6b795
MB		 716 max_loop = 0x1E;
717 buffer[0] = 0x000201CC;
2f19c287 718 } else {
e4d6b795
MB		 719 max_loop = 0xFA;
720 buffer[0] = 0x000B846E;
e4d6b795
MB		 721 }
722
723 for (i = 0; i < 5; i++)
724 b43_ram_write(dev, i * 4, buffer[i]);
725
7955d87f
RM		 726 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
727
21d889d4 728 if (dev->dev->core_rev < 11)
7955d87f 729 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
2f19c287 730 else
7955d87f
RM		 731 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
732
2f19c287 733 value = (ofdm ? 0x41 : 0x40);
7955d87f 734 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
93dbd828
RM		 735 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
736 phy->type == B43_PHYTYPE_LCN)
7955d87f
RM		 737 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
738
739 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
740 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
741
742 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
743 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
744 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
745 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
93dbd828
RM		 746
747 if (!pa_on && phy->type == B43_PHYTYPE_N)
748 ; /*b43_nphy_pa_override(dev, false) */
2f19c287
GS		 749
750 switch (phy->type) {
751 case B43_PHYTYPE_N:
93dbd828 752 case B43_PHYTYPE_LCN:
7955d87f 753 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
2f19c287
GS		 754 break;
755 case B43_PHYTYPE_LP:
7955d87f 756 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
2f19c287
GS		 757 break;
758 default:
7955d87f 759 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
2f19c287 760 }
93dbd828 761 b43_read16(dev, B43_MMIO_TXE0_AUX);
e4d6b795
MB		 762
763 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
764 b43_radio_write16(dev, 0x0051, 0x0017);
765 for (i = 0x00; i < max_loop; i++) {
7955d87f 766 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
e4d6b795
MB		 767 if (value & 0x0080)
768 break;
769 udelay(10);
770 }
771 for (i = 0x00; i < 0x0A; i++) {
7955d87f 772 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
e4d6b795
MB		 773 if (value & 0x0400)
774 break;
775 udelay(10);
776 }
1d280ddc 777 for (i = 0x00; i < 0x19; i++) {
7955d87f 778 value = b43_read16(dev, B43_MMIO_IFSSTAT);
e4d6b795
MB		 779 if (!(value & 0x0100))
780 break;
781 udelay(10);
782 }
783 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
784 b43_radio_write16(dev, 0x0051, 0x0037);
785}
786
787static void key_write(struct b43_wldev *dev,
99da185a 788 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 789{
790 unsigned int i;
791 u32 offset;
792 u16 value;
793 u16 kidx;
794
795 /* Key index/algo block */
796 kidx = b43_kidx_to_fw(dev, index);
797 value = ((kidx << 4) | algorithm);
798 b43_shm_write16(dev, B43_SHM_SHARED,
799 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
800
801 /* Write the key to the Key Table Pointer offset */
802 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
803 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
804 value = key[i];
805 value |= (u16) (key[i + 1]) << 8;
806 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
807 }
808}
809
99da185a 810static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 811{
812 u32 addrtmp[2] = { 0, 0, };
66d2d089 813 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 814
815 if (b43_new_kidx_api(dev))
66d2d089 816 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 817
66d2d089
MB		 818 B43_WARN_ON(index < pairwise_keys_start);
819 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 820 * Physical mac 0 is mapped to physical key 4 or 8, depending
821 * on the firmware version.
822 * So we must adjust the index here.
823 */
66d2d089
MB		 824 index -= pairwise_keys_start;
825 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 826
827 if (addr) {
828 addrtmp[0] = addr[0];
829 addrtmp[0] |= ((u32) (addr[1]) << 8);
830 addrtmp[0] |= ((u32) (addr[2]) << 16);
831 addrtmp[0] |= ((u32) (addr[3]) << 24);
832 addrtmp[1] = addr[4];
833 addrtmp[1] |= ((u32) (addr[5]) << 8);
834 }
835
66d2d089
MB		 836 /* Receive match transmitter address (RCMTA) mechanism */
837 b43_shm_write32(dev, B43_SHM_RCMTA,
838 (index * 2) + 0, addrtmp[0]);
839 b43_shm_write16(dev, B43_SHM_RCMTA,
840 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 841}
842
035d0243 843/* The ucode will use phase1 key with TEK key to decrypt rx packets.
844 * When a packet is received, the iv32 is checked.
845 * - if it doesn't the packet is returned without modification (and software
846 * decryption can be done). That's what happen when iv16 wrap.
847 * - if it does, the rc4 key is computed, and decryption is tried.
848 * Either it will success and B43_RX_MAC_DEC is returned,
849 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
850 * and the packet is not usable (it got modified by the ucode).
851 * So in order to never have B43_RX_MAC_DECERR, we should provide
852 * a iv32 and phase1key that match. Because we drop packets in case of
853 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
854 * packets will be lost without higher layer knowing (ie no resync possible
855 * until next wrap).
856 *
857 * NOTE : this should support 50 key like RCMTA because
858 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
859 */
860static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
861 u16 *phase1key)
862{
863 unsigned int i;
864 u32 offset;
865 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
866
867 if (!modparam_hwtkip)
868 return;
869
870 if (b43_new_kidx_api(dev))
871 pairwise_keys_start = B43_NR_GROUP_KEYS;
872
873 B43_WARN_ON(index < pairwise_keys_start);
874 /* We have four default TX keys and possibly four default RX keys.
875 * Physical mac 0 is mapped to physical key 4 or 8, depending
876 * on the firmware version.
877 * So we must adjust the index here.
878 */
879 index -= pairwise_keys_start;
880 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
881
882 if (b43_debug(dev, B43_DBG_KEYS)) {
883 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
884 index, iv32);
885 }
886 /* Write the key to the RX tkip shared mem */
887 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
888 for (i = 0; i < 10; i += 2) {
889 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
890 phase1key ? phase1key[i / 2] : 0);
891 }
892 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
893 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
894}
895
896static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 897 struct ieee80211_vif *vif,
898 struct ieee80211_key_conf *keyconf,
899 struct ieee80211_sta *sta,
900 u32 iv32, u16 *phase1key)
035d0243 901{
902 struct b43_wl *wl = hw_to_b43_wl(hw);
903 struct b43_wldev *dev;
904 int index = keyconf->hw_key_idx;
905
906 if (B43_WARN_ON(!modparam_hwtkip))
907 return;
908
96869a39
MB		 909 /* This is only called from the RX path through mac80211, where
910 * our mutex is already locked. */
911 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
035d0243 912 dev = wl->current_dev;
96869a39 913 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
035d0243 914
915 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
916
917 rx_tkip_phase1_write(dev, index, iv32, phase1key);
b3fbdcf4
JB		 918 /* only pairwise TKIP keys are supported right now */
919 if (WARN_ON(!sta))
96869a39 920 return;
b3fbdcf4 921 keymac_write(dev, index, sta->addr);
035d0243 922}
923
e4d6b795
MB		 924static void do_key_write(struct b43_wldev *dev,
925 u8 index, u8 algorithm,
99da185a 926 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 927{
928 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 929 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 930
931 if (b43_new_kidx_api(dev))
66d2d089 932 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 933
66d2d089 934 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 935 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
936
66d2d089 937 if (index >= pairwise_keys_start)
e4d6b795 938 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 939 if (algorithm == B43_SEC_ALGO_TKIP) {
940 /*
941 * We should provide an initial iv32, phase1key pair.
942 * We could start with iv32=0 and compute the corresponding
943 * phase1key, but this means calling ieee80211_get_tkip_key
944 * with a fake skb (or export other tkip function).
945 * Because we are lazy we hope iv32 won't start with
946 * 0xffffffff and let's b43_op_update_tkip_key provide a
947 * correct pair.
948 */
949 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
950 } else if (index >= pairwise_keys_start) /* clear it */
951 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 952 if (key)
953 memcpy(buf, key, key_len);
954 key_write(dev, index, algorithm, buf);
66d2d089 955 if (index >= pairwise_keys_start)
e4d6b795
MB		 956 keymac_write(dev, index, mac_addr);
957
958 dev->key[index].algorithm = algorithm;
959}
960
961static int b43_key_write(struct b43_wldev *dev,
962 int index, u8 algorithm,
99da185a
JD		 963 const u8 *key, size_t key_len,
964 const u8 *mac_addr,
e4d6b795
MB		 965 struct ieee80211_key_conf *keyconf)
966{
967 int i;
66d2d089 968 int pairwise_keys_start;
e4d6b795 969
035d0243 970 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
971 * - Temporal Encryption Key (128 bits)
972 * - Temporal Authenticator Tx MIC Key (64 bits)
973 * - Temporal Authenticator Rx MIC Key (64 bits)
974 *
975 * Hardware only store TEK
976 */
977 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
978 key_len = 16;
e4d6b795
MB		 979 if (key_len > B43_SEC_KEYSIZE)
980 return -EINVAL;
66d2d089 981 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 982 /* Check that we don't already have this key. */
983 B43_WARN_ON(dev->key[i].keyconf == keyconf);
984 }
985 if (index < 0) {
e808e586 986 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 987 if (b43_new_kidx_api(dev))
66d2d089 988 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 989 else
66d2d089
MB		 990 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
991 for (i = pairwise_keys_start;
992 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
993 i++) {
994 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 995 if (!dev->key[i].keyconf) {
996 /* found empty */
997 index = i;
998 break;
999 }
1000 }
1001 if (index < 0) {
e808e586 1002 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 1003 return -ENOSPC;
1004 }
1005 } else
1006 B43_WARN_ON(index > 3);
1007
1008 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1009 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1010 /* Default RX key */
1011 B43_WARN_ON(mac_addr);
1012 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1013 }
1014 keyconf->hw_key_idx = index;
1015 dev->key[index].keyconf = keyconf;
1016
1017 return 0;
1018}
1019
1020static int b43_key_clear(struct b43_wldev *dev, int index)
1021{
66d2d089 1022 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 1023 return -EINVAL;
1024 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1025 NULL, B43_SEC_KEYSIZE, NULL);
1026 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1027 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1028 NULL, B43_SEC_KEYSIZE, NULL);
1029 }
1030 dev->key[index].keyconf = NULL;
1031
1032 return 0;
1033}
1034
1035static void b43_clear_keys(struct b43_wldev *dev)
1036{
66d2d089 1037 int i, count;
e4d6b795 1038
66d2d089
MB		 1039 if (b43_new_kidx_api(dev))
1040 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1041 else
1042 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1043 for (i = 0; i < count; i++)
e4d6b795
MB		 1044 b43_key_clear(dev, i);
1045}
1046
9cf7f247
MB		 1047static void b43_dump_keymemory(struct b43_wldev *dev)
1048{
66d2d089 1049 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 1050 u8 mac[ETH_ALEN];
1051 u16 algo;
1052 u32 rcmta0;
1053 u16 rcmta1;
1054 u64 hf;
1055 struct b43_key *key;
1056
1057 if (!b43_debug(dev, B43_DBG_KEYS))
1058 return;
1059
1060 hf = b43_hf_read(dev);
1061 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1062 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1063 if (b43_new_kidx_api(dev)) {
1064 pairwise_keys_start = B43_NR_GROUP_KEYS;
1065 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1066 } else {
1067 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1068 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1069 }
1070 for (index = 0; index < count; index++) {
9cf7f247
MB		 1071 key = &(dev->key[index]);
1072 printk(KERN_DEBUG "Key slot %02u: %s",
1073 index, (key->keyconf == NULL) ? " " : "*");
1074 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1075 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1076 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1077 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1078 }
1079
1080 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1081 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1082 printk(" Algo: %04X/%02X", algo, key->algorithm);
1083
66d2d089 1084 if (index >= pairwise_keys_start) {
035d0243 1085 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1086 printk(" TKIP: ");
1087 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1088 for (i = 0; i < 14; i += 2) {
1089 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1090 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1091 }
1092 }
9cf7f247 1093 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1094 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1095 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1096 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1097 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1098 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1099 printk(" MAC: %pM", mac);
9cf7f247
MB		 1100 } else
1101 printk(" DEFAULT KEY");
1102 printk("\n");
1103 }
1104}
1105
e4d6b795
MB		 1106void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1107{
1108 u32 macctl;
1109 u16 ucstat;
1110 bool hwps;
1111 bool awake;
1112 int i;
1113
1114 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1115 (ps_flags & B43_PS_DISABLED));
1116 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1117
1118 if (ps_flags & B43_PS_ENABLED) {
3db1cd5c 1119 hwps = true;
e4d6b795 1120 } else if (ps_flags & B43_PS_DISABLED) {
3db1cd5c 1121 hwps = false;
e4d6b795
MB		 1122 } else {
1123 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1124 // and thus is not an AP and we are associated, set bit 25
1125 }
1126 if (ps_flags & B43_PS_AWAKE) {
3db1cd5c 1127 awake = true;
e4d6b795 1128 } else if (ps_flags & B43_PS_ASLEEP) {
3db1cd5c 1129 awake = false;
e4d6b795
MB		 1130 } else {
1131 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1132 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1133 // successful, set bit26
1134 }
1135
1136/* FIXME: For now we force awake-on and hwps-off */
3db1cd5c
RR		 1137 hwps = false;
1138 awake = true;
e4d6b795
MB		 1139
1140 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1141 if (hwps)
1142 macctl |= B43_MACCTL_HWPS;
1143 else
1144 macctl &= ~B43_MACCTL_HWPS;
1145 if (awake)
1146 macctl |= B43_MACCTL_AWAKE;
1147 else
1148 macctl &= ~B43_MACCTL_AWAKE;
1149 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1150 /* Commit write */
1151 b43_read32(dev, B43_MMIO_MACCTL);
21d889d4 1152 if (awake && dev->dev->core_rev >= 5) {
e4d6b795
MB		 1153 /* Wait for the microcode to wake up. */
1154 for (i = 0; i < 100; i++) {
1155 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1156 B43_SHM_SH_UCODESTAT);
1157 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1158 break;
1159 udelay(10);
1160 }
1161 }
1162}
1163
42c9a458 1164#ifdef CONFIG_B43_BCMA
49173592 1165static void b43_bcma_phy_reset(struct b43_wldev *dev)
42c9a458 1166{
49173592 1167 u32 flags;
42c9a458 1168
49173592
RM		 1169 /* Put PHY into reset */
1170 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1171 flags |= B43_BCMA_IOCTL_PHY_RESET;
42c9a458 1172 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
49173592
RM		 1173 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1174 udelay(2);
1175
1176 /* Take PHY out of reset */
1177 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1178 flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1179 flags |= BCMA_IOCTL_FGC;
1180 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1181 udelay(1);
1182
1183 /* Do not force clock anymore */
1184 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1185 flags &= ~BCMA_IOCTL_FGC;
1186 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1187 udelay(1);
1188}
42c9a458 1189
49173592
RM		 1190static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1191{
1192 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1193 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1194 b43_bcma_phy_reset(dev);
1195 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
42c9a458
RM		 1196}
1197#endif
1198
4da909e7 1199static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
e4d6b795 1200{
d48ae5c8 1201 struct ssb_device *sdev = dev->dev->sdev;
e4d6b795 1202 u32 tmslow;
4da909e7 1203 u32 flags = 0;
e4d6b795 1204
4da909e7
RM		 1205 if (gmode)
1206 flags |= B43_TMSLOW_GMODE;
e4d6b795
MB		 1207 flags |= B43_TMSLOW_PHYCLKEN;
1208 flags |= B43_TMSLOW_PHYRESET;
42ab135f
RM		 1209 if (dev->phy.type == B43_PHYTYPE_N)
1210 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
24ca39d6 1211 b43_device_enable(dev, flags);
e4d6b795
MB		 1212 msleep(2); /* Wait for the PLL to turn on. */
1213
1214 /* Now take the PHY out of Reset again */
d48ae5c8 1215 tmslow = ssb_read32(sdev, SSB_TMSLOW);
e4d6b795
MB		 1216 tmslow |= SSB_TMSLOW_FGC;
1217 tmslow &= ~B43_TMSLOW_PHYRESET;
d48ae5c8
RM		 1218 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1219 ssb_read32(sdev, SSB_TMSLOW); /* flush */
e4d6b795
MB		 1220 msleep(1);
1221 tmslow &= ~SSB_TMSLOW_FGC;
d48ae5c8
RM		 1222 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1223 ssb_read32(sdev, SSB_TMSLOW); /* flush */
e4d6b795 1224 msleep(1);
1495298d
RM		 1225}
1226
4da909e7 1227void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1495298d
RM		 1228{
1229 u32 macctl;
1230
6cbab0d9 1231 switch (dev->dev->bus_type) {
42c9a458
RM		 1232#ifdef CONFIG_B43_BCMA
1233 case B43_BUS_BCMA:
1234 b43_bcma_wireless_core_reset(dev, gmode);
1235 break;
1236#endif
6cbab0d9
RM		 1237#ifdef CONFIG_B43_SSB
1238 case B43_BUS_SSB:
1239 b43_ssb_wireless_core_reset(dev, gmode);
1240 break;
1241#endif
1242 }
e4d6b795 1243
fb11137a
MB		 1244 /* Turn Analog ON, but only if we already know the PHY-type.
1245 * This protects against very early setup where we don't know the
1246 * PHY-type, yet. wireless_core_reset will be called once again later,
1247 * when we know the PHY-type. */
1248 if (dev->phy.ops)
cb24f57f 1249 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1250
1251 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1252 macctl &= ~B43_MACCTL_GMODE;
4da909e7 1253 if (gmode)
e4d6b795
MB		 1254 macctl |= B43_MACCTL_GMODE;
1255 macctl |= B43_MACCTL_IHR_ENABLED;
1256 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1257}
1258
1259static void handle_irq_transmit_status(struct b43_wldev *dev)
1260{
1261 u32 v0, v1;
1262 u16 tmp;
1263 struct b43_txstatus stat;
1264
1265 while (1) {
1266 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1267 if (!(v0 & 0x00000001))
1268 break;
1269 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1270
1271 stat.cookie = (v0 >> 16);
1272 stat.seq = (v1 & 0x0000FFFF);
1273 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1274 tmp = (v0 & 0x0000FFFF);
1275 stat.frame_count = ((tmp & 0xF000) >> 12);
1276 stat.rts_count = ((tmp & 0x0F00) >> 8);
1277 stat.supp_reason = ((tmp & 0x001C) >> 2);
1278 stat.pm_indicated = !!(tmp & 0x0080);
1279 stat.intermediate = !!(tmp & 0x0040);
1280 stat.for_ampdu = !!(tmp & 0x0020);
1281 stat.acked = !!(tmp & 0x0002);
1282
1283 b43_handle_txstatus(dev, &stat);
1284 }
1285}
1286
1287static void drain_txstatus_queue(struct b43_wldev *dev)
1288{
1289 u32 dummy;
1290
21d889d4 1291 if (dev->dev->core_rev < 5)
e4d6b795
MB		 1292 return;
1293 /* Read all entries from the microcode TXstatus FIFO
1294 * and throw them away.
1295 */
1296 while (1) {
1297 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1298 if (!(dummy & 0x00000001))
1299 break;
1300 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1301 }
1302}
1303
1304static u32 b43_jssi_read(struct b43_wldev *dev)
1305{
1306 u32 val = 0;
1307
1308 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1309 val <<= 16;
1310 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1311
1312 return val;
1313}
1314
1315static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1316{
1317 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1318 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1319}
1320
1321static void b43_generate_noise_sample(struct b43_wldev *dev)
1322{
1323 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1324 b43_write32(dev, B43_MMIO_MACCMD,
1325 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1326}
1327
1328static void b43_calculate_link_quality(struct b43_wldev *dev)
1329{
1330 /* Top half of Link Quality calculation. */
1331
ef1a628d
MB		 1332 if (dev->phy.type != B43_PHYTYPE_G)
1333 return;
e4d6b795
MB		 1334 if (dev->noisecalc.calculation_running)
1335 return;
3db1cd5c 1336 dev->noisecalc.calculation_running = true;
e4d6b795
MB		 1337 dev->noisecalc.nr_samples = 0;
1338
1339 b43_generate_noise_sample(dev);
1340}
1341
1342static void handle_irq_noise(struct b43_wldev *dev)
1343{
ef1a628d 1344 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1345 u16 tmp;
1346 u8 noise[4];
1347 u8 i, j;
1348 s32 average;
1349
1350 /* Bottom half of Link Quality calculation. */
1351
ef1a628d
MB		 1352 if (dev->phy.type != B43_PHYTYPE_G)
1353 return;
1354
98a3b2fe
MB		 1355 /* Possible race condition: It might be possible that the user
1356 * changed to a different channel in the meantime since we
1357 * started the calculation. We ignore that fact, since it's
1358 * not really that much of a problem. The background noise is
1359 * an estimation only anyway. Slightly wrong results will get damped
1360 * by the averaging of the 8 sample rounds. Additionally the
1361 * value is shortlived. So it will be replaced by the next noise
1362 * calculation round soon. */
1363
e4d6b795 1364 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1365 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1366 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1367 noise[2] == 0x7F || noise[3] == 0x7F)
1368 goto generate_new;
1369
1370 /* Get the noise samples. */
1371 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1372 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1373 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1374 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1375 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1376 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1377 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1378 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1379 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1380 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1381 dev->noisecalc.nr_samples++;
1382 if (dev->noisecalc.nr_samples == 8) {
1383 /* Calculate the Link Quality by the noise samples. */
1384 average = 0;
1385 for (i = 0; i < 8; i++) {
1386 for (j = 0; j < 4; j++)
1387 average += dev->noisecalc.samples[i][j];
1388 }
1389 average /= (8 * 4);
1390 average *= 125;
1391 average += 64;
1392 average /= 128;
1393 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1394 tmp = (tmp / 128) & 0x1F;
1395 if (tmp >= 8)
1396 average += 2;
1397 else
1398 average -= 25;
1399 if (tmp == 8)
1400 average -= 72;
1401 else
1402 average -= 48;
1403
1404 dev->stats.link_noise = average;
3db1cd5c 1405 dev->noisecalc.calculation_running = false;
e4d6b795
MB		 1406 return;
1407 }
98a3b2fe 1408generate_new:
e4d6b795
MB		 1409 b43_generate_noise_sample(dev);
1410}
1411
1412static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1413{
05c914fe 1414 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1415 ///TODO: PS TBTT
1416 } else {
1417 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1418 b43_power_saving_ctl_bits(dev, 0);
1419 }
05c914fe 1420 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3db1cd5c 1421 dev->dfq_valid = true;
e4d6b795
MB		 1422}
1423
1424static void handle_irq_atim_end(struct b43_wldev *dev)
1425{
aa6c7ae2
MB		 1426 if (dev->dfq_valid) {
1427 b43_write32(dev, B43_MMIO_MACCMD,
1428 b43_read32(dev, B43_MMIO_MACCMD)
1429 | B43_MACCMD_DFQ_VALID);
3db1cd5c 1430 dev->dfq_valid = false;
aa6c7ae2 1431 }
e4d6b795
MB		 1432}
1433
1434static void handle_irq_pmq(struct b43_wldev *dev)
1435{
1436 u32 tmp;
1437
1438 //TODO: AP mode.
1439
1440 while (1) {
1441 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1442 if (!(tmp & 0x00000008))
1443 break;
1444 }
1445 /* 16bit write is odd, but correct. */
1446 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1447}
1448
1449static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1450 const u8 *data, u16 size,
e4d6b795
MB		 1451 u16 ram_offset,
1452 u16 shm_size_offset, u8 rate)
1453{
1454 u32 i, tmp;
1455 struct b43_plcp_hdr4 plcp;
1456
1457 plcp.data = 0;
1458 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1459 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1460 ram_offset += sizeof(u32);
1461 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1462 * So leave the first two bytes of the next write blank.
1463 */
1464 tmp = (u32) (data[0]) << 16;
1465 tmp |= (u32) (data[1]) << 24;
1466 b43_ram_write(dev, ram_offset, tmp);
1467 ram_offset += sizeof(u32);
1468 for (i = 2; i < size; i += sizeof(u32)) {
1469 tmp = (u32) (data[i + 0]);
1470 if (i + 1 < size)
1471 tmp |= (u32) (data[i + 1]) << 8;
1472 if (i + 2 < size)
1473 tmp |= (u32) (data[i + 2]) << 16;
1474 if (i + 3 < size)
1475 tmp |= (u32) (data[i + 3]) << 24;
1476 b43_ram_write(dev, ram_offset + i - 2, tmp);
1477 }
1478 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1479 size + sizeof(struct b43_plcp_hdr6));
1480}
1481
5042c507
MB		 1482/* Check if the use of the antenna that ieee80211 told us to
1483 * use is possible. This will fall back to DEFAULT.
1484 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1485u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1486 u8 antenna_nr)
1487{
1488 u8 antenna_mask;
1489
1490 if (antenna_nr == 0) {
1491 /* Zero means "use default antenna". That's always OK. */
1492 return 0;
1493 }
1494
1495 /* Get the mask of available antennas. */
1496 if (dev->phy.gmode)
0581483a 1497 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
5042c507 1498 else
0581483a 1499 antenna_mask = dev->dev->bus_sprom->ant_available_a;
5042c507
MB		 1500
1501 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1502 /* This antenna is not available. Fall back to default. */
1503 return 0;
1504 }
1505
1506 return antenna_nr;
1507}
1508
5042c507
MB		 1509/* Convert a b43 antenna number value to the PHY TX control value. */
1510static u16 b43_antenna_to_phyctl(int antenna)
1511{
1512 switch (antenna) {
1513 case B43_ANTENNA0:
1514 return B43_TXH_PHY_ANT0;
1515 case B43_ANTENNA1:
1516 return B43_TXH_PHY_ANT1;
1517 case B43_ANTENNA2:
1518 return B43_TXH_PHY_ANT2;
1519 case B43_ANTENNA3:
1520 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1521 case B43_ANTENNA_AUTO0:
1522 case B43_ANTENNA_AUTO1:
5042c507
MB		 1523 return B43_TXH_PHY_ANT01AUTO;
1524 }
1525 B43_WARN_ON(1);
1526 return 0;
1527}
1528
e4d6b795
MB		 1529static void b43_write_beacon_template(struct b43_wldev *dev,
1530 u16 ram_offset,
5042c507 1531 u16 shm_size_offset)
e4d6b795 1532{
47f76ca3 1533 unsigned int i, len, variable_len;
e66fee6a
MB		 1534 const struct ieee80211_mgmt *bcn;
1535 const u8 *ie;
3db1cd5c 1536 bool tim_found = false;
5042c507
MB		 1537 unsigned int rate;
1538 u16 ctl;
1539 int antenna;
e039fa4a 1540 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1541
e66fee6a
MB		 1542 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1543 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1544 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1545 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1546
1547 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1548 len, ram_offset, shm_size_offset, rate);
e66fee6a 1549
5042c507 1550 /* Write the PHY TX control parameters. */
0f4ac38b 1551 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1552 antenna = b43_antenna_to_phyctl(antenna);
1553 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1554 /* We can't send beacons with short preamble. Would get PHY errors. */
1555 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1556 ctl &= ~B43_TXH_PHY_ANT;
1557 ctl &= ~B43_TXH_PHY_ENC;
1558 ctl |= antenna;
1559 if (b43_is_cck_rate(rate))
1560 ctl |= B43_TXH_PHY_ENC_CCK;
1561 else
1562 ctl |= B43_TXH_PHY_ENC_OFDM;
1563 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1564
e66fee6a
MB		 1565 /* Find the position of the TIM and the DTIM_period value
1566 * and write them to SHM. */
1567 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1568 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1569 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1570 uint8_t ie_id, ie_len;
1571
1572 ie_id = ie[i];
1573 ie_len = ie[i + 1];
1574 if (ie_id == 5) {
1575 u16 tim_position;
1576 u16 dtim_period;
1577 /* This is the TIM Information Element */
1578
1579 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1580 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1581 break;
1582 /* A valid TIM is at least 4 bytes long. */
1583 if (ie_len < 4)
1584 break;
3db1cd5c 1585 tim_found = true;
e66fee6a
MB		 1586
1587 tim_position = sizeof(struct b43_plcp_hdr6);
1588 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1589 tim_position += i;
1590
1591 dtim_period = ie[i + 3];
1592
1593 b43_shm_write16(dev, B43_SHM_SHARED,
1594 B43_SHM_SH_TIMBPOS, tim_position);
1595 b43_shm_write16(dev, B43_SHM_SHARED,
1596 B43_SHM_SH_DTIMPER, dtim_period);
1597 break;
1598 }
1599 i += ie_len + 2;
1600 }
1601 if (!tim_found) {
04dea136
JB		 1602 /*
1603 * If ucode wants to modify TIM do it behind the beacon, this
1604 * will happen, for example, when doing mesh networking.
1605 */
1606 b43_shm_write16(dev, B43_SHM_SHARED,
1607 B43_SHM_SH_TIMBPOS,
1608 len + sizeof(struct b43_plcp_hdr6));
1609 b43_shm_write16(dev, B43_SHM_SHARED,
1610 B43_SHM_SH_DTIMPER, 0);
1611 }
1612 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1613}
1614
6b4bec01
MB		 1615static void b43_upload_beacon0(struct b43_wldev *dev)
1616{
1617 struct b43_wl *wl = dev->wl;
1618
1619 if (wl->beacon0_uploaded)
1620 return;
1621 b43_write_beacon_template(dev, 0x68, 0x18);
3db1cd5c 1622 wl->beacon0_uploaded = true;
6b4bec01
MB		 1623}
1624
1625static void b43_upload_beacon1(struct b43_wldev *dev)
1626{
1627 struct b43_wl *wl = dev->wl;
1628
1629 if (wl->beacon1_uploaded)
1630 return;
1631 b43_write_beacon_template(dev, 0x468, 0x1A);
3db1cd5c 1632 wl->beacon1_uploaded = true;
6b4bec01
MB		 1633}
1634
c97a4ccc
MB		 1635static void handle_irq_beacon(struct b43_wldev *dev)
1636{
1637 struct b43_wl *wl = dev->wl;
1638 u32 cmd, beacon0_valid, beacon1_valid;
1639
05c914fe 1640 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
8c23516f
MM		 1641 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1642 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
c97a4ccc
MB		 1643 return;
1644
1645 /* This is the bottom half of the asynchronous beacon update. */
1646
1647 /* Ignore interrupt in the future. */
13790728 1648 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1649
1650 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1651 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1652 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1653
1654 /* Schedule interrupt manually, if busy. */
1655 if (beacon0_valid && beacon1_valid) {
1656 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1657 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1658 return;
1659 }
1660
6b4bec01
MB		 1661 if (unlikely(wl->beacon_templates_virgin)) {
1662 /* We never uploaded a beacon before.
1663 * Upload both templates now, but only mark one valid. */
3db1cd5c 1664 wl->beacon_templates_virgin = false;
6b4bec01
MB		 1665 b43_upload_beacon0(dev);
1666 b43_upload_beacon1(dev);
c97a4ccc
MB		 1667 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1668 cmd |= B43_MACCMD_BEACON0_VALID;
1669 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1670 } else {
1671 if (!beacon0_valid) {
1672 b43_upload_beacon0(dev);
1673 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1674 cmd |= B43_MACCMD_BEACON0_VALID;
1675 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1676 } else if (!beacon1_valid) {
1677 b43_upload_beacon1(dev);
1678 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1679 cmd |= B43_MACCMD_BEACON1_VALID;
1680 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1681 }
c97a4ccc
MB		 1682 }
1683}
1684
36dbd954
MB		 1685static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1686{
1687 u32 old_irq_mask = dev->irq_mask;
1688
1689 /* update beacon right away or defer to irq */
1690 handle_irq_beacon(dev);
1691 if (old_irq_mask != dev->irq_mask) {
1692 /* The handler updated the IRQ mask. */
1693 B43_WARN_ON(!dev->irq_mask);
1694 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1695 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1696 } else {
1697 /* Device interrupts are currently disabled. That means
1698 * we just ran the hardirq handler and scheduled the
1699 * IRQ thread. The thread will write the IRQ mask when
1700 * it finished, so there's nothing to do here. Writing
1701 * the mask _here_ would incorrectly re-enable IRQs. */
1702 }
1703 }
1704}
1705
a82d9922
MB		 1706static void b43_beacon_update_trigger_work(struct work_struct *work)
1707{
1708 struct b43_wl *wl = container_of(work, struct b43_wl,
1709 beacon_update_trigger);
1710 struct b43_wldev *dev;
1711
1712 mutex_lock(&wl->mutex);
1713 dev = wl->current_dev;
1714 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
505fb019 1715 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 1716 /* wl->mutex is enough. */
1717 b43_do_beacon_update_trigger_work(dev);
1718 mmiowb();
1719 } else {
1720 spin_lock_irq(&wl->hardirq_lock);
1721 b43_do_beacon_update_trigger_work(dev);
1722 mmiowb();
1723 spin_unlock_irq(&wl->hardirq_lock);
1724 }
a82d9922
MB		 1725 }
1726 mutex_unlock(&wl->mutex);
1727}
1728
d4df6f1a 1729/* Asynchronously update the packet templates in template RAM.
36dbd954 1730 * Locking: Requires wl->mutex to be locked. */
9d139c81 1731static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1732{
9d139c81
JB		 1733 struct sk_buff *beacon;
1734
e66fee6a
MB		 1735 /* This is the top half of the ansynchronous beacon update.
1736 * The bottom half is the beacon IRQ.
1737 * Beacon update must be asynchronous to avoid sending an
1738 * invalid beacon. This can happen for example, if the firmware
1739 * transmits a beacon while we are updating it. */
e4d6b795 1740
9d139c81
JB		 1741 /* We could modify the existing beacon and set the aid bit in
1742 * the TIM field, but that would probably require resizing and
1743 * moving of data within the beacon template.
1744 * Simply request a new beacon and let mac80211 do the hard work. */
1745 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1746 if (unlikely(!beacon))
1747 return;
1748
e66fee6a
MB		 1749 if (wl->current_beacon)
1750 dev_kfree_skb_any(wl->current_beacon);
1751 wl->current_beacon = beacon;
3db1cd5c
RR		 1752 wl->beacon0_uploaded = false;
1753 wl->beacon1_uploaded = false;
42935eca 1754 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1755}
1756
e4d6b795
MB		 1757static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1758{
1759 b43_time_lock(dev);
21d889d4 1760 if (dev->dev->core_rev >= 3) {
a82d9922
MB		 1761 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1762 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1763 } else {
1764 b43_write16(dev, 0x606, (beacon_int >> 6));
1765 b43_write16(dev, 0x610, beacon_int);
1766 }
1767 b43_time_unlock(dev);
a82d9922 1768 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1769}
1770
afa83e23
MB		 1771static void b43_handle_firmware_panic(struct b43_wldev *dev)
1772{
1773 u16 reason;
1774
1775 /* Read the register that contains the reason code for the panic. */
1776 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1777 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1778
1779 switch (reason) {
1780 default:
1781 b43dbg(dev->wl, "The panic reason is unknown.\n");
1782 /* fallthrough */
1783 case B43_FWPANIC_DIE:
1784 /* Do not restart the controller or firmware.
1785 * The device is nonfunctional from now on.
1786 * Restarting would result in this panic to trigger again,
1787 * so we avoid that recursion. */
1788 break;
1789 case B43_FWPANIC_RESTART:
1790 b43_controller_restart(dev, "Microcode panic");
1791 break;
1792 }
1793}
1794
e4d6b795
MB		 1795static void handle_irq_ucode_debug(struct b43_wldev *dev)
1796{
e48b0eeb 1797 unsigned int i, cnt;
53c06856 1798 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1799 __le16 *buf;
1800
1801 /* The proprietary firmware doesn't have this IRQ. */
1802 if (!dev->fw.opensource)
1803 return;
1804
afa83e23
MB		 1805 /* Read the register that contains the reason code for this IRQ. */
1806 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1807
e48b0eeb
MB		 1808 switch (reason) {
1809 case B43_DEBUGIRQ_PANIC:
afa83e23 1810 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1811 break;
1812 case B43_DEBUGIRQ_DUMP_SHM:
1813 if (!B43_DEBUG)
1814 break; /* Only with driver debugging enabled. */
1815 buf = kmalloc(4096, GFP_ATOMIC);
1816 if (!buf) {
1817 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1818 goto out;
1819 }
1820 for (i = 0; i < 4096; i += 2) {
1821 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1822 buf[i / 2] = cpu_to_le16(tmp);
1823 }
1824 b43info(dev->wl, "Shared memory dump:\n");
1825 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1826 16, 2, buf, 4096, 1);
1827 kfree(buf);
1828 break;
1829 case B43_DEBUGIRQ_DUMP_REGS:
1830 if (!B43_DEBUG)
1831 break; /* Only with driver debugging enabled. */
1832 b43info(dev->wl, "Microcode register dump:\n");
1833 for (i = 0, cnt = 0; i < 64; i++) {
1834 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1835 if (cnt == 0)
1836 printk(KERN_INFO);
1837 printk("r%02u: 0x%04X ", i, tmp);
1838 cnt++;
1839 if (cnt == 6) {
1840 printk("\n");
1841 cnt = 0;
1842 }
1843 }
1844 printk("\n");
1845 break;
53c06856
MB		 1846 case B43_DEBUGIRQ_MARKER:
1847 if (!B43_DEBUG)
1848 break; /* Only with driver debugging enabled. */
1849 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1850 B43_MARKER_ID_REG);
1851 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1852 B43_MARKER_LINE_REG);
1853 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1854 "at line number %u\n",
1855 marker_id, marker_line);
1856 break;
e48b0eeb
MB		 1857 default:
1858 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1859 reason);
1860 }
1861out:
afa83e23
MB		 1862 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1863 b43_shm_write16(dev, B43_SHM_SCRATCH,
1864 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1865}
1866
36dbd954 1867static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1868{
1869 u32 reason;
1870 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1871 u32 merged_dma_reason = 0;
21954c36 1872 int i;
e4d6b795 1873
36dbd954
MB		 1874 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1875 return;
e4d6b795
MB		 1876
1877 reason = dev->irq_reason;
1878 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1879 dma_reason[i] = dev->dma_reason[i];
1880 merged_dma_reason |= dma_reason[i];
1881 }
1882
1883 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1884 b43err(dev->wl, "MAC transmission error\n");
1885
00e0b8cb 1886 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1887 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1888 rmb();
1889 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1890 atomic_set(&dev->phy.txerr_cnt,
1891 B43_PHY_TX_BADNESS_LIMIT);
1892 b43err(dev->wl, "Too many PHY TX errors, "
1893 "restarting the controller\n");
1894 b43_controller_restart(dev, "PHY TX errors");
1895 }
1896 }
e4d6b795
MB		 1897
1898 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1899 B43_DMAIRQ_NONFATALMASK))) {
1900 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1901 b43err(dev->wl, "Fatal DMA error: "
1902 "0x%08X, 0x%08X, 0x%08X, "
1903 "0x%08X, 0x%08X, 0x%08X\n",
1904 dma_reason[0], dma_reason[1],
1905 dma_reason[2], dma_reason[3],
1906 dma_reason[4], dma_reason[5]);
214ac9a4 1907 b43err(dev->wl, "This device does not support DMA "
bb64d95e 1908 "on your system. It will now be switched to PIO.\n");
9e3bd919 1909 /* Fall back to PIO transfers if we get fatal DMA errors! */
3db1cd5c 1910 dev->use_pio = true;
9e3bd919 1911 b43_controller_restart(dev, "DMA error");
e4d6b795
MB		 1912 return;
1913 }
1914 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1915 b43err(dev->wl, "DMA error: "
1916 "0x%08X, 0x%08X, 0x%08X, "
1917 "0x%08X, 0x%08X, 0x%08X\n",
1918 dma_reason[0], dma_reason[1],
1919 dma_reason[2], dma_reason[3],
1920 dma_reason[4], dma_reason[5]);
1921 }
1922 }
1923
1924 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1925 handle_irq_ucode_debug(dev);
1926 if (reason & B43_IRQ_TBTT_INDI)
1927 handle_irq_tbtt_indication(dev);
1928 if (reason & B43_IRQ_ATIM_END)
1929 handle_irq_atim_end(dev);
1930 if (reason & B43_IRQ_BEACON)
1931 handle_irq_beacon(dev);
1932 if (reason & B43_IRQ_PMQ)
1933 handle_irq_pmq(dev);
21954c36
MB		 1934 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1935 ;/* TODO */
1936 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1937 handle_irq_noise(dev);
1938
1939 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1940 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1941 if (b43_using_pio_transfers(dev))
1942 b43_pio_rx(dev->pio.rx_queue);
1943 else
1944 b43_dma_rx(dev->dma.rx_ring);
1945 }
e4d6b795
MB		 1946 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1947 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1948 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1949 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1950 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1951
21954c36 1952 if (reason & B43_IRQ_TX_OK)
e4d6b795 1953 handle_irq_transmit_status(dev);
e4d6b795 1954
36dbd954 1955 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1956 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
990b86f4
MB		 1957
1958#if B43_DEBUG
1959 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1960 dev->irq_count++;
1961 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1962 if (reason & (1 << i))
1963 dev->irq_bit_count[i]++;
1964 }
1965 }
1966#endif
e4d6b795
MB		 1967}
1968
36dbd954
MB		 1969/* Interrupt thread handler. Handles device interrupts in thread context. */
1970static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1971{
36dbd954 1972 struct b43_wldev *dev = dev_id;
e4d6b795 1973
36dbd954
MB		 1974 mutex_lock(&dev->wl->mutex);
1975 b43_do_interrupt_thread(dev);
1976 mmiowb();
1977 mutex_unlock(&dev->wl->mutex);
1978
1979 return IRQ_HANDLED;
e4d6b795
MB		 1980}
1981
36dbd954 1982static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 1983{
e4d6b795
MB		 1984 u32 reason;
1985
36dbd954
MB		 1986 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1987 * On SDIO, this runs under wl->mutex. */
e4d6b795 1988
e4d6b795
MB		 1989 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1990 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 1991 return IRQ_NONE;
13790728 1992 reason &= dev->irq_mask;
e4d6b795 1993 if (!reason)
cae56147 1994 return IRQ_NONE;
e4d6b795
MB		 1995
1996 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1997 & 0x0001DC00;
1998 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1999 & 0x0000DC00;
2000 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2001 & 0x0000DC00;
2002 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2003 & 0x0001DC00;
2004 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2005 & 0x0000DC00;
13790728 2006/* Unused ring
e4d6b795
MB		 2007 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2008 & 0x0000DC00;
13790728 2009*/
e4d6b795 2010
36dbd954
MB		 2011 /* ACK the interrupt. */
2012 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2013 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2014 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2015 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2016 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2017 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2018/* Unused ring
2019 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2020*/
2021
2022 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 2023 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 2024 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 2025 dev->irq_reason = reason;
36dbd954
MB		 2026
2027 return IRQ_WAKE_THREAD;
2028}
2029
2030/* Interrupt handler top-half. This runs with interrupts disabled. */
2031static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2032{
2033 struct b43_wldev *dev = dev_id;
2034 irqreturn_t ret;
2035
2036 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2037 return IRQ_NONE;
2038
2039 spin_lock(&dev->wl->hardirq_lock);
2040 ret = b43_do_interrupt(dev);
e4d6b795 2041 mmiowb();
36dbd954 2042 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 2043
2044 return ret;
2045}
2046
3dbba8e2
AH		 2047/* SDIO interrupt handler. This runs in process context. */
2048static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2049{
2050 struct b43_wl *wl = dev->wl;
3dbba8e2
AH		 2051 irqreturn_t ret;
2052
3dbba8e2 2053 mutex_lock(&wl->mutex);
3dbba8e2
AH		 2054
2055 ret = b43_do_interrupt(dev);
2056 if (ret == IRQ_WAKE_THREAD)
2057 b43_do_interrupt_thread(dev);
2058
3dbba8e2
AH		 2059 mutex_unlock(&wl->mutex);
2060}
2061
1a9f5093 2062void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 2063{
2064 release_firmware(fw->data);
2065 fw->data = NULL;
2066 fw->filename = NULL;
2067}
2068
e4d6b795
MB		 2069static void b43_release_firmware(struct b43_wldev *dev)
2070{
1a9f5093
MB		 2071 b43_do_release_fw(&dev->fw.ucode);
2072 b43_do_release_fw(&dev->fw.pcm);
2073 b43_do_release_fw(&dev->fw.initvals);
2074 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 2075}
2076
eb189d8b 2077static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 2078{
fc68ed4f
HE		 2079 const char text[] =
2080 "You must go to " \
2081 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2082 "and download the correct firmware for this driver version. " \
2083 "Please carefully read all instructions on this website.\n";
eb189d8b 2084
eb189d8b
MB		 2085 if (error)
2086 b43err(wl, text);
2087 else
2088 b43warn(wl, text);
e4d6b795
MB		 2089}
2090
1a9f5093
MB		 2091int b43_do_request_fw(struct b43_request_fw_context *ctx,
2092 const char *name,
2093 struct b43_firmware_file *fw)
e4d6b795 2094{
61cb5dd6 2095 const struct firmware *blob;
e4d6b795
MB		 2096 struct b43_fw_header *hdr;
2097 u32 size;
2098 int err;
2099
61cb5dd6
MB		 2100 if (!name) {
2101 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 2102 /* FIXME: We should probably keep it anyway, to save some headache
2103 * on suspend/resume with multiband devices. */
2104 b43_do_release_fw(fw);
e4d6b795 2105 return 0;
61cb5dd6
MB		 2106 }
2107 if (fw->filename) {
1a9f5093
MB		 2108 if ((fw->type == ctx->req_type) &&
2109 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 2110 return 0; /* Already have this fw. */
2111 /* Free the cached firmware first. */
1a9f5093
MB		 2112 /* FIXME: We should probably do this later after we successfully
2113 * got the new fw. This could reduce headache with multiband devices.
2114 * We could also redesign this to cache the firmware for all possible
2115 * bands all the time. */
2116 b43_do_release_fw(fw);
61cb5dd6 2117 }
e4d6b795 2118
1a9f5093
MB		 2119 switch (ctx->req_type) {
2120 case B43_FWTYPE_PROPRIETARY:
2121 snprintf(ctx->fwname, sizeof(ctx->fwname),
2122 "b43%s/%s.fw",
2123 modparam_fwpostfix, name);
2124 break;
2125 case B43_FWTYPE_OPENSOURCE:
2126 snprintf(ctx->fwname, sizeof(ctx->fwname),
2127 "b43-open%s/%s.fw",
2128 modparam_fwpostfix, name);
2129 break;
2130 default:
2131 B43_WARN_ON(1);
2132 return -ENOSYS;
2133 }
a18c715e 2134 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 2135 if (err == -ENOENT) {
1a9f5093
MB		 2136 snprintf(ctx->errors[ctx->req_type],
2137 sizeof(ctx->errors[ctx->req_type]),
2138 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 2139 return err;
2140 } else if (err) {
1a9f5093
MB		 2141 snprintf(ctx->errors[ctx->req_type],
2142 sizeof(ctx->errors[ctx->req_type]),
2143 "Firmware file \"%s\" request failed (err=%d)\n",
2144 ctx->fwname, err);
e4d6b795
MB		 2145 return err;
2146 }
61cb5dd6 2147 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2148 goto err_format;
61cb5dd6 2149 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2150 switch (hdr->type) {
2151 case B43_FW_TYPE_UCODE:
2152 case B43_FW_TYPE_PCM:
2153 size = be32_to_cpu(hdr->size);
61cb5dd6 2154 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2155 goto err_format;
2156 /* fallthrough */
2157 case B43_FW_TYPE_IV:
2158 if (hdr->ver != 1)
2159 goto err_format;
2160 break;
2161 default:
2162 goto err_format;
2163 }
2164
61cb5dd6
MB		 2165 fw->data = blob;
2166 fw->filename = name;
1a9f5093 2167 fw->type = ctx->req_type;
61cb5dd6
MB		 2168
2169 return 0;
e4d6b795
MB		 2170
2171err_format:
1a9f5093
MB		 2172 snprintf(ctx->errors[ctx->req_type],
2173 sizeof(ctx->errors[ctx->req_type]),
2174 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2175 release_firmware(blob);
2176
e4d6b795
MB		 2177 return -EPROTO;
2178}
2179
1a9f5093 2180static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2181{
1a9f5093
MB		 2182 struct b43_wldev *dev = ctx->dev;
2183 struct b43_firmware *fw = &ctx->dev->fw;
21d889d4 2184 const u8 rev = ctx->dev->dev->core_rev;
e4d6b795
MB		 2185 const char *filename;
2186 u32 tmshigh;
2187 int err;
2188
8b9bda75
RM		 2189 /* Files for HT and LCN were found by trying one by one */
2190
61cb5dd6 2191 /* Get microcode */
6ff1e5cf 2192 if ((rev >= 5) && (rev <= 10)) {
61cb5dd6 2193 filename = "ucode5";
6ff1e5cf 2194 } else if ((rev >= 11) && (rev <= 12)) {
61cb5dd6 2195 filename = "ucode11";
6ff1e5cf 2196 } else if (rev == 13) {
61cb5dd6 2197 filename = "ucode13";
6ff1e5cf 2198 } else if (rev == 14) {
759b973b 2199 filename = "ucode14";
6ff1e5cf 2200 } else if (rev == 15) {
759b973b 2201 filename = "ucode15";
6ff1e5cf
RM		 2202 } else {
2203 switch (dev->phy.type) {
2204 case B43_PHYTYPE_N:
2205 if (rev >= 16)
2206 filename = "ucode16_mimo";
2207 else
2208 goto err_no_ucode;
2209 break;
8b9bda75
RM		 2210 case B43_PHYTYPE_HT:
2211 if (rev == 29)
2212 filename = "ucode29_mimo";
2213 else
2214 goto err_no_ucode;
2215 break;
2216 case B43_PHYTYPE_LCN:
2217 if (rev == 24)
2218 filename = "ucode24_mimo";
2219 else
2220 goto err_no_ucode;
2221 break;
6ff1e5cf
RM		 2222 default:
2223 goto err_no_ucode;
2224 }
2225 }
1a9f5093 2226 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2227 if (err)
2228 goto err_load;
2229
2230 /* Get PCM code */
2231 if ((rev >= 5) && (rev <= 10))
2232 filename = "pcm5";
2233 else if (rev >= 11)
2234 filename = NULL;
2235 else
2236 goto err_no_pcm;
3db1cd5c 2237 fw->pcm_request_failed = false;
1a9f5093 2238 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2239 if (err == -ENOENT) {
2240 /* We did not find a PCM file? Not fatal, but
2241 * core rev <= 10 must do without hwcrypto then. */
3db1cd5c 2242 fw->pcm_request_failed = true;
68217832 2243 } else if (err)
61cb5dd6
MB		 2244 goto err_load;
2245
2246 /* Get initvals */
2247 switch (dev->phy.type) {
2248 case B43_PHYTYPE_A:
2249 if ((rev >= 5) && (rev <= 10)) {
d48ae5c8 2250 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
61cb5dd6
MB		 2251 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2252 filename = "a0g1initvals5";
2253 else
2254 filename = "a0g0initvals5";
2255 } else
2256 goto err_no_initvals;
2257 break;
2258 case B43_PHYTYPE_G:
e4d6b795 2259 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2260 filename = "b0g0initvals5";
e4d6b795 2261 else if (rev >= 13)
e9304882 2262 filename = "b0g0initvals13";
e4d6b795 2263 else
61cb5dd6
MB		 2264 goto err_no_initvals;
2265 break;
2266 case B43_PHYTYPE_N:
e41596a1
RM		 2267 if (rev >= 16)
2268 filename = "n0initvals16";
2269 else if ((rev >= 11) && (rev <= 12))
61cb5dd6
MB		 2270 filename = "n0initvals11";
2271 else
2272 goto err_no_initvals;
2273 break;
759b973b
GS		 2274 case B43_PHYTYPE_LP:
2275 if (rev == 13)
2276 filename = "lp0initvals13";
2277 else if (rev == 14)
2278 filename = "lp0initvals14";
2279 else if (rev >= 15)
2280 filename = "lp0initvals15";
2281 else
2282 goto err_no_initvals;
2283 break;
8b9bda75
RM		 2284 case B43_PHYTYPE_HT:
2285 if (rev == 29)
2286 filename = "ht0initvals29";
2287 else
2288 goto err_no_initvals;
2289 break;
2290 case B43_PHYTYPE_LCN:
2291 if (rev == 24)
2292 filename = "lcn0initvals24";
2293 else
2294 goto err_no_initvals;
2295 break;
61cb5dd6
MB		 2296 default:
2297 goto err_no_initvals;
e4d6b795 2298 }
1a9f5093 2299 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2300 if (err)
2301 goto err_load;
2302
2303 /* Get bandswitch initvals */
2304 switch (dev->phy.type) {
2305 case B43_PHYTYPE_A:
2306 if ((rev >= 5) && (rev <= 10)) {
d48ae5c8 2307 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
61cb5dd6
MB		 2308 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2309 filename = "a0g1bsinitvals5";
2310 else
2311 filename = "a0g0bsinitvals5";
2312 } else if (rev >= 11)
2313 filename = NULL;
2314 else
2315 goto err_no_initvals;
2316 break;
2317 case B43_PHYTYPE_G:
e4d6b795 2318 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2319 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2320 else if (rev >= 11)
2321 filename = NULL;
2322 else
e4d6b795 2323 goto err_no_initvals;
61cb5dd6
MB		 2324 break;
2325 case B43_PHYTYPE_N:
e41596a1
RM		 2326 if (rev >= 16)
2327 filename = "n0bsinitvals16";
2328 else if ((rev >= 11) && (rev <= 12))
61cb5dd6
MB		 2329 filename = "n0bsinitvals11";
2330 else
e4d6b795 2331 goto err_no_initvals;
61cb5dd6 2332 break;
759b973b
GS		 2333 case B43_PHYTYPE_LP:
2334 if (rev == 13)
2335 filename = "lp0bsinitvals13";
2336 else if (rev == 14)
2337 filename = "lp0bsinitvals14";
2338 else if (rev >= 15)
2339 filename = "lp0bsinitvals15";
2340 else
2341 goto err_no_initvals;
2342 break;
8b9bda75
RM		 2343 case B43_PHYTYPE_HT:
2344 if (rev == 29)
2345 filename = "ht0bsinitvals29";
2346 else
2347 goto err_no_initvals;
2348 break;
2349 case B43_PHYTYPE_LCN:
2350 if (rev == 24)
2351 filename = "lcn0bsinitvals24";
2352 else
2353 goto err_no_initvals;
2354 break;
61cb5dd6
MB		 2355 default:
2356 goto err_no_initvals;
e4d6b795 2357 }
1a9f5093 2358 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2359 if (err)
2360 goto err_load;
e4d6b795
MB		 2361
2362 return 0;
2363
e4d6b795 2364err_no_ucode:
1a9f5093
MB		 2365 err = ctx->fatal_failure = -EOPNOTSUPP;
2366 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2367 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2368 goto error;
2369
2370err_no_pcm:
1a9f5093
MB		 2371 err = ctx->fatal_failure = -EOPNOTSUPP;
2372 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2373 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2374 goto error;
2375
2376err_no_initvals:
1a9f5093
MB		 2377 err = ctx->fatal_failure = -EOPNOTSUPP;
2378 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2379 "is required for your device (wl-core rev %u)\n", rev);
2380 goto error;
2381
2382err_load:
2383 /* We failed to load this firmware image. The error message
2384 * already is in ctx->errors. Return and let our caller decide
2385 * what to do. */
e4d6b795
MB		 2386 goto error;
2387
2388error:
2389 b43_release_firmware(dev);
2390 return err;
2391}
2392
6b6fa586
LF		 2393static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2394static void b43_one_core_detach(struct b43_bus_dev *dev);
2395
2396static void b43_request_firmware(struct work_struct *work)
1a9f5093 2397{
6b6fa586
LF		 2398 struct b43_wl *wl = container_of(work,
2399 struct b43_wl, firmware_load);
2400 struct b43_wldev *dev = wl->current_dev;
1a9f5093
MB		 2401 struct b43_request_fw_context *ctx;
2402 unsigned int i;
2403 int err;
2404 const char *errmsg;
2405
2406 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2407 if (!ctx)
6b6fa586 2408 return;
1a9f5093
MB		 2409 ctx->dev = dev;
2410
2411 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2412 err = b43_try_request_fw(ctx);
2413 if (!err)
6b6fa586
LF		 2414 goto start_ieee80211; /* Successfully loaded it. */
2415 /* Was fw version known? */
2416 if (ctx->fatal_failure)
1a9f5093
MB		 2417 goto out;
2418
6b6fa586 2419 /* proprietary fw not found, try open source */
1a9f5093
MB		 2420 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2421 err = b43_try_request_fw(ctx);
2422 if (!err)
6b6fa586
LF		 2423 goto start_ieee80211; /* Successfully loaded it. */
2424 if(ctx->fatal_failure)
1a9f5093
MB		 2425 goto out;
2426
2427 /* Could not find a usable firmware. Print the errors. */
2428 for (i = 0; i < B43_NR_FWTYPES; i++) {
2429 errmsg = ctx->errors[i];
2430 if (strlen(errmsg))
2431 b43err(dev->wl, errmsg);
2432 }
2433 b43_print_fw_helptext(dev->wl, 1);
6b6fa586
LF		 2434 goto out;
2435
2436start_ieee80211:
2437 err = ieee80211_register_hw(wl->hw);
2438 if (err)
2439 goto err_one_core_detach;
e64add27 2440 wl->hw_registred = true;
6b6fa586
LF		 2441 b43_leds_register(wl->current_dev);
2442 goto out;
2443
2444err_one_core_detach:
2445 b43_one_core_detach(dev->dev);
1a9f5093
MB		 2446
2447out:
2448 kfree(ctx);
1a9f5093
MB		 2449}
2450
e4d6b795
MB		 2451static int b43_upload_microcode(struct b43_wldev *dev)
2452{
652caa5b 2453 struct wiphy *wiphy = dev->wl->hw->wiphy;
e4d6b795
MB		 2454 const size_t hdr_len = sizeof(struct b43_fw_header);
2455 const __be32 *data;
2456 unsigned int i, len;
2457 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2458 u32 tmp, macctl;
e4d6b795
MB		 2459 int err = 0;
2460
1f7d87b0
MB		 2461 /* Jump the microcode PSM to offset 0 */
2462 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2463 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2464 macctl |= B43_MACCTL_PSM_JMP0;
2465 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2466 /* Zero out all microcode PSM registers and shared memory. */
2467 for (i = 0; i < 64; i++)
2468 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2469 for (i = 0; i < 4096; i += 2)
2470 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2471
e4d6b795 2472 /* Upload Microcode. */
61cb5dd6
MB		 2473 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2474 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2475 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2476 for (i = 0; i < len; i++) {
2477 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2478 udelay(10);
2479 }
2480
61cb5dd6 2481 if (dev->fw.pcm.data) {
e4d6b795 2482 /* Upload PCM data. */
61cb5dd6
MB		 2483 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2484 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2485 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2486 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2487 /* No need for autoinc bit in SHM_HW */
2488 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2489 for (i = 0; i < len; i++) {
2490 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2491 udelay(10);
2492 }
2493 }
2494
2495 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2496
2497 /* Start the microcode PSM */
5056635c
RM		 2498 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2499 B43_MACCTL_PSM_RUN);
e4d6b795
MB		 2500
2501 /* Wait for the microcode to load and respond */
2502 i = 0;
2503 while (1) {
2504 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2505 if (tmp == B43_IRQ_MAC_SUSPENDED)
2506 break;
2507 i++;
1f7d87b0 2508 if (i >= 20) {
e4d6b795 2509 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2510 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2511 err = -ENODEV;
1f7d87b0
MB		 2512 goto error;
2513 }
e175e996 2514 msleep(50);
e4d6b795
MB		 2515 }
2516 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2517
2518 /* Get and check the revisions. */
2519 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2520 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2521 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2522 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2523
2524 if (fwrev <= 0x128) {
2525 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2526 "binary drivers older than version 4.x is unsupported. "
2527 "You must upgrade your firmware files.\n");
eb189d8b 2528 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2529 err = -EOPNOTSUPP;
1f7d87b0 2530 goto error;
e4d6b795 2531 }
e4d6b795
MB		 2532 dev->fw.rev = fwrev;
2533 dev->fw.patch = fwpatch;
5d852905
RM		 2534 if (dev->fw.rev >= 598)
2535 dev->fw.hdr_format = B43_FW_HDR_598;
2536 else if (dev->fw.rev >= 410)
efe0249b
RM		 2537 dev->fw.hdr_format = B43_FW_HDR_410;
2538 else
2539 dev->fw.hdr_format = B43_FW_HDR_351;
e48b0eeb
MB		 2540 dev->fw.opensource = (fwdate == 0xFFFF);
2541
403a3a13
MB		 2542 /* Default to use-all-queues. */
2543 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2544 dev->qos_enabled = !!modparam_qos;
2545 /* Default to firmware/hardware crypto acceleration. */
3db1cd5c 2546 dev->hwcrypto_enabled = true;
403a3a13 2547
e48b0eeb 2548 if (dev->fw.opensource) {
403a3a13
MB		 2549 u16 fwcapa;
2550
e48b0eeb
MB		 2551 /* Patchlevel info is encoded in the "time" field. */
2552 dev->fw.patch = fwtime;
403a3a13
MB		 2553 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2554 dev->fw.rev, dev->fw.patch);
2555
2556 fwcapa = b43_fwcapa_read(dev);
2557 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2558 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2559 /* Disable hardware crypto and fall back to software crypto. */
3db1cd5c 2560 dev->hwcrypto_enabled = false;
403a3a13
MB		 2561 }
2562 if (!(fwcapa & B43_FWCAPA_QOS)) {
2563 b43info(dev->wl, "QoS not supported by firmware\n");
2564 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2565 * ieee80211_unregister to make sure the networking core can
2566 * properly free possible resources. */
2567 dev->wl->hw->queues = 1;
3db1cd5c 2568 dev->qos_enabled = false;
403a3a13 2569 }
e48b0eeb
MB		 2570 } else {
2571 b43info(dev->wl, "Loading firmware version %u.%u "
2572 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2573 fwrev, fwpatch,
2574 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2575 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2576 if (dev->fw.pcm_request_failed) {
2577 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2578 "Hardware accelerated cryptography is disabled.\n");
2579 b43_print_fw_helptext(dev->wl, 0);
2580 }
e48b0eeb 2581 }
e4d6b795 2582
652caa5b
JL		 2583 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2584 dev->fw.rev, dev->fw.patch);
21d889d4 2585 wiphy->hw_version = dev->dev->core_id;
652caa5b 2586
efe0249b 2587 if (dev->fw.hdr_format == B43_FW_HDR_351) {
c557289c
MB		 2588 /* We're over the deadline, but we keep support for old fw
2589 * until it turns out to be in major conflict with something new. */
eb189d8b 2590 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2591 "Support for old firmware will be removed soon "
2592 "(official deadline was July 2008).\n");
eb189d8b
MB		 2593 b43_print_fw_helptext(dev->wl, 0);
2594 }
2595
1f7d87b0
MB		 2596 return 0;
2597
2598error:
5056635c
RM		 2599 /* Stop the microcode PSM. */
2600 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2601 B43_MACCTL_PSM_JMP0);
1f7d87b0 2602
e4d6b795
MB		 2603 return err;
2604}
2605
2606static int b43_write_initvals(struct b43_wldev *dev,
2607 const struct b43_iv *ivals,
2608 size_t count,
2609 size_t array_size)
2610{
2611 const struct b43_iv *iv;
2612 u16 offset;
2613 size_t i;
2614 bool bit32;
2615
2616 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2617 iv = ivals;
2618 for (i = 0; i < count; i++) {
2619 if (array_size < sizeof(iv->offset_size))
2620 goto err_format;
2621 array_size -= sizeof(iv->offset_size);
2622 offset = be16_to_cpu(iv->offset_size);
2623 bit32 = !!(offset & B43_IV_32BIT);
2624 offset &= B43_IV_OFFSET_MASK;
2625 if (offset >= 0x1000)
2626 goto err_format;
2627 if (bit32) {
2628 u32 value;
2629
2630 if (array_size < sizeof(iv->data.d32))
2631 goto err_format;
2632 array_size -= sizeof(iv->data.d32);
2633
533dd1b0 2634 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2635 b43_write32(dev, offset, value);
2636
2637 iv = (const struct b43_iv *)((const uint8_t *)iv +
2638 sizeof(__be16) +
2639 sizeof(__be32));
2640 } else {
2641 u16 value;
2642
2643 if (array_size < sizeof(iv->data.d16))
2644 goto err_format;
2645 array_size -= sizeof(iv->data.d16);
2646
2647 value = be16_to_cpu(iv->data.d16);
2648 b43_write16(dev, offset, value);
2649
2650 iv = (const struct b43_iv *)((const uint8_t *)iv +
2651 sizeof(__be16) +
2652 sizeof(__be16));
2653 }
2654 }
2655 if (array_size)
2656 goto err_format;
2657
2658 return 0;
2659
2660err_format:
2661 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2662 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2663
2664 return -EPROTO;
2665}
2666
2667static int b43_upload_initvals(struct b43_wldev *dev)
2668{
2669 const size_t hdr_len = sizeof(struct b43_fw_header);
2670 const struct b43_fw_header *hdr;
2671 struct b43_firmware *fw = &dev->fw;
2672 const struct b43_iv *ivals;
2673 size_t count;
2674 int err;
2675
61cb5dd6
MB		 2676 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2677 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2678 count = be32_to_cpu(hdr->size);
2679 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2680 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2681 if (err)
2682 goto out;
61cb5dd6
MB		 2683 if (fw->initvals_band.data) {
2684 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2685 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2686 count = be32_to_cpu(hdr->size);
2687 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2688 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2689 if (err)
2690 goto out;
2691 }
2692out:
2693
2694 return err;
2695}
2696
2697/* Initialize the GPIOs
2698 * http://bcm-specs.sipsolutions.net/GPIO
2699 */
c4a2a081 2700static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
e4d6b795 2701{
d48ae5c8 2702 struct ssb_bus *bus = dev->dev->sdev->bus;
c4a2a081
RM		 2703
2704#ifdef CONFIG_SSB_DRIVER_PCICORE
2705 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2706#else
2707 return bus->chipco.dev;
2708#endif
2709}
2710
e4d6b795
MB		 2711static int b43_gpio_init(struct b43_wldev *dev)
2712{
c4a2a081 2713 struct ssb_device *gpiodev;
e4d6b795
MB		 2714 u32 mask, set;
2715
5056635c
RM		 2716 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2717 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
e4d6b795
MB		 2718
2719 mask = 0x0000001F;
2720 set = 0x0000000F;
c244e08c 2721 if (dev->dev->chip_id == 0x4301) {
e4d6b795
MB		 2722 mask |= 0x0060;
2723 set |= 0x0060;
2724 }
58098021
HM		 2725 if (dev->dev->chip_id == 0x5354)
2726 set &= 0xff02;
e4d6b795
MB		 2727 if (0 /* FIXME: conditional unknown */ ) {
2728 b43_write16(dev, B43_MMIO_GPIO_MASK,
2729 b43_read16(dev, B43_MMIO_GPIO_MASK)
2730 | 0x0100);
2731 mask |= 0x0180;
2732 set |= 0x0180;
2733 }
0581483a 2734 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2735 b43_write16(dev, B43_MMIO_GPIO_MASK,
2736 b43_read16(dev, B43_MMIO_GPIO_MASK)
2737 | 0x0200);
2738 mask |= 0x0200;
2739 set |= 0x0200;
2740 }
21d889d4 2741 if (dev->dev->core_rev >= 2)
e4d6b795
MB		 2742 mask |= 0x0010; /* FIXME: This is redundant. */
2743
6cbab0d9 2744 switch (dev->dev->bus_type) {
42c9a458
RM		 2745#ifdef CONFIG_B43_BCMA
2746 case B43_BUS_BCMA:
2747 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2748 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2749 BCMA_CC_GPIOCTL) & mask) | set);
2750 break;
2751#endif
6cbab0d9
RM		 2752#ifdef CONFIG_B43_SSB
2753 case B43_BUS_SSB:
2754 gpiodev = b43_ssb_gpio_dev(dev);
2755 if (gpiodev)
2756 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2757 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2758 & mask) | set);
2759 break;
2760#endif
2761 }
e4d6b795
MB		 2762
2763 return 0;
2764}
2765
2766/* Turn off all GPIO stuff. Call this on module unload, for example. */
2767static void b43_gpio_cleanup(struct b43_wldev *dev)
2768{
c4a2a081 2769 struct ssb_device *gpiodev;
e4d6b795 2770
6cbab0d9 2771 switch (dev->dev->bus_type) {
42c9a458
RM		 2772#ifdef CONFIG_B43_BCMA
2773 case B43_BUS_BCMA:
2774 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2775 0);
2776 break;
2777#endif
6cbab0d9
RM		 2778#ifdef CONFIG_B43_SSB
2779 case B43_BUS_SSB:
2780 gpiodev = b43_ssb_gpio_dev(dev);
2781 if (gpiodev)
2782 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2783 break;
2784#endif
2785 }
e4d6b795
MB		 2786}
2787
2788/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2789void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2790{
923fd703
MB		 2791 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2792 u16 fwstate;
2793
2794 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2795 B43_SHM_SH_UCODESTAT);
2796 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2797 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2798 b43err(dev->wl, "b43_mac_enable(): The firmware "
2799 "should be suspended, but current state is %u\n",
2800 fwstate);
2801 }
2802 }
2803
e4d6b795
MB		 2804 dev->mac_suspended--;
2805 B43_WARN_ON(dev->mac_suspended < 0);
2806 if (dev->mac_suspended == 0) {
5056635c 2807 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
e4d6b795
MB		 2808 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2809 B43_IRQ_MAC_SUSPENDED);
2810 /* Commit writes */
2811 b43_read32(dev, B43_MMIO_MACCTL);
2812 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2813 b43_power_saving_ctl_bits(dev, 0);
2814 }
2815}
2816
2817/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2818void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2819{
2820 int i;
2821 u32 tmp;
2822
05b64b36 2823 might_sleep();
e4d6b795 2824 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2825
e4d6b795
MB		 2826 if (dev->mac_suspended == 0) {
2827 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
5056635c 2828 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
e4d6b795
MB		 2829 /* force pci to flush the write */
2830 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2831 for (i = 35; i; i--) {
2832 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2833 if (tmp & B43_IRQ_MAC_SUSPENDED)
2834 goto out;
2835 udelay(10);
2836 }
2837 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2838 for (i = 40; i; i--) {
e4d6b795
MB		 2839 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2840 if (tmp & B43_IRQ_MAC_SUSPENDED)
2841 goto out;
05b64b36 2842 msleep(1);
e4d6b795
MB		 2843 }
2844 b43err(dev->wl, "MAC suspend failed\n");
2845 }
05b64b36 2846out:
e4d6b795
MB		 2847 dev->mac_suspended++;
2848}
2849
858a1652
RM		 2850/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2851void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2852{
6cbab0d9
RM		 2853 u32 tmp;
2854
2855 switch (dev->dev->bus_type) {
42c9a458
RM		 2856#ifdef CONFIG_B43_BCMA
2857 case B43_BUS_BCMA:
36677874 2858 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
42c9a458
RM		 2859 if (on)
2860 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2861 else
2862 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
36677874 2863 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
42c9a458
RM		 2864 break;
2865#endif
6cbab0d9
RM		 2866#ifdef CONFIG_B43_SSB
2867 case B43_BUS_SSB:
2868 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2869 if (on)
2870 tmp |= B43_TMSLOW_MACPHYCLKEN;
2871 else
2872 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2873 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2874 break;
2875#endif
2876 }
858a1652
RM		 2877}
2878
e4d6b795
MB		 2879static void b43_adjust_opmode(struct b43_wldev *dev)
2880{
2881 struct b43_wl *wl = dev->wl;
2882 u32 ctl;
2883 u16 cfp_pretbtt;
2884
2885 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2886 /* Reset status to STA infrastructure mode. */
2887 ctl &= ~B43_MACCTL_AP;
2888 ctl &= ~B43_MACCTL_KEEP_CTL;
2889 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2890 ctl &= ~B43_MACCTL_KEEP_BAD;
2891 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2892 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2893 ctl |= B43_MACCTL_INFRA;
2894
05c914fe
JB		 2895 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2896 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2897 ctl |= B43_MACCTL_AP;
05c914fe 2898 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2899 ctl &= ~B43_MACCTL_INFRA;
2900
2901 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2902 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2903 if (wl->filter_flags & FIF_FCSFAIL)
2904 ctl |= B43_MACCTL_KEEP_BAD;
2905 if (wl->filter_flags & FIF_PLCPFAIL)
2906 ctl |= B43_MACCTL_KEEP_BADPLCP;
2907 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2908 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2909 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2910 ctl |= B43_MACCTL_BEACPROMISC;
2911
e4d6b795
MB		 2912 /* Workaround: On old hardware the HW-MAC-address-filter
2913 * doesn't work properly, so always run promisc in filter
2914 * it in software. */
21d889d4 2915 if (dev->dev->core_rev <= 4)
e4d6b795
MB		 2916 ctl |= B43_MACCTL_PROMISC;
2917
2918 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2919
2920 cfp_pretbtt = 2;
2921 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
c244e08c
RM		 2922 if (dev->dev->chip_id == 0x4306 &&
2923 dev->dev->chip_rev == 3)
e4d6b795
MB		 2924 cfp_pretbtt = 100;
2925 else
2926 cfp_pretbtt = 50;
2927 }
2928 b43_write16(dev, 0x612, cfp_pretbtt);
09ebe2f9
MB		 2929
2930 /* FIXME: We don't currently implement the PMQ mechanism,
2931 * so always disable it. If we want to implement PMQ,
2932 * we need to enable it here (clear DISCPMQ) in AP mode.
2933 */
5056635c
RM		 2934 if (0 /* ctl & B43_MACCTL_AP */)
2935 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
2936 else
2937 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
e4d6b795
MB		 2938}
2939
2940static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2941{
2942 u16 offset;
2943
2944 if (is_ofdm) {
2945 offset = 0x480;
2946 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2947 } else {
2948 offset = 0x4C0;
2949 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2950 }
2951 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2952 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2953}
2954
2955static void b43_rate_memory_init(struct b43_wldev *dev)
2956{
2957 switch (dev->phy.type) {
2958 case B43_PHYTYPE_A:
2959 case B43_PHYTYPE_G:
53a6e234 2960 case B43_PHYTYPE_N:
9d86a2d5 2961 case B43_PHYTYPE_LP:
6a461c23 2962 case B43_PHYTYPE_HT:
0b4ff45d 2963 case B43_PHYTYPE_LCN:
e4d6b795
MB		 2964 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2965 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2966 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2967 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2968 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2969 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2970 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2971 if (dev->phy.type == B43_PHYTYPE_A)
2972 break;
2973 /* fallthrough */
2974 case B43_PHYTYPE_B:
2975 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2976 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2977 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2978 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2979 break;
2980 default:
2981 B43_WARN_ON(1);
2982 }
2983}
2984
5042c507
MB		 2985/* Set the default values for the PHY TX Control Words. */
2986static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2987{
2988 u16 ctl = 0;
2989
2990 ctl |= B43_TXH_PHY_ENC_CCK;
2991 ctl |= B43_TXH_PHY_ANT01AUTO;
2992 ctl |= B43_TXH_PHY_TXPWR;
2993
2994 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2995 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2996 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2997}
2998
e4d6b795
MB		 2999/* Set the TX-Antenna for management frames sent by firmware. */
3000static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3001{
5042c507 3002 u16 ant;
e4d6b795
MB		 3003 u16 tmp;
3004
5042c507 3005 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 3006
e4d6b795
MB		 3007 /* For ACK/CTS */
3008 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 3009 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3010 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3011 /* For Probe Resposes */
3012 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 3013 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3014 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3015}
3016
3017/* This is the opposite of b43_chip_init() */
3018static void b43_chip_exit(struct b43_wldev *dev)
3019{
fb11137a 3020 b43_phy_exit(dev);
e4d6b795
MB		 3021 b43_gpio_cleanup(dev);
3022 /* firmware is released later */
3023}
3024
3025/* Initialize the chip
3026 * http://bcm-specs.sipsolutions.net/ChipInit
3027 */
3028static int b43_chip_init(struct b43_wldev *dev)
3029{
3030 struct b43_phy *phy = &dev->phy;
ef1a628d 3031 int err;
858a1652 3032 u32 macctl;
e4d6b795
MB		 3033 u16 value16;
3034
1f7d87b0
MB		 3035 /* Initialize the MAC control */
3036 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3037 if (dev->phy.gmode)
3038 macctl |= B43_MACCTL_GMODE;
3039 macctl |= B43_MACCTL_INFRA;
3040 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795 3041
e4d6b795
MB		 3042 err = b43_upload_microcode(dev);
3043 if (err)
3044 goto out; /* firmware is released later */
3045
3046 err = b43_gpio_init(dev);
3047 if (err)
3048 goto out; /* firmware is released later */
21954c36 3049
e4d6b795
MB		 3050 err = b43_upload_initvals(dev);
3051 if (err)
1a8d1227 3052 goto err_gpio_clean;
e4d6b795 3053
0b7dcd96
MB		 3054 /* Turn the Analog on and initialize the PHY. */
3055 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 3056 err = b43_phy_init(dev);
3057 if (err)
ef1a628d 3058 goto err_gpio_clean;
e4d6b795 3059
ef1a628d
MB		 3060 /* Disable Interference Mitigation. */
3061 if (phy->ops->interf_mitigation)
3062 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 3063
ef1a628d
MB		 3064 /* Select the antennae */
3065 if (phy->ops->set_rx_antenna)
3066 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 3067 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3068
3069 if (phy->type == B43_PHYTYPE_B) {
3070 value16 = b43_read16(dev, 0x005E);
3071 value16 |= 0x0004;
3072 b43_write16(dev, 0x005E, value16);
3073 }
3074 b43_write32(dev, 0x0100, 0x01000000);
21d889d4 3075 if (dev->dev->core_rev < 5)
e4d6b795
MB		 3076 b43_write32(dev, 0x010C, 0x01000000);
3077
5056635c
RM		 3078 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3079 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
e4d6b795 3080
e4d6b795
MB		 3081 /* Probe Response Timeout value */
3082 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3083 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3084
3085 /* Initially set the wireless operation mode. */
3086 b43_adjust_opmode(dev);
3087
21d889d4 3088 if (dev->dev->core_rev < 3) {
e4d6b795
MB		 3089 b43_write16(dev, 0x060E, 0x0000);
3090 b43_write16(dev, 0x0610, 0x8000);
3091 b43_write16(dev, 0x0604, 0x0000);
3092 b43_write16(dev, 0x0606, 0x0200);
3093 } else {
3094 b43_write32(dev, 0x0188, 0x80000000);
3095 b43_write32(dev, 0x018C, 0x02000000);
3096 }
3097 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3098 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3099 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3100 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3101 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3102 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3103 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3104
858a1652 3105 b43_mac_phy_clock_set(dev, true);
e4d6b795 3106
6cbab0d9 3107 switch (dev->dev->bus_type) {
42c9a458
RM		 3108#ifdef CONFIG_B43_BCMA
3109 case B43_BUS_BCMA:
3110 /* FIXME: 0xE74 is quite common, but should be read from CC */
3111 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3112 break;
3113#endif
6cbab0d9
RM		 3114#ifdef CONFIG_B43_SSB
3115 case B43_BUS_SSB:
3116 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3117 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3118 break;
3119#endif
3120 }
e4d6b795
MB		 3121
3122 err = 0;
3123 b43dbg(dev->wl, "Chip initialized\n");
21954c36 3124out:
e4d6b795
MB		 3125 return err;
3126
1a8d1227 3127err_gpio_clean:
e4d6b795 3128 b43_gpio_cleanup(dev);
21954c36 3129 return err;
e4d6b795
MB		 3130}
3131
e4d6b795
MB		 3132static void b43_periodic_every60sec(struct b43_wldev *dev)
3133{
ef1a628d 3134 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 3135
ef1a628d
MB		 3136 if (ops->pwork_60sec)
3137 ops->pwork_60sec(dev);
18c8adeb
MB		 3138
3139 /* Force check the TX power emission now. */
3140 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 3141}
3142
3143static void b43_periodic_every30sec(struct b43_wldev *dev)
3144{
3145 /* Update device statistics. */
3146 b43_calculate_link_quality(dev);
3147}
3148
3149static void b43_periodic_every15sec(struct b43_wldev *dev)
3150{
3151 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 3152 u16 wdr;
3153
3154 if (dev->fw.opensource) {
3155 /* Check if the firmware is still alive.
3156 * It will reset the watchdog counter to 0 in its idle loop. */
3157 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3158 if (unlikely(wdr)) {
3159 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3160 b43_controller_restart(dev, "Firmware watchdog");
3161 return;
3162 } else {
3163 b43_shm_write16(dev, B43_SHM_SCRATCH,
3164 B43_WATCHDOG_REG, 1);
3165 }
3166 }
e4d6b795 3167
ef1a628d
MB		 3168 if (phy->ops->pwork_15sec)
3169 phy->ops->pwork_15sec(dev);
3170
00e0b8cb
SB		 3171 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3172 wmb();
990b86f4
MB		 3173
3174#if B43_DEBUG
3175 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3176 unsigned int i;
3177
3178 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3179 dev->irq_count / 15,
3180 dev->tx_count / 15,
3181 dev->rx_count / 15);
3182 dev->irq_count = 0;
3183 dev->tx_count = 0;
3184 dev->rx_count = 0;
3185 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3186 if (dev->irq_bit_count[i]) {
3187 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3188 dev->irq_bit_count[i] / 15, i, (1 << i));
3189 dev->irq_bit_count[i] = 0;
3190 }
3191 }
3192 }
3193#endif
e4d6b795
MB		 3194}
3195
e4d6b795
MB		 3196static void do_periodic_work(struct b43_wldev *dev)
3197{
3198 unsigned int state;
3199
3200 state = dev->periodic_state;
42bb4cd5 3201 if (state % 4 == 0)
e4d6b795 3202 b43_periodic_every60sec(dev);
42bb4cd5 3203 if (state % 2 == 0)
e4d6b795 3204 b43_periodic_every30sec(dev);
42bb4cd5 3205 b43_periodic_every15sec(dev);
e4d6b795
MB		 3206}
3207
05b64b36
MB		 3208/* Periodic work locking policy:
3209 * The whole periodic work handler is protected by
3210 * wl->mutex. If another lock is needed somewhere in the
21ae2956 3211 * pwork callchain, it's acquired in-place, where it's needed.
e4d6b795 3212 */
e4d6b795
MB		 3213static void b43_periodic_work_handler(struct work_struct *work)
3214{
05b64b36
MB		 3215 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3216 periodic_work.work);
3217 struct b43_wl *wl = dev->wl;
3218 unsigned long delay;
e4d6b795 3219
05b64b36 3220 mutex_lock(&wl->mutex);
e4d6b795
MB		 3221
3222 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3223 goto out;
3224 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3225 goto out_requeue;
3226
05b64b36 3227 do_periodic_work(dev);
e4d6b795 3228
e4d6b795 3229 dev->periodic_state++;
42bb4cd5 3230out_requeue:
e4d6b795
MB		 3231 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3232 delay = msecs_to_jiffies(50);
3233 else
82cd682d 3234 delay = round_jiffies_relative(HZ * 15);
42935eca 3235 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 3236out:
05b64b36 3237 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3238}
3239
3240static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3241{
3242 struct delayed_work *work = &dev->periodic_work;
3243
3244 dev->periodic_state = 0;
3245 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 3246 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 3247}
3248
f3dd3fcc 3249/* Check if communication with the device works correctly. */
e4d6b795
MB		 3250static int b43_validate_chipaccess(struct b43_wldev *dev)
3251{
f62ae6cd 3252 u32 v, backup0, backup4;
e4d6b795 3253
f62ae6cd
MB		 3254 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3255 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 3256
3257 /* Check for read/write and endianness problems. */
e4d6b795
MB		 3258 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3259 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3260 goto error;
f3dd3fcc
MB		 3261 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3262 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 3263 goto error;
3264
f62ae6cd
MB		 3265 /* Check if unaligned 32bit SHM_SHARED access works properly.
3266 * However, don't bail out on failure, because it's noncritical. */
3267 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3268 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3269 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3270 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3271 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3272 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3273 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3274 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3275 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3276 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3277 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3278 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3279
3280 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3281 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc 3282
21d889d4 3283 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
f3dd3fcc
MB		 3284 /* The 32bit register shadows the two 16bit registers
3285 * with update sideeffects. Validate this. */
3286 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3287 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3288 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3289 goto error;
3290 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3291 goto error;
3292 }
3293 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3294
3295 v = b43_read32(dev, B43_MMIO_MACCTL);
3296 v |= B43_MACCTL_GMODE;
3297 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3298 goto error;
3299
3300 return 0;
f3dd3fcc 3301error:
e4d6b795
MB		 3302 b43err(dev->wl, "Failed to validate the chipaccess\n");
3303 return -ENODEV;
3304}
3305
3306static void b43_security_init(struct b43_wldev *dev)
3307{
e4d6b795
MB		 3308 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3309 /* KTP is a word address, but we address SHM bytewise.
3310 * So multiply by two.
3311 */
3312 dev->ktp *= 2;
66d2d089
MB		 3313 /* Number of RCMTA address slots */
3314 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3315 /* Clear the key memory. */
e4d6b795
MB		 3316 b43_clear_keys(dev);
3317}
3318
616de35d 3319#ifdef CONFIG_B43_HWRNG
99da185a 3320static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3321{
3322 struct b43_wl *wl = (struct b43_wl *)rng->priv;
a78b3bb2
MB		 3323 struct b43_wldev *dev;
3324 int count = -ENODEV;
e4d6b795 3325
a78b3bb2
MB		 3326 mutex_lock(&wl->mutex);
3327 dev = wl->current_dev;
3328 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3329 *data = b43_read16(dev, B43_MMIO_RNG);
3330 count = sizeof(u16);
3331 }
3332 mutex_unlock(&wl->mutex);
e4d6b795 3333
a78b3bb2 3334 return count;
e4d6b795 3335}
616de35d 3336#endif /* CONFIG_B43_HWRNG */
e4d6b795 3337
b844eba2 3338static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3339{
616de35d 3340#ifdef CONFIG_B43_HWRNG
e4d6b795 3341 if (wl->rng_initialized)
b844eba2 3342 hwrng_unregister(&wl->rng);
616de35d 3343#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3344}
3345
3346static int b43_rng_init(struct b43_wl *wl)
3347{
616de35d 3348 int err = 0;
e4d6b795 3349
616de35d 3350#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3351 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3352 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3353 wl->rng.name = wl->rng_name;
3354 wl->rng.data_read = b43_rng_read;
3355 wl->rng.priv = (unsigned long)wl;
3db1cd5c 3356 wl->rng_initialized = true;
e4d6b795
MB		 3357 err = hwrng_register(&wl->rng);
3358 if (err) {
3db1cd5c 3359 wl->rng_initialized = false;
e4d6b795
MB		 3360 b43err(wl, "Failed to register the random "
3361 "number generator (%d)\n", err);
3362 }
616de35d 3363#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3364
3365 return err;
3366}
3367
f5d40eed 3368static void b43_tx_work(struct work_struct *work)
e4d6b795 3369{
f5d40eed
MB		 3370 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3371 struct b43_wldev *dev;
3372 struct sk_buff *skb;
bad69194 3373 int queue_num;
f5d40eed 3374 int err = 0;
e4d6b795 3375
f5d40eed
MB		 3376 mutex_lock(&wl->mutex);
3377 dev = wl->current_dev;
3378 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3379 mutex_unlock(&wl->mutex);
3380 return;
5100d5ac 3381 }
21a75d77 3382
bad69194 3383 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3384 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3385 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3386 if (b43_using_pio_transfers(dev))
3387 err = b43_pio_tx(dev, skb);
3388 else
3389 err = b43_dma_tx(dev, skb);
3390 if (err == -ENOSPC) {
3391 wl->tx_queue_stopped[queue_num] = 1;
3392 ieee80211_stop_queue(wl->hw, queue_num);
3393 skb_queue_head(&wl->tx_queue[queue_num], skb);
3394 break;
3395 }
3396 if (unlikely(err))
3397 dev_kfree_skb(skb); /* Drop it */
3398 err = 0;
3399 }
21a75d77 3400
bad69194 3401 if (!err)
3402 wl->tx_queue_stopped[queue_num] = 0;
21a75d77
MB		 3403 }
3404
990b86f4
MB		 3405#if B43_DEBUG
3406 dev->tx_count++;
3407#endif
f5d40eed
MB		 3408 mutex_unlock(&wl->mutex);
3409}
21a75d77 3410
7bb45683 3411static void b43_op_tx(struct ieee80211_hw *hw,
f5d40eed
MB		 3412 struct sk_buff *skb)
3413{
3414 struct b43_wl *wl = hw_to_b43_wl(hw);
3415
3416 if (unlikely(skb->len < 2 + 2 + 6)) {
3417 /* Too short, this can't be a valid frame. */
3418 dev_kfree_skb_any(skb);
7bb45683 3419 return;
f5d40eed
MB		 3420 }
3421 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3422
bad69194 3423 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3424 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3425 ieee80211_queue_work(wl->hw, &wl->tx_work);
3426 } else {
3427 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3428 }
e4d6b795
MB		 3429}
3430
e6f5b934
MB		 3431static void b43_qos_params_upload(struct b43_wldev *dev,
3432 const struct ieee80211_tx_queue_params *p,
3433 u16 shm_offset)
3434{
3435 u16 params[B43_NR_QOSPARAMS];
0b57664c 3436 int bslots, tmp;
e6f5b934
MB		 3437 unsigned int i;
3438
b0544eb6
MB		 3439 if (!dev->qos_enabled)
3440 return;
3441
0b57664c 3442 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3443
3444 memset(&params, 0, sizeof(params));
3445
3446 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3447 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3448 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3449 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3450 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3451 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3452 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3453
3454 for (i = 0; i < ARRAY_SIZE(params); i++) {
3455 if (i == B43_QOSPARAM_STATUS) {
3456 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3457 shm_offset + (i * 2));
3458 /* Mark the parameters as updated. */
3459 tmp |= 0x100;
3460 b43_shm_write16(dev, B43_SHM_SHARED,
3461 shm_offset + (i * 2),
3462 tmp);
3463 } else {
3464 b43_shm_write16(dev, B43_SHM_SHARED,
3465 shm_offset + (i * 2),
3466 params[i]);
3467 }
3468 }
3469}
3470
c40c1129
MB		 3471/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3472static const u16 b43_qos_shm_offsets[] = {
3473 /* [mac80211-queue-nr] = SHM_OFFSET, */
3474 [0] = B43_QOS_VOICE,
3475 [1] = B43_QOS_VIDEO,
3476 [2] = B43_QOS_BESTEFFORT,
3477 [3] = B43_QOS_BACKGROUND,
3478};
3479
5a5f3b40
MB		 3480/* Update all QOS parameters in hardware. */
3481static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3482{
3483 struct b43_wl *wl = dev->wl;
3484 struct b43_qos_params *params;
e6f5b934
MB		 3485 unsigned int i;
3486
b0544eb6
MB		 3487 if (!dev->qos_enabled)
3488 return;
3489
c40c1129
MB		 3490 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3491 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3492
3493 b43_mac_suspend(dev);
e6f5b934
MB		 3494 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3495 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3496 b43_qos_params_upload(dev, &(params->p),
3497 b43_qos_shm_offsets[i]);
e6f5b934 3498 }
e6f5b934
MB		 3499 b43_mac_enable(dev);
3500}
3501
3502static void b43_qos_clear(struct b43_wl *wl)
3503{
3504 struct b43_qos_params *params;
3505 unsigned int i;
3506
c40c1129
MB		 3507 /* Initialize QoS parameters to sane defaults. */
3508
3509 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3510 ARRAY_SIZE(wl->qos_params));
3511
e6f5b934
MB		 3512 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3513 params = &(wl->qos_params[i]);
3514
c40c1129
MB		 3515 switch (b43_qos_shm_offsets[i]) {
3516 case B43_QOS_VOICE:
3517 params->p.txop = 0;
3518 params->p.aifs = 2;
3519 params->p.cw_min = 0x0001;
3520 params->p.cw_max = 0x0001;
3521 break;
3522 case B43_QOS_VIDEO:
3523 params->p.txop = 0;
3524 params->p.aifs = 2;
3525 params->p.cw_min = 0x0001;
3526 params->p.cw_max = 0x0001;
3527 break;
3528 case B43_QOS_BESTEFFORT:
3529 params->p.txop = 0;
3530 params->p.aifs = 3;
3531 params->p.cw_min = 0x0001;
3532 params->p.cw_max = 0x03FF;
3533 break;
3534 case B43_QOS_BACKGROUND:
3535 params->p.txop = 0;
3536 params->p.aifs = 7;
3537 params->p.cw_min = 0x0001;
3538 params->p.cw_max = 0x03FF;
3539 break;
3540 default:
3541 B43_WARN_ON(1);
3542 }
e6f5b934
MB		 3543 }
3544}
3545
3546/* Initialize the core's QOS capabilities */
3547static void b43_qos_init(struct b43_wldev *dev)
3548{
b0544eb6
MB		 3549 if (!dev->qos_enabled) {
3550 /* Disable QOS support. */
3551 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3552 b43_write16(dev, B43_MMIO_IFSCTL,
3553 b43_read16(dev, B43_MMIO_IFSCTL)
3554 & ~B43_MMIO_IFSCTL_USE_EDCF);
3555 b43dbg(dev->wl, "QoS disabled\n");
3556 return;
3557 }
3558
e6f5b934 3559 /* Upload the current QOS parameters. */
5a5f3b40 3560 b43_qos_upload_all(dev);
e6f5b934
MB		 3561
3562 /* Enable QOS support. */
3563 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3564 b43_write16(dev, B43_MMIO_IFSCTL,
3565 b43_read16(dev, B43_MMIO_IFSCTL)
3566 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3567 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3568}
3569
8a3a3c85
EP		 3570static int b43_op_conf_tx(struct ieee80211_hw *hw,
3571 struct ieee80211_vif *vif, u16 _queue,
40faacc4 3572 const struct ieee80211_tx_queue_params *params)
e4d6b795 3573{
e6f5b934 3574 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3575 struct b43_wldev *dev;
e6f5b934 3576 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3577 int err = -ENODEV;
e6f5b934
MB		 3578
3579 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3580 /* Queue not available or don't support setting
3581 * params on this queue. Return success to not
3582 * confuse mac80211. */
3583 return 0;
3584 }
5a5f3b40
MB		 3585 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3586 ARRAY_SIZE(wl->qos_params));
e6f5b934 3587
5a5f3b40
MB		 3588 mutex_lock(&wl->mutex);
3589 dev = wl->current_dev;
3590 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3591 goto out_unlock;
e6f5b934 3592
5a5f3b40
MB		 3593 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3594 b43_mac_suspend(dev);
3595 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3596 b43_qos_shm_offsets[queue]);
3597 b43_mac_enable(dev);
3598 err = 0;
e6f5b934 3599
5a5f3b40
MB		 3600out_unlock:
3601 mutex_unlock(&wl->mutex);
3602
3603 return err;
e4d6b795
MB		 3604}
3605
40faacc4
MB		 3606static int b43_op_get_stats(struct ieee80211_hw *hw,
3607 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3608{
3609 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3610
36dbd954 3611 mutex_lock(&wl->mutex);
e4d6b795 3612 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3613 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3614
3615 return 0;
3616}
3617
37a41b4a 3618static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
08e87a83
AF		 3619{
3620 struct b43_wl *wl = hw_to_b43_wl(hw);
3621 struct b43_wldev *dev;
3622 u64 tsf;
3623
3624 mutex_lock(&wl->mutex);
08e87a83
AF		 3625 dev = wl->current_dev;
3626
3627 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3628 b43_tsf_read(dev, &tsf);
3629 else
3630 tsf = 0;
3631
08e87a83
AF		 3632 mutex_unlock(&wl->mutex);
3633
3634 return tsf;
3635}
3636
37a41b4a
EP		 3637static void b43_op_set_tsf(struct ieee80211_hw *hw,
3638 struct ieee80211_vif *vif, u64 tsf)
08e87a83
AF		 3639{
3640 struct b43_wl *wl = hw_to_b43_wl(hw);
3641 struct b43_wldev *dev;
3642
3643 mutex_lock(&wl->mutex);
08e87a83
AF		 3644 dev = wl->current_dev;
3645
3646 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3647 b43_tsf_write(dev, tsf);
3648
08e87a83
AF		 3649 mutex_unlock(&wl->mutex);
3650}
3651
e4d6b795
MB		 3652static void b43_put_phy_into_reset(struct b43_wldev *dev)
3653{
6cbab0d9 3654 u32 tmp;
e4d6b795 3655
6cbab0d9 3656 switch (dev->dev->bus_type) {
42c9a458
RM		 3657#ifdef CONFIG_B43_BCMA
3658 case B43_BUS_BCMA:
3659 b43err(dev->wl,
3660 "Putting PHY into reset not supported on BCMA\n");
3661 break;
3662#endif
6cbab0d9
RM		 3663#ifdef CONFIG_B43_SSB
3664 case B43_BUS_SSB:
3665 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3666 tmp &= ~B43_TMSLOW_GMODE;
3667 tmp |= B43_TMSLOW_PHYRESET;
3668 tmp |= SSB_TMSLOW_FGC;
3669 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3670 msleep(1);
3671
3672 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3673 tmp &= ~SSB_TMSLOW_FGC;
3674 tmp |= B43_TMSLOW_PHYRESET;
3675 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3676 msleep(1);
e4d6b795 3677
6cbab0d9
RM		 3678 break;
3679#endif
3680 }
e4d6b795
MB		 3681}
3682
99da185a 3683static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3684{
3685 switch (band) {
3686 case IEEE80211_BAND_5GHZ:
3687 return "5";
3688 case IEEE80211_BAND_2GHZ:
3689 return "2.4";
3690 default:
3691 break;
3692 }
3693 B43_WARN_ON(1);
3694 return "";
3695}
3696
e4d6b795 3697/* Expects wl->mutex locked */
bb1eeff1 3698static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3699{
bb1eeff1 3700 struct b43_wldev *up_dev = NULL;
e4d6b795 3701 struct b43_wldev *down_dev;
bb1eeff1 3702 struct b43_wldev *d;
e4d6b795 3703 int err;
922d8a0b 3704 bool uninitialized_var(gmode);
e4d6b795
MB		 3705 int prev_status;
3706
bb1eeff1
MB		 3707 /* Find a device and PHY which supports the band. */
3708 list_for_each_entry(d, &wl->devlist, list) {
3709 switch (chan->band) {
3710 case IEEE80211_BAND_5GHZ:
3711 if (d->phy.supports_5ghz) {
3712 up_dev = d;
3db1cd5c 3713 gmode = false;
bb1eeff1
MB		 3714 }
3715 break;
3716 case IEEE80211_BAND_2GHZ:
3717 if (d->phy.supports_2ghz) {
3718 up_dev = d;
3db1cd5c 3719 gmode = true;
bb1eeff1
MB		 3720 }
3721 break;
3722 default:
3723 B43_WARN_ON(1);
3724 return -EINVAL;
3725 }
3726 if (up_dev)
3727 break;
3728 }
3729 if (!up_dev) {
3730 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3731 band_to_string(chan->band));
3732 return -ENODEV;
e4d6b795
MB		 3733 }
3734 if ((up_dev == wl->current_dev) &&
3735 (!!wl->current_dev->phy.gmode == !!gmode)) {
3736 /* This device is already running. */
3737 return 0;
3738 }
bb1eeff1
MB		 3739 b43dbg(wl, "Switching to %s-GHz band\n",
3740 band_to_string(chan->band));
e4d6b795
MB		 3741 down_dev = wl->current_dev;
3742
3743 prev_status = b43_status(down_dev);
3744 /* Shutdown the currently running core. */
3745 if (prev_status >= B43_STAT_STARTED)
36dbd954 3746 down_dev = b43_wireless_core_stop(down_dev);
e4d6b795
MB		 3747 if (prev_status >= B43_STAT_INITIALIZED)
3748 b43_wireless_core_exit(down_dev);
3749
3750 if (down_dev != up_dev) {
3751 /* We switch to a different core, so we put PHY into
3752 * RESET on the old core. */
3753 b43_put_phy_into_reset(down_dev);
3754 }
3755
3756 /* Now start the new core. */
3757 up_dev->phy.gmode = gmode;
3758 if (prev_status >= B43_STAT_INITIALIZED) {
3759 err = b43_wireless_core_init(up_dev);
3760 if (err) {
3761 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3762 "selected %s-GHz band\n",
3763 band_to_string(chan->band));
e4d6b795
MB		 3764 goto init_failure;
3765 }
3766 }
3767 if (prev_status >= B43_STAT_STARTED) {
3768 err = b43_wireless_core_start(up_dev);
3769 if (err) {
02b7d834 3770 b43err(wl, "Fatal: Could not start device for "
bb1eeff1
MB		 3771 "selected %s-GHz band\n",
3772 band_to_string(chan->band));
e4d6b795
MB		 3773 b43_wireless_core_exit(up_dev);
3774 goto init_failure;
3775 }
3776 }
3777 B43_WARN_ON(b43_status(up_dev) != prev_status);
3778
3779 wl->current_dev = up_dev;
3780
3781 return 0;
bb1eeff1 3782init_failure:
e4d6b795
MB		 3783 /* Whoops, failed to init the new core. No core is operating now. */
3784 wl->current_dev = NULL;
3785 return err;
3786}
3787
9124b077
JB		 3788/* Write the short and long frame retry limit values. */
3789static void b43_set_retry_limits(struct b43_wldev *dev,
3790 unsigned int short_retry,
3791 unsigned int long_retry)
3792{
3793 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3794 * the chip-internal counter. */
3795 short_retry = min(short_retry, (unsigned int)0xF);
3796 long_retry = min(long_retry, (unsigned int)0xF);
3797
3798 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3799 short_retry);
3800 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3801 long_retry);
3802}
3803
e8975581 3804static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3805{
3806 struct b43_wl *wl = hw_to_b43_wl(hw);
3807 struct b43_wldev *dev;
3808 struct b43_phy *phy;
e8975581 3809 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3810 int antenna;
e4d6b795 3811 int err = 0;
2a190322 3812 bool reload_bss = false;
e4d6b795 3813
e4d6b795
MB		 3814 mutex_lock(&wl->mutex);
3815
2a190322
FF		 3816 dev = wl->current_dev;
3817
bb1eeff1
MB		 3818 /* Switch the band (if necessary). This might change the active core. */
3819 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3820 if (err)
3821 goto out_unlock_mutex;
2a190322
FF		 3822
3823 /* Need to reload all settings if the core changed */
3824 if (dev != wl->current_dev) {
3825 dev = wl->current_dev;
3826 changed = ~0;
3827 reload_bss = true;
3828 }
3829
e4d6b795
MB		 3830 phy = &dev->phy;
3831
aa4c7b2a
RM		 3832 if (conf_is_ht(conf))
3833 phy->is_40mhz =
3834 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3835 else
3836 phy->is_40mhz = false;
3837
d10d0e57
MB		 3838 b43_mac_suspend(dev);
3839
9124b077
JB		 3840 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3841 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3842 conf->long_frame_max_tx_count);
3843 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3844 if (!changed)
d10d0e57 3845 goto out_mac_enable;
e4d6b795
MB		 3846
3847 /* Switch to the requested channel.
3848 * The firmware takes care of races with the TX handler. */
8318d78a 3849 if (conf->channel->hw_value != phy->channel)
ef1a628d 3850 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3851
0869aea0 3852 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
d42ce84a 3853
e4d6b795
MB		 3854 /* Adjust the desired TX power level. */
3855 if (conf->power_level != 0) {
18c8adeb
MB		 3856 if (conf->power_level != phy->desired_txpower) {
3857 phy->desired_txpower = conf->power_level;
3858 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3859 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3860 }
3861 }
3862
3863 /* Antennas for RX and management frame TX. */
0f4ac38b 3864 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3865 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3866 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3867 if (phy->ops->set_rx_antenna)
3868 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3869
fd4973c5
LF		 3870 if (wl->radio_enabled != phy->radio_on) {
3871 if (wl->radio_enabled) {
19d337df 3872 b43_software_rfkill(dev, false);
fda9abcf
MB		 3873 b43info(dev->wl, "Radio turned on by software\n");
3874 if (!dev->radio_hw_enable) {
3875 b43info(dev->wl, "The hardware RF-kill button "
3876 "still turns the radio physically off. "
3877 "Press the button to turn it on.\n");
3878 }
3879 } else {
19d337df 3880 b43_software_rfkill(dev, true);
fda9abcf
MB		 3881 b43info(dev->wl, "Radio turned off by software\n");
3882 }
3883 }
3884
d10d0e57
MB		 3885out_mac_enable:
3886 b43_mac_enable(dev);
3887out_unlock_mutex:
e4d6b795
MB		 3888 mutex_unlock(&wl->mutex);
3889
2a190322
FF		 3890 if (wl->vif && reload_bss)
3891 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3892
e4d6b795
MB		 3893 return err;
3894}
3895
881d948c 3896static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3897{
3898 struct ieee80211_supported_band *sband =
3899 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3900 struct ieee80211_rate *rate;
3901 int i;
3902 u16 basic, direct, offset, basic_offset, rateptr;
3903
3904 for (i = 0; i < sband->n_bitrates; i++) {
3905 rate = &sband->bitrates[i];
3906
3907 if (b43_is_cck_rate(rate->hw_value)) {
3908 direct = B43_SHM_SH_CCKDIRECT;
3909 basic = B43_SHM_SH_CCKBASIC;
3910 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3911 offset &= 0xF;
3912 } else {
3913 direct = B43_SHM_SH_OFDMDIRECT;
3914 basic = B43_SHM_SH_OFDMBASIC;
3915 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3916 offset &= 0xF;
3917 }
3918
3919 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3920
3921 if (b43_is_cck_rate(rate->hw_value)) {
3922 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3923 basic_offset &= 0xF;
3924 } else {
3925 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3926 basic_offset &= 0xF;
3927 }
3928
3929 /*
3930 * Get the pointer that we need to point to
3931 * from the direct map
3932 */
3933 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3934 direct + 2 * basic_offset);
3935 /* and write it to the basic map */
3936 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3937 rateptr);
3938 }
3939}
3940
3941static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3942 struct ieee80211_vif *vif,
3943 struct ieee80211_bss_conf *conf,
3944 u32 changed)
3945{
3946 struct b43_wl *wl = hw_to_b43_wl(hw);
3947 struct b43_wldev *dev;
c7ab5ef9
JB		 3948
3949 mutex_lock(&wl->mutex);
3950
3951 dev = wl->current_dev;
d10d0e57 3952 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3953 goto out_unlock_mutex;
2d0ddec5
JB		 3954
3955 B43_WARN_ON(wl->vif != vif);
3956
3957 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3958 if (conf->bssid)
3959 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3960 else
3961 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3962 }
2d0ddec5 3963
3f0d843b
JB		 3964 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3965 if (changed & BSS_CHANGED_BEACON &&
3966 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3967 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3968 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3969 b43_update_templates(wl);
3970
3971 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3972 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 3973 }
3974
c7ab5ef9
JB		 3975 b43_mac_suspend(dev);
3976
57c4d7b4
JB		 3977 /* Update templates for AP/mesh mode. */
3978 if (changed & BSS_CHANGED_BEACON_INT &&
3979 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3980 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
2a190322
FF		 3981 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3982 conf->beacon_int)
57c4d7b4
JB		 3983 b43_set_beacon_int(dev, conf->beacon_int);
3984
c7ab5ef9
JB		 3985 if (changed & BSS_CHANGED_BASIC_RATES)
3986 b43_update_basic_rates(dev, conf->basic_rates);
3987
3988 if (changed & BSS_CHANGED_ERP_SLOT) {
3989 if (conf->use_short_slot)
3990 b43_short_slot_timing_enable(dev);
3991 else
3992 b43_short_slot_timing_disable(dev);
3993 }
3994
3995 b43_mac_enable(dev);
d10d0e57 3996out_unlock_mutex:
c7ab5ef9 3997 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 3998}
3999
40faacc4 4000static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 4001 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4002 struct ieee80211_key_conf *key)
e4d6b795
MB		 4003{
4004 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 4005 struct b43_wldev *dev;
e4d6b795
MB		 4006 u8 algorithm;
4007 u8 index;
c6dfc9a8 4008 int err;
060210f9 4009 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 4010
4011 if (modparam_nohwcrypt)
4012 return -ENOSPC; /* User disabled HW-crypto */
4013
78f9c850
AQ		 4014 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4015 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4016 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4017 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4018 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4019 /*
4020 * For now, disable hw crypto for the RSN IBSS group keys. This
4021 * could be optimized in the future, but until that gets
4022 * implemented, use of software crypto for group addressed
4023 * frames is a acceptable to allow RSN IBSS to be used.
4024 */
4025 return -EOPNOTSUPP;
4026 }
4027
c6dfc9a8 4028 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 4029
4030 dev = wl->current_dev;
4031 err = -ENODEV;
4032 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4033 goto out_unlock;
4034
403a3a13 4035 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 4036 /* We don't have firmware for the crypto engine.
4037 * Must use software-crypto. */
4038 err = -EOPNOTSUPP;
4039 goto out_unlock;
4040 }
4041
c6dfc9a8 4042 err = -EINVAL;
97359d12
JB		 4043 switch (key->cipher) {
4044 case WLAN_CIPHER_SUITE_WEP40:
4045 algorithm = B43_SEC_ALGO_WEP40;
4046 break;
4047 case WLAN_CIPHER_SUITE_WEP104:
4048 algorithm = B43_SEC_ALGO_WEP104;
e4d6b795 4049 break;
97359d12 4050 case WLAN_CIPHER_SUITE_TKIP:
e4d6b795
MB		 4051 algorithm = B43_SEC_ALGO_TKIP;
4052 break;
97359d12 4053 case WLAN_CIPHER_SUITE_CCMP:
e4d6b795
MB		 4054 algorithm = B43_SEC_ALGO_AES;
4055 break;
4056 default:
4057 B43_WARN_ON(1);
c6dfc9a8 4058 goto out_unlock;
e4d6b795 4059 }
e4d6b795
MB		 4060 index = (u8) (key->keyidx);
4061 if (index > 3)
e4d6b795 4062 goto out_unlock;
e4d6b795
MB		 4063
4064 switch (cmd) {
4065 case SET_KEY:
035d0243 4066 if (algorithm == B43_SEC_ALGO_TKIP &&
4067 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4068 !modparam_hwtkip)) {
4069 /* We support only pairwise key */
e4d6b795
MB		 4070 err = -EOPNOTSUPP;
4071 goto out_unlock;
4072 }
4073
e808e586 4074 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 4075 if (WARN_ON(!sta)) {
4076 err = -EOPNOTSUPP;
4077 goto out_unlock;
4078 }
e808e586 4079 /* Pairwise key with an assigned MAC address. */
e4d6b795 4080 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 4081 key->key, key->keylen,
4082 sta->addr, key);
e808e586
MB		 4083 } else {
4084 /* Group key */
4085 err = b43_key_write(dev, index, algorithm,
4086 key->key, key->keylen, NULL, key);
e4d6b795
MB		 4087 }
4088 if (err)
4089 goto out_unlock;
4090
4091 if (algorithm == B43_SEC_ALGO_WEP40 ||
4092 algorithm == B43_SEC_ALGO_WEP104) {
4093 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4094 } else {
4095 b43_hf_write(dev,
4096 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4097 }
4098 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 4099 if (algorithm == B43_SEC_ALGO_TKIP)
4100 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 4101 break;
4102 case DISABLE_KEY: {
4103 err = b43_key_clear(dev, key->hw_key_idx);
4104 if (err)
4105 goto out_unlock;
4106 break;
4107 }
4108 default:
4109 B43_WARN_ON(1);
4110 }
9cf7f247 4111
e4d6b795 4112out_unlock:
e4d6b795
MB		 4113 if (!err) {
4114 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 4115 "mac: %pM\n",
e4d6b795 4116 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 4117 sta ? sta->addr : bcast_addr);
9cf7f247 4118 b43_dump_keymemory(dev);
e4d6b795 4119 }
9cf7f247
MB		 4120 mutex_unlock(&wl->mutex);
4121
e4d6b795
MB		 4122 return err;
4123}
4124
40faacc4
MB		 4125static void b43_op_configure_filter(struct ieee80211_hw *hw,
4126 unsigned int changed, unsigned int *fflags,
3ac64bee 4127 u64 multicast)
e4d6b795
MB		 4128{
4129 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 4130 struct b43_wldev *dev;
e4d6b795 4131
36dbd954
MB		 4132 mutex_lock(&wl->mutex);
4133 dev = wl->current_dev;
4150c572
JB		 4134 if (!dev) {
4135 *fflags = 0;
36dbd954 4136 goto out_unlock;
e4d6b795 4137 }
4150c572 4138
4150c572
JB		 4139 *fflags &= FIF_PROMISC_IN_BSS |
4140 FIF_ALLMULTI |
4141 FIF_FCSFAIL |
4142 FIF_PLCPFAIL |
4143 FIF_CONTROL |
4144 FIF_OTHER_BSS |
4145 FIF_BCN_PRBRESP_PROMISC;
4146
4147 changed &= FIF_PROMISC_IN_BSS |
4148 FIF_ALLMULTI |
4149 FIF_FCSFAIL |
4150 FIF_PLCPFAIL |
4151 FIF_CONTROL |
4152 FIF_OTHER_BSS |
4153 FIF_BCN_PRBRESP_PROMISC;
4154
4155 wl->filter_flags = *fflags;
4156
4157 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4158 b43_adjust_opmode(dev);
36dbd954
MB		 4159
4160out_unlock:
4161 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4162}
4163
36dbd954
MB		 4164/* Locking: wl->mutex
4165 * Returns the current dev. This might be different from the passed in dev,
4166 * because the core might be gone away while we unlocked the mutex. */
4167static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795 4168{
9a53bf54 4169 struct b43_wl *wl;
36dbd954 4170 struct b43_wldev *orig_dev;
49d965c8 4171 u32 mask;
bad69194 4172 int queue_num;
e4d6b795 4173
9a53bf54
LF		 4174 if (!dev)
4175 return NULL;
4176 wl = dev->wl;
36dbd954
MB		 4177redo:
4178 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4179 return dev;
a19d12d7 4180
f5d40eed 4181 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 4182 mutex_unlock(&wl->mutex);
4183 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 4184 cancel_work_sync(&wl->tx_work);
6b6fa586 4185 cancel_work_sync(&wl->firmware_load);
36dbd954
MB		 4186 mutex_lock(&wl->mutex);
4187 dev = wl->current_dev;
4188 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4189 /* Whoops, aliens ate up the device while we were unlocked. */
4190 return dev;
4191 }
a19d12d7 4192
36dbd954 4193 /* Disable interrupts on the device. */
e4d6b795 4194 b43_set_status(dev, B43_STAT_INITIALIZED);
505fb019 4195 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 4196 /* wl->mutex is locked. That is enough. */
4197 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4198 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4199 } else {
4200 spin_lock_irq(&wl->hardirq_lock);
4201 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4202 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4203 spin_unlock_irq(&wl->hardirq_lock);
4204 }
176e9f6a 4205 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
36dbd954 4206 orig_dev = dev;
e4d6b795 4207 mutex_unlock(&wl->mutex);
505fb019 4208 if (b43_bus_host_is_sdio(dev->dev)) {
176e9f6a
MB		 4209 b43_sdio_free_irq(dev);
4210 } else {
a18c715e
RM		 4211 synchronize_irq(dev->dev->irq);
4212 free_irq(dev->dev->irq, dev);
176e9f6a 4213 }
e4d6b795 4214 mutex_lock(&wl->mutex);
36dbd954
MB		 4215 dev = wl->current_dev;
4216 if (!dev)
4217 return dev;
4218 if (dev != orig_dev) {
4219 if (b43_status(dev) >= B43_STAT_STARTED)
4220 goto redo;
4221 return dev;
4222 }
49d965c8
MB		 4223 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4224 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
e4d6b795 4225
bad69194 4226 /* Drain all TX queues. */
4227 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
4228 while (skb_queue_len(&wl->tx_queue[queue_num]))
4229 dev_kfree_skb(skb_dequeue(&wl->tx_queue[queue_num]));
4230 }
f5d40eed 4231
e4d6b795 4232 b43_mac_suspend(dev);
a78b3bb2 4233 b43_leds_exit(dev);
e4d6b795 4234 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 4235
4236 return dev;
e4d6b795
MB		 4237}
4238
4239/* Locking: wl->mutex */
4240static int b43_wireless_core_start(struct b43_wldev *dev)
4241{
4242 int err;
4243
4244 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4245
4246 drain_txstatus_queue(dev);
505fb019 4247 if (b43_bus_host_is_sdio(dev->dev)) {
3dbba8e2
AH		 4248 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4249 if (err) {
4250 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4251 goto out;
4252 }
4253 } else {
a18c715e 4254 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3dbba8e2
AH		 4255 b43_interrupt_thread_handler,
4256 IRQF_SHARED, KBUILD_MODNAME, dev);
4257 if (err) {
dedb1eb9 4258 b43err(dev->wl, "Cannot request IRQ-%d\n",
a18c715e 4259 dev->dev->irq);
3dbba8e2
AH		 4260 goto out;
4261 }
e4d6b795
MB		 4262 }
4263
4264 /* We are ready to run. */
0866b03c 4265 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4266 b43_set_status(dev, B43_STAT_STARTED);
4267
4268 /* Start data flow (TX/RX). */
4269 b43_mac_enable(dev);
13790728 4270 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795 4271
25985edc 4272 /* Start maintenance work */
e4d6b795
MB		 4273 b43_periodic_tasks_setup(dev);
4274
a78b3bb2
MB		 4275 b43_leds_init(dev);
4276
e4d6b795 4277 b43dbg(dev->wl, "Wireless interface started\n");
a78b3bb2 4278out:
e4d6b795
MB		 4279 return err;
4280}
4281
4282/* Get PHY and RADIO versioning numbers */
4283static int b43_phy_versioning(struct b43_wldev *dev)
4284{
4285 struct b43_phy *phy = &dev->phy;
4286 u32 tmp;
4287 u8 analog_type;
4288 u8 phy_type;
4289 u8 phy_rev;
4290 u16 radio_manuf;
4291 u16 radio_ver;
4292 u16 radio_rev;
4293 int unsupported = 0;
4294
4295 /* Get PHY versioning */
4296 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4297 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4298 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4299 phy_rev = (tmp & B43_PHYVER_VERSION);
4300 switch (phy_type) {
4301 case B43_PHYTYPE_A:
4302 if (phy_rev >= 4)
4303 unsupported = 1;
4304 break;
4305 case B43_PHYTYPE_B:
4306 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4307 && phy_rev != 7)
4308 unsupported = 1;
4309 break;
4310 case B43_PHYTYPE_G:
013978b6 4311 if (phy_rev > 9)
e4d6b795
MB		 4312 unsupported = 1;
4313 break;
692d2c0f 4314#ifdef CONFIG_B43_PHY_N
d5c71e46 4315 case B43_PHYTYPE_N:
ab72efdf 4316 if (phy_rev > 9)
d5c71e46
MB		 4317 unsupported = 1;
4318 break;
6b1c7c67
MB		 4319#endif
4320#ifdef CONFIG_B43_PHY_LP
4321 case B43_PHYTYPE_LP:
9d86a2d5 4322 if (phy_rev > 2)
6b1c7c67
MB		 4323 unsupported = 1;
4324 break;
d7520b1d
RM		 4325#endif
4326#ifdef CONFIG_B43_PHY_HT
4327 case B43_PHYTYPE_HT:
4328 if (phy_rev > 1)
4329 unsupported = 1;
4330 break;
1d738e64
RM		 4331#endif
4332#ifdef CONFIG_B43_PHY_LCN
4333 case B43_PHYTYPE_LCN:
4334 if (phy_rev > 1)
4335 unsupported = 1;
4336 break;
d5c71e46 4337#endif
e4d6b795
MB		 4338 default:
4339 unsupported = 1;
6403eab1 4340 }
e4d6b795
MB		 4341 if (unsupported) {
4342 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4343 "(Analog %u, Type %u, Revision %u)\n",
4344 analog_type, phy_type, phy_rev);
4345 return -EOPNOTSUPP;
4346 }
4347 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4348 analog_type, phy_type, phy_rev);
4349
4350 /* Get RADIO versioning */
3fd48508 4351 if (dev->dev->core_rev >= 24) {
544e5d8b
RM		 4352 u16 radio24[3];
4353
4354 for (tmp = 0; tmp < 3; tmp++) {
4355 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4356 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4357 }
4358
4359 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4360 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4361
4362 radio_manuf = 0x17F;
4363 radio_ver = (radio24[2] << 8) | radio24[1];
4364 radio_rev = (radio24[0] & 0xF);
e4d6b795 4365 } else {
3fd48508
RM		 4366 if (dev->dev->chip_id == 0x4317) {
4367 if (dev->dev->chip_rev == 0)
4368 tmp = 0x3205017F;
4369 else if (dev->dev->chip_rev == 1)
4370 tmp = 0x4205017F;
4371 else
4372 tmp = 0x5205017F;
4373 } else {
4374 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4375 B43_RADIOCTL_ID);
4376 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4377 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4378 B43_RADIOCTL_ID);
4379 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4380 << 16;
4381 }
4382 radio_manuf = (tmp & 0x00000FFF);
4383 radio_ver = (tmp & 0x0FFFF000) >> 12;
4384 radio_rev = (tmp & 0xF0000000) >> 28;
e4d6b795 4385 }
3fd48508 4386
96c755a3
MB		 4387 if (radio_manuf != 0x17F /* Broadcom */)
4388 unsupported = 1;
e4d6b795
MB		 4389 switch (phy_type) {
4390 case B43_PHYTYPE_A:
4391 if (radio_ver != 0x2060)
4392 unsupported = 1;
4393 if (radio_rev != 1)
4394 unsupported = 1;
4395 if (radio_manuf != 0x17F)
4396 unsupported = 1;
4397 break;
4398 case B43_PHYTYPE_B:
4399 if ((radio_ver & 0xFFF0) != 0x2050)
4400 unsupported = 1;
4401 break;
4402 case B43_PHYTYPE_G:
4403 if (radio_ver != 0x2050)
4404 unsupported = 1;
4405 break;
96c755a3 4406 case B43_PHYTYPE_N:
bb519bee 4407 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 4408 unsupported = 1;
4409 break;
6b1c7c67 4410 case B43_PHYTYPE_LP:
9d86a2d5 4411 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 4412 unsupported = 1;
4413 break;
d7520b1d
RM		 4414 case B43_PHYTYPE_HT:
4415 if (radio_ver != 0x2059)
4416 unsupported = 1;
4417 break;
1d738e64
RM		 4418 case B43_PHYTYPE_LCN:
4419 if (radio_ver != 0x2064)
4420 unsupported = 1;
4421 break;
e4d6b795
MB		 4422 default:
4423 B43_WARN_ON(1);
4424 }
4425 if (unsupported) {
4426 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4427 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4428 radio_manuf, radio_ver, radio_rev);
4429 return -EOPNOTSUPP;
4430 }
4431 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4432 radio_manuf, radio_ver, radio_rev);
4433
4434 phy->radio_manuf = radio_manuf;
4435 phy->radio_ver = radio_ver;
4436 phy->radio_rev = radio_rev;
4437
4438 phy->analog = analog_type;
4439 phy->type = phy_type;
4440 phy->rev = phy_rev;
4441
4442 return 0;
4443}
4444
4445static void setup_struct_phy_for_init(struct b43_wldev *dev,
4446 struct b43_phy *phy)
4447{
e4d6b795 4448 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4449 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4450 /* PHY TX errors counter. */
4451 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4452
4453#if B43_DEBUG
3db1cd5c
RR		 4454 phy->phy_locked = false;
4455 phy->radio_locked = false;
591f3dc2 4456#endif
e4d6b795
MB		 4457}
4458
4459static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4460{
3db1cd5c 4461 dev->dfq_valid = false;
aa6c7ae2 4462
6a724d68
MB		 4463 /* Assume the radio is enabled. If it's not enabled, the state will
4464 * immediately get fixed on the first periodic work run. */
3db1cd5c 4465 dev->radio_hw_enable = true;
e4d6b795
MB		 4466
4467 /* Stats */
4468 memset(&dev->stats, 0, sizeof(dev->stats));
4469
4470 setup_struct_phy_for_init(dev, &dev->phy);
4471
4472 /* IRQ related flags */
4473 dev->irq_reason = 0;
4474 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4475 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4476 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4477 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4478
4479 dev->mac_suspended = 1;
4480
4481 /* Noise calculation context */
4482 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4483}
4484
4485static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4486{
0581483a 4487 struct ssb_sprom *sprom = dev->dev->bus_sprom;
a259d6a4 4488 u64 hf;
e4d6b795 4489
1855ba78
MB		 4490 if (!modparam_btcoex)
4491 return;
95de2841 4492 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4493 return;
4494 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4495 return;
4496
4497 hf = b43_hf_read(dev);
95de2841 4498 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4499 hf |= B43_HF_BTCOEXALT;
4500 else
4501 hf |= B43_HF_BTCOEX;
4502 b43_hf_write(dev, hf);
e4d6b795
MB		 4503}
4504
4505static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4506{
4507 if (!modparam_btcoex)
4508 return;
4509 //TODO
e4d6b795
MB		 4510}
4511
4512static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4513{
d48ae5c8 4514 struct ssb_bus *bus;
e4d6b795
MB		 4515 u32 tmp;
4516
d48ae5c8
RM		 4517 if (dev->dev->bus_type != B43_BUS_SSB)
4518 return;
4519
4520 bus = dev->dev->sdev->bus;
4521
0fd82eaf
RM		 4522 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4523 (bus->chip_id == 0x4312)) {
d48ae5c8 4524 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
0fd82eaf
RM		 4525 tmp &= ~SSB_IMCFGLO_REQTO;
4526 tmp &= ~SSB_IMCFGLO_SERTO;
4527 tmp |= 0x3;
d48ae5c8 4528 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
0fd82eaf 4529 ssb_commit_settings(bus);
e4d6b795 4530 }
e4d6b795
MB		 4531}
4532
d59f720d
MB		 4533static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4534{
4535 u16 pu_delay;
4536
4537 /* The time value is in microseconds. */
4538 if (dev->phy.type == B43_PHYTYPE_A)
4539 pu_delay = 3700;
4540 else
4541 pu_delay = 1050;
05c914fe 4542 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4543 pu_delay = 500;
4544 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4545 pu_delay = max(pu_delay, (u16)2400);
4546
4547 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4548}
4549
4550/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4551static void b43_set_pretbtt(struct b43_wldev *dev)
4552{
4553 u16 pretbtt;
4554
4555 /* The time value is in microseconds. */
05c914fe 4556 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4557 pretbtt = 2;
4558 } else {
4559 if (dev->phy.type == B43_PHYTYPE_A)
4560 pretbtt = 120;
4561 else
4562 pretbtt = 250;
4563 }
4564 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4565 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4566}
4567
e4d6b795
MB		 4568/* Shutdown a wireless core */
4569/* Locking: wl->mutex */
4570static void b43_wireless_core_exit(struct b43_wldev *dev)
4571{
36dbd954
MB		 4572 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4573 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795 4574 return;
84c164a3
JL		 4575
4576 /* Unregister HW RNG driver */
4577 b43_rng_exit(dev->wl);
4578
e4d6b795
MB		 4579 b43_set_status(dev, B43_STAT_UNINIT);
4580
1f7d87b0 4581 /* Stop the microcode PSM. */
5056635c
RM		 4582 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4583 B43_MACCTL_PSM_JMP0);
1f7d87b0 4584
e4d6b795 4585 b43_dma_free(dev);
5100d5ac 4586 b43_pio_free(dev);
e4d6b795 4587 b43_chip_exit(dev);
cb24f57f 4588 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4589 if (dev->wl->current_beacon) {
4590 dev_kfree_skb_any(dev->wl->current_beacon);
4591 dev->wl->current_beacon = NULL;
4592 }
4593
24ca39d6
RM		 4594 b43_device_disable(dev, 0);
4595 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4596}
4597
4598/* Initialize a wireless core */
4599static int b43_wireless_core_init(struct b43_wldev *dev)
4600{
0581483a 4601 struct ssb_sprom *sprom = dev->dev->bus_sprom;
e4d6b795
MB		 4602 struct b43_phy *phy = &dev->phy;
4603 int err;
a259d6a4 4604 u64 hf;
e4d6b795
MB		 4605
4606 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4607
24ca39d6 4608 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 4609 if (err)
4610 goto out;
4da909e7
RM		 4611 if (!b43_device_is_enabled(dev))
4612 b43_wireless_core_reset(dev, phy->gmode);
e4d6b795 4613
fb11137a 4614 /* Reset all data structures. */
e4d6b795 4615 setup_struct_wldev_for_init(dev);
fb11137a 4616 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4617
4618 /* Enable IRQ routing to this device. */
6cbab0d9 4619 switch (dev->dev->bus_type) {
42c9a458
RM		 4620#ifdef CONFIG_B43_BCMA
4621 case B43_BUS_BCMA:
4622 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4623 dev->dev->bdev, true);
4624 break;
4625#endif
6cbab0d9
RM		 4626#ifdef CONFIG_B43_SSB
4627 case B43_BUS_SSB:
4628 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4629 dev->dev->sdev);
4630 break;
4631#endif
4632 }
e4d6b795
MB		 4633
4634 b43_imcfglo_timeouts_workaround(dev);
4635 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4636 if (phy->ops->prepare_hardware) {
4637 err = phy->ops->prepare_hardware(dev);
ef1a628d 4638 if (err)
fb11137a 4639 goto err_busdown;
ef1a628d 4640 }
e4d6b795
MB		 4641 err = b43_chip_init(dev);
4642 if (err)
fb11137a 4643 goto err_busdown;
e4d6b795 4644 b43_shm_write16(dev, B43_SHM_SHARED,
21d889d4 4645 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
e4d6b795
MB		 4646 hf = b43_hf_read(dev);
4647 if (phy->type == B43_PHYTYPE_G) {
4648 hf |= B43_HF_SYMW;
4649 if (phy->rev == 1)
4650 hf |= B43_HF_GDCW;
95de2841 4651 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4652 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4653 }
4654 if (phy->radio_ver == 0x2050) {
4655 if (phy->radio_rev == 6)
4656 hf |= B43_HF_4318TSSI;
4657 if (phy->radio_rev < 6)
4658 hf |= B43_HF_VCORECALC;
e4d6b795 4659 }
1cc8f476
MB		 4660 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4661 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
1a77733c 4662#ifdef CONFIG_SSB_DRIVER_PCICORE
6cbab0d9
RM		 4663 if (dev->dev->bus_type == B43_BUS_SSB &&
4664 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4665 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
8821905c 4666 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4667#endif
25d3ef59 4668 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4669 b43_hf_write(dev, hf);
4670
74cfdba7
MB		 4671 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4672 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4673 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4674 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4675
4676 /* Disable sending probe responses from firmware.
4677 * Setting the MaxTime to one usec will always trigger
4678 * a timeout, so we never send any probe resp.
4679 * A timeout of zero is infinite. */
4680 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4681
4682 b43_rate_memory_init(dev);
5042c507 4683 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4684
4685 /* Minimum Contention Window */
c5a079f4 4686 if (phy->type == B43_PHYTYPE_B)
e4d6b795 4687 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
c5a079f4 4688 else
e4d6b795 4689 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
e4d6b795
MB		 4690 /* Maximum Contention Window */
4691 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4692
505fb019 4693 if (b43_bus_host_is_pcmcia(dev->dev) ||
cbe1e82a 4694 b43_bus_host_is_sdio(dev->dev)) {
3db1cd5c 4695 dev->__using_pio_transfers = true;
cbe1e82a
RM		 4696 err = b43_pio_init(dev);
4697 } else if (dev->use_pio) {
4698 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4699 "This should not be needed and will result in lower "
4700 "performance.\n");
3db1cd5c 4701 dev->__using_pio_transfers = true;
5100d5ac
MB		 4702 err = b43_pio_init(dev);
4703 } else {
3db1cd5c 4704 dev->__using_pio_transfers = false;
5100d5ac
MB		 4705 err = b43_dma_init(dev);
4706 }
e4d6b795
MB		 4707 if (err)
4708 goto err_chip_exit;
03b29773 4709 b43_qos_init(dev);
d59f720d 4710 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4711 b43_bluetooth_coext_enable(dev);
4712
24ca39d6 4713 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4714 b43_upload_card_macaddress(dev);
e4d6b795 4715 b43_security_init(dev);
e4d6b795 4716
5ab9549a 4717 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4718
4719 b43_set_status(dev, B43_STAT_INITIALIZED);
4720
84c164a3
JL		 4721 /* Register HW RNG driver */
4722 b43_rng_init(dev->wl);
4723
1a8d1227 4724out:
e4d6b795
MB		 4725 return err;
4726
ef1a628d 4727err_chip_exit:
e4d6b795 4728 b43_chip_exit(dev);
ef1a628d 4729err_busdown:
24ca39d6 4730 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4731 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4732 return err;
4733}
4734
40faacc4 4735static int b43_op_add_interface(struct ieee80211_hw *hw,
1ed32e4f 4736 struct ieee80211_vif *vif)
e4d6b795
MB		 4737{
4738 struct b43_wl *wl = hw_to_b43_wl(hw);
4739 struct b43_wldev *dev;
e4d6b795 4740 int err = -EOPNOTSUPP;
4150c572
JB		 4741
4742 /* TODO: allow WDS/AP devices to coexist */
4743
1ed32e4f
JB		 4744 if (vif->type != NL80211_IFTYPE_AP &&
4745 vif->type != NL80211_IFTYPE_MESH_POINT &&
4746 vif->type != NL80211_IFTYPE_STATION &&
4747 vif->type != NL80211_IFTYPE_WDS &&
4748 vif->type != NL80211_IFTYPE_ADHOC)
4150c572 4749 return -EOPNOTSUPP;
e4d6b795
MB		 4750
4751 mutex_lock(&wl->mutex);
4150c572 4752 if (wl->operating)
e4d6b795
MB		 4753 goto out_mutex_unlock;
4754
1ed32e4f 4755 b43dbg(wl, "Adding Interface type %d\n", vif->type);
e4d6b795
MB		 4756
4757 dev = wl->current_dev;
3db1cd5c 4758 wl->operating = true;
1ed32e4f
JB		 4759 wl->vif = vif;
4760 wl->if_type = vif->type;
4761 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4150c572 4762
4150c572 4763 b43_adjust_opmode(dev);
d59f720d
MB		 4764 b43_set_pretbtt(dev);
4765 b43_set_synth_pu_delay(dev, 0);
4150c572 4766 b43_upload_card_macaddress(dev);
4150c572
JB		 4767
4768 err = 0;
4769 out_mutex_unlock:
4770 mutex_unlock(&wl->mutex);
4771
2a190322
FF		 4772 if (err == 0)
4773 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4774
4150c572
JB		 4775 return err;
4776}
4777
40faacc4 4778static void b43_op_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4779 struct ieee80211_vif *vif)
4150c572
JB		 4780{
4781 struct b43_wl *wl = hw_to_b43_wl(hw);
4782 struct b43_wldev *dev = wl->current_dev;
4150c572 4783
1ed32e4f 4784 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4150c572
JB		 4785
4786 mutex_lock(&wl->mutex);
4787
4788 B43_WARN_ON(!wl->operating);
1ed32e4f 4789 B43_WARN_ON(wl->vif != vif);
32bfd35d 4790 wl->vif = NULL;
4150c572 4791
3db1cd5c 4792 wl->operating = false;
4150c572 4793
4150c572
JB		 4794 b43_adjust_opmode(dev);
4795 memset(wl->mac_addr, 0, ETH_ALEN);
4796 b43_upload_card_macaddress(dev);
4150c572
JB		 4797
4798 mutex_unlock(&wl->mutex);
4799}
4800
40faacc4 4801static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4802{
4803 struct b43_wl *wl = hw_to_b43_wl(hw);
4804 struct b43_wldev *dev = wl->current_dev;
4805 int did_init = 0;
923403b8 4806 int err = 0;
4150c572 4807
7be1bb6b
MB		 4808 /* Kill all old instance specific information to make sure
4809 * the card won't use it in the short timeframe between start
4810 * and mac80211 reconfiguring it. */
4811 memset(wl->bssid, 0, ETH_ALEN);
4812 memset(wl->mac_addr, 0, ETH_ALEN);
4813 wl->filter_flags = 0;
3db1cd5c 4814 wl->radiotap_enabled = false;
e6f5b934 4815 b43_qos_clear(wl);
3db1cd5c
RR		 4816 wl->beacon0_uploaded = false;
4817 wl->beacon1_uploaded = false;
4818 wl->beacon_templates_virgin = true;
4819 wl->radio_enabled = true;
7be1bb6b 4820
4150c572
JB		 4821 mutex_lock(&wl->mutex);
4822
e4d6b795
MB		 4823 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4824 err = b43_wireless_core_init(dev);
f41f3f37 4825 if (err)
e4d6b795
MB		 4826 goto out_mutex_unlock;
4827 did_init = 1;
4828 }
4150c572 4829
e4d6b795
MB		 4830 if (b43_status(dev) < B43_STAT_STARTED) {
4831 err = b43_wireless_core_start(dev);
4832 if (err) {
4833 if (did_init)
4834 b43_wireless_core_exit(dev);
4835 goto out_mutex_unlock;
4836 }
4837 }
4838
f41f3f37
JB		 4839 /* XXX: only do if device doesn't support rfkill irq */
4840 wiphy_rfkill_start_polling(hw->wiphy);
4841
4150c572 4842 out_mutex_unlock:
e4d6b795
MB		 4843 mutex_unlock(&wl->mutex);
4844
dbdedbdf
SF		 4845 /*
4846 * Configuration may have been overwritten during initialization.
4847 * Reload the configuration, but only if initialization was
4848 * successful. Reloading the configuration after a failed init
4849 * may hang the system.
4850 */
4851 if (!err)
4852 b43_op_config(hw, ~0);
2a190322 4853
e4d6b795
MB		 4854 return err;
4855}
4856
40faacc4 4857static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4858{
4859 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4860 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4861
a82d9922 4862 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4863
ccde8a45
GL		 4864 if (!dev)
4865 goto out;
4866
e4d6b795 4867 mutex_lock(&wl->mutex);
36dbd954
MB		 4868 if (b43_status(dev) >= B43_STAT_STARTED) {
4869 dev = b43_wireless_core_stop(dev);
4870 if (!dev)
4871 goto out_unlock;
4872 }
4150c572 4873 b43_wireless_core_exit(dev);
3db1cd5c 4874 wl->radio_enabled = false;
36dbd954
MB		 4875
4876out_unlock:
e4d6b795 4877 mutex_unlock(&wl->mutex);
ccde8a45 4878out:
18c8adeb 4879 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4880}
4881
17741cdc
JB		 4882static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4883 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4884{
4885 struct b43_wl *wl = hw_to_b43_wl(hw);
4886
8f611288 4887 /* FIXME: add locking */
9d139c81 4888 b43_update_templates(wl);
e66fee6a
MB		 4889
4890 return 0;
4891}
4892
38968d09
JB		 4893static void b43_op_sta_notify(struct ieee80211_hw *hw,
4894 struct ieee80211_vif *vif,
4895 enum sta_notify_cmd notify_cmd,
17741cdc 4896 struct ieee80211_sta *sta)
38968d09
JB		 4897{
4898 struct b43_wl *wl = hw_to_b43_wl(hw);
4899
4900 B43_WARN_ON(!vif || wl->vif != vif);
4901}
4902
25d3ef59
MB		 4903static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4904{
4905 struct b43_wl *wl = hw_to_b43_wl(hw);
4906 struct b43_wldev *dev;
4907
4908 mutex_lock(&wl->mutex);
4909 dev = wl->current_dev;
4910 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4911 /* Disable CFP update during scan on other channels. */
4912 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4913 }
4914 mutex_unlock(&wl->mutex);
4915}
4916
4917static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4918{
4919 struct b43_wl *wl = hw_to_b43_wl(hw);
4920 struct b43_wldev *dev;
4921
4922 mutex_lock(&wl->mutex);
4923 dev = wl->current_dev;
4924 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4925 /* Re-enable CFP update. */
4926 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4927 }
4928 mutex_unlock(&wl->mutex);
4929}
4930
354b4f04
JL		 4931static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4932 struct survey_info *survey)
4933{
4934 struct b43_wl *wl = hw_to_b43_wl(hw);
4935 struct b43_wldev *dev = wl->current_dev;
4936 struct ieee80211_conf *conf = &hw->conf;
4937
4938 if (idx != 0)
4939 return -ENOENT;
4940
4941 survey->channel = conf->channel;
4942 survey->filled = SURVEY_INFO_NOISE_DBM;
4943 survey->noise = dev->stats.link_noise;
4944
4945 return 0;
4946}
4947
e4d6b795 4948static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4949 .tx = b43_op_tx,
4950 .conf_tx = b43_op_conf_tx,
4951 .add_interface = b43_op_add_interface,
4952 .remove_interface = b43_op_remove_interface,
4953 .config = b43_op_config,
c7ab5ef9 4954 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4955 .configure_filter = b43_op_configure_filter,
4956 .set_key = b43_op_set_key,
035d0243 4957 .update_tkip_key = b43_op_update_tkip_key,
40faacc4 4958 .get_stats = b43_op_get_stats,
08e87a83
AF		 4959 .get_tsf = b43_op_get_tsf,
4960 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4961 .start = b43_op_start,
4962 .stop = b43_op_stop,
e66fee6a 4963 .set_tim = b43_op_beacon_set_tim,
38968d09 4964 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 4965 .sw_scan_start = b43_op_sw_scan_start_notifier,
4966 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
354b4f04 4967 .get_survey = b43_op_get_survey,
f41f3f37 4968 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 4969};
4970
4971/* Hard-reset the chip. Do not call this directly.
4972 * Use b43_controller_restart()
4973 */
4974static void b43_chip_reset(struct work_struct *work)
4975{
4976 struct b43_wldev *dev =
4977 container_of(work, struct b43_wldev, restart_work);
4978 struct b43_wl *wl = dev->wl;
4979 int err = 0;
4980 int prev_status;
4981
4982 mutex_lock(&wl->mutex);
4983
4984 prev_status = b43_status(dev);
4985 /* Bring the device down... */
36dbd954
MB		 4986 if (prev_status >= B43_STAT_STARTED) {
4987 dev = b43_wireless_core_stop(dev);
4988 if (!dev) {
4989 err = -ENODEV;
4990 goto out;
4991 }
4992 }
e4d6b795
MB		 4993 if (prev_status >= B43_STAT_INITIALIZED)
4994 b43_wireless_core_exit(dev);
4995
4996 /* ...and up again. */
4997 if (prev_status >= B43_STAT_INITIALIZED) {
4998 err = b43_wireless_core_init(dev);
4999 if (err)
5000 goto out;
5001 }
5002 if (prev_status >= B43_STAT_STARTED) {
5003 err = b43_wireless_core_start(dev);
5004 if (err) {
5005 b43_wireless_core_exit(dev);
5006 goto out;
5007 }
5008 }
3bf0a32e
MB		 5009out:
5010 if (err)
5011 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795 5012 mutex_unlock(&wl->mutex);
2a190322
FF		 5013
5014 if (err) {
e4d6b795 5015 b43err(wl, "Controller restart FAILED\n");
2a190322
FF		 5016 return;
5017 }
5018
5019 /* reload configuration */
5020 b43_op_config(wl->hw, ~0);
5021 if (wl->vif)
5022 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5023
5024 b43info(wl, "Controller restarted\n");
e4d6b795
MB		 5025}
5026
bb1eeff1 5027static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 5028 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 5029{
5030 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 5031
bb1eeff1
MB		 5032 if (have_2ghz_phy)
5033 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
5034 if (dev->phy.type == B43_PHYTYPE_N) {
5035 if (have_5ghz_phy)
5036 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
5037 } else {
5038 if (have_5ghz_phy)
5039 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5040 }
96c755a3 5041
bb1eeff1
MB		 5042 dev->phy.supports_2ghz = have_2ghz_phy;
5043 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 5044
5045 return 0;
5046}
5047
5048static void b43_wireless_core_detach(struct b43_wldev *dev)
5049{
5050 /* We release firmware that late to not be required to re-request
5051 * is all the time when we reinit the core. */
5052 b43_release_firmware(dev);
fb11137a 5053 b43_phy_free(dev);
e4d6b795
MB		 5054}
5055
5056static int b43_wireless_core_attach(struct b43_wldev *dev)
5057{
5058 struct b43_wl *wl = dev->wl;
6cbab0d9 5059 struct pci_dev *pdev = NULL;
e4d6b795 5060 int err;
40c62269 5061 u32 tmp;
3db1cd5c 5062 bool have_2ghz_phy = false, have_5ghz_phy = false;
e4d6b795
MB		 5063
5064 /* Do NOT do any device initialization here.
5065 * Do it in wireless_core_init() instead.
5066 * This function is for gathering basic information about the HW, only.
5067 * Also some structs may be set up here. But most likely you want to have
5068 * that in core_init(), too.
5069 */
5070
6cbab0d9
RM		 5071#ifdef CONFIG_B43_SSB
5072 if (dev->dev->bus_type == B43_BUS_SSB &&
5073 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5074 pdev = dev->dev->sdev->bus->host_pci;
5075#endif
5076
24ca39d6 5077 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 5078 if (err) {
5079 b43err(wl, "Bus powerup failed\n");
5080 goto out;
5081 }
e4d6b795 5082
6cbab0d9
RM		 5083 /* Get the PHY type. */
5084 switch (dev->dev->bus_type) {
42c9a458
RM		 5085#ifdef CONFIG_B43_BCMA
5086 case B43_BUS_BCMA:
40c62269
RM		 5087 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5088 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5089 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
42c9a458
RM		 5090 break;
5091#endif
6cbab0d9
RM		 5092#ifdef CONFIG_B43_SSB
5093 case B43_BUS_SSB:
5094 if (dev->dev->core_rev >= 5) {
40c62269
RM		 5095 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5096 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5097 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
6cbab0d9
RM		 5098 } else
5099 B43_WARN_ON(1);
5100 break;
5101#endif
5102 }
e4d6b795 5103
96c755a3 5104 dev->phy.gmode = have_2ghz_phy;
3db1cd5c 5105 dev->phy.radio_on = true;
4da909e7 5106 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5107
5108 err = b43_phy_versioning(dev);
5109 if (err)
21954c36 5110 goto err_powerdown;
e4d6b795
MB		 5111 /* Check if this device supports multiband. */
5112 if (!pdev ||
5113 (pdev->device != 0x4312 &&
5114 pdev->device != 0x4319 && pdev->device != 0x4324)) {
5115 /* No multiband support. */
3db1cd5c
RR		 5116 have_2ghz_phy = false;
5117 have_5ghz_phy = false;
e4d6b795
MB		 5118 switch (dev->phy.type) {
5119 case B43_PHYTYPE_A:
3db1cd5c 5120 have_5ghz_phy = true;
e4d6b795 5121 break;
9d86a2d5 5122 case B43_PHYTYPE_LP: //FIXME not always!
86b2892a 5123#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
9d86a2d5 5124 have_5ghz_phy = 1;
86b2892a 5125#endif
e4d6b795 5126 case B43_PHYTYPE_G:
96c755a3 5127 case B43_PHYTYPE_N:
8b9bda75
RM		 5128 case B43_PHYTYPE_HT:
5129 case B43_PHYTYPE_LCN:
3db1cd5c 5130 have_2ghz_phy = true;
e4d6b795
MB		 5131 break;
5132 default:
5133 B43_WARN_ON(1);
5134 }
5135 }
96c755a3
MB		 5136 if (dev->phy.type == B43_PHYTYPE_A) {
5137 /* FIXME */
5138 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5139 err = -EOPNOTSUPP;
5140 goto err_powerdown;
5141 }
2e35af14
MB		 5142 if (1 /* disable A-PHY */) {
5143 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
9d86a2d5
GS		 5144 if (dev->phy.type != B43_PHYTYPE_N &&
5145 dev->phy.type != B43_PHYTYPE_LP) {
3db1cd5c
RR		 5146 have_2ghz_phy = true;
5147 have_5ghz_phy = false;
2e35af14
MB		 5148 }
5149 }
5150
fb11137a
MB		 5151 err = b43_phy_allocate(dev);
5152 if (err)
5153 goto err_powerdown;
5154
96c755a3 5155 dev->phy.gmode = have_2ghz_phy;
4da909e7 5156 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5157
5158 err = b43_validate_chipaccess(dev);
5159 if (err)
fb11137a 5160 goto err_phy_free;
bb1eeff1 5161 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 5162 if (err)
fb11137a 5163 goto err_phy_free;
e4d6b795
MB		 5164
5165 /* Now set some default "current_dev" */
5166 if (!wl->current_dev)
5167 wl->current_dev = dev;
5168 INIT_WORK(&dev->restart_work, b43_chip_reset);
5169
cb24f57f 5170 dev->phy.ops->switch_analog(dev, 0);
24ca39d6
RM		 5171 b43_device_disable(dev, 0);
5172 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5173
5174out:
5175 return err;
5176
fb11137a
MB		 5177err_phy_free:
5178 b43_phy_free(dev);
e4d6b795 5179err_powerdown:
24ca39d6 5180 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5181 return err;
5182}
5183
482f0538 5184static void b43_one_core_detach(struct b43_bus_dev *dev)
e4d6b795
MB		 5185{
5186 struct b43_wldev *wldev;
5187 struct b43_wl *wl;
5188
3bf0a32e
MB		 5189 /* Do not cancel ieee80211-workqueue based work here.
5190 * See comment in b43_remove(). */
5191
74abacb6 5192 wldev = b43_bus_get_wldev(dev);
e4d6b795 5193 wl = wldev->wl;
e4d6b795
MB		 5194 b43_debugfs_remove_device(wldev);
5195 b43_wireless_core_detach(wldev);
5196 list_del(&wldev->list);
5197 wl->nr_devs--;
74abacb6 5198 b43_bus_set_wldev(dev, NULL);
e4d6b795
MB		 5199 kfree(wldev);
5200}
5201
482f0538 5202static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5203{
5204 struct b43_wldev *wldev;
e4d6b795
MB		 5205 int err = -ENOMEM;
5206
e4d6b795
MB		 5207 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5208 if (!wldev)
5209 goto out;
5210
9e3bd919 5211 wldev->use_pio = b43_modparam_pio;
482f0538 5212 wldev->dev = dev;
e4d6b795
MB		 5213 wldev->wl = wl;
5214 b43_set_status(wldev, B43_STAT_UNINIT);
5215 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 5216 INIT_LIST_HEAD(&wldev->list);
5217
5218 err = b43_wireless_core_attach(wldev);
5219 if (err)
5220 goto err_kfree_wldev;
5221
5222 list_add(&wldev->list, &wl->devlist);
5223 wl->nr_devs++;
74abacb6 5224 b43_bus_set_wldev(dev, wldev);
e4d6b795
MB		 5225 b43_debugfs_add_device(wldev);
5226
5227 out:
5228 return err;
5229
5230 err_kfree_wldev:
5231 kfree(wldev);
5232 return err;
5233}
5234
9fc38458
MB		 5235#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5236 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5237 (pdev->device == _device) && \
5238 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5239 (pdev->subsystem_device == _subdevice) )
5240
e4d6b795
MB		 5241static void b43_sprom_fixup(struct ssb_bus *bus)
5242{
1855ba78
MB		 5243 struct pci_dev *pdev;
5244
e4d6b795
MB		 5245 /* boardflags workarounds */
5246 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5a20ef3d 5247 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
95de2841 5248 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795 5249 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5a20ef3d 5250 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
95de2841 5251 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 5252 if (bus->bustype == SSB_BUSTYPE_PCI) {
5253 pdev = bus->host_pci;
9fc38458 5254 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 5255 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 5256 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 5257 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 5258 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 5259 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5260 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 5261 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5262 }
e4d6b795
MB		 5263}
5264
482f0538 5265static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5266{
5267 struct ieee80211_hw *hw = wl->hw;
5268
482f0538 5269 ssb_set_devtypedata(dev->sdev, NULL);
e4d6b795
MB		 5270 ieee80211_free_hw(hw);
5271}
5272
d1507051 5273static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
e4d6b795 5274{
d1507051 5275 struct ssb_sprom *sprom = dev->bus_sprom;
e4d6b795
MB		 5276 struct ieee80211_hw *hw;
5277 struct b43_wl *wl;
2729df25 5278 char chip_name[6];
bad69194 5279 int queue_num;
e4d6b795
MB		 5280
5281 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5282 if (!hw) {
5283 b43err(NULL, "Could not allocate ieee80211 device\n");
0355a345 5284 return ERR_PTR(-ENOMEM);
e4d6b795 5285 }
403a3a13 5286 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 5287
5288 /* fill hw info */
605a0bd6 5289 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
f5c044e5 5290 IEEE80211_HW_SIGNAL_DBM;
566bfe5a 5291
f59ac048
LR		 5292 hw->wiphy->interface_modes =
5293 BIT(NL80211_IFTYPE_AP) |
5294 BIT(NL80211_IFTYPE_MESH_POINT) |
5295 BIT(NL80211_IFTYPE_STATION) |
5296 BIT(NL80211_IFTYPE_WDS) |
5297 BIT(NL80211_IFTYPE_ADHOC);
5298
78f9c850
AQ		 5299 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5300
bad69194 5301 hw->queues = modparam_qos ? B43_QOS_QUEUE_NUM : 1;
403a3a13 5302 wl->mac80211_initially_registered_queues = hw->queues;
e64add27 5303 wl->hw_registred = false;
e6a9854b 5304 hw->max_rates = 2;
e4d6b795 5305 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 5306 if (is_valid_ether_addr(sprom->et1mac))
5307 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 5308 else
95de2841 5309 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 5310
403a3a13 5311 /* Initialize struct b43_wl */
e4d6b795 5312 wl->hw = hw;
e4d6b795 5313 mutex_init(&wl->mutex);
36dbd954 5314 spin_lock_init(&wl->hardirq_lock);
e4d6b795 5315 INIT_LIST_HEAD(&wl->devlist);
a82d9922 5316 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 5317 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed 5318 INIT_WORK(&wl->tx_work, b43_tx_work);
bad69194 5319
5320 /* Initialize queues and flags. */
5321 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5322 skb_queue_head_init(&wl->tx_queue[queue_num]);
5323 wl->tx_queue_stopped[queue_num] = 0;
5324 }
e4d6b795 5325
2729df25
RM		 5326 snprintf(chip_name, ARRAY_SIZE(chip_name),
5327 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5328 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5329 dev->core_rev);
0355a345 5330 return wl;
e4d6b795
MB		 5331}
5332
3c65ab62
RM		 5333#ifdef CONFIG_B43_BCMA
5334static int b43_bcma_probe(struct bcma_device *core)
5335{
397915c3 5336 struct b43_bus_dev *dev;
24aad3f4
RM		 5337 struct b43_wl *wl;
5338 int err;
397915c3
RM		 5339
5340 dev = b43_bus_dev_bcma_init(core);
5341 if (!dev)
5342 return -ENODEV;
5343
24aad3f4
RM		 5344 wl = b43_wireless_init(dev);
5345 if (IS_ERR(wl)) {
5346 err = PTR_ERR(wl);
5347 goto bcma_out;
5348 }
5349
5350 err = b43_one_core_attach(dev, wl);
5351 if (err)
5352 goto bcma_err_wireless_exit;
5353
6b6fa586
LF		 5354 /* setup and start work to load firmware */
5355 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5356 schedule_work(&wl->firmware_load);
24aad3f4
RM		 5357
5358bcma_out:
5359 return err;
5360
24aad3f4
RM		 5361bcma_err_wireless_exit:
5362 ieee80211_free_hw(wl->hw);
5363 return err;
3c65ab62
RM		 5364}
5365
5366static void b43_bcma_remove(struct bcma_device *core)
5367{
24aad3f4
RM		 5368 struct b43_wldev *wldev = bcma_get_drvdata(core);
5369 struct b43_wl *wl = wldev->wl;
5370
5371 /* We must cancel any work here before unregistering from ieee80211,
5372 * as the ieee80211 unreg will destroy the workqueue. */
5373 cancel_work_sync(&wldev->restart_work);
5374
e64add27
OR		 5375 B43_WARN_ON(!wl);
5376 if (wl->current_dev == wldev && wl->hw_registred) {
5377 /* Restore the queues count before unregistering, because firmware detect
5378 * might have modified it. Restoring is important, so the networking
5379 * stack can properly free resources. */
5380 wl->hw->queues = wl->mac80211_initially_registered_queues;
5381 b43_leds_stop(wldev);
5382 ieee80211_unregister_hw(wl->hw);
5383 }
24aad3f4
RM		 5384
5385 b43_one_core_detach(wldev->dev);
5386
5387 b43_leds_unregister(wl);
5388
5389 ieee80211_free_hw(wl->hw);
3c65ab62
RM		 5390}
5391
5392static struct bcma_driver b43_bcma_driver = {
5393 .name = KBUILD_MODNAME,
5394 .id_table = b43_bcma_tbl,
5395 .probe = b43_bcma_probe,
5396 .remove = b43_bcma_remove,
5397};
5398#endif
5399
aec7ffdf 5400#ifdef CONFIG_B43_SSB
aa63418a
RM		 5401static
5402int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
e4d6b795 5403{
482f0538 5404 struct b43_bus_dev *dev;
e4d6b795
MB		 5405 struct b43_wl *wl;
5406 int err;
5407 int first = 0;
5408
482f0538 5409 dev = b43_bus_dev_ssb_init(sdev);
5b49b35a
DC		 5410 if (!dev)
5411 return -ENOMEM;
482f0538 5412
aa63418a 5413 wl = ssb_get_devtypedata(sdev);
e4d6b795
MB		 5414 if (!wl) {
5415 /* Probing the first core. Must setup common struct b43_wl */
5416 first = 1;
aa63418a 5417 b43_sprom_fixup(sdev->bus);
d1507051 5418 wl = b43_wireless_init(dev);
0355a345
RM		 5419 if (IS_ERR(wl)) {
5420 err = PTR_ERR(wl);
e4d6b795 5421 goto out;
0355a345 5422 }
aa63418a
RM		 5423 ssb_set_devtypedata(sdev, wl);
5424 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
e4d6b795
MB		 5425 }
5426 err = b43_one_core_attach(dev, wl);
5427 if (err)
5428 goto err_wireless_exit;
5429
6b6fa586
LF		 5430 /* setup and start work to load firmware */
5431 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5432 schedule_work(&wl->firmware_load);
e4d6b795
MB		 5433
5434 out:
5435 return err;
5436
e4d6b795
MB		 5437 err_wireless_exit:
5438 if (first)
5439 b43_wireless_exit(dev, wl);
5440 return err;
5441}
5442
aa63418a 5443static void b43_ssb_remove(struct ssb_device *sdev)
e4d6b795 5444{
aa63418a
RM		 5445 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5446 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
e61b52d1 5447 struct b43_bus_dev *dev = wldev->dev;
e4d6b795 5448
3bf0a32e
MB		 5449 /* We must cancel any work here before unregistering from ieee80211,
5450 * as the ieee80211 unreg will destroy the workqueue. */
5451 cancel_work_sync(&wldev->restart_work);
5452
e4d6b795 5453 B43_WARN_ON(!wl);
e64add27 5454 if (wl->current_dev == wldev && wl->hw_registred) {
403a3a13
MB		 5455 /* Restore the queues count before unregistering, because firmware detect
5456 * might have modified it. Restoring is important, so the networking
5457 * stack can properly free resources. */
5458 wl->hw->queues = wl->mac80211_initially_registered_queues;
82905ace 5459 b43_leds_stop(wldev);
e4d6b795 5460 ieee80211_unregister_hw(wl->hw);
403a3a13 5461 }
e4d6b795 5462
e61b52d1 5463 b43_one_core_detach(dev);
e4d6b795
MB		 5464
5465 if (list_empty(&wl->devlist)) {
727c9885 5466 b43_leds_unregister(wl);
e4d6b795
MB		 5467 /* Last core on the chip unregistered.
5468 * We can destroy common struct b43_wl.
5469 */
e61b52d1 5470 b43_wireless_exit(dev, wl);
e4d6b795
MB		 5471 }
5472}
5473
aec7ffdf
RM		 5474static struct ssb_driver b43_ssb_driver = {
5475 .name = KBUILD_MODNAME,
5476 .id_table = b43_ssb_tbl,
5477 .probe = b43_ssb_probe,
5478 .remove = b43_ssb_remove,
5479};
5480#endif /* CONFIG_B43_SSB */
5481
e4d6b795
MB		 5482/* Perform a hardware reset. This can be called from any context. */
5483void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5484{
5485 /* Must avoid requeueing, if we are in shutdown. */
5486 if (b43_status(dev) < B43_STAT_INITIALIZED)
5487 return;
5488 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 5489 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 5490}
5491
26bc783f
MB		 5492static void b43_print_driverinfo(void)
5493{
5494 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
3dbba8e2 5495 *feat_leds = "", *feat_sdio = "";
26bc783f
MB		 5496
5497#ifdef CONFIG_B43_PCI_AUTOSELECT
5498 feat_pci = "P";
5499#endif
5500#ifdef CONFIG_B43_PCMCIA
5501 feat_pcmcia = "M";
5502#endif
692d2c0f 5503#ifdef CONFIG_B43_PHY_N
26bc783f
MB		 5504 feat_nphy = "N";
5505#endif
5506#ifdef CONFIG_B43_LEDS
5507 feat_leds = "L";
3dbba8e2
AH		 5508#endif
5509#ifdef CONFIG_B43_SDIO
5510 feat_sdio = "S";
26bc783f
MB		 5511#endif
5512 printk(KERN_INFO "Broadcom 43xx driver loaded "
8b0be90c 5513 "[ Features: %s%s%s%s%s ]\n",
26bc783f 5514 feat_pci, feat_pcmcia, feat_nphy,
3dbba8e2 5515 feat_leds, feat_sdio);
26bc783f
MB		 5516}
5517
e4d6b795
MB		 5518static int __init b43_init(void)
5519{
5520 int err;
5521
5522 b43_debugfs_init();
5523 err = b43_pcmcia_init();
5524 if (err)
5525 goto err_dfs_exit;
3dbba8e2 5526 err = b43_sdio_init();
e4d6b795
MB		 5527 if (err)
5528 goto err_pcmcia_exit;
3c65ab62
RM		 5529#ifdef CONFIG_B43_BCMA
5530 err = bcma_driver_register(&b43_bcma_driver);
3dbba8e2
AH		 5531 if (err)
5532 goto err_sdio_exit;
3c65ab62 5533#endif
aec7ffdf 5534#ifdef CONFIG_B43_SSB
3c65ab62
RM		 5535 err = ssb_driver_register(&b43_ssb_driver);
5536 if (err)
5537 goto err_bcma_driver_exit;
aec7ffdf 5538#endif
26bc783f 5539 b43_print_driverinfo();
e4d6b795
MB		 5540
5541 return err;
5542
aec7ffdf 5543#ifdef CONFIG_B43_SSB
3c65ab62 5544err_bcma_driver_exit:
aec7ffdf 5545#endif
3c65ab62
RM		 5546#ifdef CONFIG_B43_BCMA
5547 bcma_driver_unregister(&b43_bcma_driver);
3dbba8e2 5548err_sdio_exit:
3c65ab62 5549#endif
3dbba8e2 5550 b43_sdio_exit();
e4d6b795
MB		 5551err_pcmcia_exit:
5552 b43_pcmcia_exit();
5553err_dfs_exit:
5554 b43_debugfs_exit();
5555 return err;
5556}
5557
5558static void __exit b43_exit(void)
5559{
aec7ffdf 5560#ifdef CONFIG_B43_SSB
e4d6b795 5561 ssb_driver_unregister(&b43_ssb_driver);
aec7ffdf 5562#endif
3c65ab62
RM		 5563#ifdef CONFIG_B43_BCMA
5564 bcma_driver_unregister(&b43_bcma_driver);
5565#endif
3dbba8e2 5566 b43_sdio_exit();
e4d6b795
MB		 5567 b43_pcmcia_exit();
5568 b43_debugfs_exit();
5569}
5570
5571module_init(b43_init)
5572module_exit(b43_exit)
kernel source for telekom puls (alcatel/mediatek)