Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
6dcc3444 SM |
22 | static void ath9k_set_assoc_state(struct ath_softc *sc, |
23 | struct ieee80211_vif *vif); | |
24 | ||
313eb87f | 25 | u8 ath9k_parse_mpdudensity(u8 mpdudensity) |
ff37e337 S |
26 | { |
27 | /* | |
28 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
29 | * 0 for no restriction | |
30 | * 1 for 1/4 us | |
31 | * 2 for 1/2 us | |
32 | * 3 for 1 us | |
33 | * 4 for 2 us | |
34 | * 5 for 4 us | |
35 | * 6 for 8 us | |
36 | * 7 for 16 us | |
37 | */ | |
38 | switch (mpdudensity) { | |
39 | case 0: | |
40 | return 0; | |
41 | case 1: | |
42 | case 2: | |
43 | case 3: | |
44 | /* Our lower layer calculations limit our precision to | |
45 | 1 microsecond */ | |
46 | return 1; | |
47 | case 4: | |
48 | return 2; | |
49 | case 5: | |
50 | return 4; | |
51 | case 6: | |
52 | return 8; | |
53 | case 7: | |
54 | return 16; | |
55 | default: | |
56 | return 0; | |
57 | } | |
58 | } | |
59 | ||
69081624 VT |
60 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
61 | { | |
62 | bool pending = false; | |
63 | ||
64 | spin_lock_bh(&txq->axq_lock); | |
65 | ||
66 | if (txq->axq_depth || !list_empty(&txq->axq_acq)) | |
67 | pending = true; | |
69081624 VT |
68 | |
69 | spin_unlock_bh(&txq->axq_lock); | |
70 | return pending; | |
71 | } | |
72 | ||
6d79cb4c | 73 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
74 | { |
75 | unsigned long flags; | |
76 | bool ret; | |
77 | ||
9ecdef4b LR |
78 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
79 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
80 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
81 | |
82 | return ret; | |
83 | } | |
84 | ||
a91d75ae LR |
85 | void ath9k_ps_wakeup(struct ath_softc *sc) |
86 | { | |
898c914a | 87 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 88 | unsigned long flags; |
fbb078fc | 89 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
90 | |
91 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
92 | if (++sc->ps_usecount != 1) | |
93 | goto unlock; | |
94 | ||
fbb078fc | 95 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 96 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 97 | |
898c914a FF |
98 | /* |
99 | * While the hardware is asleep, the cycle counters contain no | |
100 | * useful data. Better clear them now so that they don't mess up | |
101 | * survey data results. | |
102 | */ | |
fbb078fc FF |
103 | if (power_mode != ATH9K_PM_AWAKE) { |
104 | spin_lock(&common->cc_lock); | |
105 | ath_hw_cycle_counters_update(common); | |
106 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
c9ae6ab4 | 107 | memset(&common->cc_ani, 0, sizeof(common->cc_ani)); |
fbb078fc FF |
108 | spin_unlock(&common->cc_lock); |
109 | } | |
898c914a | 110 | |
a91d75ae LR |
111 | unlock: |
112 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
113 | } | |
114 | ||
115 | void ath9k_ps_restore(struct ath_softc *sc) | |
116 | { | |
898c914a | 117 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c6c539f0 | 118 | enum ath9k_power_mode mode; |
a91d75ae | 119 | unsigned long flags; |
ad128860 | 120 | bool reset; |
a91d75ae LR |
121 | |
122 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
123 | if (--sc->ps_usecount != 0) | |
124 | goto unlock; | |
125 | ||
ad128860 SM |
126 | if (sc->ps_idle) { |
127 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
128 | ath9k_hw_stopdmarecv(sc->sc_ah, &reset); | |
c6c539f0 | 129 | mode = ATH9K_PM_FULL_SLEEP; |
ad128860 SM |
130 | } else if (sc->ps_enabled && |
131 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
132 | PS_WAIT_FOR_CAB | | |
133 | PS_WAIT_FOR_PSPOLL_DATA | | |
424749c7 RM |
134 | PS_WAIT_FOR_TX_ACK | |
135 | PS_WAIT_FOR_ANI))) { | |
c6c539f0 | 136 | mode = ATH9K_PM_NETWORK_SLEEP; |
08d4df41 RM |
137 | if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) |
138 | ath9k_btcoex_stop_gen_timer(sc); | |
ad128860 | 139 | } else { |
c6c539f0 | 140 | goto unlock; |
ad128860 | 141 | } |
c6c539f0 FF |
142 | |
143 | spin_lock(&common->cc_lock); | |
144 | ath_hw_cycle_counters_update(common); | |
145 | spin_unlock(&common->cc_lock); | |
146 | ||
1a8f0d39 | 147 | ath9k_hw_setpower(sc->sc_ah, mode); |
a91d75ae LR |
148 | |
149 | unlock: | |
150 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
151 | } | |
152 | ||
9adcf440 | 153 | static void __ath_cancel_work(struct ath_softc *sc) |
ff37e337 | 154 | { |
5ee08656 FF |
155 | cancel_work_sync(&sc->paprd_work); |
156 | cancel_work_sync(&sc->hw_check_work); | |
157 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
181fb18d | 158 | cancel_delayed_work_sync(&sc->hw_pll_work); |
fad29cd2 | 159 | |
bf52592f | 160 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
fad29cd2 SM |
161 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
162 | cancel_work_sync(&sc->mci_work); | |
bf52592f | 163 | #endif |
9adcf440 | 164 | } |
5ee08656 | 165 | |
9adcf440 FF |
166 | static void ath_cancel_work(struct ath_softc *sc) |
167 | { | |
168 | __ath_cancel_work(sc); | |
169 | cancel_work_sync(&sc->hw_reset_work); | |
170 | } | |
3cbb5dd7 | 171 | |
af68abad SM |
172 | static void ath_restart_work(struct ath_softc *sc) |
173 | { | |
af68abad SM |
174 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
175 | ||
c12b6021 GJ |
176 | if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) || |
177 | AR_SREV_9550(sc->sc_ah)) | |
af68abad SM |
178 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, |
179 | msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); | |
180 | ||
181 | ath_start_rx_poll(sc, 3); | |
da0d45f7 | 182 | ath_start_ani(sc); |
af68abad SM |
183 | } |
184 | ||
9ebea382 | 185 | static bool ath_prepare_reset(struct ath_softc *sc) |
9adcf440 FF |
186 | { |
187 | struct ath_hw *ah = sc->sc_ah; | |
ceea2a51 | 188 | bool ret = true; |
6a6733f2 | 189 | |
9adcf440 | 190 | ieee80211_stop_queues(sc->hw); |
5e848f78 | 191 | |
9adcf440 | 192 | sc->hw_busy_count = 0; |
da0d45f7 | 193 | ath_stop_ani(sc); |
01e18918 | 194 | del_timer_sync(&sc->rx_poll_timer); |
ff37e337 | 195 | |
9adcf440 FF |
196 | ath9k_debug_samp_bb_mac(sc); |
197 | ath9k_hw_disable_interrupts(ah); | |
8b3f4616 | 198 | |
1381559b | 199 | if (!ath_drain_all_txq(sc)) |
9adcf440 | 200 | ret = false; |
c0d7c7af | 201 | |
0a62acb1 | 202 | if (!ath_stoprecv(sc)) |
ceea2a51 FF |
203 | ret = false; |
204 | ||
9adcf440 FF |
205 | return ret; |
206 | } | |
ff37e337 | 207 | |
9adcf440 FF |
208 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
209 | { | |
210 | struct ath_hw *ah = sc->sc_ah; | |
211 | struct ath_common *common = ath9k_hw_common(ah); | |
196fb860 | 212 | unsigned long flags; |
c0d7c7af | 213 | |
c0d7c7af | 214 | if (ath_startrecv(sc) != 0) { |
3800276a | 215 | ath_err(common, "Unable to restart recv logic\n"); |
9adcf440 | 216 | return false; |
c0d7c7af LR |
217 | } |
218 | ||
5048e8c3 RM |
219 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
220 | sc->config.txpowlimit, &sc->curtxpow); | |
b74713d0 SM |
221 | |
222 | clear_bit(SC_OP_HW_RESET, &sc->sc_flags); | |
72d874c6 | 223 | ath9k_hw_set_interrupts(ah); |
b037b693 | 224 | ath9k_hw_enable_interrupts(ah); |
3989279c | 225 | |
4cb54fa3 | 226 | if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { |
196fb860 SM |
227 | if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) |
228 | goto work; | |
229 | ||
196fb860 SM |
230 | if (ah->opmode == NL80211_IFTYPE_STATION && |
231 | test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
232 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
233 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
234 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
a6768280 SM |
235 | } else { |
236 | ath9k_set_beacon(sc); | |
196fb860 SM |
237 | } |
238 | work: | |
af68abad | 239 | ath_restart_work(sc); |
5ee08656 FF |
240 | } |
241 | ||
8da07830 SM |
242 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) |
243 | ath_ant_comb_update(sc); | |
43c35284 | 244 | |
9adcf440 FF |
245 | ieee80211_wake_queues(sc->hw); |
246 | ||
247 | return true; | |
248 | } | |
249 | ||
1381559b | 250 | static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) |
9adcf440 FF |
251 | { |
252 | struct ath_hw *ah = sc->sc_ah; | |
253 | struct ath_common *common = ath9k_hw_common(ah); | |
254 | struct ath9k_hw_cal_data *caldata = NULL; | |
255 | bool fastcc = true; | |
9adcf440 FF |
256 | int r; |
257 | ||
258 | __ath_cancel_work(sc); | |
259 | ||
4668cce5 | 260 | tasklet_disable(&sc->intr_tq); |
9adcf440 | 261 | spin_lock_bh(&sc->sc_pcu_lock); |
92460412 | 262 | |
4cb54fa3 | 263 | if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { |
9adcf440 FF |
264 | fastcc = false; |
265 | caldata = &sc->caldata; | |
266 | } | |
267 | ||
268 | if (!hchan) { | |
269 | fastcc = false; | |
9adcf440 FF |
270 | hchan = ah->curchan; |
271 | } | |
272 | ||
9ebea382 | 273 | if (!ath_prepare_reset(sc)) |
9adcf440 FF |
274 | fastcc = false; |
275 | ||
d2182b69 | 276 | ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", |
feced201 | 277 | hchan->channel, IS_CHAN_HT40(hchan), fastcc); |
9adcf440 FF |
278 | |
279 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | |
280 | if (r) { | |
281 | ath_err(common, | |
282 | "Unable to reset channel, reset status %d\n", r); | |
f50b1cd3 RS |
283 | |
284 | ath9k_hw_enable_interrupts(ah); | |
285 | ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); | |
286 | ||
9adcf440 FF |
287 | goto out; |
288 | } | |
289 | ||
e82cb03f RM |
290 | if (ath9k_hw_mci_is_enabled(sc->sc_ah) && |
291 | (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) | |
292 | ath9k_mci_set_txpower(sc, true, false); | |
293 | ||
9adcf440 FF |
294 | if (!ath_complete_reset(sc, true)) |
295 | r = -EIO; | |
296 | ||
297 | out: | |
6a6733f2 | 298 | spin_unlock_bh(&sc->sc_pcu_lock); |
4668cce5 FF |
299 | tasklet_enable(&sc->intr_tq); |
300 | ||
9adcf440 FF |
301 | return r; |
302 | } | |
303 | ||
304 | ||
305 | /* | |
306 | * Set/change channels. If the channel is really being changed, it's done | |
307 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
308 | * DMA, then restart stuff. | |
309 | */ | |
310 | static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
311 | struct ath9k_channel *hchan) | |
312 | { | |
313 | int r; | |
314 | ||
781b14a3 | 315 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) |
9adcf440 FF |
316 | return -EIO; |
317 | ||
1381559b | 318 | r = ath_reset_internal(sc, hchan); |
6a6733f2 | 319 | |
3989279c | 320 | return r; |
ff37e337 S |
321 | } |
322 | ||
7e1e3864 BG |
323 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, |
324 | struct ieee80211_vif *vif) | |
ff37e337 S |
325 | { |
326 | struct ath_node *an; | |
ff37e337 S |
327 | an = (struct ath_node *)sta->drv_priv; |
328 | ||
a145daf7 | 329 | an->sc = sc; |
7f010c93 | 330 | an->sta = sta; |
7e1e3864 | 331 | an->vif = vif; |
3d4e20f2 | 332 | |
dd5ee59b SM |
333 | ath_tx_node_init(sc, an); |
334 | ||
335 | if (sta->ht_cap.ht_supported) { | |
9e98ac65 | 336 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc | 337 | sta->ht_cap.ampdu_factor); |
dd5ee59b | 338 | an->mpdudensity = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); |
87792efc | 339 | } |
ff37e337 S |
340 | } |
341 | ||
342 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
343 | { | |
344 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
dd5ee59b | 345 | ath_tx_node_cleanup(sc, an); |
ff37e337 S |
346 | } |
347 | ||
55624204 | 348 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
349 | { |
350 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 351 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 352 | struct ath_common *common = ath9k_hw_common(ah); |
124b979b | 353 | enum ath_reset_type type; |
07c15a3f | 354 | unsigned long flags; |
17d7904d | 355 | u32 status = sc->intrstatus; |
b5c80475 | 356 | u32 rxmask; |
ff37e337 | 357 | |
e3927007 FF |
358 | ath9k_ps_wakeup(sc); |
359 | spin_lock(&sc->sc_pcu_lock); | |
360 | ||
a4d86d95 RM |
361 | if ((status & ATH9K_INT_FATAL) || |
362 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
030d6294 FF |
363 | |
364 | if (status & ATH9K_INT_FATAL) | |
365 | type = RESET_TYPE_FATAL_INT; | |
366 | else | |
367 | type = RESET_TYPE_BB_WATCHDOG; | |
368 | ||
124b979b | 369 | ath9k_queue_reset(sc, type); |
e3927007 | 370 | goto out; |
063d8be3 | 371 | } |
ff37e337 | 372 | |
07c15a3f | 373 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
4105f807 RM |
374 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
375 | /* | |
376 | * TSF sync does not look correct; remain awake to sync with | |
377 | * the next Beacon. | |
378 | */ | |
d2182b69 | 379 | ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); |
e8fe7336 | 380 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
4105f807 | 381 | } |
07c15a3f | 382 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
4105f807 | 383 | |
b5c80475 FF |
384 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
385 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
386 | ATH9K_INT_RXORN); | |
387 | else | |
388 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
389 | ||
390 | if (status & rxmask) { | |
b5c80475 FF |
391 | /* Check for high priority Rx first */ |
392 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
393 | (status & ATH9K_INT_RXHP)) | |
394 | ath_rx_tasklet(sc, 0, true); | |
395 | ||
396 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
397 | } |
398 | ||
e5003249 VT |
399 | if (status & ATH9K_INT_TX) { |
400 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
401 | ath_tx_edma_tasklet(sc); | |
402 | else | |
403 | ath_tx_tasklet(sc); | |
404 | } | |
063d8be3 | 405 | |
56ca0dba | 406 | ath9k_btcoex_handle_interrupt(sc, status); |
19686ddf | 407 | |
e3927007 | 408 | out: |
ff37e337 | 409 | /* re-enable hardware interrupt */ |
4df3071e | 410 | ath9k_hw_enable_interrupts(ah); |
6a6733f2 | 411 | |
52671e43 | 412 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 413 | ath9k_ps_restore(sc); |
ff37e337 S |
414 | } |
415 | ||
6baff7f9 | 416 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 417 | { |
063d8be3 S |
418 | #define SCHED_INTR ( \ |
419 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 420 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
421 | ATH9K_INT_RXORN | \ |
422 | ATH9K_INT_RXEOL | \ | |
423 | ATH9K_INT_RX | \ | |
b5c80475 FF |
424 | ATH9K_INT_RXLP | \ |
425 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
426 | ATH9K_INT_TX | \ |
427 | ATH9K_INT_BMISS | \ | |
428 | ATH9K_INT_CST | \ | |
ebb8e1d7 | 429 | ATH9K_INT_TSFOOR | \ |
40dc5392 MSS |
430 | ATH9K_INT_GENTIMER | \ |
431 | ATH9K_INT_MCI) | |
063d8be3 | 432 | |
ff37e337 | 433 | struct ath_softc *sc = dev; |
cbe61d8a | 434 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 435 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
436 | enum ath9k_int status; |
437 | bool sched = false; | |
438 | ||
063d8be3 S |
439 | /* |
440 | * The hardware is not ready/present, don't | |
441 | * touch anything. Note this can happen early | |
442 | * on if the IRQ is shared. | |
443 | */ | |
781b14a3 | 444 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) |
063d8be3 | 445 | return IRQ_NONE; |
ff37e337 | 446 | |
063d8be3 S |
447 | /* shared irq, not for us */ |
448 | ||
153e080d | 449 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 450 | return IRQ_NONE; |
063d8be3 | 451 | |
f41a9b3b FF |
452 | if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) { |
453 | ath9k_hw_kill_interrupts(ah); | |
b74713d0 | 454 | return IRQ_HANDLED; |
f41a9b3b | 455 | } |
b74713d0 | 456 | |
063d8be3 S |
457 | /* |
458 | * Figure out the reason(s) for the interrupt. Note | |
459 | * that the hal returns a pseudo-ISR that may include | |
460 | * bits we haven't explicitly enabled so we mask the | |
461 | * value to insure we only process bits we requested. | |
462 | */ | |
463 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 464 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 465 | |
063d8be3 S |
466 | /* |
467 | * If there are no status bits set, then this interrupt was not | |
468 | * for me (should have been caught above). | |
469 | */ | |
153e080d | 470 | if (!status) |
063d8be3 | 471 | return IRQ_NONE; |
ff37e337 | 472 | |
063d8be3 S |
473 | /* Cache the status */ |
474 | sc->intrstatus = status; | |
475 | ||
476 | if (status & SCHED_INTR) | |
477 | sched = true; | |
478 | ||
479 | /* | |
480 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
481 | * chip immediately. | |
482 | */ | |
b5c80475 FF |
483 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
484 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
485 | goto chip_reset; |
486 | ||
08578b8f LR |
487 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
488 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
489 | |
490 | spin_lock(&common->cc_lock); | |
491 | ath_hw_cycle_counters_update(common); | |
08578b8f | 492 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
493 | spin_unlock(&common->cc_lock); |
494 | ||
08578b8f LR |
495 | goto chip_reset; |
496 | } | |
ca90ef44 RM |
497 | #ifdef CONFIG_PM_SLEEP |
498 | if (status & ATH9K_INT_BMISS) { | |
499 | if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { | |
500 | ath_dbg(common, ANY, "during WoW we got a BMISS\n"); | |
501 | atomic_inc(&sc->wow_got_bmiss_intr); | |
502 | atomic_dec(&sc->wow_sleep_proc_intr); | |
503 | } | |
504 | } | |
505 | #endif | |
063d8be3 S |
506 | if (status & ATH9K_INT_SWBA) |
507 | tasklet_schedule(&sc->bcon_tasklet); | |
508 | ||
509 | if (status & ATH9K_INT_TXURN) | |
510 | ath9k_hw_updatetxtriglevel(ah, true); | |
511 | ||
0682c9b5 RM |
512 | if (status & ATH9K_INT_RXEOL) { |
513 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 514 | ath9k_hw_set_interrupts(ah); |
b5c80475 FF |
515 | } |
516 | ||
153e080d VT |
517 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
518 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
519 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
520 | goto chip_reset; | |
063d8be3 S |
521 | /* Clear RxAbort bit so that we can |
522 | * receive frames */ | |
9ecdef4b | 523 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
07c15a3f | 524 | spin_lock(&sc->sc_pm_lock); |
153e080d | 525 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 526 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
07c15a3f | 527 | spin_unlock(&sc->sc_pm_lock); |
ff37e337 | 528 | } |
063d8be3 S |
529 | |
530 | chip_reset: | |
ff37e337 | 531 | |
817e11de S |
532 | ath_debug_stat_interrupt(sc, status); |
533 | ||
ff37e337 | 534 | if (sched) { |
4df3071e FF |
535 | /* turn off every interrupt */ |
536 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
537 | tasklet_schedule(&sc->intr_tq); |
538 | } | |
539 | ||
540 | return IRQ_HANDLED; | |
063d8be3 S |
541 | |
542 | #undef SCHED_INTR | |
ff37e337 S |
543 | } |
544 | ||
1381559b | 545 | static int ath_reset(struct ath_softc *sc) |
ff37e337 | 546 | { |
1381559b | 547 | int i, r; |
ff37e337 | 548 | |
783cd01e | 549 | ath9k_ps_wakeup(sc); |
6a6733f2 | 550 | |
1381559b | 551 | r = ath_reset_internal(sc, NULL); |
ff37e337 | 552 | |
1381559b FF |
553 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
554 | if (!ATH_TXQ_SETUP(sc, i)) | |
555 | continue; | |
556 | ||
557 | spin_lock_bh(&sc->tx.txq[i].axq_lock); | |
558 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
559 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
560 | } |
561 | ||
783cd01e | 562 | ath9k_ps_restore(sc); |
2ab81d4a | 563 | |
ae8d2858 | 564 | return r; |
ff37e337 S |
565 | } |
566 | ||
124b979b RM |
567 | void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) |
568 | { | |
569 | #ifdef CONFIG_ATH9K_DEBUGFS | |
570 | RESET_STAT_INC(sc, type); | |
571 | #endif | |
572 | set_bit(SC_OP_HW_RESET, &sc->sc_flags); | |
573 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | |
574 | } | |
575 | ||
236de514 FF |
576 | void ath_reset_work(struct work_struct *work) |
577 | { | |
578 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | |
579 | ||
1381559b | 580 | ath_reset(sc); |
236de514 FF |
581 | } |
582 | ||
ff37e337 S |
583 | /**********************/ |
584 | /* mac80211 callbacks */ | |
585 | /**********************/ | |
586 | ||
8feceb67 | 587 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 588 | { |
9ac58615 | 589 | struct ath_softc *sc = hw->priv; |
af03abec | 590 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 591 | struct ath_common *common = ath9k_hw_common(ah); |
675a0b04 | 592 | struct ieee80211_channel *curchan = hw->conf.chandef.chan; |
ff37e337 | 593 | struct ath9k_channel *init_channel; |
82880a7c | 594 | int r; |
f078f209 | 595 | |
d2182b69 | 596 | ath_dbg(common, CONFIG, |
226afe68 JP |
597 | "Starting driver with initial channel: %d MHz\n", |
598 | curchan->center_freq); | |
f078f209 | 599 | |
f62d816f | 600 | ath9k_ps_wakeup(sc); |
141b38b6 S |
601 | mutex_lock(&sc->mutex); |
602 | ||
c344c9cb | 603 | init_channel = ath9k_cmn_get_curchannel(hw, ah); |
ff37e337 S |
604 | |
605 | /* Reset SERDES registers */ | |
84c87dc8 | 606 | ath9k_hw_configpcipowersave(ah, false); |
ff37e337 S |
607 | |
608 | /* | |
609 | * The basic interface to setting the hardware in a good | |
610 | * state is ``reset''. On return the hardware is known to | |
611 | * be powered up and with interrupts disabled. This must | |
612 | * be followed by initialization of the appropriate bits | |
613 | * and then setup of the interrupt mask. | |
614 | */ | |
4bdd1e97 | 615 | spin_lock_bh(&sc->sc_pcu_lock); |
c0c11741 FF |
616 | |
617 | atomic_set(&ah->intr_ref_cnt, -1); | |
618 | ||
20bd2a09 | 619 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 620 | if (r) { |
3800276a JP |
621 | ath_err(common, |
622 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
623 | r, curchan->center_freq); | |
ceb26a60 | 624 | ah->reset_power_on = false; |
ff37e337 | 625 | } |
ff37e337 | 626 | |
ff37e337 | 627 | /* Setup our intr mask. */ |
b5c80475 FF |
628 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
629 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
630 | ATH9K_INT_GLOBAL; | |
631 | ||
632 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
633 | ah->imask |= ATH9K_INT_RXHP | |
634 | ATH9K_INT_RXLP | | |
635 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
636 | else |
637 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 638 | |
364734fa | 639 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 640 | |
af03abec | 641 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 642 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 643 | |
e270e776 | 644 | ath_mci_enable(sc); |
40dc5392 | 645 | |
781b14a3 | 646 | clear_bit(SC_OP_INVALID, &sc->sc_flags); |
5f841b41 | 647 | sc->sc_ah->is_monitoring = false; |
ff37e337 | 648 | |
ceb26a60 FF |
649 | if (!ath_complete_reset(sc, false)) |
650 | ah->reset_power_on = false; | |
ff37e337 | 651 | |
c0c11741 FF |
652 | if (ah->led_pin >= 0) { |
653 | ath9k_hw_cfg_output(ah, ah->led_pin, | |
654 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
655 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); | |
656 | } | |
657 | ||
658 | /* | |
659 | * Reset key cache to sane defaults (all entries cleared) instead of | |
660 | * semi-random values after suspend/resume. | |
661 | */ | |
662 | ath9k_cmn_init_crypto(sc->sc_ah); | |
663 | ||
9adcf440 | 664 | spin_unlock_bh(&sc->sc_pcu_lock); |
164ace38 | 665 | |
141b38b6 S |
666 | mutex_unlock(&sc->mutex); |
667 | ||
f62d816f FF |
668 | ath9k_ps_restore(sc); |
669 | ||
ceb26a60 | 670 | return 0; |
f078f209 LR |
671 | } |
672 | ||
36323f81 TH |
673 | static void ath9k_tx(struct ieee80211_hw *hw, |
674 | struct ieee80211_tx_control *control, | |
675 | struct sk_buff *skb) | |
f078f209 | 676 | { |
9ac58615 | 677 | struct ath_softc *sc = hw->priv; |
c46917bb | 678 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 679 | struct ath_tx_control txctl; |
1bc14880 | 680 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
07c15a3f | 681 | unsigned long flags; |
528f0c6b | 682 | |
96148326 | 683 | if (sc->ps_enabled) { |
dc8c4585 JM |
684 | /* |
685 | * mac80211 does not set PM field for normal data frames, so we | |
686 | * need to update that based on the current PS mode. | |
687 | */ | |
688 | if (ieee80211_is_data(hdr->frame_control) && | |
689 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
690 | !ieee80211_has_pm(hdr->frame_control)) { | |
d2182b69 | 691 | ath_dbg(common, PS, |
226afe68 | 692 | "Add PM=1 for a TX frame while in PS mode\n"); |
dc8c4585 JM |
693 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
694 | } | |
695 | } | |
696 | ||
ad128860 | 697 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { |
9a23f9ca JM |
698 | /* |
699 | * We are using PS-Poll and mac80211 can request TX while in | |
700 | * power save mode. Need to wake up hardware for the TX to be | |
701 | * completed and if needed, also for RX of buffered frames. | |
702 | */ | |
9a23f9ca | 703 | ath9k_ps_wakeup(sc); |
07c15a3f | 704 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
fdf76622 VT |
705 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
706 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 707 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
d2182b69 | 708 | ath_dbg(common, PS, |
226afe68 | 709 | "Sending PS-Poll to pick a buffered frame\n"); |
1b04b930 | 710 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 711 | } else { |
d2182b69 | 712 | ath_dbg(common, PS, "Wake up to complete TX\n"); |
1b04b930 | 713 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
714 | } |
715 | /* | |
716 | * The actual restore operation will happen only after | |
ad128860 | 717 | * the ps_flags bit is cleared. We are just dropping |
9a23f9ca JM |
718 | * the ps_usecount here. |
719 | */ | |
07c15a3f | 720 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
9a23f9ca JM |
721 | ath9k_ps_restore(sc); |
722 | } | |
723 | ||
ad128860 SM |
724 | /* |
725 | * Cannot tx while the hardware is in full sleep, it first needs a full | |
726 | * chip reset to recover from that | |
727 | */ | |
728 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { | |
729 | ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); | |
730 | goto exit; | |
731 | } | |
732 | ||
528f0c6b | 733 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 734 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
36323f81 | 735 | txctl.sta = control->sta; |
528f0c6b | 736 | |
d2182b69 | 737 | ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 738 | |
c52f33d0 | 739 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
d2182b69 | 740 | ath_dbg(common, XMIT, "TX failed\n"); |
a5a0bca1 | 741 | TX_STAT_INC(txctl.txq->axq_qnum, txfailed); |
528f0c6b | 742 | goto exit; |
8feceb67 VT |
743 | } |
744 | ||
7bb45683 | 745 | return; |
528f0c6b | 746 | exit: |
249ee722 | 747 | ieee80211_free_txskb(hw, skb); |
f078f209 LR |
748 | } |
749 | ||
8feceb67 | 750 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 751 | { |
9ac58615 | 752 | struct ath_softc *sc = hw->priv; |
af03abec | 753 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 754 | struct ath_common *common = ath9k_hw_common(ah); |
c0c11741 | 755 | bool prev_idle; |
f078f209 | 756 | |
4c483817 S |
757 | mutex_lock(&sc->mutex); |
758 | ||
9adcf440 | 759 | ath_cancel_work(sc); |
01e18918 | 760 | del_timer_sync(&sc->rx_poll_timer); |
c94dbff7 | 761 | |
781b14a3 | 762 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { |
d2182b69 | 763 | ath_dbg(common, ANY, "Device not present\n"); |
4c483817 | 764 | mutex_unlock(&sc->mutex); |
9c84b797 S |
765 | return; |
766 | } | |
8feceb67 | 767 | |
3867cf6a S |
768 | /* Ensure HW is awake when we try to shut it down. */ |
769 | ath9k_ps_wakeup(sc); | |
770 | ||
6a6733f2 LR |
771 | spin_lock_bh(&sc->sc_pcu_lock); |
772 | ||
203043f5 SG |
773 | /* prevent tasklets to enable interrupts once we disable them */ |
774 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
775 | ||
ff37e337 S |
776 | /* make sure h/w will not generate any interrupt |
777 | * before setting the invalid flag. */ | |
4df3071e | 778 | ath9k_hw_disable_interrupts(ah); |
ff37e337 | 779 | |
c0c11741 FF |
780 | spin_unlock_bh(&sc->sc_pcu_lock); |
781 | ||
782 | /* we can now sync irq and kill any running tasklets, since we already | |
783 | * disabled interrupts and not holding a spin lock */ | |
784 | synchronize_irq(sc->irq); | |
785 | tasklet_kill(&sc->intr_tq); | |
786 | tasklet_kill(&sc->bcon_tasklet); | |
787 | ||
788 | prev_idle = sc->ps_idle; | |
789 | sc->ps_idle = true; | |
790 | ||
791 | spin_lock_bh(&sc->sc_pcu_lock); | |
792 | ||
793 | if (ah->led_pin >= 0) { | |
794 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
795 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
796 | } | |
797 | ||
9ebea382 | 798 | ath_prepare_reset(sc); |
ff37e337 | 799 | |
0d95521e FF |
800 | if (sc->rx.frag) { |
801 | dev_kfree_skb_any(sc->rx.frag); | |
802 | sc->rx.frag = NULL; | |
803 | } | |
804 | ||
c0c11741 FF |
805 | if (!ah->curchan) |
806 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); | |
6a6733f2 | 807 | |
c0c11741 FF |
808 | ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
809 | ath9k_hw_phy_disable(ah); | |
6a6733f2 | 810 | |
c0c11741 | 811 | ath9k_hw_configpcipowersave(ah, true); |
203043f5 | 812 | |
c0c11741 | 813 | spin_unlock_bh(&sc->sc_pcu_lock); |
3867cf6a | 814 | |
c0c11741 | 815 | ath9k_ps_restore(sc); |
ff37e337 | 816 | |
781b14a3 | 817 | set_bit(SC_OP_INVALID, &sc->sc_flags); |
c0c11741 | 818 | sc->ps_idle = prev_idle; |
500c064d | 819 | |
141b38b6 S |
820 | mutex_unlock(&sc->mutex); |
821 | ||
d2182b69 | 822 | ath_dbg(common, CONFIG, "Driver halt\n"); |
f078f209 LR |
823 | } |
824 | ||
4801416c BG |
825 | bool ath9k_uses_beacons(int type) |
826 | { | |
827 | switch (type) { | |
828 | case NL80211_IFTYPE_AP: | |
829 | case NL80211_IFTYPE_ADHOC: | |
830 | case NL80211_IFTYPE_MESH_POINT: | |
831 | return true; | |
832 | default: | |
833 | return false; | |
834 | } | |
835 | } | |
836 | ||
4801416c BG |
837 | static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
838 | { | |
839 | struct ath9k_vif_iter_data *iter_data = data; | |
840 | int i; | |
841 | ||
ab11bb28 | 842 | if (iter_data->has_hw_macaddr) { |
4801416c BG |
843 | for (i = 0; i < ETH_ALEN; i++) |
844 | iter_data->mask[i] &= | |
845 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
ab11bb28 FF |
846 | } else { |
847 | memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); | |
848 | iter_data->has_hw_macaddr = true; | |
849 | } | |
141b38b6 | 850 | |
1ed32e4f | 851 | switch (vif->type) { |
4801416c BG |
852 | case NL80211_IFTYPE_AP: |
853 | iter_data->naps++; | |
f078f209 | 854 | break; |
4801416c BG |
855 | case NL80211_IFTYPE_STATION: |
856 | iter_data->nstations++; | |
e51f3eff | 857 | break; |
05c914fe | 858 | case NL80211_IFTYPE_ADHOC: |
4801416c BG |
859 | iter_data->nadhocs++; |
860 | break; | |
9cb5412b | 861 | case NL80211_IFTYPE_MESH_POINT: |
4801416c BG |
862 | iter_data->nmeshes++; |
863 | break; | |
864 | case NL80211_IFTYPE_WDS: | |
865 | iter_data->nwds++; | |
f078f209 LR |
866 | break; |
867 | default: | |
4801416c | 868 | break; |
f078f209 | 869 | } |
4801416c | 870 | } |
f078f209 | 871 | |
6dcc3444 SM |
872 | static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
873 | { | |
874 | struct ath_softc *sc = data; | |
875 | struct ath_vif *avp = (void *)vif->drv_priv; | |
876 | ||
877 | if (vif->type != NL80211_IFTYPE_STATION) | |
878 | return; | |
879 | ||
880 | if (avp->primary_sta_vif) | |
881 | ath9k_set_assoc_state(sc, vif); | |
882 | } | |
883 | ||
4801416c BG |
884 | /* Called with sc->mutex held. */ |
885 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
886 | struct ieee80211_vif *vif, | |
887 | struct ath9k_vif_iter_data *iter_data) | |
888 | { | |
9ac58615 | 889 | struct ath_softc *sc = hw->priv; |
4801416c BG |
890 | struct ath_hw *ah = sc->sc_ah; |
891 | struct ath_common *common = ath9k_hw_common(ah); | |
8feceb67 | 892 | |
4801416c BG |
893 | /* |
894 | * Use the hardware MAC address as reference, the hardware uses it | |
895 | * together with the BSSID mask when matching addresses. | |
896 | */ | |
897 | memset(iter_data, 0, sizeof(*iter_data)); | |
4801416c | 898 | memset(&iter_data->mask, 0xff, ETH_ALEN); |
5640b08e | 899 | |
4801416c BG |
900 | if (vif) |
901 | ath9k_vif_iter(iter_data, vif->addr, vif); | |
902 | ||
903 | /* Get list of all active MAC addresses */ | |
8b2c9824 JB |
904 | ieee80211_iterate_active_interfaces_atomic( |
905 | sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, | |
906 | ath9k_vif_iter, iter_data); | |
ab11bb28 FF |
907 | |
908 | memcpy(common->macaddr, iter_data->hw_macaddr, ETH_ALEN); | |
4801416c | 909 | } |
8ca21f01 | 910 | |
4801416c BG |
911 | /* Called with sc->mutex held. */ |
912 | static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, | |
913 | struct ieee80211_vif *vif) | |
914 | { | |
9ac58615 | 915 | struct ath_softc *sc = hw->priv; |
4801416c BG |
916 | struct ath_hw *ah = sc->sc_ah; |
917 | struct ath_common *common = ath9k_hw_common(ah); | |
918 | struct ath9k_vif_iter_data iter_data; | |
6dcc3444 | 919 | enum nl80211_iftype old_opmode = ah->opmode; |
8ca21f01 | 920 | |
4801416c | 921 | ath9k_calculate_iter_data(hw, vif, &iter_data); |
2c3db3d5 | 922 | |
4801416c BG |
923 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); |
924 | ath_hw_setbssidmask(common); | |
925 | ||
4801416c | 926 | if (iter_data.naps > 0) { |
60ca9f87 | 927 | ath9k_hw_set_tsfadjust(ah, true); |
4801416c BG |
928 | ah->opmode = NL80211_IFTYPE_AP; |
929 | } else { | |
60ca9f87 | 930 | ath9k_hw_set_tsfadjust(ah, false); |
5640b08e | 931 | |
fd5999cf JC |
932 | if (iter_data.nmeshes) |
933 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
934 | else if (iter_data.nwds) | |
4801416c BG |
935 | ah->opmode = NL80211_IFTYPE_AP; |
936 | else if (iter_data.nadhocs) | |
937 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
938 | else | |
939 | ah->opmode = NL80211_IFTYPE_STATION; | |
940 | } | |
5640b08e | 941 | |
df35d29e SM |
942 | ath9k_hw_setopmode(ah); |
943 | ||
198823fd | 944 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) |
3069168c | 945 | ah->imask |= ATH9K_INT_TSFOOR; |
198823fd | 946 | else |
4801416c | 947 | ah->imask &= ~ATH9K_INT_TSFOOR; |
4af9cf4f | 948 | |
72d874c6 | 949 | ath9k_hw_set_interrupts(ah); |
6dcc3444 SM |
950 | |
951 | /* | |
952 | * If we are changing the opmode to STATION, | |
953 | * a beacon sync needs to be done. | |
954 | */ | |
955 | if (ah->opmode == NL80211_IFTYPE_STATION && | |
956 | old_opmode == NL80211_IFTYPE_AP && | |
957 | test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
8b2c9824 JB |
958 | ieee80211_iterate_active_interfaces_atomic( |
959 | sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, | |
960 | ath9k_sta_vif_iter, sc); | |
6dcc3444 | 961 | } |
4801416c | 962 | } |
6f255425 | 963 | |
4801416c BG |
964 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
965 | struct ieee80211_vif *vif) | |
6b3b991d | 966 | { |
9ac58615 | 967 | struct ath_softc *sc = hw->priv; |
4801416c BG |
968 | struct ath_hw *ah = sc->sc_ah; |
969 | struct ath_common *common = ath9k_hw_common(ah); | |
6b3b991d | 970 | |
4801416c | 971 | mutex_lock(&sc->mutex); |
6b3b991d | 972 | |
d2182b69 | 973 | ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); |
4801416c BG |
974 | sc->nvifs++; |
975 | ||
327967cb | 976 | ath9k_ps_wakeup(sc); |
130ef6e9 | 977 | ath9k_calculate_summary_state(hw, vif); |
327967cb MSS |
978 | ath9k_ps_restore(sc); |
979 | ||
130ef6e9 SM |
980 | if (ath9k_uses_beacons(vif->type)) |
981 | ath9k_beacon_assign_slot(sc, vif); | |
982 | ||
4801416c | 983 | mutex_unlock(&sc->mutex); |
327967cb | 984 | return 0; |
6b3b991d RM |
985 | } |
986 | ||
987 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
988 | struct ieee80211_vif *vif, | |
989 | enum nl80211_iftype new_type, | |
990 | bool p2p) | |
991 | { | |
9ac58615 | 992 | struct ath_softc *sc = hw->priv; |
6b3b991d RM |
993 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
994 | ||
d2182b69 | 995 | ath_dbg(common, CONFIG, "Change Interface\n"); |
6b3b991d | 996 | mutex_lock(&sc->mutex); |
4801416c | 997 | |
4801416c | 998 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 999 | ath9k_beacon_remove_slot(sc, vif); |
4801416c | 1000 | |
6b3b991d RM |
1001 | vif->type = new_type; |
1002 | vif->p2p = p2p; | |
1003 | ||
327967cb | 1004 | ath9k_ps_wakeup(sc); |
130ef6e9 | 1005 | ath9k_calculate_summary_state(hw, vif); |
327967cb MSS |
1006 | ath9k_ps_restore(sc); |
1007 | ||
130ef6e9 SM |
1008 | if (ath9k_uses_beacons(vif->type)) |
1009 | ath9k_beacon_assign_slot(sc, vif); | |
1010 | ||
6b3b991d | 1011 | mutex_unlock(&sc->mutex); |
327967cb | 1012 | return 0; |
6b3b991d RM |
1013 | } |
1014 | ||
8feceb67 | 1015 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1016 | struct ieee80211_vif *vif) |
f078f209 | 1017 | { |
9ac58615 | 1018 | struct ath_softc *sc = hw->priv; |
c46917bb | 1019 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 | 1020 | |
d2182b69 | 1021 | ath_dbg(common, CONFIG, "Detach Interface\n"); |
f078f209 | 1022 | |
141b38b6 S |
1023 | mutex_lock(&sc->mutex); |
1024 | ||
4801416c | 1025 | sc->nvifs--; |
580f0b8a | 1026 | |
4801416c | 1027 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1028 | ath9k_beacon_remove_slot(sc, vif); |
2c3db3d5 | 1029 | |
327967cb | 1030 | ath9k_ps_wakeup(sc); |
4801416c | 1031 | ath9k_calculate_summary_state(hw, NULL); |
327967cb | 1032 | ath9k_ps_restore(sc); |
141b38b6 S |
1033 | |
1034 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1035 | } |
1036 | ||
fbab7390 | 1037 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1038 | { |
3069168c | 1039 | struct ath_hw *ah = sc->sc_ah; |
ad128860 | 1040 | struct ath_common *common = ath9k_hw_common(ah); |
3069168c | 1041 | |
3f7c5c10 | 1042 | sc->ps_enabled = true; |
3069168c PR |
1043 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1044 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1045 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1046 | ath9k_hw_set_interrupts(ah); |
3f7c5c10 | 1047 | } |
fdf76622 | 1048 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1049 | } |
ad128860 | 1050 | ath_dbg(common, PS, "PowerSave enabled\n"); |
3f7c5c10 SB |
1051 | } |
1052 | ||
845d708e SB |
1053 | static void ath9k_disable_ps(struct ath_softc *sc) |
1054 | { | |
1055 | struct ath_hw *ah = sc->sc_ah; | |
ad128860 | 1056 | struct ath_common *common = ath9k_hw_common(ah); |
845d708e SB |
1057 | |
1058 | sc->ps_enabled = false; | |
1059 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1060 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1061 | ath9k_hw_setrxabort(ah, 0); | |
1062 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1063 | PS_WAIT_FOR_CAB | | |
1064 | PS_WAIT_FOR_PSPOLL_DATA | | |
1065 | PS_WAIT_FOR_TX_ACK); | |
1066 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1067 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1068 | ath9k_hw_set_interrupts(ah); |
845d708e SB |
1069 | } |
1070 | } | |
ad128860 | 1071 | ath_dbg(common, PS, "PowerSave disabled\n"); |
845d708e SB |
1072 | } |
1073 | ||
e93d083f SW |
1074 | void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw) |
1075 | { | |
1076 | struct ath_softc *sc = hw->priv; | |
1077 | struct ath_hw *ah = sc->sc_ah; | |
1078 | struct ath_common *common = ath9k_hw_common(ah); | |
1079 | u32 rxfilter; | |
1080 | ||
1081 | if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { | |
1082 | ath_err(common, "spectrum analyzer not implemented on this hardware\n"); | |
1083 | return; | |
1084 | } | |
1085 | ||
1086 | ath9k_ps_wakeup(sc); | |
1087 | rxfilter = ath9k_hw_getrxfilter(ah); | |
1088 | ath9k_hw_setrxfilter(ah, rxfilter | | |
1089 | ATH9K_RX_FILTER_PHYRADAR | | |
1090 | ATH9K_RX_FILTER_PHYERR); | |
1091 | ||
1092 | /* TODO: usually this should not be neccesary, but for some reason | |
1093 | * (or in some mode?) the trigger must be called after the | |
1094 | * configuration, otherwise the register will have its values reset | |
1095 | * (on my ar9220 to value 0x01002310) | |
1096 | */ | |
1097 | ath9k_spectral_scan_config(hw, sc->spectral_mode); | |
1098 | ath9k_hw_ops(ah)->spectral_scan_trigger(ah); | |
1099 | ath9k_ps_restore(sc); | |
1100 | } | |
1101 | ||
1102 | int ath9k_spectral_scan_config(struct ieee80211_hw *hw, | |
1103 | enum spectral_mode spectral_mode) | |
1104 | { | |
1105 | struct ath_softc *sc = hw->priv; | |
1106 | struct ath_hw *ah = sc->sc_ah; | |
1107 | struct ath_common *common = ath9k_hw_common(ah); | |
e93d083f SW |
1108 | |
1109 | if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { | |
1110 | ath_err(common, "spectrum analyzer not implemented on this hardware\n"); | |
1111 | return -1; | |
1112 | } | |
1113 | ||
e93d083f SW |
1114 | switch (spectral_mode) { |
1115 | case SPECTRAL_DISABLED: | |
04ccd4a1 | 1116 | sc->spec_config.enabled = 0; |
e93d083f SW |
1117 | break; |
1118 | case SPECTRAL_BACKGROUND: | |
1119 | /* send endless samples. | |
1120 | * TODO: is this really useful for "background"? | |
1121 | */ | |
04ccd4a1 SW |
1122 | sc->spec_config.endless = 1; |
1123 | sc->spec_config.enabled = 1; | |
e93d083f SW |
1124 | break; |
1125 | case SPECTRAL_CHANSCAN: | |
e93d083f | 1126 | case SPECTRAL_MANUAL: |
04ccd4a1 SW |
1127 | sc->spec_config.endless = 0; |
1128 | sc->spec_config.enabled = 1; | |
e93d083f SW |
1129 | break; |
1130 | default: | |
1131 | return -1; | |
1132 | } | |
1133 | ||
1134 | ath9k_ps_wakeup(sc); | |
04ccd4a1 | 1135 | ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config); |
e93d083f SW |
1136 | ath9k_ps_restore(sc); |
1137 | ||
1138 | sc->spectral_mode = spectral_mode; | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
e8975581 | 1143 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1144 | { |
9ac58615 | 1145 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1146 | struct ath_hw *ah = sc->sc_ah; |
1147 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1148 | struct ieee80211_conf *conf = &hw->conf; |
75600abf | 1149 | bool reset_channel = false; |
f078f209 | 1150 | |
c0c11741 | 1151 | ath9k_ps_wakeup(sc); |
aa33de09 | 1152 | mutex_lock(&sc->mutex); |
141b38b6 | 1153 | |
daa1b6ee | 1154 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 | 1155 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
b73f3e78 | 1156 | if (sc->ps_idle) { |
daa1b6ee | 1157 | ath_cancel_work(sc); |
b73f3e78 RM |
1158 | ath9k_stop_btcoex(sc); |
1159 | } else { | |
1160 | ath9k_start_btcoex(sc); | |
75600abf FF |
1161 | /* |
1162 | * The chip needs a reset to properly wake up from | |
1163 | * full sleep | |
1164 | */ | |
1165 | reset_channel = ah->chip_fullsleep; | |
b73f3e78 | 1166 | } |
daa1b6ee | 1167 | } |
64839170 | 1168 | |
e7824a50 LR |
1169 | /* |
1170 | * We just prepare to enable PS. We have to wait until our AP has | |
1171 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1172 | * those ACKs and end up retransmitting the same null data frames. | |
1173 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1174 | */ | |
3cbb5dd7 | 1175 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1176 | unsigned long flags; |
1177 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1178 | if (conf->flags & IEEE80211_CONF_PS) |
1179 | ath9k_enable_ps(sc); | |
845d708e SB |
1180 | else |
1181 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1182 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1183 | } |
1184 | ||
199afd9d S |
1185 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1186 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
d2182b69 | 1187 | ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); |
5f841b41 RM |
1188 | sc->sc_ah->is_monitoring = true; |
1189 | } else { | |
d2182b69 | 1190 | ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); |
5f841b41 | 1191 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1192 | } |
1193 | } | |
1194 | ||
75600abf | 1195 | if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { |
675a0b04 KB |
1196 | struct ieee80211_channel *curchan = hw->conf.chandef.chan; |
1197 | enum nl80211_channel_type channel_type = | |
1198 | cfg80211_get_chandef_type(&conf->chandef); | |
5f8e077c | 1199 | int pos = curchan->hw_value; |
3430098a FF |
1200 | int old_pos = -1; |
1201 | unsigned long flags; | |
1202 | ||
1203 | if (ah->curchan) | |
1204 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1205 | |
d2182b69 | 1206 | ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", |
675a0b04 | 1207 | curchan->center_freq, channel_type); |
f078f209 | 1208 | |
3430098a FF |
1209 | /* update survey stats for the old channel before switching */ |
1210 | spin_lock_irqsave(&common->cc_lock, flags); | |
1211 | ath_update_survey_stats(sc); | |
1212 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1213 | ||
e338a85e RM |
1214 | /* |
1215 | * Preserve the current channel values, before updating | |
1216 | * the same channel | |
1217 | */ | |
1a19f77f RM |
1218 | if (ah->curchan && (old_pos == pos)) |
1219 | ath9k_hw_getnf(ah, ah->curchan); | |
e338a85e RM |
1220 | |
1221 | ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], | |
675a0b04 | 1222 | curchan, channel_type); |
e338a85e | 1223 | |
3430098a FF |
1224 | /* |
1225 | * If the operating channel changes, change the survey in-use flags | |
1226 | * along with it. | |
1227 | * Reset the survey data for the new channel, unless we're switching | |
1228 | * back to the operating channel from an off-channel operation. | |
1229 | */ | |
1230 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1231 | sc->cur_survey != &sc->survey[pos]) { | |
1232 | ||
1233 | if (sc->cur_survey) | |
1234 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1235 | ||
1236 | sc->cur_survey = &sc->survey[pos]; | |
1237 | ||
1238 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1239 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1240 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1241 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1242 | } | |
1243 | ||
0e2dedf9 | 1244 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
3800276a | 1245 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1246 | mutex_unlock(&sc->mutex); |
8389fb3f | 1247 | ath9k_ps_restore(sc); |
e11602b7 S |
1248 | return -EINVAL; |
1249 | } | |
3430098a FF |
1250 | |
1251 | /* | |
1252 | * The most recent snapshot of channel->noisefloor for the old | |
1253 | * channel is only available after the hardware reset. Copy it to | |
1254 | * the survey stats now. | |
1255 | */ | |
1256 | if (old_pos >= 0) | |
1257 | ath_update_survey_nf(sc, old_pos); | |
e93d083f | 1258 | |
73e4937d ZK |
1259 | /* |
1260 | * Enable radar pulse detection if on a DFS channel. Spectral | |
1261 | * scanning and radar detection can not be used concurrently. | |
1262 | */ | |
1263 | if (hw->conf.radar_enabled) { | |
1264 | u32 rxfilter; | |
1265 | ||
1266 | /* set HW specific DFS configuration */ | |
1267 | ath9k_hw_set_radar_params(ah); | |
1268 | rxfilter = ath9k_hw_getrxfilter(ah); | |
1269 | rxfilter |= ATH9K_RX_FILTER_PHYRADAR | | |
1270 | ATH9K_RX_FILTER_PHYERR; | |
1271 | ath9k_hw_setrxfilter(ah, rxfilter); | |
1272 | ath_dbg(common, DFS, "DFS enabled at freq %d\n", | |
1273 | curchan->center_freq); | |
1274 | } else { | |
1275 | /* perform spectral scan if requested. */ | |
1276 | if (sc->scanning && | |
1277 | sc->spectral_mode == SPECTRAL_CHANSCAN) | |
1278 | ath9k_spectral_scan_trigger(hw); | |
1279 | } | |
094d05dc | 1280 | } |
f078f209 | 1281 | |
c9f6a656 | 1282 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
d2182b69 | 1283 | ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); |
17d7904d | 1284 | sc->config.txpowlimit = 2 * conf->power_level; |
5048e8c3 RM |
1285 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1286 | sc->config.txpowlimit, &sc->curtxpow); | |
64839170 LR |
1287 | } |
1288 | ||
aa33de09 | 1289 | mutex_unlock(&sc->mutex); |
c0c11741 | 1290 | ath9k_ps_restore(sc); |
141b38b6 | 1291 | |
f078f209 LR |
1292 | return 0; |
1293 | } | |
1294 | ||
8feceb67 VT |
1295 | #define SUPPORTED_FILTERS \ |
1296 | (FIF_PROMISC_IN_BSS | \ | |
1297 | FIF_ALLMULTI | \ | |
1298 | FIF_CONTROL | \ | |
af6a3fc7 | 1299 | FIF_PSPOLL | \ |
8feceb67 VT |
1300 | FIF_OTHER_BSS | \ |
1301 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1302 | FIF_PROBE_REQ | \ |
8feceb67 | 1303 | FIF_FCSFAIL) |
c83be688 | 1304 | |
8feceb67 VT |
1305 | /* FIXME: sc->sc_full_reset ? */ |
1306 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1307 | unsigned int changed_flags, | |
1308 | unsigned int *total_flags, | |
3ac64bee | 1309 | u64 multicast) |
8feceb67 | 1310 | { |
9ac58615 | 1311 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1312 | u32 rfilt; |
f078f209 | 1313 | |
8feceb67 VT |
1314 | changed_flags &= SUPPORTED_FILTERS; |
1315 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1316 | |
b77f483f | 1317 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1318 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1319 | rfilt = ath_calcrxfilter(sc); |
1320 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1321 | ath9k_ps_restore(sc); |
f078f209 | 1322 | |
d2182b69 JP |
1323 | ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", |
1324 | rfilt); | |
8feceb67 | 1325 | } |
f078f209 | 1326 | |
4ca77860 JB |
1327 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1328 | struct ieee80211_vif *vif, | |
1329 | struct ieee80211_sta *sta) | |
8feceb67 | 1330 | { |
9ac58615 | 1331 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1332 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1333 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1334 | struct ieee80211_key_conf ps_key = { }; | |
4ef69d03 | 1335 | int key; |
f078f209 | 1336 | |
7e1e3864 | 1337 | ath_node_attach(sc, sta, vif); |
f59a59fe FF |
1338 | |
1339 | if (vif->type != NL80211_IFTYPE_AP && | |
1340 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1341 | return 0; | |
1342 | ||
4ef69d03 FF |
1343 | key = ath_key_config(common, vif, sta, &ps_key); |
1344 | if (key > 0) | |
1345 | an->ps_key = key; | |
4ca77860 JB |
1346 | |
1347 | return 0; | |
1348 | } | |
1349 | ||
93ae2dd2 FF |
1350 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1351 | struct ieee80211_vif *vif, | |
1352 | struct ieee80211_sta *sta) | |
1353 | { | |
1354 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1355 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1356 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1357 | ||
1358 | if (!an->ps_key) | |
1359 | return; | |
1360 | ||
1361 | ath_key_delete(common, &ps_key); | |
4ef69d03 | 1362 | an->ps_key = 0; |
93ae2dd2 FF |
1363 | } |
1364 | ||
4ca77860 JB |
1365 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1366 | struct ieee80211_vif *vif, | |
1367 | struct ieee80211_sta *sta) | |
1368 | { | |
9ac58615 | 1369 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1370 | |
93ae2dd2 | 1371 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1372 | ath_node_detach(sc, sta); |
1373 | ||
1374 | return 0; | |
f078f209 LR |
1375 | } |
1376 | ||
5519541d FF |
1377 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1378 | struct ieee80211_vif *vif, | |
1379 | enum sta_notify_cmd cmd, | |
1380 | struct ieee80211_sta *sta) | |
1381 | { | |
1382 | struct ath_softc *sc = hw->priv; | |
1383 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1384 | ||
3d4e20f2 | 1385 | if (!sta->ht_cap.ht_supported) |
b25bfda3 MSS |
1386 | return; |
1387 | ||
5519541d FF |
1388 | switch (cmd) { |
1389 | case STA_NOTIFY_SLEEP: | |
1390 | an->sleeping = true; | |
042ec453 | 1391 | ath_tx_aggr_sleep(sta, sc, an); |
5519541d FF |
1392 | break; |
1393 | case STA_NOTIFY_AWAKE: | |
1394 | an->sleeping = false; | |
1395 | ath_tx_aggr_wakeup(sc, an); | |
1396 | break; | |
1397 | } | |
1398 | } | |
1399 | ||
8a3a3c85 EP |
1400 | static int ath9k_conf_tx(struct ieee80211_hw *hw, |
1401 | struct ieee80211_vif *vif, u16 queue, | |
8feceb67 | 1402 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1403 | { |
9ac58615 | 1404 | struct ath_softc *sc = hw->priv; |
c46917bb | 1405 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1406 | struct ath_txq *txq; |
8feceb67 | 1407 | struct ath9k_tx_queue_info qi; |
066dae93 | 1408 | int ret = 0; |
f078f209 | 1409 | |
bea843c7 | 1410 | if (queue >= IEEE80211_NUM_ACS) |
8feceb67 | 1411 | return 0; |
f078f209 | 1412 | |
066dae93 FF |
1413 | txq = sc->tx.txq_map[queue]; |
1414 | ||
96f372c9 | 1415 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1416 | mutex_lock(&sc->mutex); |
1417 | ||
1ffb0610 S |
1418 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1419 | ||
8feceb67 VT |
1420 | qi.tqi_aifs = params->aifs; |
1421 | qi.tqi_cwmin = params->cw_min; | |
1422 | qi.tqi_cwmax = params->cw_max; | |
531bd079 | 1423 | qi.tqi_burstTime = params->txop * 32; |
f078f209 | 1424 | |
d2182b69 | 1425 | ath_dbg(common, CONFIG, |
226afe68 JP |
1426 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1427 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1428 | params->cw_max, params->txop); | |
f078f209 | 1429 | |
aa5955c3 | 1430 | ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); |
066dae93 | 1431 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1432 | if (ret) |
3800276a | 1433 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1434 | |
141b38b6 | 1435 | mutex_unlock(&sc->mutex); |
96f372c9 | 1436 | ath9k_ps_restore(sc); |
141b38b6 | 1437 | |
8feceb67 VT |
1438 | return ret; |
1439 | } | |
f078f209 | 1440 | |
8feceb67 VT |
1441 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1442 | enum set_key_cmd cmd, | |
dc822b5d JB |
1443 | struct ieee80211_vif *vif, |
1444 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1445 | struct ieee80211_key_conf *key) |
1446 | { | |
9ac58615 | 1447 | struct ath_softc *sc = hw->priv; |
c46917bb | 1448 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1449 | int ret = 0; |
f078f209 | 1450 | |
3e6109c5 | 1451 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1452 | return -ENOSPC; |
1453 | ||
5bd5e9a6 CYY |
1454 | if ((vif->type == NL80211_IFTYPE_ADHOC || |
1455 | vif->type == NL80211_IFTYPE_MESH_POINT) && | |
cfdc9a8b JM |
1456 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || |
1457 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1458 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1459 | /* | |
1460 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1461 | * could be optimized in the future to use a modified key cache | |
1462 | * design to support per-STA RX GTK, but until that gets | |
1463 | * implemented, use of software crypto for group addressed | |
1464 | * frames is a acceptable to allow RSN IBSS to be used. | |
1465 | */ | |
1466 | return -EOPNOTSUPP; | |
1467 | } | |
1468 | ||
141b38b6 | 1469 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1470 | ath9k_ps_wakeup(sc); |
d2182b69 | 1471 | ath_dbg(common, CONFIG, "Set HW Key\n"); |
f078f209 | 1472 | |
8feceb67 VT |
1473 | switch (cmd) { |
1474 | case SET_KEY: | |
93ae2dd2 FF |
1475 | if (sta) |
1476 | ath9k_del_ps_key(sc, vif, sta); | |
1477 | ||
040e539e | 1478 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1479 | if (ret >= 0) { |
1480 | key->hw_key_idx = ret; | |
8feceb67 VT |
1481 | /* push IV and Michael MIC generation to stack */ |
1482 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1483 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1484 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1485 | if (sc->sc_ah->sw_mgmt_crypto && |
1486 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
e548c49e | 1487 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; |
6ace2891 | 1488 | ret = 0; |
8feceb67 VT |
1489 | } |
1490 | break; | |
1491 | case DISABLE_KEY: | |
040e539e | 1492 | ath_key_delete(common, key); |
8feceb67 VT |
1493 | break; |
1494 | default: | |
1495 | ret = -EINVAL; | |
1496 | } | |
f078f209 | 1497 | |
3cbb5dd7 | 1498 | ath9k_ps_restore(sc); |
141b38b6 S |
1499 | mutex_unlock(&sc->mutex); |
1500 | ||
8feceb67 VT |
1501 | return ret; |
1502 | } | |
6c43c090 SM |
1503 | |
1504 | static void ath9k_set_assoc_state(struct ath_softc *sc, | |
1505 | struct ieee80211_vif *vif) | |
4f5ef75b | 1506 | { |
4f5ef75b | 1507 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4f5ef75b | 1508 | struct ath_vif *avp = (void *)vif->drv_priv; |
6c43c090 | 1509 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; |
07c15a3f | 1510 | unsigned long flags; |
6c43c090 SM |
1511 | |
1512 | set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); | |
1513 | avp->primary_sta_vif = true; | |
1514 | ||
2e5ef459 | 1515 | /* |
6c43c090 SM |
1516 | * Set the AID, BSSID and do beacon-sync only when |
1517 | * the HW opmode is STATION. | |
1518 | * | |
1519 | * But the primary bit is set above in any case. | |
2e5ef459 | 1520 | */ |
6c43c090 | 1521 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
2e5ef459 RM |
1522 | return; |
1523 | ||
6c43c090 SM |
1524 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1525 | common->curaid = bss_conf->aid; | |
1526 | ath9k_hw_write_associd(sc->sc_ah); | |
07c15a3f | 1527 | |
6c43c090 SM |
1528 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
1529 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
99e4d43a | 1530 | |
6c43c090 SM |
1531 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
1532 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
1533 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
05c0be2f | 1534 | |
50072ebc RM |
1535 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
1536 | ath9k_mci_update_wlan_channels(sc, false); | |
1537 | ||
6c43c090 SM |
1538 | ath_dbg(common, CONFIG, |
1539 | "Primary Station interface: %pM, BSSID: %pM\n", | |
1540 | vif->addr, common->curbssid); | |
4f5ef75b RM |
1541 | } |
1542 | ||
6c43c090 | 1543 | static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
4f5ef75b | 1544 | { |
6c43c090 | 1545 | struct ath_softc *sc = data; |
4f5ef75b | 1546 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; |
4f5ef75b | 1547 | |
6c43c090 | 1548 | if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) |
2e5ef459 RM |
1549 | return; |
1550 | ||
6c43c090 SM |
1551 | if (bss_conf->assoc) |
1552 | ath9k_set_assoc_state(sc, vif); | |
4f5ef75b | 1553 | } |
f078f209 | 1554 | |
8feceb67 VT |
1555 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1556 | struct ieee80211_vif *vif, | |
1557 | struct ieee80211_bss_conf *bss_conf, | |
1558 | u32 changed) | |
1559 | { | |
da0d45f7 SM |
1560 | #define CHECK_ANI \ |
1561 | (BSS_CHANGED_ASSOC | \ | |
1562 | BSS_CHANGED_IBSS | \ | |
1563 | BSS_CHANGED_BEACON_ENABLED) | |
1564 | ||
9ac58615 | 1565 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 1566 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1567 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1568 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1569 | int slottime; |
f078f209 | 1570 | |
96f372c9 | 1571 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1572 | mutex_lock(&sc->mutex); |
1573 | ||
9f61903c | 1574 | if (changed & BSS_CHANGED_ASSOC) { |
6c43c090 SM |
1575 | ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", |
1576 | bss_conf->bssid, bss_conf->assoc); | |
1577 | ||
1578 | if (avp->primary_sta_vif && !bss_conf->assoc) { | |
1579 | clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); | |
1580 | avp->primary_sta_vif = false; | |
1581 | ||
1582 | if (ah->opmode == NL80211_IFTYPE_STATION) | |
1583 | clear_bit(SC_OP_BEACONS, &sc->sc_flags); | |
1584 | } | |
1585 | ||
8b2c9824 JB |
1586 | ieee80211_iterate_active_interfaces_atomic( |
1587 | sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, | |
1588 | ath9k_bss_assoc_iter, sc); | |
2d0ddec5 | 1589 | |
6c43c090 SM |
1590 | if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) && |
1591 | ah->opmode == NL80211_IFTYPE_STATION) { | |
1592 | memset(common->curbssid, 0, ETH_ALEN); | |
1593 | common->curaid = 0; | |
1594 | ath9k_hw_write_associd(sc->sc_ah); | |
50072ebc RM |
1595 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
1596 | ath9k_mci_update_wlan_channels(sc, true); | |
6c43c090 | 1597 | } |
c6089ccc | 1598 | } |
2d0ddec5 | 1599 | |
2e5ef459 | 1600 | if (changed & BSS_CHANGED_IBSS) { |
2e5ef459 RM |
1601 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1602 | common->curaid = bss_conf->aid; | |
1603 | ath9k_hw_write_associd(sc->sc_ah); | |
2e5ef459 RM |
1604 | } |
1605 | ||
ef4ad633 SM |
1606 | if ((changed & BSS_CHANGED_BEACON_ENABLED) || |
1607 | (changed & BSS_CHANGED_BEACON_INT)) { | |
2f8e82e8 SM |
1608 | if (ah->opmode == NL80211_IFTYPE_AP && |
1609 | bss_conf->enable_beacon) | |
1610 | ath9k_set_tsfadjust(sc, vif); | |
ef4ad633 SM |
1611 | if (ath9k_allow_beacon_config(sc, vif)) |
1612 | ath9k_beacon_config(sc, vif, changed); | |
0005baf4 FF |
1613 | } |
1614 | ||
1615 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1616 | if (bss_conf->use_short_slot) | |
1617 | slottime = 9; | |
1618 | else | |
1619 | slottime = 20; | |
1620 | if (vif->type == NL80211_IFTYPE_AP) { | |
1621 | /* | |
1622 | * Defer update, so that connected stations can adjust | |
1623 | * their settings at the same time. | |
1624 | * See beacon.c for more details | |
1625 | */ | |
1626 | sc->beacon.slottime = slottime; | |
1627 | sc->beacon.updateslot = UPDATE; | |
1628 | } else { | |
1629 | ah->slottime = slottime; | |
1630 | ath9k_hw_init_global_settings(ah); | |
1631 | } | |
2d0ddec5 JB |
1632 | } |
1633 | ||
da0d45f7 SM |
1634 | if (changed & CHECK_ANI) |
1635 | ath_check_ani(sc); | |
1636 | ||
141b38b6 | 1637 | mutex_unlock(&sc->mutex); |
96f372c9 | 1638 | ath9k_ps_restore(sc); |
da0d45f7 SM |
1639 | |
1640 | #undef CHECK_ANI | |
8feceb67 | 1641 | } |
f078f209 | 1642 | |
37a41b4a | 1643 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1644 | { |
9ac58615 | 1645 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1646 | u64 tsf; |
f078f209 | 1647 | |
141b38b6 | 1648 | mutex_lock(&sc->mutex); |
9abbfb27 | 1649 | ath9k_ps_wakeup(sc); |
141b38b6 | 1650 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 1651 | ath9k_ps_restore(sc); |
141b38b6 | 1652 | mutex_unlock(&sc->mutex); |
f078f209 | 1653 | |
8feceb67 VT |
1654 | return tsf; |
1655 | } | |
f078f209 | 1656 | |
37a41b4a EP |
1657 | static void ath9k_set_tsf(struct ieee80211_hw *hw, |
1658 | struct ieee80211_vif *vif, | |
1659 | u64 tsf) | |
3b5d665b | 1660 | { |
9ac58615 | 1661 | struct ath_softc *sc = hw->priv; |
3b5d665b | 1662 | |
141b38b6 | 1663 | mutex_lock(&sc->mutex); |
9abbfb27 | 1664 | ath9k_ps_wakeup(sc); |
141b38b6 | 1665 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 1666 | ath9k_ps_restore(sc); |
141b38b6 | 1667 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
1668 | } |
1669 | ||
37a41b4a | 1670 | static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1671 | { |
9ac58615 | 1672 | struct ath_softc *sc = hw->priv; |
c83be688 | 1673 | |
141b38b6 | 1674 | mutex_lock(&sc->mutex); |
21526d57 LR |
1675 | |
1676 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1677 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1678 | ath9k_ps_restore(sc); |
1679 | ||
141b38b6 | 1680 | mutex_unlock(&sc->mutex); |
8feceb67 | 1681 | } |
f078f209 | 1682 | |
8feceb67 | 1683 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1684 | struct ieee80211_vif *vif, |
141b38b6 S |
1685 | enum ieee80211_ampdu_mlme_action action, |
1686 | struct ieee80211_sta *sta, | |
0b01f030 | 1687 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 1688 | { |
9ac58615 | 1689 | struct ath_softc *sc = hw->priv; |
16e23428 | 1690 | bool flush = false; |
8feceb67 | 1691 | int ret = 0; |
f078f209 | 1692 | |
85ad181e JB |
1693 | local_bh_disable(); |
1694 | ||
8feceb67 VT |
1695 | switch (action) { |
1696 | case IEEE80211_AMPDU_RX_START: | |
8feceb67 VT |
1697 | break; |
1698 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1699 | break; |
1700 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1701 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
1702 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
1703 | if (!ret) | |
1704 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 1705 | ath9k_ps_restore(sc); |
8feceb67 | 1706 | break; |
18b559d5 JB |
1707 | case IEEE80211_AMPDU_TX_STOP_FLUSH: |
1708 | case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: | |
16e23428 FF |
1709 | flush = true; |
1710 | case IEEE80211_AMPDU_TX_STOP_CONT: | |
8b685ba9 | 1711 | ath9k_ps_wakeup(sc); |
08c96abd FF |
1712 | ath_tx_aggr_stop(sc, sta, tid); |
1713 | if (!flush) | |
16e23428 | 1714 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1715 | ath9k_ps_restore(sc); |
8feceb67 | 1716 | break; |
b1720231 | 1717 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1718 | ath9k_ps_wakeup(sc); |
8469cdef | 1719 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1720 | ath9k_ps_restore(sc); |
8469cdef | 1721 | break; |
8feceb67 | 1722 | default: |
3800276a | 1723 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
1724 | } |
1725 | ||
85ad181e JB |
1726 | local_bh_enable(); |
1727 | ||
8feceb67 | 1728 | return ret; |
f078f209 LR |
1729 | } |
1730 | ||
62dad5b0 BP |
1731 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1732 | struct survey_info *survey) | |
1733 | { | |
9ac58615 | 1734 | struct ath_softc *sc = hw->priv; |
3430098a | 1735 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 1736 | struct ieee80211_supported_band *sband; |
3430098a FF |
1737 | struct ieee80211_channel *chan; |
1738 | unsigned long flags; | |
1739 | int pos; | |
1740 | ||
1741 | spin_lock_irqsave(&common->cc_lock, flags); | |
1742 | if (idx == 0) | |
1743 | ath_update_survey_stats(sc); | |
39162dbe FF |
1744 | |
1745 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
1746 | if (sband && idx >= sband->n_channels) { | |
1747 | idx -= sband->n_channels; | |
1748 | sband = NULL; | |
1749 | } | |
62dad5b0 | 1750 | |
39162dbe FF |
1751 | if (!sband) |
1752 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 1753 | |
3430098a FF |
1754 | if (!sband || idx >= sband->n_channels) { |
1755 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1756 | return -ENOENT; | |
4f1a5a4b | 1757 | } |
62dad5b0 | 1758 | |
3430098a FF |
1759 | chan = &sband->channels[idx]; |
1760 | pos = chan->hw_value; | |
1761 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
1762 | survey->channel = chan; | |
1763 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1764 | ||
62dad5b0 BP |
1765 | return 0; |
1766 | } | |
1767 | ||
e239d859 FF |
1768 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
1769 | { | |
9ac58615 | 1770 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
1771 | struct ath_hw *ah = sc->sc_ah; |
1772 | ||
1773 | mutex_lock(&sc->mutex); | |
1774 | ah->coverage_class = coverage_class; | |
8b2a3827 MSS |
1775 | |
1776 | ath9k_ps_wakeup(sc); | |
e239d859 | 1777 | ath9k_hw_init_global_settings(ah); |
8b2a3827 MSS |
1778 | ath9k_ps_restore(sc); |
1779 | ||
e239d859 FF |
1780 | mutex_unlock(&sc->mutex); |
1781 | } | |
1782 | ||
39ecc01d | 1783 | static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop) |
69081624 | 1784 | { |
69081624 | 1785 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
1786 | struct ath_hw *ah = sc->sc_ah; |
1787 | struct ath_common *common = ath9k_hw_common(ah); | |
86271e46 FF |
1788 | int timeout = 200; /* ms */ |
1789 | int i, j; | |
2f6fc351 | 1790 | bool drain_txq; |
69081624 VT |
1791 | |
1792 | mutex_lock(&sc->mutex); | |
69081624 VT |
1793 | cancel_delayed_work_sync(&sc->tx_complete_work); |
1794 | ||
6a6b3f3e | 1795 | if (ah->ah_flags & AH_UNPLUGGED) { |
d2182b69 | 1796 | ath_dbg(common, ANY, "Device has been unplugged!\n"); |
6a6b3f3e MSS |
1797 | mutex_unlock(&sc->mutex); |
1798 | return; | |
1799 | } | |
1800 | ||
781b14a3 | 1801 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { |
d2182b69 | 1802 | ath_dbg(common, ANY, "Device not present\n"); |
99aa55b6 MSS |
1803 | mutex_unlock(&sc->mutex); |
1804 | return; | |
1805 | } | |
1806 | ||
86271e46 | 1807 | for (j = 0; j < timeout; j++) { |
108697c4 | 1808 | bool npend = false; |
86271e46 FF |
1809 | |
1810 | if (j) | |
1811 | usleep_range(1000, 2000); | |
69081624 | 1812 | |
86271e46 FF |
1813 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
1814 | if (!ATH_TXQ_SETUP(sc, i)) | |
1815 | continue; | |
1816 | ||
108697c4 MSS |
1817 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); |
1818 | ||
1819 | if (npend) | |
1820 | break; | |
69081624 | 1821 | } |
86271e46 FF |
1822 | |
1823 | if (!npend) | |
9df0d6a2 | 1824 | break; |
69081624 VT |
1825 | } |
1826 | ||
9df0d6a2 FF |
1827 | if (drop) { |
1828 | ath9k_ps_wakeup(sc); | |
1829 | spin_lock_bh(&sc->sc_pcu_lock); | |
1381559b | 1830 | drain_txq = ath_drain_all_txq(sc); |
9df0d6a2 | 1831 | spin_unlock_bh(&sc->sc_pcu_lock); |
9adcf440 | 1832 | |
9df0d6a2 | 1833 | if (!drain_txq) |
1381559b | 1834 | ath_reset(sc); |
9adcf440 | 1835 | |
9df0d6a2 FF |
1836 | ath9k_ps_restore(sc); |
1837 | ieee80211_wake_queues(hw); | |
1838 | } | |
d78f4b3e | 1839 | |
69081624 VT |
1840 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
1841 | mutex_unlock(&sc->mutex); | |
1842 | } | |
1843 | ||
15b91e83 VN |
1844 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
1845 | { | |
1846 | struct ath_softc *sc = hw->priv; | |
1847 | int i; | |
1848 | ||
1849 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1850 | if (!ATH_TXQ_SETUP(sc, i)) | |
1851 | continue; | |
1852 | ||
1853 | if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) | |
1854 | return true; | |
1855 | } | |
1856 | return false; | |
1857 | } | |
1858 | ||
5595f119 | 1859 | static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
ba4903f9 FF |
1860 | { |
1861 | struct ath_softc *sc = hw->priv; | |
1862 | struct ath_hw *ah = sc->sc_ah; | |
1863 | struct ieee80211_vif *vif; | |
1864 | struct ath_vif *avp; | |
1865 | struct ath_buf *bf; | |
1866 | struct ath_tx_status ts; | |
4286df60 | 1867 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
ba4903f9 FF |
1868 | int status; |
1869 | ||
1870 | vif = sc->beacon.bslot[0]; | |
1871 | if (!vif) | |
1872 | return 0; | |
1873 | ||
aa45fe96 | 1874 | if (!vif->bss_conf.enable_beacon) |
ba4903f9 FF |
1875 | return 0; |
1876 | ||
aa45fe96 SM |
1877 | avp = (void *)vif->drv_priv; |
1878 | ||
4286df60 | 1879 | if (!sc->beacon.tx_processed && !edma) { |
ba4903f9 FF |
1880 | tasklet_disable(&sc->bcon_tasklet); |
1881 | ||
1882 | bf = avp->av_bcbuf; | |
1883 | if (!bf || !bf->bf_mpdu) | |
1884 | goto skip; | |
1885 | ||
1886 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
1887 | if (status == -EINPROGRESS) | |
1888 | goto skip; | |
1889 | ||
1890 | sc->beacon.tx_processed = true; | |
1891 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
1892 | ||
1893 | skip: | |
1894 | tasklet_enable(&sc->bcon_tasklet); | |
1895 | } | |
1896 | ||
1897 | return sc->beacon.tx_last; | |
1898 | } | |
1899 | ||
52c94f41 MSS |
1900 | static int ath9k_get_stats(struct ieee80211_hw *hw, |
1901 | struct ieee80211_low_level_stats *stats) | |
1902 | { | |
1903 | struct ath_softc *sc = hw->priv; | |
1904 | struct ath_hw *ah = sc->sc_ah; | |
1905 | struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; | |
1906 | ||
1907 | stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; | |
1908 | stats->dot11RTSFailureCount = mib_stats->rts_bad; | |
1909 | stats->dot11FCSErrorCount = mib_stats->fcs_bad; | |
1910 | stats->dot11RTSSuccessCount = mib_stats->rts_good; | |
1911 | return 0; | |
1912 | } | |
1913 | ||
43c35284 FF |
1914 | static u32 fill_chainmask(u32 cap, u32 new) |
1915 | { | |
1916 | u32 filled = 0; | |
1917 | int i; | |
1918 | ||
1919 | for (i = 0; cap && new; i++, cap >>= 1) { | |
1920 | if (!(cap & BIT(0))) | |
1921 | continue; | |
1922 | ||
1923 | if (new & BIT(0)) | |
1924 | filled |= BIT(i); | |
1925 | ||
1926 | new >>= 1; | |
1927 | } | |
1928 | ||
1929 | return filled; | |
1930 | } | |
1931 | ||
5d9c7e3c FF |
1932 | static bool validate_antenna_mask(struct ath_hw *ah, u32 val) |
1933 | { | |
fea92cbf FF |
1934 | if (AR_SREV_9300_20_OR_LATER(ah)) |
1935 | return true; | |
1936 | ||
5d9c7e3c FF |
1937 | switch (val & 0x7) { |
1938 | case 0x1: | |
1939 | case 0x3: | |
1940 | case 0x7: | |
1941 | return true; | |
1942 | case 0x2: | |
1943 | return (ah->caps.rx_chainmask == 1); | |
1944 | default: | |
1945 | return false; | |
1946 | } | |
1947 | } | |
1948 | ||
43c35284 FF |
1949 | static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) |
1950 | { | |
1951 | struct ath_softc *sc = hw->priv; | |
1952 | struct ath_hw *ah = sc->sc_ah; | |
1953 | ||
5d9c7e3c FF |
1954 | if (ah->caps.rx_chainmask != 1) |
1955 | rx_ant |= tx_ant; | |
1956 | ||
1957 | if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) | |
43c35284 FF |
1958 | return -EINVAL; |
1959 | ||
1960 | sc->ant_rx = rx_ant; | |
1961 | sc->ant_tx = tx_ant; | |
1962 | ||
1963 | if (ah->caps.rx_chainmask == 1) | |
1964 | return 0; | |
1965 | ||
1966 | /* AR9100 runs into calibration issues if not all rx chains are enabled */ | |
1967 | if (AR_SREV_9100(ah)) | |
1968 | ah->rxchainmask = 0x7; | |
1969 | else | |
1970 | ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); | |
1971 | ||
1972 | ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); | |
1973 | ath9k_reload_chainmask_settings(sc); | |
1974 | ||
1975 | return 0; | |
1976 | } | |
1977 | ||
1978 | static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | |
1979 | { | |
1980 | struct ath_softc *sc = hw->priv; | |
1981 | ||
1982 | *tx_ant = sc->ant_tx; | |
1983 | *rx_ant = sc->ant_rx; | |
1984 | return 0; | |
1985 | } | |
1986 | ||
b11e640a MSS |
1987 | #ifdef CONFIG_PM_SLEEP |
1988 | ||
1989 | static void ath9k_wow_map_triggers(struct ath_softc *sc, | |
1990 | struct cfg80211_wowlan *wowlan, | |
1991 | u32 *wow_triggers) | |
1992 | { | |
1993 | if (wowlan->disconnect) | |
1994 | *wow_triggers |= AH_WOW_LINK_CHANGE | | |
1995 | AH_WOW_BEACON_MISS; | |
1996 | if (wowlan->magic_pkt) | |
1997 | *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN; | |
1998 | ||
1999 | if (wowlan->n_patterns) | |
2000 | *wow_triggers |= AH_WOW_USER_PATTERN_EN; | |
2001 | ||
2002 | sc->wow_enabled = *wow_triggers; | |
2003 | ||
2004 | } | |
2005 | ||
2006 | static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc) | |
2007 | { | |
2008 | struct ath_hw *ah = sc->sc_ah; | |
2009 | struct ath_common *common = ath9k_hw_common(ah); | |
2010 | struct ath9k_hw_capabilities *pcaps = &ah->caps; | |
2011 | int pattern_count = 0; | |
2012 | int i, byte_cnt; | |
2013 | u8 dis_deauth_pattern[MAX_PATTERN_SIZE]; | |
2014 | u8 dis_deauth_mask[MAX_PATTERN_SIZE]; | |
2015 | ||
2016 | memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE); | |
2017 | memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE); | |
2018 | ||
2019 | /* | |
2020 | * Create Dissassociate / Deauthenticate packet filter | |
2021 | * | |
2022 | * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes | |
2023 | * +--------------+----------+---------+--------+--------+---- | |
2024 | * + Frame Control+ Duration + DA + SA + BSSID + | |
2025 | * +--------------+----------+---------+--------+--------+---- | |
2026 | * | |
2027 | * The above is the management frame format for disassociate/ | |
2028 | * deauthenticate pattern, from this we need to match the first byte | |
2029 | * of 'Frame Control' and DA, SA, and BSSID fields | |
2030 | * (skipping 2nd byte of FC and Duration feild. | |
2031 | * | |
2032 | * Disassociate pattern | |
2033 | * -------------------- | |
2034 | * Frame control = 00 00 1010 | |
2035 | * DA, SA, BSSID = x:x:x:x:x:x | |
2036 | * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x | |
2037 | * | x:x:x:x:x:x -- 22 bytes | |
2038 | * | |
2039 | * Deauthenticate pattern | |
2040 | * ---------------------- | |
2041 | * Frame control = 00 00 1100 | |
2042 | * DA, SA, BSSID = x:x:x:x:x:x | |
2043 | * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x | |
2044 | * | x:x:x:x:x:x -- 22 bytes | |
2045 | */ | |
2046 | ||
2047 | /* Create Disassociate Pattern first */ | |
2048 | ||
2049 | byte_cnt = 0; | |
2050 | ||
2051 | /* Fill out the mask with all FF's */ | |
2052 | ||
2053 | for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++) | |
2054 | dis_deauth_mask[i] = 0xff; | |
2055 | ||
2056 | /* copy the first byte of frame control field */ | |
2057 | dis_deauth_pattern[byte_cnt] = 0xa0; | |
2058 | byte_cnt++; | |
2059 | ||
2060 | /* skip 2nd byte of frame control and Duration field */ | |
2061 | byte_cnt += 3; | |
2062 | ||
2063 | /* | |
2064 | * need not match the destination mac address, it can be a broadcast | |
2065 | * mac address or an unicast to this station | |
2066 | */ | |
2067 | byte_cnt += 6; | |
2068 | ||
2069 | /* copy the source mac address */ | |
2070 | memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); | |
2071 | ||
2072 | byte_cnt += 6; | |
2073 | ||
2074 | /* copy the bssid, its same as the source mac address */ | |
2075 | ||
2076 | memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); | |
2077 | ||
2078 | /* Create Disassociate pattern mask */ | |
2079 | ||
2080 | if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) { | |
2081 | ||
2082 | if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) { | |
2083 | /* | |
2084 | * for AR9280, because of hardware limitation, the | |
2085 | * first 4 bytes have to be matched for all patterns. | |
2086 | * the mask for disassociation and de-auth pattern | |
2087 | * matching need to enable the first 4 bytes. | |
2088 | * also the duration field needs to be filled. | |
2089 | */ | |
2090 | dis_deauth_mask[0] = 0xf0; | |
2091 | ||
2092 | /* | |
2093 | * fill in duration field | |
2094 | FIXME: what is the exact value ? | |
2095 | */ | |
2096 | dis_deauth_pattern[2] = 0xff; | |
2097 | dis_deauth_pattern[3] = 0xff; | |
2098 | } else { | |
2099 | dis_deauth_mask[0] = 0xfe; | |
2100 | } | |
2101 | ||
2102 | dis_deauth_mask[1] = 0x03; | |
2103 | dis_deauth_mask[2] = 0xc0; | |
2104 | } else { | |
2105 | dis_deauth_mask[0] = 0xef; | |
2106 | dis_deauth_mask[1] = 0x3f; | |
2107 | dis_deauth_mask[2] = 0x00; | |
2108 | dis_deauth_mask[3] = 0xfc; | |
2109 | } | |
2110 | ||
2111 | ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n"); | |
2112 | ||
2113 | ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, | |
2114 | pattern_count, byte_cnt); | |
2115 | ||
2116 | pattern_count++; | |
2117 | /* | |
2118 | * for de-authenticate pattern, only the first byte of the frame | |
2119 | * control field gets changed from 0xA0 to 0xC0 | |
2120 | */ | |
2121 | dis_deauth_pattern[0] = 0xC0; | |
2122 | ||
2123 | ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, | |
2124 | pattern_count, byte_cnt); | |
2125 | ||
2126 | } | |
2127 | ||
2128 | static void ath9k_wow_add_pattern(struct ath_softc *sc, | |
2129 | struct cfg80211_wowlan *wowlan) | |
2130 | { | |
2131 | struct ath_hw *ah = sc->sc_ah; | |
2132 | struct ath9k_wow_pattern *wow_pattern = NULL; | |
2133 | struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns; | |
2134 | int mask_len; | |
2135 | s8 i = 0; | |
2136 | ||
2137 | if (!wowlan->n_patterns) | |
2138 | return; | |
2139 | ||
2140 | /* | |
2141 | * Add the new user configured patterns | |
2142 | */ | |
2143 | for (i = 0; i < wowlan->n_patterns; i++) { | |
2144 | ||
2145 | wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL); | |
2146 | ||
2147 | if (!wow_pattern) | |
2148 | return; | |
2149 | ||
2150 | /* | |
2151 | * TODO: convert the generic user space pattern to | |
2152 | * appropriate chip specific/802.11 pattern. | |
2153 | */ | |
2154 | ||
2155 | mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8); | |
2156 | memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE); | |
2157 | memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE); | |
2158 | memcpy(wow_pattern->pattern_bytes, patterns[i].pattern, | |
2159 | patterns[i].pattern_len); | |
2160 | memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len); | |
2161 | wow_pattern->pattern_len = patterns[i].pattern_len; | |
2162 | ||
2163 | /* | |
2164 | * just need to take care of deauth and disssoc pattern, | |
2165 | * make sure we don't overwrite them. | |
2166 | */ | |
2167 | ||
2168 | ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes, | |
2169 | wow_pattern->mask_bytes, | |
2170 | i + 2, | |
2171 | wow_pattern->pattern_len); | |
2172 | kfree(wow_pattern); | |
2173 | ||
2174 | } | |
2175 | ||
2176 | } | |
2177 | ||
2178 | static int ath9k_suspend(struct ieee80211_hw *hw, | |
2179 | struct cfg80211_wowlan *wowlan) | |
2180 | { | |
2181 | struct ath_softc *sc = hw->priv; | |
2182 | struct ath_hw *ah = sc->sc_ah; | |
2183 | struct ath_common *common = ath9k_hw_common(ah); | |
2184 | u32 wow_triggers_enabled = 0; | |
2185 | int ret = 0; | |
2186 | ||
2187 | mutex_lock(&sc->mutex); | |
2188 | ||
2189 | ath_cancel_work(sc); | |
5686cac5 | 2190 | ath_stop_ani(sc); |
b11e640a MSS |
2191 | del_timer_sync(&sc->rx_poll_timer); |
2192 | ||
2193 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { | |
2194 | ath_dbg(common, ANY, "Device not present\n"); | |
2195 | ret = -EINVAL; | |
2196 | goto fail_wow; | |
2197 | } | |
2198 | ||
2199 | if (WARN_ON(!wowlan)) { | |
2200 | ath_dbg(common, WOW, "None of the WoW triggers enabled\n"); | |
2201 | ret = -EINVAL; | |
2202 | goto fail_wow; | |
2203 | } | |
2204 | ||
2205 | if (!device_can_wakeup(sc->dev)) { | |
2206 | ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n"); | |
2207 | ret = 1; | |
2208 | goto fail_wow; | |
2209 | } | |
2210 | ||
2211 | /* | |
2212 | * none of the sta vifs are associated | |
2213 | * and we are not currently handling multivif | |
2214 | * cases, for instance we have to seperately | |
2215 | * configure 'keep alive frame' for each | |
2216 | * STA. | |
2217 | */ | |
2218 | ||
2219 | if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
2220 | ath_dbg(common, WOW, "None of the STA vifs are associated\n"); | |
2221 | ret = 1; | |
2222 | goto fail_wow; | |
2223 | } | |
2224 | ||
2225 | if (sc->nvifs > 1) { | |
2226 | ath_dbg(common, WOW, "WoW for multivif is not yet supported\n"); | |
2227 | ret = 1; | |
2228 | goto fail_wow; | |
2229 | } | |
2230 | ||
2231 | ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled); | |
2232 | ||
2233 | ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n", | |
2234 | wow_triggers_enabled); | |
2235 | ||
2236 | ath9k_ps_wakeup(sc); | |
2237 | ||
2238 | ath9k_stop_btcoex(sc); | |
2239 | ||
2240 | /* | |
2241 | * Enable wake up on recieving disassoc/deauth | |
2242 | * frame by default. | |
2243 | */ | |
2244 | ath9k_wow_add_disassoc_deauth_pattern(sc); | |
2245 | ||
2246 | if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN) | |
2247 | ath9k_wow_add_pattern(sc, wowlan); | |
2248 | ||
2249 | spin_lock_bh(&sc->sc_pcu_lock); | |
2250 | /* | |
2251 | * To avoid false wake, we enable beacon miss interrupt only | |
2252 | * when we go to sleep. We save the current interrupt mask | |
2253 | * so we can restore it after the system wakes up | |
2254 | */ | |
2255 | sc->wow_intr_before_sleep = ah->imask; | |
2256 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
2257 | ath9k_hw_disable_interrupts(ah); | |
2258 | ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL; | |
2259 | ath9k_hw_set_interrupts(ah); | |
2260 | ath9k_hw_enable_interrupts(ah); | |
2261 | ||
2262 | spin_unlock_bh(&sc->sc_pcu_lock); | |
2263 | ||
2264 | /* | |
2265 | * we can now sync irq and kill any running tasklets, since we already | |
2266 | * disabled interrupts and not holding a spin lock | |
2267 | */ | |
2268 | synchronize_irq(sc->irq); | |
2269 | tasklet_kill(&sc->intr_tq); | |
2270 | ||
2271 | ath9k_hw_wow_enable(ah, wow_triggers_enabled); | |
2272 | ||
2273 | ath9k_ps_restore(sc); | |
2274 | ath_dbg(common, ANY, "WoW enabled in ath9k\n"); | |
2275 | atomic_inc(&sc->wow_sleep_proc_intr); | |
2276 | ||
2277 | fail_wow: | |
2278 | mutex_unlock(&sc->mutex); | |
2279 | return ret; | |
2280 | } | |
2281 | ||
2282 | static int ath9k_resume(struct ieee80211_hw *hw) | |
2283 | { | |
2284 | struct ath_softc *sc = hw->priv; | |
2285 | struct ath_hw *ah = sc->sc_ah; | |
2286 | struct ath_common *common = ath9k_hw_common(ah); | |
2287 | u32 wow_status; | |
2288 | ||
2289 | mutex_lock(&sc->mutex); | |
2290 | ||
2291 | ath9k_ps_wakeup(sc); | |
2292 | ||
2293 | spin_lock_bh(&sc->sc_pcu_lock); | |
2294 | ||
2295 | ath9k_hw_disable_interrupts(ah); | |
2296 | ah->imask = sc->wow_intr_before_sleep; | |
2297 | ath9k_hw_set_interrupts(ah); | |
2298 | ath9k_hw_enable_interrupts(ah); | |
2299 | ||
2300 | spin_unlock_bh(&sc->sc_pcu_lock); | |
2301 | ||
2302 | wow_status = ath9k_hw_wow_wakeup(ah); | |
2303 | ||
2304 | if (atomic_read(&sc->wow_got_bmiss_intr) == 0) { | |
2305 | /* | |
2306 | * some devices may not pick beacon miss | |
2307 | * as the reason they woke up so we add | |
2308 | * that here for that shortcoming. | |
2309 | */ | |
2310 | wow_status |= AH_WOW_BEACON_MISS; | |
2311 | atomic_dec(&sc->wow_got_bmiss_intr); | |
2312 | ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n"); | |
2313 | } | |
2314 | ||
2315 | atomic_dec(&sc->wow_sleep_proc_intr); | |
2316 | ||
2317 | if (wow_status) { | |
2318 | ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n", | |
2319 | ath9k_hw_wow_event_to_string(wow_status), wow_status); | |
2320 | } | |
2321 | ||
2322 | ath_restart_work(sc); | |
2323 | ath9k_start_btcoex(sc); | |
2324 | ||
2325 | ath9k_ps_restore(sc); | |
2326 | mutex_unlock(&sc->mutex); | |
2327 | ||
2328 | return 0; | |
2329 | } | |
2330 | ||
2331 | static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) | |
2332 | { | |
2333 | struct ath_softc *sc = hw->priv; | |
2334 | ||
2335 | mutex_lock(&sc->mutex); | |
2336 | device_init_wakeup(sc->dev, 1); | |
2337 | device_set_wakeup_enable(sc->dev, enabled); | |
2338 | mutex_unlock(&sc->mutex); | |
2339 | } | |
2340 | ||
2341 | #endif | |
e93d083f SW |
2342 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2343 | { | |
2344 | struct ath_softc *sc = hw->priv; | |
2345 | ||
2346 | sc->scanning = 1; | |
2347 | } | |
2348 | ||
2349 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) | |
2350 | { | |
2351 | struct ath_softc *sc = hw->priv; | |
2352 | ||
2353 | sc->scanning = 0; | |
2354 | } | |
b11e640a | 2355 | |
6baff7f9 | 2356 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2357 | .tx = ath9k_tx, |
2358 | .start = ath9k_start, | |
2359 | .stop = ath9k_stop, | |
2360 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2361 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2362 | .remove_interface = ath9k_remove_interface, |
2363 | .config = ath9k_config, | |
8feceb67 | 2364 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2365 | .sta_add = ath9k_sta_add, |
2366 | .sta_remove = ath9k_sta_remove, | |
5519541d | 2367 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2368 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2369 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2370 | .set_key = ath9k_set_key, |
8feceb67 | 2371 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2372 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2373 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2374 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2375 | .get_survey = ath9k_get_survey, |
3b319aae | 2376 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2377 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2378 | .flush = ath9k_flush, |
15b91e83 | 2379 | .tx_frames_pending = ath9k_tx_frames_pending, |
52c94f41 MSS |
2380 | .tx_last_beacon = ath9k_tx_last_beacon, |
2381 | .get_stats = ath9k_get_stats, | |
43c35284 FF |
2382 | .set_antenna = ath9k_set_antenna, |
2383 | .get_antenna = ath9k_get_antenna, | |
b90bd9d1 | 2384 | |
b11e640a MSS |
2385 | #ifdef CONFIG_PM_SLEEP |
2386 | .suspend = ath9k_suspend, | |
2387 | .resume = ath9k_resume, | |
2388 | .set_wakeup = ath9k_set_wakeup, | |
2389 | #endif | |
2390 | ||
b90bd9d1 BG |
2391 | #ifdef CONFIG_ATH9K_DEBUGFS |
2392 | .get_et_sset_count = ath9k_get_et_sset_count, | |
a145daf7 SM |
2393 | .get_et_stats = ath9k_get_et_stats, |
2394 | .get_et_strings = ath9k_get_et_strings, | |
2395 | #endif | |
2396 | ||
2397 | #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS) | |
2398 | .sta_add_debugfs = ath9k_sta_add_debugfs, | |
2399 | .sta_remove_debugfs = ath9k_sta_remove_debugfs, | |
b90bd9d1 | 2400 | #endif |
e93d083f SW |
2401 | .sw_scan_start = ath9k_sw_scan_start, |
2402 | .sw_scan_complete = ath9k_sw_scan_complete, | |
8feceb67 | 2403 | }; |