projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
ff37e337
S		 21static void ath_update_txpow(struct ath_softc *sc)
22{
cbe61d8a 23 struct ath_hw *ah = sc->sc_ah;
ff37e337 24
17d7904d 25 if (sc->curtxpow != sc->config.txpowlimit) {
de40f316 26 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
ff37e337 27 /* read back in case value is clamped */
9cc3271f 28 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
ff37e337
S		 29 }
30}
31
32static u8 parse_mpdudensity(u8 mpdudensity)
33{
34 /*
35 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
36 * 0 for no restriction
37 * 1 for 1/4 us
38 * 2 for 1/2 us
39 * 3 for 1 us
40 * 4 for 2 us
41 * 5 for 4 us
42 * 6 for 8 us
43 * 7 for 16 us
44 */
45 switch (mpdudensity) {
46 case 0:
47 return 0;
48 case 1:
49 case 2:
50 case 3:
51 /* Our lower layer calculations limit our precision to
52 1 microsecond */
53 return 1;
54 case 4:
55 return 2;
56 case 5:
57 return 4;
58 case 6:
59 return 8;
60 case 7:
61 return 16;
62 default:
63 return 0;
64 }
65}
66
82880a7c
VT		 67static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
68 struct ieee80211_hw *hw)
69{
70 struct ieee80211_channel *curchan = hw->conf.channel;
71 struct ath9k_channel *channel;
72 u8 chan_idx;
73
74 chan_idx = curchan->hw_value;
75 channel = &sc->sc_ah->channels[chan_idx];
76 ath9k_update_ichannel(sc, hw, channel);
77 return channel;
78}
79
55624204 80bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 81{
82 unsigned long flags;
83 bool ret;
84
9ecdef4b
LR		 85 spin_lock_irqsave(&sc->sc_pm_lock, flags);
86 ret = ath9k_hw_setpower(sc->sc_ah, mode);
87 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 88
89 return ret;
90}
91
a91d75ae
LR		 92void ath9k_ps_wakeup(struct ath_softc *sc)
93{
898c914a 94 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 95 unsigned long flags;
fbb078fc 96 enum ath9k_power_mode power_mode;
a91d75ae
LR		 97
98 spin_lock_irqsave(&sc->sc_pm_lock, flags);
99 if (++sc->ps_usecount != 1)
100 goto unlock;
101
fbb078fc 102 power_mode = sc->sc_ah->power_mode;
9ecdef4b 103 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 104
898c914a
FF		 105 /*
106 * While the hardware is asleep, the cycle counters contain no
107 * useful data. Better clear them now so that they don't mess up
108 * survey data results.
109 */
fbb078fc
FF		 110 if (power_mode != ATH9K_PM_AWAKE) {
111 spin_lock(&common->cc_lock);
112 ath_hw_cycle_counters_update(common);
113 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
114 spin_unlock(&common->cc_lock);
115 }
898c914a 116
a91d75ae
LR		 117 unlock:
118 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
119}
120
121void ath9k_ps_restore(struct ath_softc *sc)
122{
898c914a 123 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae
LR		 124 unsigned long flags;
125
126 spin_lock_irqsave(&sc->sc_pm_lock, flags);
127 if (--sc->ps_usecount != 0)
128 goto unlock;
129
898c914a
FF		 130 spin_lock(&common->cc_lock);
131 ath_hw_cycle_counters_update(common);
132 spin_unlock(&common->cc_lock);
133
1dbfd9d4
VN		 134 if (sc->ps_idle)
135 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
136 else if (sc->ps_enabled &&
137 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S		 138 PS_WAIT_FOR_CAB |
139 PS_WAIT_FOR_PSPOLL_DATA |
140 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 141 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR		 142
143 unlock:
144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
145}
146
5ee08656
FF		 147static void ath_start_ani(struct ath_common *common)
148{
149 struct ath_hw *ah = common->ah;
150 unsigned long timestamp = jiffies_to_msecs(jiffies);
151 struct ath_softc *sc = (struct ath_softc *) common->priv;
152
153 if (!(sc->sc_flags & SC_OP_ANI_RUN))
154 return;
155
156 if (sc->sc_flags & SC_OP_OFFCHANNEL)
157 return;
158
159 common->ani.longcal_timer = timestamp;
160 common->ani.shortcal_timer = timestamp;
161 common->ani.checkani_timer = timestamp;
162
163 mod_timer(&common->ani.timer,
164 jiffies +
165 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
166}
167
3430098a
FF		 168static void ath_update_survey_nf(struct ath_softc *sc, int channel)
169{
170 struct ath_hw *ah = sc->sc_ah;
171 struct ath9k_channel *chan = &ah->channels[channel];
172 struct survey_info *survey = &sc->survey[channel];
173
174 if (chan->noisefloor) {
175 survey->filled |= SURVEY_INFO_NOISE_DBM;
176 survey->noise = chan->noisefloor;
177 }
178}
179
180static void ath_update_survey_stats(struct ath_softc *sc)
181{
182 struct ath_hw *ah = sc->sc_ah;
183 struct ath_common *common = ath9k_hw_common(ah);
184 int pos = ah->curchan - &ah->channels[0];
185 struct survey_info *survey = &sc->survey[pos];
186 struct ath_cycle_counters *cc = &common->cc_survey;
187 unsigned int div = common->clockrate * 1000;
188
0845735e
FF		 189 if (!ah->curchan)
190 return;
191
898c914a
FF		 192 if (ah->power_mode == ATH9K_PM_AWAKE)
193 ath_hw_cycle_counters_update(common);
3430098a
FF		 194
195 if (cc->cycles > 0) {
196 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
197 SURVEY_INFO_CHANNEL_TIME_BUSY |
198 SURVEY_INFO_CHANNEL_TIME_RX |
199 SURVEY_INFO_CHANNEL_TIME_TX;
200 survey->channel_time += cc->cycles / div;
201 survey->channel_time_busy += cc->rx_busy / div;
202 survey->channel_time_rx += cc->rx_frame / div;
203 survey->channel_time_tx += cc->tx_frame / div;
204 }
205 memset(cc, 0, sizeof(*cc));
206
207 ath_update_survey_nf(sc, pos);
208}
209
ff37e337
S		 210/*
211 * Set/change channels. If the channel is really being changed, it's done
212 * by reseting the chip. To accomplish this we must first cleanup any pending
213 * DMA, then restart stuff.
214*/
0e2dedf9
JM		 215int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
216 struct ath9k_channel *hchan)
ff37e337 217{
20bd2a09 218 struct ath_wiphy *aphy = hw->priv;
cbe61d8a 219 struct ath_hw *ah = sc->sc_ah;
c46917bb 220 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 221 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 222 bool fastcc = true, stopped;
ae8d2858 223 struct ieee80211_channel *channel = hw->conf.channel;
20bd2a09 224 struct ath9k_hw_cal_data *caldata = NULL;
ae8d2858 225 int r;
ff37e337
S		 226
227 if (sc->sc_flags & SC_OP_INVALID)
228 return -EIO;
229
5ee08656
FF		 230 del_timer_sync(&common->ani.timer);
231 cancel_work_sync(&sc->paprd_work);
232 cancel_work_sync(&sc->hw_check_work);
233 cancel_delayed_work_sync(&sc->tx_complete_work);
234
3cbb5dd7
VN		 235 ath9k_ps_wakeup(sc);
236
6a6733f2
LR		 237 spin_lock_bh(&sc->sc_pcu_lock);
238
c0d7c7af
LR		 239 /*
240 * This is only performed if the channel settings have
241 * actually changed.
242 *
243 * To switch channels clear any pending DMA operations;
244 * wait long enough for the RX fifo to drain, reset the
245 * hardware at the new frequency, and then re-enable
246 * the relevant bits of the h/w.
247 */
4df3071e 248 ath9k_hw_disable_interrupts(ah);
080e1a25 249 stopped = ath_drain_all_txq(sc, false);
5e848f78 250
080e1a25
FF		 251 if (!ath_stoprecv(sc))
252 stopped = false;
ff37e337 253
c0d7c7af
LR		 254 /* XXX: do not flush receive queue here. We don't want
255 * to flush data frames already in queue because of
256 * changing channel. */
ff37e337 257
5ee08656 258 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
c0d7c7af
LR		 259 fastcc = false;
260
20bd2a09
FF		 261 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
262 caldata = &aphy->caldata;
263
226afe68
JP		 264 ath_dbg(common, ATH_DBG_CONFIG,
265 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
266 sc->sc_ah->curchan->channel,
267 channel->center_freq, conf_is_ht40(conf),
268 fastcc);
ff37e337 269
20bd2a09 270 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
c0d7c7af 271 if (r) {
3800276a
JP		 272 ath_err(common,
273 "Unable to reset channel (%u MHz), reset status %d\n",
274 channel->center_freq, r);
3989279c 275 goto ps_restore;
ff37e337 276 }
c0d7c7af 277
c0d7c7af 278 if (ath_startrecv(sc) != 0) {
3800276a 279 ath_err(common, "Unable to restart recv logic\n");
3989279c
GJ		 280 r = -EIO;
281 goto ps_restore;
c0d7c7af
LR		 282 }
283
c0d7c7af 284 ath_update_txpow(sc);
3069168c 285 ath9k_hw_set_interrupts(ah, ah->imask);
3989279c 286
48a6a468
LR		 287 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
288 ath_beacon_config(sc, NULL);
5ee08656 289 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
48a6a468 290 ath_start_ani(common);
5ee08656
FF		 291 }
292
3989279c 293 ps_restore:
6a6733f2
LR		 294 spin_unlock_bh(&sc->sc_pcu_lock);
295
3cbb5dd7 296 ath9k_ps_restore(sc);
3989279c 297 return r;
ff37e337
S		 298}
299
9f42c2b6
FF		 300static void ath_paprd_activate(struct ath_softc *sc)
301{
302 struct ath_hw *ah = sc->sc_ah;
20bd2a09 303 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 304 struct ath_common *common = ath9k_hw_common(ah);
9f42c2b6
FF		 305 int chain;
306
20bd2a09 307 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF		 308 return;
309
310 ath9k_ps_wakeup(sc);
ddfef792 311 ar9003_paprd_enable(ah, false);
9f42c2b6 312 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 313 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF		 314 continue;
315
20bd2a09 316 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF		 317 }
318
319 ar9003_paprd_enable(ah, true);
320 ath9k_ps_restore(sc);
321}
322
323void ath_paprd_calibrate(struct work_struct *work)
324{
325 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
326 struct ieee80211_hw *hw = sc->hw;
327 struct ath_hw *ah = sc->sc_ah;
328 struct ieee80211_hdr *hdr;
329 struct sk_buff *skb = NULL;
330 struct ieee80211_tx_info *tx_info;
331 int band = hw->conf.channel->band;
332 struct ieee80211_supported_band *sband = &sc->sbands[band];
333 struct ath_tx_control txctl;
20bd2a09 334 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 335 struct ath_common *common = ath9k_hw_common(ah);
066dae93 336 int ftype;
9f42c2b6
FF		 337 int chain_ok = 0;
338 int chain;
339 int len = 1800;
340 int time_left;
341 int i;
342
20bd2a09
FF		 343 if (!caldata)
344 return;
345
9f42c2b6
FF		 346 skb = alloc_skb(len, GFP_KERNEL);
347 if (!skb)
348 return;
349
350 tx_info = IEEE80211_SKB_CB(skb);
351
352 skb_put(skb, len);
353 memset(skb->data, 0, len);
354 hdr = (struct ieee80211_hdr *)skb->data;
355 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
356 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 357 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF		 358 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
359 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
360 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
361
362 memset(&txctl, 0, sizeof(txctl));
066dae93 363 txctl.txq = sc->tx.txq_map[WME_AC_BE];
9f42c2b6 364
47399f1a 365 ath9k_ps_wakeup(sc);
9f42c2b6
FF		 366 ar9003_paprd_init_table(ah);
367 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 368 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF		 369 continue;
370
371 chain_ok = 0;
372 memset(tx_info, 0, sizeof(*tx_info));
373 tx_info->band = band;
374
375 for (i = 0; i < 4; i++) {
376 tx_info->control.rates[i].idx = sband->n_bitrates - 1;
377 tx_info->control.rates[i].count = 6;
378 }
379
380 init_completion(&sc->paprd_complete);
82259b77 381 sc->paprd_pending = true;
9f42c2b6
FF		 382 ar9003_paprd_setup_gain_table(ah, chain);
383 txctl.paprd = BIT(chain);
384 if (ath_tx_start(hw, skb, &txctl) != 0)
385 break;
386
387 time_left = wait_for_completion_timeout(&sc->paprd_complete,
ca369eb4 388 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
82259b77 389 sc->paprd_pending = false;
9f42c2b6 390 if (!time_left) {
226afe68
JP		 391 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
392 "Timeout waiting for paprd training on TX chain %d\n",
393 chain);
ca369eb4 394 goto fail_paprd;
9f42c2b6
FF		 395 }
396
397 if (!ar9003_paprd_is_done(ah))
398 break;
399
20bd2a09 400 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
9f42c2b6
FF		 401 break;
402
403 chain_ok = 1;
404 }
405 kfree_skb(skb);
406
407 if (chain_ok) {
20bd2a09 408 caldata->paprd_done = true;
9f42c2b6
FF		 409 ath_paprd_activate(sc);
410 }
411
ca369eb4 412fail_paprd:
9f42c2b6
FF		 413 ath9k_ps_restore(sc);
414}
415
ff37e337
S		 416/*
417 * This routine performs the periodic noise floor calibration function
418 * that is used to adjust and optimize the chip performance. This
419 * takes environmental changes (location, temperature) into account.
420 * When the task is complete, it reschedules itself depending on the
421 * appropriate interval that was calculated.
422 */
55624204 423void ath_ani_calibrate(unsigned long data)
ff37e337 424{
20977d3e
S		 425 struct ath_softc *sc = (struct ath_softc *)data;
426 struct ath_hw *ah = sc->sc_ah;
c46917bb 427 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 428 bool longcal = false;
429 bool shortcal = false;
430 bool aniflag = false;
431 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 432 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 433 unsigned long flags;
6044474e
FF		 434
435 if (ah->caldata && ah->caldata->nfcal_interference)
436 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
437 else
438 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 439
20977d3e
S		 440 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
441 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 442
1ffc1c61
JM		 443 /* Only calibrate if awake */
444 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
445 goto set_timer;
446
447 ath9k_ps_wakeup(sc);
448
ff37e337 449 /* Long calibration runs independently of short calibration. */
6044474e 450 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 451 longcal = true;
226afe68 452 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 453 common->ani.longcal_timer = timestamp;
ff37e337
S		 454 }
455
17d7904d 456 /* Short calibration applies only while caldone is false */
3d536acf
LR		 457 if (!common->ani.caldone) {
458 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 459 shortcal = true;
226afe68
JP		 460 ath_dbg(common, ATH_DBG_ANI,
461 "shortcal @%lu\n", jiffies);
3d536acf
LR		 462 common->ani.shortcal_timer = timestamp;
463 common->ani.resetcal_timer = timestamp;
ff37e337
S		 464 }
465 } else {
3d536acf 466 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 467 ATH_RESTART_CALINTERVAL) {
3d536acf
LR		 468 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
469 if (common->ani.caldone)
470 common->ani.resetcal_timer = timestamp;
ff37e337
S		 471 }
472 }
473
474 /* Verify whether we must check ANI */
e36b27af
LR		 475 if ((timestamp - common->ani.checkani_timer) >=
476 ah->config.ani_poll_interval) {
ff37e337 477 aniflag = true;
3d536acf 478 common->ani.checkani_timer = timestamp;
ff37e337
S		 479 }
480
481 /* Skip all processing if there's nothing to do. */
482 if (longcal || shortcal || aniflag) {
483 /* Call ANI routine if necessary */
b5bfc568
FF		 484 if (aniflag) {
485 spin_lock_irqsave(&common->cc_lock, flags);
22e66a4c 486 ath9k_hw_ani_monitor(ah, ah->curchan);
3430098a 487 ath_update_survey_stats(sc);
b5bfc568
FF		 488 spin_unlock_irqrestore(&common->cc_lock, flags);
489 }
ff37e337
S		 490
491 /* Perform calibration if necessary */
492 if (longcal || shortcal) {
3d536acf 493 common->ani.caldone =
43c27613
LR		 494 ath9k_hw_calibrate(ah,
495 ah->curchan,
496 common->rx_chainmask,
497 longcal);
ff37e337
S		 498 }
499 }
500
1ffc1c61
JM		 501 ath9k_ps_restore(sc);
502
20977d3e 503set_timer:
ff37e337
S		 504 /*
505 * Set timer interval based on previous results.
506 * The interval must be the shortest necessary to satisfy ANI,
507 * short calibration and long calibration.
508 */
aac9207e 509 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 510 if (sc->sc_ah->config.enable_ani)
e36b27af
LR		 511 cal_interval = min(cal_interval,
512 (u32)ah->config.ani_poll_interval);
3d536acf 513 if (!common->ani.caldone)
20977d3e 514 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 515
3d536acf 516 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF		 517 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
518 if (!ah->caldata->paprd_done)
9f42c2b6
FF		 519 ieee80211_queue_work(sc->hw, &sc->paprd_work);
520 else
521 ath_paprd_activate(sc);
522 }
ff37e337
S		 523}
524
525/*
526 * Update tx/rx chainmask. For legacy association,
527 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 528 * the chainmask configuration, for bt coexistence, use
529 * the chainmask configuration even in legacy mode.
ff37e337 530 */
0e2dedf9 531void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 532{
af03abec 533 struct ath_hw *ah = sc->sc_ah;
43c27613 534 struct ath_common *common = ath9k_hw_common(ah);
af03abec 535
5ee08656 536 if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht ||
766ec4a9 537 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
43c27613
LR		 538 common->tx_chainmask = ah->caps.tx_chainmask;
539 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337 540 } else {
43c27613
LR		 541 common->tx_chainmask = 1;
542 common->rx_chainmask = 1;
ff37e337
S		 543 }
544
226afe68
JP		 545 ath_dbg(common, ATH_DBG_CONFIG,
546 "tx chmask: %d, rx chmask: %d\n",
547 common->tx_chainmask,
548 common->rx_chainmask);
ff37e337
S		 549}
550
551static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
552{
553 struct ath_node *an;
ea066d5a 554 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 555 an = (struct ath_node *)sta->drv_priv;
556
ea066d5a
MSS		 557 if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
558 sc->sc_flags |= SC_OP_ENABLE_APM;
559
87792efc 560 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 561 ath_tx_node_init(sc, an);
9e98ac65 562 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 563 sta->ht_cap.ampdu_factor);
564 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
565 }
ff37e337
S		 566}
567
568static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
569{
570 struct ath_node *an = (struct ath_node *)sta->drv_priv;
571
572 if (sc->sc_flags & SC_OP_TXAGGR)
573 ath_tx_node_cleanup(sc, an);
574}
575
347809fc
FF		 576void ath_hw_check(struct work_struct *work)
577{
578 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
579 int i;
580
581 ath9k_ps_wakeup(sc);
582
583 for (i = 0; i < 3; i++) {
584 if (ath9k_hw_check_alive(sc->sc_ah))
585 goto out;
586
587 msleep(1);
588 }
fac6b6a0 589 ath_reset(sc, true);
347809fc
FF		 590
591out:
592 ath9k_ps_restore(sc);
593}
594
55624204 595void ath9k_tasklet(unsigned long data)
ff37e337
S		 596{
597 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 598 struct ath_hw *ah = sc->sc_ah;
c46917bb 599 struct ath_common *common = ath9k_hw_common(ah);
af03abec 600
17d7904d 601 u32 status = sc->intrstatus;
b5c80475 602 u32 rxmask;
ff37e337 603
153e080d
VT		 604 ath9k_ps_wakeup(sc);
605
347809fc 606 if (status & ATH9K_INT_FATAL) {
fac6b6a0 607 ath_reset(sc, true);
153e080d 608 ath9k_ps_restore(sc);
ff37e337 609 return;
063d8be3 610 }
ff37e337 611
6a6733f2
LR		 612 spin_lock_bh(&sc->sc_pcu_lock);
613
347809fc
FF		 614 if (!ath9k_hw_check_alive(ah))
615 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
616
b5c80475
FF		 617 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
618 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
619 ATH9K_INT_RXORN);
620 else
621 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
622
623 if (status & rxmask) {
b5c80475
FF		 624 /* Check for high priority Rx first */
625 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
626 (status & ATH9K_INT_RXHP))
627 ath_rx_tasklet(sc, 0, true);
628
629 ath_rx_tasklet(sc, 0, false);
ff37e337
S		 630 }
631
e5003249
VT		 632 if (status & ATH9K_INT_TX) {
633 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
634 ath_tx_edma_tasklet(sc);
635 else
636 ath_tx_tasklet(sc);
637 }
063d8be3 638
96148326 639 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 640 /*
641 * TSF sync does not look correct; remain awake to sync with
642 * the next Beacon.
643 */
226afe68
JP		 644 ath_dbg(common, ATH_DBG_PS,
645 "TSFOOR - Sync with next Beacon\n");
1b04b930 646 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
54ce846e
JM		 647 }
648
766ec4a9 649 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT		 650 if (status & ATH9K_INT_GENTIMER)
651 ath_gen_timer_isr(sc->sc_ah);
652
ff37e337 653 /* re-enable hardware interrupt */
4df3071e 654 ath9k_hw_enable_interrupts(ah);
6a6733f2
LR		 655
656 spin_unlock_bh(&sc->sc_pcu_lock);
153e080d 657 ath9k_ps_restore(sc);
ff37e337
S		 658}
659
6baff7f9 660irqreturn_t ath_isr(int irq, void *dev)
ff37e337 661{
063d8be3
S		 662#define SCHED_INTR ( \
663 ATH9K_INT_FATAL | \
664 ATH9K_INT_RXORN | \
665 ATH9K_INT_RXEOL | \
666 ATH9K_INT_RX | \
b5c80475
FF		 667 ATH9K_INT_RXLP | \
668 ATH9K_INT_RXHP | \
063d8be3
S		 669 ATH9K_INT_TX | \
670 ATH9K_INT_BMISS | \
671 ATH9K_INT_CST | \
ebb8e1d7
VT		 672 ATH9K_INT_TSFOOR | \
673 ATH9K_INT_GENTIMER)
063d8be3 674
ff37e337 675 struct ath_softc *sc = dev;
cbe61d8a 676 struct ath_hw *ah = sc->sc_ah;
b5bfc568 677 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 678 enum ath9k_int status;
679 bool sched = false;
680
063d8be3
S		 681 /*
682 * The hardware is not ready/present, don't
683 * touch anything. Note this can happen early
684 * on if the IRQ is shared.
685 */
686 if (sc->sc_flags & SC_OP_INVALID)
687 return IRQ_NONE;
ff37e337 688
063d8be3
S		 689
690 /* shared irq, not for us */
691
153e080d 692 if (!ath9k_hw_intrpend(ah))
063d8be3 693 return IRQ_NONE;
063d8be3
S		 694
695 /*
696 * Figure out the reason(s) for the interrupt. Note
697 * that the hal returns a pseudo-ISR that may include
698 * bits we haven't explicitly enabled so we mask the
699 * value to insure we only process bits we requested.
700 */
701 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 702 status &= ah->imask; /* discard unasked-for bits */
ff37e337 703
063d8be3
S		 704 /*
705 * If there are no status bits set, then this interrupt was not
706 * for me (should have been caught above).
707 */
153e080d 708 if (!status)
063d8be3 709 return IRQ_NONE;
ff37e337 710
063d8be3
S		 711 /* Cache the status */
712 sc->intrstatus = status;
713
714 if (status & SCHED_INTR)
715 sched = true;
716
717 /*
718 * If a FATAL or RXORN interrupt is received, we have to reset the
719 * chip immediately.
720 */
b5c80475
FF		 721 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
722 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S		 723 goto chip_reset;
724
08578b8f
LR		 725 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
726 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF		 727
728 spin_lock(&common->cc_lock);
729 ath_hw_cycle_counters_update(common);
08578b8f 730 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF		 731 spin_unlock(&common->cc_lock);
732
08578b8f
LR		 733 goto chip_reset;
734 }
735
063d8be3
S		 736 if (status & ATH9K_INT_SWBA)
737 tasklet_schedule(&sc->bcon_tasklet);
738
739 if (status & ATH9K_INT_TXURN)
740 ath9k_hw_updatetxtriglevel(ah, true);
741
b5c80475
FF		 742 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
743 if (status & ATH9K_INT_RXEOL) {
744 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
745 ath9k_hw_set_interrupts(ah, ah->imask);
746 }
747 }
748
063d8be3 749 if (status & ATH9K_INT_MIB) {
ff37e337 750 /*
063d8be3
S		 751 * Disable interrupts until we service the MIB
752 * interrupt; otherwise it will continue to
753 * fire.
ff37e337 754 */
4df3071e 755 ath9k_hw_disable_interrupts(ah);
063d8be3
S		 756 /*
757 * Let the hal handle the event. We assume
758 * it will clear whatever condition caused
759 * the interrupt.
760 */
88eac2da 761 spin_lock(&common->cc_lock);
bfc472bb 762 ath9k_hw_proc_mib_event(ah);
88eac2da 763 spin_unlock(&common->cc_lock);
4df3071e 764 ath9k_hw_enable_interrupts(ah);
063d8be3 765 }
ff37e337 766
153e080d
VT		 767 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
768 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR		 769 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
770 goto chip_reset;
063d8be3
S		 771 /* Clear RxAbort bit so that we can
772 * receive frames */
9ecdef4b 773 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 774 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 775 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 776 }
063d8be3
S		 777
778chip_reset:
ff37e337 779
817e11de
S		 780 ath_debug_stat_interrupt(sc, status);
781
ff37e337 782 if (sched) {
4df3071e
FF		 783 /* turn off every interrupt */
784 ath9k_hw_disable_interrupts(ah);
ff37e337
S		 785 tasklet_schedule(&sc->intr_tq);
786 }
787
788 return IRQ_HANDLED;
063d8be3
S		 789
790#undef SCHED_INTR
ff37e337
S		 791}
792
f078f209 793static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 794 struct ieee80211_channel *chan,
094d05dc 795 enum nl80211_channel_type channel_type)
f078f209
LR		 796{
797 u32 chanmode = 0;
f078f209
LR		 798
799 switch (chan->band) {
800 case IEEE80211_BAND_2GHZ:
094d05dc
S		 801 switch(channel_type) {
802 case NL80211_CHAN_NO_HT:
803 case NL80211_CHAN_HT20:
f078f209 804 chanmode = CHANNEL_G_HT20;
094d05dc
S		 805 break;
806 case NL80211_CHAN_HT40PLUS:
f078f209 807 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 808 break;
809 case NL80211_CHAN_HT40MINUS:
f078f209 810 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 811 break;
812 }
f078f209
LR		 813 break;
814 case IEEE80211_BAND_5GHZ:
094d05dc
S		 815 switch(channel_type) {
816 case NL80211_CHAN_NO_HT:
817 case NL80211_CHAN_HT20:
f078f209 818 chanmode = CHANNEL_A_HT20;
094d05dc
S		 819 break;
820 case NL80211_CHAN_HT40PLUS:
f078f209 821 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 822 break;
823 case NL80211_CHAN_HT40MINUS:
f078f209 824 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 825 break;
826 }
f078f209
LR		 827 break;
828 default:
829 break;
830 }
831
832 return chanmode;
833}
834
8feceb67 835static void ath9k_bss_assoc_info(struct ath_softc *sc,
9fa23e17 836 struct ieee80211_hw *hw,
5640b08e 837 struct ieee80211_vif *vif,
8feceb67 838 struct ieee80211_bss_conf *bss_conf)
f078f209 839{
9fa23e17 840 struct ath_wiphy *aphy = hw->priv;
f2b2143e 841 struct ath_hw *ah = sc->sc_ah;
1510718d 842 struct ath_common *common = ath9k_hw_common(ah);
f078f209 843
8feceb67 844 if (bss_conf->assoc) {
226afe68
JP		 845 ath_dbg(common, ATH_DBG_CONFIG,
846 "Bss Info ASSOC %d, bssid: %pM\n",
847 bss_conf->aid, common->curbssid);
f078f209 848
8feceb67 849 /* New association, store aid */
1510718d 850 common->curaid = bss_conf->aid;
f2b2143e 851 ath9k_hw_write_associd(ah);
2664f201
SB		 852
853 /*
854 * Request a re-configuration of Beacon related timers
855 * on the receipt of the first Beacon frame (i.e.,
856 * after time sync with the AP).
857 */
1b04b930 858 sc->ps_flags |= PS_BEACON_SYNC;
f078f209 859
8feceb67 860 /* Configure the beacon */
2c3db3d5 861 ath_beacon_config(sc, vif);
f078f209 862
8feceb67 863 /* Reset rssi stats */
9fa23e17 864 aphy->last_rssi = ATH_RSSI_DUMMY_MARKER;
22e66a4c 865 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 866
6c3118e2 867 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 868 ath_start_ani(common);
8feceb67 869 } else {
226afe68 870 ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 871 common->curaid = 0;
f38faa31 872 /* Stop ANI */
6c3118e2 873 sc->sc_flags &= ~SC_OP_ANI_RUN;
3d536acf 874 del_timer_sync(&common->ani.timer);
f078f209 875 }
8feceb67 876}
f078f209 877
68a89116 878void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 879{
cbe61d8a 880 struct ath_hw *ah = sc->sc_ah;
c46917bb 881 struct ath_common *common = ath9k_hw_common(ah);
68a89116 882 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 883 int r;
500c064d 884
3cbb5dd7 885 ath9k_ps_wakeup(sc);
6a6733f2
LR		 886 spin_lock_bh(&sc->sc_pcu_lock);
887
93b1b37f 888 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 889
159cd468
VT		 890 if (!ah->curchan)
891 ah->curchan = ath_get_curchannel(sc, sc->hw);
892
20bd2a09 893 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 894 if (r) {
3800276a
JP		 895 ath_err(common,
896 "Unable to reset channel (%u MHz), reset status %d\n",
897 channel->center_freq, r);
500c064d 898 }
500c064d
VT		 899
900 ath_update_txpow(sc);
901 if (ath_startrecv(sc) != 0) {
3800276a 902 ath_err(common, "Unable to restart recv logic\n");
4bdd1e97 903 spin_unlock_bh(&sc->sc_pcu_lock);
500c064d
VT		 904 return;
905 }
500c064d 906 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 907 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 908
909 /* Re-Enable interrupts */
3069168c 910 ath9k_hw_set_interrupts(ah, ah->imask);
500c064d
VT		 911
912 /* Enable LED */
08fc5c1b 913 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 914 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 915 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 916
68a89116 917 ieee80211_wake_queues(hw);
6a6733f2
LR		 918 spin_unlock_bh(&sc->sc_pcu_lock);
919
3cbb5dd7 920 ath9k_ps_restore(sc);
500c064d
VT		 921}
922
68a89116 923void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 924{
cbe61d8a 925 struct ath_hw *ah = sc->sc_ah;
68a89116 926 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 927 int r;
500c064d 928
3cbb5dd7 929 ath9k_ps_wakeup(sc);
6a6733f2
LR		 930 spin_lock_bh(&sc->sc_pcu_lock);
931
68a89116 932 ieee80211_stop_queues(hw);
500c064d 933
982723df
VN		 934 /*
935 * Keep the LED on when the radio is disabled
936 * during idle unassociated state.
937 */
938 if (!sc->ps_idle) {
939 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
940 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
941 }
500c064d
VT		 942
943 /* Disable interrupts */
4df3071e 944 ath9k_hw_disable_interrupts(ah);
500c064d 945
043a0405 946 ath_drain_all_txq(sc, false); /* clear pending tx frames */
5e848f78 947
500c064d
VT		 948 ath_stoprecv(sc); /* turn off frame recv */
949 ath_flushrecv(sc); /* flush recv queue */
950
159cd468 951 if (!ah->curchan)
68a89116 952 ah->curchan = ath_get_curchannel(sc, hw);
159cd468 953
20bd2a09 954 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 955 if (r) {
3800276a
JP		 956 ath_err(ath9k_hw_common(sc->sc_ah),
957 "Unable to reset channel (%u MHz), reset status %d\n",
958 channel->center_freq, r);
500c064d 959 }
500c064d
VT		 960
961 ath9k_hw_phy_disable(ah);
5e848f78 962
93b1b37f 963 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR		 964
965 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 966 ath9k_ps_restore(sc);
6a6733f2 967
9ecdef4b 968 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 969}
970
ff37e337
S		 971int ath_reset(struct ath_softc *sc, bool retry_tx)
972{
cbe61d8a 973 struct ath_hw *ah = sc->sc_ah;
c46917bb 974 struct ath_common *common = ath9k_hw_common(ah);
030bb495 975 struct ieee80211_hw *hw = sc->hw;
ae8d2858 976 int r;
ff37e337 977
2ab81d4a
S		 978 /* Stop ANI */
979 del_timer_sync(&common->ani.timer);
980
6a6733f2
LR		 981 spin_lock_bh(&sc->sc_pcu_lock);
982
cc9c378a
S		 983 ieee80211_stop_queues(hw);
984
4df3071e 985 ath9k_hw_disable_interrupts(ah);
043a0405 986 ath_drain_all_txq(sc, retry_tx);
5e848f78 987
ff37e337
S		 988 ath_stoprecv(sc);
989 ath_flushrecv(sc);
990
20bd2a09 991 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
ae8d2858 992 if (r)
3800276a
JP		 993 ath_err(common,
994 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 995
996 if (ath_startrecv(sc) != 0)
3800276a 997 ath_err(common, "Unable to start recv logic\n");
ff37e337
S		 998
999 /*
1000 * We may be doing a reset in response to a request
1001 * that changes the channel so update any state that
1002 * might change as a result.
1003 */
ff37e337
S		 1004 ath_update_txpow(sc);
1005
52b8ac92 1006 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
2c3db3d5 1007 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1008
3069168c 1009 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337
S		 1010
1011 if (retry_tx) {
1012 int i;
1013 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1014 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1015 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1016 ath_txq_schedule(sc, &sc->tx.txq[i]);
1017 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1018 }
1019 }
1020 }
1021
cc9c378a 1022 ieee80211_wake_queues(hw);
6a6733f2 1023 spin_unlock_bh(&sc->sc_pcu_lock);
cc9c378a 1024
2ab81d4a
S		 1025 /* Start ANI */
1026 ath_start_ani(common);
1027
ae8d2858 1028 return r;
ff37e337
S		 1029}
1030
5f8e077c
LR		 1031/* XXX: Remove me once we don't depend on ath9k_channel for all
1032 * this redundant data */
0e2dedf9
JM		 1033void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1034 struct ath9k_channel *ichan)
5f8e077c 1035{
5f8e077c
LR		 1036 struct ieee80211_channel *chan = hw->conf.channel;
1037 struct ieee80211_conf *conf = &hw->conf;
1038
1039 ichan->channel = chan->center_freq;
1040 ichan->chan = chan;
1041
1042 if (chan->band == IEEE80211_BAND_2GHZ) {
1043 ichan->chanmode = CHANNEL_G;
8813262e 1044 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR		 1045 } else {
1046 ichan->chanmode = CHANNEL_A;
1047 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1048 }
1049
25c56eec 1050 if (conf_is_ht(conf))
5f8e077c
LR		 1051 ichan->chanmode = ath_get_extchanmode(sc, chan,
1052 conf->channel_type);
5f8e077c
LR		 1053}
1054
ff37e337
S		 1055/**********************/
1056/* mac80211 callbacks */
1057/**********************/
1058
8feceb67 1059static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1060{
bce048d7
JM		 1061 struct ath_wiphy *aphy = hw->priv;
1062 struct ath_softc *sc = aphy->sc;
af03abec 1063 struct ath_hw *ah = sc->sc_ah;
c46917bb 1064 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1065 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1066 struct ath9k_channel *init_channel;
82880a7c 1067 int r;
f078f209 1068
226afe68
JP		 1069 ath_dbg(common, ATH_DBG_CONFIG,
1070 "Starting driver with initial channel: %d MHz\n",
1071 curchan->center_freq);
f078f209 1072
141b38b6
S		 1073 mutex_lock(&sc->mutex);
1074
9580a222
JM		 1075 if (ath9k_wiphy_started(sc)) {
1076 if (sc->chan_idx == curchan->hw_value) {
1077 /*
1078 * Already on the operational channel, the new wiphy
1079 * can be marked active.
1080 */
1081 aphy->state = ATH_WIPHY_ACTIVE;
1082 ieee80211_wake_queues(hw);
1083 } else {
1084 /*
1085 * Another wiphy is on another channel, start the new
1086 * wiphy in paused state.
1087 */
1088 aphy->state = ATH_WIPHY_PAUSED;
1089 ieee80211_stop_queues(hw);
1090 }
1091 mutex_unlock(&sc->mutex);
1092 return 0;
1093 }
1094 aphy->state = ATH_WIPHY_ACTIVE;
1095
8feceb67 1096 /* setup initial channel */
f078f209 1097
82880a7c 1098 sc->chan_idx = curchan->hw_value;
f078f209 1099
82880a7c 1100 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 1101
1102 /* Reset SERDES registers */
af03abec 1103 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S		 1104
1105 /*
1106 * The basic interface to setting the hardware in a good
1107 * state is ``reset''. On return the hardware is known to
1108 * be powered up and with interrupts disabled. This must
1109 * be followed by initialization of the appropriate bits
1110 * and then setup of the interrupt mask.
1111 */
4bdd1e97 1112 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1113 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1114 if (r) {
3800276a
JP		 1115 ath_err(common,
1116 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1117 r, curchan->center_freq);
4bdd1e97 1118 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1119 goto mutex_unlock;
ff37e337 1120 }
ff37e337
S		 1121
1122 /*
1123 * This is needed only to setup initial state
1124 * but it's best done after a reset.
1125 */
1126 ath_update_txpow(sc);
8feceb67 1127
ff37e337
S		 1128 /*
1129 * Setup the hardware after reset:
1130 * The receive engine is set going.
1131 * Frame transmit is handled entirely
1132 * in the frame output path; there's nothing to do
1133 * here except setup the interrupt mask.
1134 */
1135 if (ath_startrecv(sc) != 0) {
3800276a 1136 ath_err(common, "Unable to start recv logic\n");
141b38b6 1137 r = -EIO;
4bdd1e97 1138 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1139 goto mutex_unlock;
f078f209 1140 }
4bdd1e97 1141 spin_unlock_bh(&sc->sc_pcu_lock);
8feceb67 1142
ff37e337 1143 /* Setup our intr mask. */
b5c80475
FF		 1144 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1145 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1146 ATH9K_INT_GLOBAL;
1147
1148 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR		 1149 ah->imask |= ATH9K_INT_RXHP |
1150 ATH9K_INT_RXLP |
1151 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF		 1152 else
1153 ah->imask |= ATH9K_INT_RX;
ff37e337 1154
364734fa 1155 ah->imask |= ATH9K_INT_GTT;
ff37e337 1156
af03abec 1157 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1158 ah->imask |= ATH9K_INT_CST;
ff37e337 1159
ff37e337 1160 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1161 sc->sc_ah->is_monitoring = false;
ff37e337
S		 1162
1163 /* Disable BMISS interrupt when we're not associated */
3069168c
PR		 1164 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1165 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337 1166
bce048d7 1167 ieee80211_wake_queues(hw);
ff37e337 1168
42935eca 1169 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1170
766ec4a9
LR		 1171 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1172 !ah->btcoex_hw.enabled) {
5e197292
LR		 1173 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1174 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1175 ath9k_hw_btcoex_enable(ah);
f985ad12 1176
5bb12791
LR		 1177 if (common->bus_ops->bt_coex_prep)
1178 common->bus_ops->bt_coex_prep(common);
766ec4a9 1179 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1180 ath9k_btcoex_timer_resume(sc);
1773912b
VT		 1181 }
1182
98c316e3 1183 pm_qos_update_request(&sc->pm_qos_req, 55);
10598c12 1184
8060e169
VT		 1185 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1186 common->bus_ops->extn_synch_en(common);
1187
141b38b6
S		 1188mutex_unlock:
1189 mutex_unlock(&sc->mutex);
1190
ae8d2858 1191 return r;
f078f209
LR		 1192}
1193
8feceb67
VT		 1194static int ath9k_tx(struct ieee80211_hw *hw,
1195 struct sk_buff *skb)
f078f209 1196{
bce048d7
JM		 1197 struct ath_wiphy *aphy = hw->priv;
1198 struct ath_softc *sc = aphy->sc;
c46917bb 1199 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1200 struct ath_tx_control txctl;
1bc14880 1201 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1202
8089cc47 1203 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
226afe68
JP		 1204 ath_dbg(common, ATH_DBG_XMIT,
1205 "ath9k: %s: TX in unexpected wiphy state %d\n",
1206 wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM		 1207 goto exit;
1208 }
1209
96148326 1210 if (sc->ps_enabled) {
dc8c4585
JM		 1211 /*
1212 * mac80211 does not set PM field for normal data frames, so we
1213 * need to update that based on the current PS mode.
1214 */
1215 if (ieee80211_is_data(hdr->frame_control) &&
1216 !ieee80211_is_nullfunc(hdr->frame_control) &&
1217 !ieee80211_has_pm(hdr->frame_control)) {
226afe68
JP		 1218 ath_dbg(common, ATH_DBG_PS,
1219 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM		 1220 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1221 }
1222 }
1223
9a23f9ca
JM		 1224 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1225 /*
1226 * We are using PS-Poll and mac80211 can request TX while in
1227 * power save mode. Need to wake up hardware for the TX to be
1228 * completed and if needed, also for RX of buffered frames.
1229 */
9a23f9ca 1230 ath9k_ps_wakeup(sc);
fdf76622
VT		 1231 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1232 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1233 if (ieee80211_is_pspoll(hdr->frame_control)) {
226afe68
JP		 1234 ath_dbg(common, ATH_DBG_PS,
1235 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1236 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1237 } else {
226afe68
JP		 1238 ath_dbg(common, ATH_DBG_PS,
1239 "Wake up to complete TX\n");
1b04b930 1240 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM		 1241 }
1242 /*
1243 * The actual restore operation will happen only after
1244 * the sc_flags bit is cleared. We are just dropping
1245 * the ps_usecount here.
1246 */
1247 ath9k_ps_restore(sc);
1248 }
1249
528f0c6b 1250 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1251 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1252
226afe68 1253 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1254
c52f33d0 1255 if (ath_tx_start(hw, skb, &txctl) != 0) {
226afe68 1256 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1257 goto exit;
8feceb67
VT		 1258 }
1259
528f0c6b
S		 1260 return 0;
1261exit:
1262 dev_kfree_skb_any(skb);
8feceb67 1263 return 0;
f078f209
LR		 1264}
1265
8feceb67 1266static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1267{
bce048d7
JM		 1268 struct ath_wiphy *aphy = hw->priv;
1269 struct ath_softc *sc = aphy->sc;
af03abec 1270 struct ath_hw *ah = sc->sc_ah;
c46917bb 1271 struct ath_common *common = ath9k_hw_common(ah);
447a42c2 1272 int i;
f078f209 1273
4c483817
S		 1274 mutex_lock(&sc->mutex);
1275
9580a222
JM		 1276 aphy->state = ATH_WIPHY_INACTIVE;
1277
9a75c2ff
VN		 1278 if (led_blink)
1279 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1280
c94dbff7 1281 cancel_delayed_work_sync(&sc->tx_complete_work);
9f42c2b6 1282 cancel_work_sync(&sc->paprd_work);
347809fc 1283 cancel_work_sync(&sc->hw_check_work);
c94dbff7 1284
447a42c2
RM		 1285 for (i = 0; i < sc->num_sec_wiphy; i++) {
1286 if (sc->sec_wiphy[i])
1287 break;
1288 }
1289
1290 if (i == sc->num_sec_wiphy) {
c94dbff7
LR		 1291 cancel_delayed_work_sync(&sc->wiphy_work);
1292 cancel_work_sync(&sc->chan_work);
1293 }
1294
9c84b797 1295 if (sc->sc_flags & SC_OP_INVALID) {
226afe68 1296 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1297 mutex_unlock(&sc->mutex);
9c84b797
S		 1298 return;
1299 }
8feceb67 1300
9580a222
JM		 1301 if (ath9k_wiphy_started(sc)) {
1302 mutex_unlock(&sc->mutex);
1303 return; /* another wiphy still in use */
1304 }
1305
3867cf6a
S		 1306 /* Ensure HW is awake when we try to shut it down. */
1307 ath9k_ps_wakeup(sc);
1308
766ec4a9 1309 if (ah->btcoex_hw.enabled) {
af03abec 1310 ath9k_hw_btcoex_disable(ah);
766ec4a9 1311 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1312 ath9k_btcoex_timer_pause(sc);
1773912b
VT		 1313 }
1314
6a6733f2
LR		 1315 spin_lock_bh(&sc->sc_pcu_lock);
1316
ff37e337
S		 1317 /* make sure h/w will not generate any interrupt
1318 * before setting the invalid flag. */
4df3071e 1319 ath9k_hw_disable_interrupts(ah);
ff37e337
S		 1320
1321 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1322 ath_drain_all_txq(sc, false);
ff37e337 1323 ath_stoprecv(sc);
af03abec 1324 ath9k_hw_phy_disable(ah);
6a6733f2 1325 } else
b77f483f 1326 sc->rx.rxlink = NULL;
ff37e337 1327
ff37e337 1328 /* disable HAL and put h/w to sleep */
af03abec
LR		 1329 ath9k_hw_disable(ah);
1330 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR		 1331
1332 spin_unlock_bh(&sc->sc_pcu_lock);
1333
3867cf6a
S		 1334 ath9k_ps_restore(sc);
1335
1336 /* Finally, put the chip in FULL SLEEP mode */
9ecdef4b 1337 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ff37e337
S		 1338
1339 sc->sc_flags |= SC_OP_INVALID;
500c064d 1340
98c316e3 1341 pm_qos_update_request(&sc->pm_qos_req, PM_QOS_DEFAULT_VALUE);
10598c12 1342
141b38b6
S		 1343 mutex_unlock(&sc->mutex);
1344
226afe68 1345 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 1346}
1347
8feceb67 1348static int ath9k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 1349 struct ieee80211_vif *vif)
f078f209 1350{
bce048d7
JM		 1351 struct ath_wiphy *aphy = hw->priv;
1352 struct ath_softc *sc = aphy->sc;
3069168c
PR		 1353 struct ath_hw *ah = sc->sc_ah;
1354 struct ath_common *common = ath9k_hw_common(ah);
1ed32e4f 1355 struct ath_vif *avp = (void *)vif->drv_priv;
d97809db 1356 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 1357 int ret = 0;
8feceb67 1358
141b38b6
S		 1359 mutex_lock(&sc->mutex);
1360
1ed32e4f 1361 switch (vif->type) {
05c914fe 1362 case NL80211_IFTYPE_STATION:
d97809db 1363 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 1364 break;
e51f3eff
BJ		 1365 case NL80211_IFTYPE_WDS:
1366 ic_opmode = NL80211_IFTYPE_WDS;
1367 break;
05c914fe 1368 case NL80211_IFTYPE_ADHOC:
05c914fe 1369 case NL80211_IFTYPE_AP:
9cb5412b 1370 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 1371 if (sc->nbcnvifs >= ATH_BCBUF) {
1372 ret = -ENOBUFS;
1373 goto out;
1374 }
1ed32e4f 1375 ic_opmode = vif->type;
f078f209
LR		 1376 break;
1377 default:
3800276a
JP		 1378 ath_err(common, "Interface type %d not yet supported\n",
1379 vif->type);
2c3db3d5
JM		 1380 ret = -EOPNOTSUPP;
1381 goto out;
f078f209
LR		 1382 }
1383
226afe68
JP		 1384 ath_dbg(common, ATH_DBG_CONFIG,
1385 "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 1386
17d7904d 1387 /* Set the VIF opmode */
5640b08e
S		 1388 avp->av_opmode = ic_opmode;
1389 avp->av_bslot = -1;
1390
2c3db3d5 1391 sc->nvifs++;
8ca21f01 1392
364734fa 1393 ath9k_set_bssid_mask(hw, vif);
8ca21f01 1394
2c3db3d5
JM		 1395 if (sc->nvifs > 1)
1396 goto out; /* skip global settings for secondary vif */
1397
b238e90e 1398 if (ic_opmode == NL80211_IFTYPE_AP) {
3069168c 1399 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e
S		 1400 sc->sc_flags |= SC_OP_TSF_RESET;
1401 }
5640b08e 1402
5640b08e 1403 /* Set the device opmode */
3069168c 1404 ah->opmode = ic_opmode;
5640b08e 1405
4e30ffa2
VN		 1406 /*
1407 * Enable MIB interrupts when there are hardware phy counters.
1408 * Note we only do this (at the moment) for station mode.
1409 */
1ed32e4f
JB		 1410 if ((vif->type == NL80211_IFTYPE_STATION) ||
1411 (vif->type == NL80211_IFTYPE_ADHOC) ||
1412 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
3448f912
LR		 1413 if (ah->config.enable_ani)
1414 ah->imask |= ATH9K_INT_MIB;
3069168c 1415 ah->imask |= ATH9K_INT_TSFOOR;
4af9cf4f
S		 1416 }
1417
3069168c 1418 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1419
1ed32e4f 1420 if (vif->type == NL80211_IFTYPE_AP ||
5f841b41 1421 vif->type == NL80211_IFTYPE_ADHOC) {
6c3118e2 1422 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 1423 ath_start_ani(common);
6c3118e2 1424 }
6f255425 1425
2c3db3d5 1426out:
141b38b6 1427 mutex_unlock(&sc->mutex);
2c3db3d5 1428 return ret;
f078f209
LR		 1429}
1430
8feceb67 1431static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1432 struct ieee80211_vif *vif)
f078f209 1433{
bce048d7
JM		 1434 struct ath_wiphy *aphy = hw->priv;
1435 struct ath_softc *sc = aphy->sc;
c46917bb 1436 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1ed32e4f 1437 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 1438
226afe68 1439 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1440
141b38b6
S		 1441 mutex_lock(&sc->mutex);
1442
6f255425 1443 /* Stop ANI */
6c3118e2 1444 sc->sc_flags &= ~SC_OP_ANI_RUN;
3d536acf 1445 del_timer_sync(&common->ani.timer);
580f0b8a 1446
8feceb67 1447 /* Reclaim beacon resources */
9cb5412b
PE		 1448 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
1449 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
1450 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
884a963f
RM		 1451 /* Disable SWBA interrupt */
1452 sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
5f70a88f 1453 ath9k_ps_wakeup(sc);
884a963f 1454 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
b77f483f 1455 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
5f70a88f 1456 ath9k_ps_restore(sc);
884a963f 1457 tasklet_kill(&sc->bcon_tasklet);
580f0b8a 1458 }
f078f209 1459
74401773 1460 ath_beacon_return(sc, avp);
8feceb67 1461 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 1462
884a963f
RM		 1463 if (sc->nbcnvifs) {
1464 /* Re-enable SWBA interrupt */
1465 sc->sc_ah->imask |= ATH9K_INT_SWBA;
46047784
RM		 1466 ath9k_ps_wakeup(sc);
1467 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
1468 ath9k_ps_restore(sc);
2c3db3d5
JM		 1469 }
1470
17d7904d 1471 sc->nvifs--;
141b38b6
S		 1472
1473 mutex_unlock(&sc->mutex);
f078f209
LR		 1474}
1475
fbab7390 1476static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1477{
3069168c
PR		 1478 struct ath_hw *ah = sc->sc_ah;
1479
3f7c5c10 1480 sc->ps_enabled = true;
3069168c
PR		 1481 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1482 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1483 ah->imask |= ATH9K_INT_TIM_TIMER;
1484 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1485 }
fdf76622 1486 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1487 }
3f7c5c10
SB		 1488}
1489
845d708e
SB		 1490static void ath9k_disable_ps(struct ath_softc *sc)
1491{
1492 struct ath_hw *ah = sc->sc_ah;
1493
1494 sc->ps_enabled = false;
1495 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1496 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1497 ath9k_hw_setrxabort(ah, 0);
1498 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1499 PS_WAIT_FOR_CAB |
1500 PS_WAIT_FOR_PSPOLL_DATA |
1501 PS_WAIT_FOR_TX_ACK);
1502 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1503 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1504 ath9k_hw_set_interrupts(ah, ah->imask);
1505 }
1506 }
1507
1508}
1509
e8975581 1510static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1511{
bce048d7
JM		 1512 struct ath_wiphy *aphy = hw->priv;
1513 struct ath_softc *sc = aphy->sc;
3430098a
FF		 1514 struct ath_hw *ah = sc->sc_ah;
1515 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1516 struct ieee80211_conf *conf = &hw->conf;
194b7c13 1517 bool disable_radio;
f078f209 1518
aa33de09 1519 mutex_lock(&sc->mutex);
141b38b6 1520
194b7c13
LR		 1521 /*
1522 * Leave this as the first check because we need to turn on the
1523 * radio if it was disabled before prior to processing the rest
1524 * of the changes. Likewise we must only disable the radio towards
1525 * the end.
1526 */
64839170 1527 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
194b7c13
LR		 1528 bool enable_radio;
1529 bool all_wiphys_idle;
1530 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
64839170
LR		 1531
1532 spin_lock_bh(&sc->wiphy_lock);
1533 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
194b7c13
LR		 1534 ath9k_set_wiphy_idle(aphy, idle);
1535
11446011 1536 enable_radio = (!idle && all_wiphys_idle);
194b7c13
LR		 1537
1538 /*
1539 * After we unlock here its possible another wiphy
1540 * can be re-renabled so to account for that we will
1541 * only disable the radio toward the end of this routine
1542 * if by then all wiphys are still idle.
1543 */
64839170
LR		 1544 spin_unlock_bh(&sc->wiphy_lock);
1545
194b7c13 1546 if (enable_radio) {
1dbfd9d4 1547 sc->ps_idle = false;
68a89116 1548 ath_radio_enable(sc, hw);
226afe68
JP		 1549 ath_dbg(common, ATH_DBG_CONFIG,
1550 "not-idle: enabling radio\n");
64839170
LR		 1551 }
1552 }
1553
e7824a50
LR		 1554 /*
1555 * We just prepare to enable PS. We have to wait until our AP has
1556 * ACK'd our null data frame to disable RX otherwise we'll ignore
1557 * those ACKs and end up retransmitting the same null data frames.
1558 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1559 */
3cbb5dd7 1560 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR		 1561 unsigned long flags;
1562 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB		 1563 if (conf->flags & IEEE80211_CONF_PS)
1564 ath9k_enable_ps(sc);
845d708e
SB		 1565 else
1566 ath9k_disable_ps(sc);
8ab2cd09 1567 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN		 1568 }
1569
199afd9d
S		 1570 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1571 if (conf->flags & IEEE80211_CONF_MONITOR) {
226afe68
JP		 1572 ath_dbg(common, ATH_DBG_CONFIG,
1573 "Monitor mode is enabled\n");
5f841b41
RM		 1574 sc->sc_ah->is_monitoring = true;
1575 } else {
226afe68
JP		 1576 ath_dbg(common, ATH_DBG_CONFIG,
1577 "Monitor mode is disabled\n");
5f841b41 1578 sc->sc_ah->is_monitoring = false;
199afd9d
S		 1579 }
1580 }
1581
4797938c 1582 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1583 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1584 int pos = curchan->hw_value;
3430098a
FF		 1585 int old_pos = -1;
1586 unsigned long flags;
1587
1588 if (ah->curchan)
1589 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1590
0e2dedf9
JM		 1591 aphy->chan_idx = pos;
1592 aphy->chan_is_ht = conf_is_ht(conf);
5ee08656
FF		 1593 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1594 sc->sc_flags |= SC_OP_OFFCHANNEL;
1595 else
1596 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1597
8089cc47
JM		 1598 if (aphy->state == ATH_WIPHY_SCAN ||
1599 aphy->state == ATH_WIPHY_ACTIVE)
1600 ath9k_wiphy_pause_all_forced(sc, aphy);
1601 else {
1602 /*
1603 * Do not change operational channel based on a paused
1604 * wiphy changes.
1605 */
1606 goto skip_chan_change;
1607 }
0e2dedf9 1608
226afe68
JP		 1609 ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1610 curchan->center_freq);
f078f209 1611
5f8e077c 1612 /* XXX: remove me eventualy */
0e2dedf9 1613 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 1614
ecf70441 1615 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 1616
3430098a
FF		 1617 /* update survey stats for the old channel before switching */
1618 spin_lock_irqsave(&common->cc_lock, flags);
1619 ath_update_survey_stats(sc);
1620 spin_unlock_irqrestore(&common->cc_lock, flags);
1621
1622 /*
1623 * If the operating channel changes, change the survey in-use flags
1624 * along with it.
1625 * Reset the survey data for the new channel, unless we're switching
1626 * back to the operating channel from an off-channel operation.
1627 */
1628 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1629 sc->cur_survey != &sc->survey[pos]) {
1630
1631 if (sc->cur_survey)
1632 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1633
1634 sc->cur_survey = &sc->survey[pos];
1635
1636 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1637 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1638 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1639 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1640 }
1641
0e2dedf9 1642 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1643 ath_err(common, "Unable to set channel\n");
aa33de09 1644 mutex_unlock(&sc->mutex);
e11602b7
S		 1645 return -EINVAL;
1646 }
3430098a
FF		 1647
1648 /*
1649 * The most recent snapshot of channel->noisefloor for the old
1650 * channel is only available after the hardware reset. Copy it to
1651 * the survey stats now.
1652 */
1653 if (old_pos >= 0)
1654 ath_update_survey_nf(sc, old_pos);
094d05dc 1655 }
f078f209 1656
8089cc47 1657skip_chan_change:
c9f6a656 1658 if (changed & IEEE80211_CONF_CHANGE_POWER) {
17d7904d 1659 sc->config.txpowlimit = 2 * conf->power_level;
c9f6a656
LR		 1660 ath_update_txpow(sc);
1661 }
f078f209 1662
194b7c13
LR		 1663 spin_lock_bh(&sc->wiphy_lock);
1664 disable_radio = ath9k_all_wiphys_idle(sc);
1665 spin_unlock_bh(&sc->wiphy_lock);
1666
64839170 1667 if (disable_radio) {
226afe68 1668 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1dbfd9d4 1669 sc->ps_idle = true;
68a89116 1670 ath_radio_disable(sc, hw);
64839170
LR		 1671 }
1672
aa33de09 1673 mutex_unlock(&sc->mutex);
141b38b6 1674
f078f209
LR		 1675 return 0;
1676}
1677
8feceb67
VT		 1678#define SUPPORTED_FILTERS \
1679 (FIF_PROMISC_IN_BSS | \
1680 FIF_ALLMULTI | \
1681 FIF_CONTROL | \
af6a3fc7 1682 FIF_PSPOLL | \
8feceb67
VT		 1683 FIF_OTHER_BSS | \
1684 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1685 FIF_PROBE_REQ | \
8feceb67 1686 FIF_FCSFAIL)
c83be688 1687
8feceb67
VT		 1688/* FIXME: sc->sc_full_reset ? */
1689static void ath9k_configure_filter(struct ieee80211_hw *hw,
1690 unsigned int changed_flags,
1691 unsigned int *total_flags,
3ac64bee 1692 u64 multicast)
8feceb67 1693{
bce048d7
JM		 1694 struct ath_wiphy *aphy = hw->priv;
1695 struct ath_softc *sc = aphy->sc;
8feceb67 1696 u32 rfilt;
f078f209 1697
8feceb67
VT		 1698 changed_flags &= SUPPORTED_FILTERS;
1699 *total_flags &= SUPPORTED_FILTERS;
f078f209 1700
b77f483f 1701 sc->rx.rxfilter = *total_flags;
aa68aeaa 1702 ath9k_ps_wakeup(sc);
8feceb67
VT		 1703 rfilt = ath_calcrxfilter(sc);
1704 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1705 ath9k_ps_restore(sc);
f078f209 1706
226afe68
JP		 1707 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1708 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1709}
f078f209 1710
4ca77860
JB		 1711static int ath9k_sta_add(struct ieee80211_hw *hw,
1712 struct ieee80211_vif *vif,
1713 struct ieee80211_sta *sta)
8feceb67 1714{
bce048d7
JM		 1715 struct ath_wiphy *aphy = hw->priv;
1716 struct ath_softc *sc = aphy->sc;
f078f209 1717
4ca77860
JB		 1718 ath_node_attach(sc, sta);
1719
1720 return 0;
1721}
1722
1723static int ath9k_sta_remove(struct ieee80211_hw *hw,
1724 struct ieee80211_vif *vif,
1725 struct ieee80211_sta *sta)
1726{
1727 struct ath_wiphy *aphy = hw->priv;
1728 struct ath_softc *sc = aphy->sc;
1729
1730 ath_node_detach(sc, sta);
1731
1732 return 0;
f078f209
LR		 1733}
1734
141b38b6 1735static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1736 const struct ieee80211_tx_queue_params *params)
f078f209 1737{
bce048d7
JM		 1738 struct ath_wiphy *aphy = hw->priv;
1739 struct ath_softc *sc = aphy->sc;
c46917bb 1740 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1741 struct ath_txq *txq;
8feceb67 1742 struct ath9k_tx_queue_info qi;
066dae93 1743 int ret = 0;
f078f209 1744
8feceb67
VT		 1745 if (queue >= WME_NUM_AC)
1746 return 0;
f078f209 1747
066dae93
FF		 1748 txq = sc->tx.txq_map[queue];
1749
141b38b6
S		 1750 mutex_lock(&sc->mutex);
1751
1ffb0610
S		 1752 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1753
8feceb67
VT		 1754 qi.tqi_aifs = params->aifs;
1755 qi.tqi_cwmin = params->cw_min;
1756 qi.tqi_cwmax = params->cw_max;
1757 qi.tqi_burstTime = params->txop;
f078f209 1758
226afe68
JP		 1759 ath_dbg(common, ATH_DBG_CONFIG,
1760 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1761 queue, txq->axq_qnum, params->aifs, params->cw_min,
1762 params->cw_max, params->txop);
f078f209 1763
066dae93 1764 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1765 if (ret)
3800276a 1766 ath_err(common, "TXQ Update failed\n");
f078f209 1767
94db2936 1768 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1769 if (queue == WME_AC_BE && !ret)
94db2936
VN		 1770 ath_beaconq_config(sc);
1771
141b38b6
S		 1772 mutex_unlock(&sc->mutex);
1773
8feceb67
VT		 1774 return ret;
1775}
f078f209 1776
8feceb67
VT		 1777static int ath9k_set_key(struct ieee80211_hw *hw,
1778 enum set_key_cmd cmd,
dc822b5d
JB		 1779 struct ieee80211_vif *vif,
1780 struct ieee80211_sta *sta,
8feceb67
VT		 1781 struct ieee80211_key_conf *key)
1782{
bce048d7
JM		 1783 struct ath_wiphy *aphy = hw->priv;
1784 struct ath_softc *sc = aphy->sc;
c46917bb 1785 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1786 int ret = 0;
f078f209 1787
b3bd89ce
JM		 1788 if (modparam_nohwcrypt)
1789 return -ENOSPC;
1790
141b38b6 1791 mutex_lock(&sc->mutex);
3cbb5dd7 1792 ath9k_ps_wakeup(sc);
226afe68 1793 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1794
8feceb67
VT		 1795 switch (cmd) {
1796 case SET_KEY:
040e539e 1797 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM		 1798 if (ret >= 0) {
1799 key->hw_key_idx = ret;
8feceb67
VT		 1800 /* push IV and Michael MIC generation to stack */
1801 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1802 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1803 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB		 1804 if (sc->sc_ah->sw_mgmt_crypto &&
1805 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1806 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1807 ret = 0;
8feceb67
VT		 1808 }
1809 break;
1810 case DISABLE_KEY:
040e539e 1811 ath_key_delete(common, key);
8feceb67
VT		 1812 break;
1813 default:
1814 ret = -EINVAL;
1815 }
f078f209 1816
3cbb5dd7 1817 ath9k_ps_restore(sc);
141b38b6
S		 1818 mutex_unlock(&sc->mutex);
1819
8feceb67
VT		 1820 return ret;
1821}
f078f209 1822
8feceb67
VT		 1823static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1824 struct ieee80211_vif *vif,
1825 struct ieee80211_bss_conf *bss_conf,
1826 u32 changed)
1827{
bce048d7
JM		 1828 struct ath_wiphy *aphy = hw->priv;
1829 struct ath_softc *sc = aphy->sc;
2d0ddec5 1830 struct ath_hw *ah = sc->sc_ah;
1510718d 1831 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1832 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1833 int slottime;
c6089ccc 1834 int error;
f078f209 1835
141b38b6
S		 1836 mutex_lock(&sc->mutex);
1837
c6089ccc
S		 1838 if (changed & BSS_CHANGED_BSSID) {
1839 /* Set BSSID */
1840 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1841 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 1842 common->curaid = 0;
f2b2143e 1843 ath9k_hw_write_associd(ah);
2d0ddec5 1844
c6089ccc
S		 1845 /* Set aggregation protection mode parameters */
1846 sc->config.ath_aggr_prot = 0;
2d0ddec5 1847
c6089ccc
S		 1848 /* Only legacy IBSS for now */
1849 if (vif->type == NL80211_IFTYPE_ADHOC)
1850 ath_update_chainmask(sc, 0);
2d0ddec5 1851
226afe68
JP		 1852 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
1853 common->curbssid, common->curaid);
2d0ddec5 1854
c6089ccc
S		 1855 /* need to reconfigure the beacon */
1856 sc->sc_flags &= ~SC_OP_BEACONS ;
1857 }
2d0ddec5 1858
c6089ccc
S		 1859 /* Enable transmission of beacons (AP, IBSS, MESH) */
1860 if ((changed & BSS_CHANGED_BEACON) ||
1861 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
1862 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1863 error = ath_beacon_alloc(aphy, vif);
1864 if (!error)
1865 ath_beacon_config(sc, vif);
0005baf4
FF		 1866 }
1867
1868 if (changed & BSS_CHANGED_ERP_SLOT) {
1869 if (bss_conf->use_short_slot)
1870 slottime = 9;
1871 else
1872 slottime = 20;
1873 if (vif->type == NL80211_IFTYPE_AP) {
1874 /*
1875 * Defer update, so that connected stations can adjust
1876 * their settings at the same time.
1877 * See beacon.c for more details
1878 */
1879 sc->beacon.slottime = slottime;
1880 sc->beacon.updateslot = UPDATE;
1881 } else {
1882 ah->slottime = slottime;
1883 ath9k_hw_init_global_settings(ah);
1884 }
2d0ddec5
JB		 1885 }
1886
c6089ccc
S		 1887 /* Disable transmission of beacons */
1888 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
1889 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5 1890
c6089ccc
S		 1891 if (changed & BSS_CHANGED_BEACON_INT) {
1892 sc->beacon_interval = bss_conf->beacon_int;
1893 /*
1894 * In case of AP mode, the HW TSF has to be reset
1895 * when the beacon interval changes.
1896 */
1897 if (vif->type == NL80211_IFTYPE_AP) {
1898 sc->sc_flags |= SC_OP_TSF_RESET;
1899 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5
JB		 1900 error = ath_beacon_alloc(aphy, vif);
1901 if (!error)
1902 ath_beacon_config(sc, vif);
c6089ccc
S		 1903 } else {
1904 ath_beacon_config(sc, vif);
2d0ddec5
JB		 1905 }
1906 }
1907
8feceb67 1908 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
226afe68
JP		 1909 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
1910 bss_conf->use_short_preamble);
8feceb67
VT		 1911 if (bss_conf->use_short_preamble)
1912 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1913 else
1914 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1915 }
f078f209 1916
8feceb67 1917 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
226afe68
JP		 1918 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
1919 bss_conf->use_cts_prot);
8feceb67
VT		 1920 if (bss_conf->use_cts_prot &&
1921 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1922 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1923 else
1924 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1925 }
f078f209 1926
8feceb67 1927 if (changed & BSS_CHANGED_ASSOC) {
226afe68 1928 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 1929 bss_conf->assoc);
9fa23e17 1930 ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
8feceb67 1931 }
141b38b6
S		 1932
1933 mutex_unlock(&sc->mutex);
8feceb67 1934}
f078f209 1935
8feceb67
VT		 1936static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1937{
1938 u64 tsf;
bce048d7
JM		 1939 struct ath_wiphy *aphy = hw->priv;
1940 struct ath_softc *sc = aphy->sc;
f078f209 1941
141b38b6
S		 1942 mutex_lock(&sc->mutex);
1943 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1944 mutex_unlock(&sc->mutex);
f078f209 1945
8feceb67
VT		 1946 return tsf;
1947}
f078f209 1948
3b5d665b
AF		 1949static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
1950{
bce048d7
JM		 1951 struct ath_wiphy *aphy = hw->priv;
1952 struct ath_softc *sc = aphy->sc;
3b5d665b 1953
141b38b6
S		 1954 mutex_lock(&sc->mutex);
1955 ath9k_hw_settsf64(sc->sc_ah, tsf);
1956 mutex_unlock(&sc->mutex);
3b5d665b
AF		 1957}
1958
8feceb67
VT		 1959static void ath9k_reset_tsf(struct ieee80211_hw *hw)
1960{
bce048d7
JM		 1961 struct ath_wiphy *aphy = hw->priv;
1962 struct ath_softc *sc = aphy->sc;
c83be688 1963
141b38b6 1964 mutex_lock(&sc->mutex);
21526d57
LR		 1965
1966 ath9k_ps_wakeup(sc);
141b38b6 1967 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 1968 ath9k_ps_restore(sc);
1969
141b38b6 1970 mutex_unlock(&sc->mutex);
8feceb67 1971}
f078f209 1972
8feceb67 1973static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1974 struct ieee80211_vif *vif,
141b38b6
S		 1975 enum ieee80211_ampdu_mlme_action action,
1976 struct ieee80211_sta *sta,
1977 u16 tid, u16 *ssn)
8feceb67 1978{
bce048d7
JM		 1979 struct ath_wiphy *aphy = hw->priv;
1980 struct ath_softc *sc = aphy->sc;
8feceb67 1981 int ret = 0;
f078f209 1982
85ad181e
JB		 1983 local_bh_disable();
1984
8feceb67
VT		 1985 switch (action) {
1986 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 1987 if (!(sc->sc_flags & SC_OP_RXAGGR))
1988 ret = -ENOTSUPP;
8feceb67
VT		 1989 break;
1990 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 1991 break;
1992 case IEEE80211_AMPDU_TX_START:
71a3bf3e
FF		 1993 if (!(sc->sc_flags & SC_OP_TXAGGR))
1994 return -EOPNOTSUPP;
1995
8b685ba9 1996 ath9k_ps_wakeup(sc);
231c3a1f
FF		 1997 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1998 if (!ret)
1999 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2000 ath9k_ps_restore(sc);
8feceb67
VT		 2001 break;
2002 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2003 ath9k_ps_wakeup(sc);
f83da965 2004 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2005 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2006 ath9k_ps_restore(sc);
8feceb67 2007 break;
b1720231 2008 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2009 ath9k_ps_wakeup(sc);
8469cdef 2010 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2011 ath9k_ps_restore(sc);
8469cdef 2012 break;
8feceb67 2013 default:
3800276a 2014 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT		 2015 }
2016
85ad181e
JB		 2017 local_bh_enable();
2018
8feceb67 2019 return ret;
f078f209
LR		 2020}
2021
62dad5b0
BP		 2022static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2023 struct survey_info *survey)
2024{
2025 struct ath_wiphy *aphy = hw->priv;
2026 struct ath_softc *sc = aphy->sc;
3430098a 2027 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2028 struct ieee80211_supported_band *sband;
3430098a
FF		 2029 struct ieee80211_channel *chan;
2030 unsigned long flags;
2031 int pos;
2032
2033 spin_lock_irqsave(&common->cc_lock, flags);
2034 if (idx == 0)
2035 ath_update_survey_stats(sc);
39162dbe
FF		 2036
2037 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2038 if (sband && idx >= sband->n_channels) {
2039 idx -= sband->n_channels;
2040 sband = NULL;
2041 }
62dad5b0 2042
39162dbe
FF		 2043 if (!sband)
2044 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2045
3430098a
FF		 2046 if (!sband || idx >= sband->n_channels) {
2047 spin_unlock_irqrestore(&common->cc_lock, flags);
2048 return -ENOENT;
4f1a5a4b 2049 }
62dad5b0 2050
3430098a
FF		 2051 chan = &sband->channels[idx];
2052 pos = chan->hw_value;
2053 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2054 survey->channel = chan;
2055 spin_unlock_irqrestore(&common->cc_lock, flags);
2056
62dad5b0
BP		 2057 return 0;
2058}
2059
0c98de65
S		 2060static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2061{
bce048d7
JM		 2062 struct ath_wiphy *aphy = hw->priv;
2063 struct ath_softc *sc = aphy->sc;
0c98de65 2064
3d832611 2065 mutex_lock(&sc->mutex);
8089cc47 2066 if (ath9k_wiphy_scanning(sc)) {
8089cc47 2067 /*
30888338
LR		 2068 * There is a race here in mac80211 but fixing it requires
2069 * we revisit how we handle the scan complete callback.
2070 * After mac80211 fixes we will not have configured hardware
2071 * to the home channel nor would we have configured the RX
2072 * filter yet.
8089cc47 2073 */
3d832611 2074 mutex_unlock(&sc->mutex);
8089cc47
JM		 2075 return;
2076 }
2077
2078 aphy->state = ATH_WIPHY_SCAN;
2079 ath9k_wiphy_pause_all_forced(sc, aphy);
3d832611 2080 mutex_unlock(&sc->mutex);
0c98de65
S		 2081}
2082
30888338
LR		 2083/*
2084 * XXX: this requires a revisit after the driver
2085 * scan_complete gets moved to another place/removed in mac80211.
2086 */
0c98de65
S		 2087static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2088{
bce048d7
JM		 2089 struct ath_wiphy *aphy = hw->priv;
2090 struct ath_softc *sc = aphy->sc;
0c98de65 2091
3d832611 2092 mutex_lock(&sc->mutex);
8089cc47 2093 aphy->state = ATH_WIPHY_ACTIVE;
3d832611 2094 mutex_unlock(&sc->mutex);
0c98de65
S		 2095}
2096
e239d859
FF		 2097static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2098{
2099 struct ath_wiphy *aphy = hw->priv;
2100 struct ath_softc *sc = aphy->sc;
2101 struct ath_hw *ah = sc->sc_ah;
2102
2103 mutex_lock(&sc->mutex);
2104 ah->coverage_class = coverage_class;
2105 ath9k_hw_init_global_settings(ah);
2106 mutex_unlock(&sc->mutex);
2107}
2108
6baff7f9 2109struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2110 .tx = ath9k_tx,
2111 .start = ath9k_start,
2112 .stop = ath9k_stop,
2113 .add_interface = ath9k_add_interface,
2114 .remove_interface = ath9k_remove_interface,
2115 .config = ath9k_config,
8feceb67 2116 .configure_filter = ath9k_configure_filter,
4ca77860
JB		 2117 .sta_add = ath9k_sta_add,
2118 .sta_remove = ath9k_sta_remove,
8feceb67 2119 .conf_tx = ath9k_conf_tx,
8feceb67 2120 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2121 .set_key = ath9k_set_key,
8feceb67 2122 .get_tsf = ath9k_get_tsf,
3b5d665b 2123 .set_tsf = ath9k_set_tsf,
8feceb67 2124 .reset_tsf = ath9k_reset_tsf,
4233df6b 2125 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2126 .get_survey = ath9k_get_survey,
0c98de65
S		 2127 .sw_scan_start = ath9k_sw_scan_start,
2128 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2129 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2130 .set_coverage_class = ath9k_set_coverage_class,
8feceb67 2131};
kernel source for telekom puls (alcatel/mediatek)