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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / tulip / tulip_core.c
CommitLineData
78a65518 1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux.
1da177e4 2
1da177e4
LT		 3 Copyright 2000,2001 The Linux Kernel Team
4 Written/copyright 1994-2001 by Donald Becker.
5
6 This software may be used and distributed according to the terms
7 of the GNU General Public License, incorporated herein by reference.
8
9 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
78a65518 10 for more information on this driver.
1da177e4 11
78a65518 12 Please submit bugs to http://bugzilla.kernel.org/ .
1da177e4
LT		 13*/
14
1da177e4
LT		 15
16#define DRV_NAME "tulip"
17#ifdef CONFIG_TULIP_NAPI
6bab99be 18#define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
1da177e4 19#else
6bab99be 20#define DRV_VERSION "1.1.15"
1da177e4 21#endif
6bab99be 22#define DRV_RELDATE "Feb 27, 2007"
1da177e4
LT		 23
24
25#include <linux/module.h>
26#include <linux/pci.h>
5a0e3ad6 27#include <linux/slab.h>
1da177e4
LT		 28#include "tulip.h"
29#include <linux/init.h>
30#include <linux/etherdevice.h>
31#include <linux/delay.h>
32#include <linux/mii.h>
33#include <linux/ethtool.h>
34#include <linux/crc32.h>
35#include <asm/unaligned.h>
36#include <asm/uaccess.h>
37
49345103 38#ifdef CONFIG_SPARC
d297c31f 39#include <asm/prom.h>
1da177e4
LT		 40#endif
41
42static char version[] __devinitdata =
43 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
44
1da177e4
LT		 45/* A few user-configurable values. */
46
47/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
48static unsigned int max_interrupt_work = 25;
49
50#define MAX_UNITS 8
51/* Used to pass the full-duplex flag, etc. */
52static int full_duplex[MAX_UNITS];
53static int options[MAX_UNITS];
54static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
55
56/* The possible media types that can be set in options[] are: */
57const char * const medianame[32] = {
58 "10baseT", "10base2", "AUI", "100baseTx",
59 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
60 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
61 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
62 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
63 "","","","", "","","","", "","","","Transceiver reset",
64};
65
66/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
8e95a202
JP		 67#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
68 defined(CONFIG_SPARC) || defined(__ia64__) || \
69 defined(__sh__) || defined(__mips__)
1da177e4
LT		 70static int rx_copybreak = 1518;
71#else
72static int rx_copybreak = 100;
73#endif
74
75/*
76 Set the bus performance register.
77 Typical: Set 16 longword cache alignment, no burst limit.
78 Cache alignment bits 15:14 Burst length 13:8
79 0000 No alignment 0x00000000 unlimited 0800 8 longwords
80 4000 8 longwords 0100 1 longword 1000 16 longwords
81 8000 16 longwords 0200 2 longwords 2000 32 longwords
82 C000 32 longwords 0400 4 longwords
83 Warning: many older 486 systems are broken and require setting 0x00A04800
84 8 longword cache alignment, 8 longword burst.
85 ToDo: Non-Intel setting could be better.
86*/
87
88#if defined(__alpha__) || defined(__ia64__)
89static int csr0 = 0x01A00000 | 0xE000;
90#elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
91static int csr0 = 0x01A00000 | 0x8000;
49345103 92#elif defined(CONFIG_SPARC) || defined(__hppa__)
1da177e4
LT		 93/* The UltraSparc PCI controllers will disconnect at every 64-byte
94 * crossing anyways so it makes no sense to tell Tulip to burst
95 * any more than that.
96 */
97static int csr0 = 0x01A00000 | 0x9000;
98#elif defined(__arm__) || defined(__sh__)
99static int csr0 = 0x01A00000 | 0x4800;
100#elif defined(__mips__)
101static int csr0 = 0x00200000 | 0x4000;
102#else
103#warning Processor architecture undefined!
104static int csr0 = 0x00A00000 | 0x4800;
105#endif
106
107/* Operational parameters that usually are not changed. */
108/* Time in jiffies before concluding the transmitter is hung. */
109#define TX_TIMEOUT (4*HZ)
110
111
112MODULE_AUTHOR("The Linux Kernel Team");
113MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
114MODULE_LICENSE("GPL");
115MODULE_VERSION(DRV_VERSION);
116module_param(tulip_debug, int, 0);
117module_param(max_interrupt_work, int, 0);
118module_param(rx_copybreak, int, 0);
119module_param(csr0, int, 0);
120module_param_array(options, int, NULL, 0);
121module_param_array(full_duplex, int, NULL, 0);
122
123#define PFX DRV_NAME ": "
124
125#ifdef TULIP_DEBUG
126int tulip_debug = TULIP_DEBUG;
127#else
128int tulip_debug = 1;
129#endif
130
0bb3cf72
FR		 131static void tulip_timer(unsigned long data)
132{
133 struct net_device *dev = (struct net_device *)data;
134 struct tulip_private *tp = netdev_priv(dev);
1da177e4 135
0bb3cf72
FR		 136 if (netif_running(dev))
137 schedule_work(&tp->media_work);
138}
1da177e4
LT		 139
140/*
141 * This table use during operation for capabilities and media timer.
142 *
143 * It is indexed via the values in 'enum chips'
144 */
145
146struct tulip_chip_table tulip_tbl[] = {
147 { }, /* placeholder for array, slot unused currently */
148 { }, /* placeholder for array, slot unused currently */
149
150 /* DC21140 */
151 { "Digital DS21140 Tulip", 128, 0x0001ebef,
0bb3cf72
FR		 152 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
153 tulip_media_task },
1da177e4
LT		 154
155 /* DC21142, DC21143 */
b892de0b 156 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
1da177e4 157 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
0bb3cf72 158 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
1da177e4
LT		 159
160 /* LC82C168 */
161 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
0bb3cf72 162 HAS_MII | HAS_PNICNWAY, pnic_timer, },
1da177e4
LT		 163
164 /* MX98713 */
165 { "Macronix 98713 PMAC", 128, 0x0001ebef,
0bb3cf72 166 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
1da177e4
LT		 167
168 /* MX98715 */
169 { "Macronix 98715 PMAC", 256, 0x0001ebef,
0bb3cf72 170 HAS_MEDIA_TABLE, mxic_timer, },
1da177e4
LT		 171
172 /* MX98725 */
173 { "Macronix 98725 PMAC", 256, 0x0001ebef,
0bb3cf72 174 HAS_MEDIA_TABLE, mxic_timer, },
1da177e4
LT		 175
176 /* AX88140 */
177 { "ASIX AX88140", 128, 0x0001fbff,
178 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
0bb3cf72 179 | IS_ASIX, tulip_timer, tulip_media_task },
1da177e4
LT		 180
181 /* PNIC2 */
182 { "Lite-On PNIC-II", 256, 0x0801fbff,
0bb3cf72 183 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
1da177e4
LT		 184
185 /* COMET */
186 { "ADMtek Comet", 256, 0x0001abef,
0bb3cf72 187 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
1da177e4
LT		 188
189 /* COMPEX9881 */
190 { "Compex 9881 PMAC", 128, 0x0001ebef,
0bb3cf72 191 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
1da177e4
LT		 192
193 /* I21145 */
194 { "Intel DS21145 Tulip", 128, 0x0801fbff,
195 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
0bb3cf72 196 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
1da177e4
LT		 197
198 /* DM910X */
4d907069 199#ifdef CONFIG_TULIP_DM910X
1da177e4
LT		 200 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
201 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
0bb3cf72 202 tulip_timer, tulip_media_task },
4d907069
BH		 203#else
204 { NULL },
205#endif
1da177e4
LT		 206
207 /* RS7112 */
208 { "Conexant LANfinity", 256, 0x0001ebef,
0bb3cf72 209 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
1da177e4 210
1da177e4
LT		 211};
212
213
a3aa1884 214static DEFINE_PCI_DEVICE_TABLE(tulip_pci_tbl) = {
1da177e4
LT		 215 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
216 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
217 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
218 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
219 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
220/* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
221 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
222 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
223 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
230 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
231 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
232 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
233 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
234 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
4d907069 235#ifdef CONFIG_TULIP_DM910X
1da177e4
LT		 236 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
237 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
4d907069 238#endif
1da177e4
LT		 239 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
240 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
241 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
242 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
244 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
245 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
246 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
247 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
248 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
249 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
1da177e4 250 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
9b25978e 251 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
60abe782 252 { 0x1414, 0x0001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Microsoft MN-120 */
1a449358 253 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
1da177e4
LT		 254 { } /* terminate list */
255};
256MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
257
258
259/* A full-duplex map for media types. */
260const char tulip_media_cap[32] =
261{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
262
263static void tulip_tx_timeout(struct net_device *dev);
264static void tulip_init_ring(struct net_device *dev);
69145635 265static void tulip_free_ring(struct net_device *dev);
ad096463
SH		 266static netdev_tx_t tulip_start_xmit(struct sk_buff *skb,
267 struct net_device *dev);
1da177e4
LT		 268static int tulip_open(struct net_device *dev);
269static int tulip_close(struct net_device *dev);
270static void tulip_up(struct net_device *dev);
271static void tulip_down(struct net_device *dev);
272static struct net_device_stats *tulip_get_stats(struct net_device *dev);
273static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
274static void set_rx_mode(struct net_device *dev);
275#ifdef CONFIG_NET_POLL_CONTROLLER
276static void poll_tulip(struct net_device *dev);
277#endif
278
279static void tulip_set_power_state (struct tulip_private *tp,
280 int sleep, int snooze)
281{
282 if (tp->flags & HAS_ACPI) {
283 u32 tmp, newtmp;
284 pci_read_config_dword (tp->pdev, CFDD, &tmp);
285 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
286 if (sleep)
287 newtmp |= CFDD_Sleep;
288 else if (snooze)
289 newtmp |= CFDD_Snooze;
290 if (tmp != newtmp)
291 pci_write_config_dword (tp->pdev, CFDD, newtmp);
292 }
293
294}
295
296
297static void tulip_up(struct net_device *dev)
298{
299 struct tulip_private *tp = netdev_priv(dev);
300 void __iomem *ioaddr = tp->base_addr;
301 int next_tick = 3*HZ;
b4482a4b 302 u32 reg;
1da177e4
LT		 303 int i;
304
bea3348e
SH		 305#ifdef CONFIG_TULIP_NAPI
306 napi_enable(&tp->napi);
307#endif
308
1da177e4
LT		 309 /* Wake the chip from sleep/snooze mode. */
310 tulip_set_power_state (tp, 0, 0);
311
312 /* On some chip revs we must set the MII/SYM port before the reset!? */
313 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
314 iowrite32(0x00040000, ioaddr + CSR6);
315
316 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
317 iowrite32(0x00000001, ioaddr + CSR0);
b4482a4b 318 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
1da177e4
LT		 319 udelay(100);
320
321 /* Deassert reset.
322 Wait the specified 50 PCI cycles after a reset by initializing
323 Tx and Rx queues and the address filter list. */
324 iowrite32(tp->csr0, ioaddr + CSR0);
b4482a4b 325 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
1da177e4
LT		 326 udelay(100);
327
328 if (tulip_debug > 1)
d60bec4e
JP		 329 printk(KERN_DEBUG "%s: tulip_up(), irq==%d\n",
330 dev->name, dev->irq);
1da177e4
LT		 331
332 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
333 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
334 tp->cur_rx = tp->cur_tx = 0;
335 tp->dirty_rx = tp->dirty_tx = 0;
336
337 if (tp->flags & MC_HASH_ONLY) {
6caf52a4
HH		 338 u32 addr_low = get_unaligned_le32(dev->dev_addr);
339 u32 addr_high = get_unaligned_le16(dev->dev_addr + 4);
1da177e4
LT		 340 if (tp->chip_id == AX88140) {
341 iowrite32(0, ioaddr + CSR13);
342 iowrite32(addr_low, ioaddr + CSR14);
343 iowrite32(1, ioaddr + CSR13);
344 iowrite32(addr_high, ioaddr + CSR14);
345 } else if (tp->flags & COMET_MAC_ADDR) {
346 iowrite32(addr_low, ioaddr + 0xA4);
347 iowrite32(addr_high, ioaddr + 0xA8);
348 iowrite32(0, ioaddr + 0xAC);
349 iowrite32(0, ioaddr + 0xB0);
350 }
351 } else {
352 /* This is set_rx_mode(), but without starting the transmitter. */
353 u16 *eaddrs = (u16 *)dev->dev_addr;
354 u16 *setup_frm = &tp->setup_frame[15*6];
355 dma_addr_t mapping;
356
357 /* 21140 bug: you must add the broadcast address. */
358 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
359 /* Fill the final entry of the table with our physical address. */
360 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
361 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
362 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
363
364 mapping = pci_map_single(tp->pdev, tp->setup_frame,
365 sizeof(tp->setup_frame),
366 PCI_DMA_TODEVICE);
367 tp->tx_buffers[tp->cur_tx].skb = NULL;
368 tp->tx_buffers[tp->cur_tx].mapping = mapping;
369
370 /* Put the setup frame on the Tx list. */
371 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
372 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
373 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
374
375 tp->cur_tx++;
376 }
377
378 tp->saved_if_port = dev->if_port;
379 if (dev->if_port == 0)
380 dev->if_port = tp->default_port;
381
382 /* Allow selecting a default media. */
383 i = 0;
384 if (tp->mtable == NULL)
385 goto media_picked;
386 if (dev->if_port) {
387 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
388 (dev->if_port == 12 ? 0 : dev->if_port);
389 for (i = 0; i < tp->mtable->leafcount; i++)
390 if (tp->mtable->mleaf[i].media == looking_for) {
d60bec4e
JP		 391 dev_info(&dev->dev,
392 "Using user-specified media %s\n",
393 medianame[dev->if_port]);
1da177e4
LT		 394 goto media_picked;
395 }
396 }
397 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
398 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
399 for (i = 0; i < tp->mtable->leafcount; i++)
400 if (tp->mtable->mleaf[i].media == looking_for) {
d60bec4e
JP		 401 dev_info(&dev->dev,
402 "Using EEPROM-set media %s\n",
403 medianame[looking_for]);
1da177e4
LT		 404 goto media_picked;
405 }
406 }
407 /* Start sensing first non-full-duplex media. */
408 for (i = tp->mtable->leafcount - 1;
409 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
410 ;
411media_picked:
412
413 tp->csr6 = 0;
414 tp->cur_index = i;
415 tp->nwayset = 0;
416
417 if (dev->if_port) {
418 if (tp->chip_id == DC21143 &&
419 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
420 /* We must reset the media CSRs when we force-select MII mode. */
421 iowrite32(0x0000, ioaddr + CSR13);
422 iowrite32(0x0000, ioaddr + CSR14);
423 iowrite32(0x0008, ioaddr + CSR15);
424 }
425 tulip_select_media(dev, 1);
426 } else if (tp->chip_id == DC21142) {
427 if (tp->mii_cnt) {
428 tulip_select_media(dev, 1);
429 if (tulip_debug > 1)
d60bec4e
JP		 430 dev_info(&dev->dev,
431 "Using MII transceiver %d, status %04x\n",
432 tp->phys[0],
433 tulip_mdio_read(dev, tp->phys[0], 1));
1da177e4
LT		 434 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
435 tp->csr6 = csr6_mask_hdcap;
436 dev->if_port = 11;
437 iowrite32(0x0000, ioaddr + CSR13);
438 iowrite32(0x0000, ioaddr + CSR14);
439 } else
440 t21142_start_nway(dev);
441 } else if (tp->chip_id == PNIC2) {
442 /* for initial startup advertise 10/100 Full and Half */
443 tp->sym_advertise = 0x01E0;
444 /* enable autonegotiate end interrupt */
445 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
446 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
447 pnic2_start_nway(dev);
448 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
449 if (tp->mii_cnt) {
450 dev->if_port = 11;
451 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
452 iowrite32(0x0001, ioaddr + CSR15);
453 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
454 pnic_do_nway(dev);
455 else {
456 /* Start with 10mbps to do autonegotiation. */
457 iowrite32(0x32, ioaddr + CSR12);
458 tp->csr6 = 0x00420000;
459 iowrite32(0x0001B078, ioaddr + 0xB8);
460 iowrite32(0x0201B078, ioaddr + 0xB8);
461 next_tick = 1*HZ;
462 }
8e95a202
JP		 463 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881) &&
464 ! tp->medialock) {
1da177e4
LT		 465 dev->if_port = 0;
466 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
467 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
468 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
469 /* Provided by BOLO, Macronix - 12/10/1998. */
470 dev->if_port = 0;
471 tp->csr6 = 0x01a80200;
472 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
473 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
474 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
475 /* Enable automatic Tx underrun recovery. */
476 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
477 dev->if_port = tp->mii_cnt ? 11 : 0;
478 tp->csr6 = 0x00040000;
479 } else if (tp->chip_id == AX88140) {
480 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
481 } else
482 tulip_select_media(dev, 1);
483
484 /* Start the chip's Tx to process setup frame. */
485 tulip_stop_rxtx(tp);
486 barrier();
487 udelay(5);
488 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
489
490 /* Enable interrupts by setting the interrupt mask. */
491 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
492 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
493 tulip_start_rxtx(tp);
494 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
495
496 if (tulip_debug > 2) {
d60bec4e
JP		 497 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %08x, CSR5 %08x CSR6 %08x\n",
498 dev->name, ioread32(ioaddr + CSR0),
499 ioread32(ioaddr + CSR5),
500 ioread32(ioaddr + CSR6));
1da177e4
LT		 501 }
502
503 /* Set the timer to switch to check for link beat and perhaps switch
504 to an alternate media type. */
505 tp->timer.expires = RUN_AT(next_tick);
506 add_timer(&tp->timer);
507#ifdef CONFIG_TULIP_NAPI
508 init_timer(&tp->oom_timer);
509 tp->oom_timer.data = (unsigned long)dev;
510 tp->oom_timer.function = oom_timer;
511#endif
512}
513
514static int
515tulip_open(struct net_device *dev)
516{
517 int retval;
518
1da177e4
LT		 519 tulip_init_ring (dev);
520
a0607fd3 521 retval = request_irq(dev->irq, tulip_interrupt, IRQF_SHARED, dev->name, dev);
69145635
KM		 522 if (retval)
523 goto free_ring;
524
1da177e4
LT		 525 tulip_up (dev);
526
527 netif_start_queue (dev);
528
529 return 0;
69145635
KM		 530
531free_ring:
532 tulip_free_ring (dev);
533 return retval;
1da177e4
LT		 534}
535
536
537static void tulip_tx_timeout(struct net_device *dev)
538{
539 struct tulip_private *tp = netdev_priv(dev);
540 void __iomem *ioaddr = tp->base_addr;
541 unsigned long flags;
542
543 spin_lock_irqsave (&tp->lock, flags);
544
545 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
546 /* Do nothing -- the media monitor should handle this. */
547 if (tulip_debug > 1)
d60bec4e
JP		 548 dev_warn(&dev->dev,
549 "Transmit timeout using MII device\n");
8e95a202
JP		 550 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142 ||
551 tp->chip_id == MX98713 || tp->chip_id == COMPEX9881 ||
552 tp->chip_id == DM910X) {
d60bec4e
JP		 553 dev_warn(&dev->dev,
554 "21140 transmit timed out, status %08x, SIA %08x %08x %08x %08x, resetting...\n",
555 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
556 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14),
557 ioread32(ioaddr + CSR15));
0bb3cf72
FR		 558 tp->timeout_recovery = 1;
559 schedule_work(&tp->media_work);
560 goto out_unlock;
1da177e4 561 } else if (tp->chip_id == PNIC2) {
d60bec4e
JP		 562 dev_warn(&dev->dev,
563 "PNIC2 transmit timed out, status %08x, CSR6/7 %08x / %08x CSR12 %08x, resetting...\n",
564 (int)ioread32(ioaddr + CSR5),
565 (int)ioread32(ioaddr + CSR6),
566 (int)ioread32(ioaddr + CSR7),
567 (int)ioread32(ioaddr + CSR12));
1da177e4 568 } else {
d60bec4e
JP		 569 dev_warn(&dev->dev,
570 "Transmit timed out, status %08x, CSR12 %08x, resetting...\n",
571 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
1da177e4
LT		 572 dev->if_port = 0;
573 }
574
575#if defined(way_too_many_messages)
576 if (tulip_debug > 3) {
577 int i;
578 for (i = 0; i < RX_RING_SIZE; i++) {
579 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
580 int j;
d60bec4e
JP		 581 printk(KERN_DEBUG
582 "%2d: %08x %08x %08x %08x %02x %02x %02x\n",
583 i,
584 (unsigned int)tp->rx_ring[i].status,
585 (unsigned int)tp->rx_ring[i].length,
586 (unsigned int)tp->rx_ring[i].buffer1,
587 (unsigned int)tp->rx_ring[i].buffer2,
588 buf[0], buf[1], buf[2]);
1da177e4 589 for (j = 0; buf[j] != 0xee && j < 1600; j++)
ad361c98 590 if (j < 100)
d60bec4e
JP		 591 pr_cont(" %02x", buf[j]);
592 pr_cont(" j=%d\n", j);
1da177e4 593 }
d60bec4e 594 printk(KERN_DEBUG " Rx ring %08x: ", (int)tp->rx_ring);
1da177e4 595 for (i = 0; i < RX_RING_SIZE; i++)
d60bec4e
JP		 596 pr_cont(" %08x", (unsigned int)tp->rx_ring[i].status);
597 printk(KERN_DEBUG " Tx ring %08x: ", (int)tp->tx_ring);
1da177e4 598 for (i = 0; i < TX_RING_SIZE; i++)
d60bec4e
JP		 599 pr_cont(" %08x", (unsigned int)tp->tx_ring[i].status);
600 pr_cont("\n");
1da177e4
LT		 601 }
602#endif
603
0bb3cf72 604 tulip_tx_timeout_complete(tp, ioaddr);
1da177e4 605
0bb3cf72 606out_unlock:
1da177e4
LT		 607 spin_unlock_irqrestore (&tp->lock, flags);
608 dev->trans_start = jiffies;
609 netif_wake_queue (dev);
610}
611
612
613/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
614static void tulip_init_ring(struct net_device *dev)
615{
616 struct tulip_private *tp = netdev_priv(dev);
617 int i;
618
619 tp->susp_rx = 0;
620 tp->ttimer = 0;
621 tp->nir = 0;
622
623 for (i = 0; i < RX_RING_SIZE; i++) {
624 tp->rx_ring[i].status = 0x00000000;
625 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
626 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
627 tp->rx_buffers[i].skb = NULL;
628 tp->rx_buffers[i].mapping = 0;
629 }
630 /* Mark the last entry as wrapping the ring. */
631 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
632 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
633
634 for (i = 0; i < RX_RING_SIZE; i++) {
635 dma_addr_t mapping;
636
637 /* Note the receive buffer must be longword aligned.
638 dev_alloc_skb() provides 16 byte alignment. But do *not*
639 use skb_reserve() to align the IP header! */
640 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
641 tp->rx_buffers[i].skb = skb;
642 if (skb == NULL)
643 break;
689be439 644 mapping = pci_map_single(tp->pdev, skb->data,
1da177e4
LT		 645 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
646 tp->rx_buffers[i].mapping = mapping;
647 skb->dev = dev; /* Mark as being used by this device. */
648 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
649 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
650 }
651 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
652
653 /* The Tx buffer descriptor is filled in as needed, but we
654 do need to clear the ownership bit. */
655 for (i = 0; i < TX_RING_SIZE; i++) {
656 tp->tx_buffers[i].skb = NULL;
657 tp->tx_buffers[i].mapping = 0;
658 tp->tx_ring[i].status = 0x00000000;
659 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
660 }
661 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
662}
663
ad096463 664static netdev_tx_t
1da177e4
LT		 665tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
666{
667 struct tulip_private *tp = netdev_priv(dev);
668 int entry;
669 u32 flag;
670 dma_addr_t mapping;
22580f89 671 unsigned long flags;
1da177e4 672
22580f89 673 spin_lock_irqsave(&tp->lock, flags);
1da177e4
LT		 674
675 /* Calculate the next Tx descriptor entry. */
676 entry = tp->cur_tx % TX_RING_SIZE;
677
678 tp->tx_buffers[entry].skb = skb;
679 mapping = pci_map_single(tp->pdev, skb->data,
680 skb->len, PCI_DMA_TODEVICE);
681 tp->tx_buffers[entry].mapping = mapping;
682 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
683
684 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
685 flag = 0x60000000; /* No interrupt */
686 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
687 flag = 0xe0000000; /* Tx-done intr. */
688 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
689 flag = 0x60000000; /* No Tx-done intr. */
690 } else { /* Leave room for set_rx_mode() to fill entries. */
691 flag = 0xe0000000; /* Tx-done intr. */
692 netif_stop_queue(dev);
693 }
694 if (entry == TX_RING_SIZE-1)
695 flag = 0xe0000000 | DESC_RING_WRAP;
696
697 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
698 /* if we were using Transmit Automatic Polling, we would need a
699 * wmb() here. */
700 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
701 wmb();
702
703 tp->cur_tx++;
704
705 /* Trigger an immediate transmit demand. */
706 iowrite32(0, tp->base_addr + CSR1);
707
22580f89 708 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 709
710 dev->trans_start = jiffies;
711
6ed10654 712 return NETDEV_TX_OK;
1da177e4
LT		 713}
714
715static void tulip_clean_tx_ring(struct tulip_private *tp)
716{
717 unsigned int dirty_tx;
718
719 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
720 dirty_tx++) {
721 int entry = dirty_tx % TX_RING_SIZE;
722 int status = le32_to_cpu(tp->tx_ring[entry].status);
723
724 if (status < 0) {
725 tp->stats.tx_errors++; /* It wasn't Txed */
726 tp->tx_ring[entry].status = 0;
727 }
728
729 /* Check for Tx filter setup frames. */
730 if (tp->tx_buffers[entry].skb == NULL) {
731 /* test because dummy frames not mapped */
732 if (tp->tx_buffers[entry].mapping)
733 pci_unmap_single(tp->pdev,
734 tp->tx_buffers[entry].mapping,
735 sizeof(tp->setup_frame),
736 PCI_DMA_TODEVICE);
737 continue;
738 }
739
740 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
741 tp->tx_buffers[entry].skb->len,
742 PCI_DMA_TODEVICE);
743
744 /* Free the original skb. */
745 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
746 tp->tx_buffers[entry].skb = NULL;
747 tp->tx_buffers[entry].mapping = 0;
748 }
749}
750
751static void tulip_down (struct net_device *dev)
752{
753 struct tulip_private *tp = netdev_priv(dev);
754 void __iomem *ioaddr = tp->base_addr;
755 unsigned long flags;
756
4bb073c0 757 cancel_work_sync(&tp->media_work);
0bb3cf72 758
bea3348e
SH		 759#ifdef CONFIG_TULIP_NAPI
760 napi_disable(&tp->napi);
761#endif
762
1da177e4
LT		 763 del_timer_sync (&tp->timer);
764#ifdef CONFIG_TULIP_NAPI
765 del_timer_sync (&tp->oom_timer);
766#endif
767 spin_lock_irqsave (&tp->lock, flags);
768
769 /* Disable interrupts by clearing the interrupt mask. */
770 iowrite32 (0x00000000, ioaddr + CSR7);
771
772 /* Stop the Tx and Rx processes. */
773 tulip_stop_rxtx(tp);
774
775 /* prepare receive buffers */
776 tulip_refill_rx(dev);
777
778 /* release any unconsumed transmit buffers */
779 tulip_clean_tx_ring(tp);
780
781 if (ioread32 (ioaddr + CSR6) != 0xffffffff)
782 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff;
783
784 spin_unlock_irqrestore (&tp->lock, flags);
785
786 init_timer(&tp->timer);
787 tp->timer.data = (unsigned long)dev;
788 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
789
790 dev->if_port = tp->saved_if_port;
791
792 /* Leave the driver in snooze, not sleep, mode. */
793 tulip_set_power_state (tp, 0, 1);
794}
795
69145635 796static void tulip_free_ring (struct net_device *dev)
1da177e4
LT		 797{
798 struct tulip_private *tp = netdev_priv(dev);
1da177e4
LT		 799 int i;
800
1da177e4
LT		 801 /* Free all the skbuffs in the Rx queue. */
802 for (i = 0; i < RX_RING_SIZE; i++) {
803 struct sk_buff *skb = tp->rx_buffers[i].skb;
804 dma_addr_t mapping = tp->rx_buffers[i].mapping;
805
806 tp->rx_buffers[i].skb = NULL;
807 tp->rx_buffers[i].mapping = 0;
808
809 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
810 tp->rx_ring[i].length = 0;
76285ee0
AV		 811 /* An invalid address. */
812 tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
1da177e4
LT		 813 if (skb) {
814 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
815 PCI_DMA_FROMDEVICE);
816 dev_kfree_skb (skb);
817 }
818 }
69145635 819
1da177e4
LT		 820 for (i = 0; i < TX_RING_SIZE; i++) {
821 struct sk_buff *skb = tp->tx_buffers[i].skb;
822
823 if (skb != NULL) {
824 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
825 skb->len, PCI_DMA_TODEVICE);
826 dev_kfree_skb (skb);
827 }
828 tp->tx_buffers[i].skb = NULL;
829 tp->tx_buffers[i].mapping = 0;
830 }
69145635
KM		 831}
832
833static int tulip_close (struct net_device *dev)
834{
835 struct tulip_private *tp = netdev_priv(dev);
836 void __iomem *ioaddr = tp->base_addr;
837
838 netif_stop_queue (dev);
839
840 tulip_down (dev);
841
842 if (tulip_debug > 1)
d60bec4e
JP		 843 dev_printk(KERN_DEBUG, &dev->dev,
844 "Shutting down ethercard, status was %02x\n",
845 ioread32 (ioaddr + CSR5));
69145635
KM		 846
847 free_irq (dev->irq, dev);
848
849 tulip_free_ring (dev);
1da177e4
LT		 850
851 return 0;
852}
853
854static struct net_device_stats *tulip_get_stats(struct net_device *dev)
855{
856 struct tulip_private *tp = netdev_priv(dev);
857 void __iomem *ioaddr = tp->base_addr;
858
859 if (netif_running(dev)) {
860 unsigned long flags;
861
862 spin_lock_irqsave (&tp->lock, flags);
863
864 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
865
866 spin_unlock_irqrestore(&tp->lock, flags);
867 }
868
869 return &tp->stats;
870}
871
872
873static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
874{
875 struct tulip_private *np = netdev_priv(dev);
876 strcpy(info->driver, DRV_NAME);
877 strcpy(info->version, DRV_VERSION);
878 strcpy(info->bus_info, pci_name(np->pdev));
879}
880
7282d491 881static const struct ethtool_ops ops = {
1da177e4
LT		 882 .get_drvinfo = tulip_get_drvinfo
883};
884
885/* Provide ioctl() calls to examine the MII xcvr state. */
886static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
887{
888 struct tulip_private *tp = netdev_priv(dev);
889 void __iomem *ioaddr = tp->base_addr;
890 struct mii_ioctl_data *data = if_mii(rq);
891 const unsigned int phy_idx = 0;
892 int phy = tp->phys[phy_idx] & 0x1f;
893 unsigned int regnum = data->reg_num;
894
895 switch (cmd) {
896 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
897 if (tp->mii_cnt)
898 data->phy_id = phy;
899 else if (tp->flags & HAS_NWAY)
900 data->phy_id = 32;
901 else if (tp->chip_id == COMET)
902 data->phy_id = 1;
903 else
904 return -ENODEV;
905
906 case SIOCGMIIREG: /* Read MII PHY register. */
907 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
908 int csr12 = ioread32 (ioaddr + CSR12);
909 int csr14 = ioread32 (ioaddr + CSR14);
910 switch (regnum) {
911 case 0:
912 if (((csr14<<5) & 0x1000) ||
913 (dev->if_port == 5 && tp->nwayset))
914 data->val_out = 0x1000;
915 else
916 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
917 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
918 break;
919 case 1:
920 data->val_out =
921 0x1848 +
922 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
923 ((csr12&0x06) == 6 ? 0 : 4);
924 data->val_out |= 0x6048;
925 break;
926 case 4:
927 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
928 data->val_out =
929 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
930 ((csr14 >> 1) & 0x20) + 1;
931 data->val_out |= ((csr14 >> 9) & 0x03C0);
932 break;
933 case 5: data->val_out = tp->lpar; break;
934 default: data->val_out = 0; break;
935 }
936 } else {
937 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
938 }
939 return 0;
940
941 case SIOCSMIIREG: /* Write MII PHY register. */
1da177e4
LT		 942 if (regnum & ~0x1f)
943 return -EINVAL;
944 if (data->phy_id == phy) {
945 u16 value = data->val_in;
946 switch (regnum) {
947 case 0: /* Check for autonegotiation on or reset. */
948 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
949 if (tp->full_duplex_lock)
950 tp->full_duplex = (value & 0x0100) ? 1 : 0;
951 break;
952 case 4:
953 tp->advertising[phy_idx] =
954 tp->mii_advertise = data->val_in;
955 break;
956 }
957 }
958 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
959 u16 value = data->val_in;
960 if (regnum == 0) {
961 if ((value & 0x1200) == 0x1200) {
962 if (tp->chip_id == PNIC2) {
963 pnic2_start_nway (dev);
964 } else {
965 t21142_start_nway (dev);
966 }
967 }
968 } else if (regnum == 4)
969 tp->sym_advertise = value;
970 } else {
971 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
972 }
973 return 0;
974 default:
975 return -EOPNOTSUPP;
976 }
977
978 return -EOPNOTSUPP;
979}
980
981
982/* Set or clear the multicast filter for this adaptor.
983 Note that we only use exclusion around actually queueing the
984 new frame, not around filling tp->setup_frame. This is non-deterministic
985 when re-entered but still correct. */
986
987#undef set_bit_le
988#define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
989
990static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
991{
992 struct tulip_private *tp = netdev_priv(dev);
993 u16 hash_table[32];
994 struct dev_mc_list *mclist;
995 int i;
996 u16 *eaddrs;
997
998 memset(hash_table, 0, sizeof(hash_table));
999 set_bit_le(255, hash_table); /* Broadcast entry */
1000 /* This should work on big-endian machines as well. */
4302b67e 1001 netdev_for_each_mc_addr(mclist, dev) {
1da177e4
LT		 1002 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
1003
1004 set_bit_le(index, hash_table);
1da177e4
LT		 1005 }
1006 for (i = 0; i < 32; i++) {
1007 *setup_frm++ = hash_table[i];
1008 *setup_frm++ = hash_table[i];
1009 }
1010 setup_frm = &tp->setup_frame[13*6];
1011
1012 /* Fill the final entry with our physical address. */
1013 eaddrs = (u16 *)dev->dev_addr;
1014 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1015 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1016 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1017}
1018
1019static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
1020{
1021 struct tulip_private *tp = netdev_priv(dev);
1022 struct dev_mc_list *mclist;
1da177e4
LT		 1023 u16 *eaddrs;
1024
1025 /* We have <= 14 addresses so we can use the wonderful
1026 16 address perfect filtering of the Tulip. */
4302b67e 1027 netdev_for_each_mc_addr(mclist, dev) {
1da177e4
LT		 1028 eaddrs = (u16 *)mclist->dmi_addr;
1029 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1030 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1031 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1032 }
1033 /* Fill the unused entries with the broadcast address. */
4302b67e 1034 memset(setup_frm, 0xff, (15 - netdev_mc_count(dev)) * 12);
1da177e4
LT		 1035 setup_frm = &tp->setup_frame[15*6];
1036
1037 /* Fill the final entry with our physical address. */
1038 eaddrs = (u16 *)dev->dev_addr;
1039 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1040 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1041 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1042}
1043
1044
1045static void set_rx_mode(struct net_device *dev)
1046{
1047 struct tulip_private *tp = netdev_priv(dev);
1048 void __iomem *ioaddr = tp->base_addr;
1049 int csr6;
1050
1051 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1052
1053 tp->csr6 &= ~0x00D5;
1054 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1055 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1056 csr6 |= AcceptAllMulticast | AcceptAllPhys;
4cd24eaf
JP		 1057 } else if ((netdev_mc_count(dev) > 1000) ||
1058 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 1059 /* Too many to filter well -- accept all multicasts. */
1060 tp->csr6 |= AcceptAllMulticast;
1061 csr6 |= AcceptAllMulticast;
1062 } else if (tp->flags & MC_HASH_ONLY) {
1063 /* Some work-alikes have only a 64-entry hash filter table. */
1064 /* Should verify correctness on big-endian/__powerpc__ */
1065 struct dev_mc_list *mclist;
4cd24eaf
JP		 1066 if (netdev_mc_count(dev) > 64) {
1067 /* Arbitrary non-effective limit. */
1da177e4
LT		 1068 tp->csr6 |= AcceptAllMulticast;
1069 csr6 |= AcceptAllMulticast;
1070 } else {
1071 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1072 int filterbit;
4302b67e 1073 netdev_for_each_mc_addr(mclist, dev) {
1da177e4
LT		 1074 if (tp->flags & COMET_MAC_ADDR)
1075 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1076 else
1077 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1078 filterbit &= 0x3f;
1079 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
e174961c 1080 if (tulip_debug > 2)
d60bec4e
JP		 1081 dev_info(&dev->dev,
1082 "Added filter for %pM %08x bit %d\n",
1083 mclist->dmi_addr,
1084 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1da177e4
LT		 1085 }
1086 if (mc_filter[0] == tp->mc_filter[0] &&
1087 mc_filter[1] == tp->mc_filter[1])
1088 ; /* No change. */
1089 else if (tp->flags & IS_ASIX) {
1090 iowrite32(2, ioaddr + CSR13);
1091 iowrite32(mc_filter[0], ioaddr + CSR14);
1092 iowrite32(3, ioaddr + CSR13);
1093 iowrite32(mc_filter[1], ioaddr + CSR14);
1094 } else if (tp->flags & COMET_MAC_ADDR) {
1095 iowrite32(mc_filter[0], ioaddr + 0xAC);
1096 iowrite32(mc_filter[1], ioaddr + 0xB0);
1097 }
1098 tp->mc_filter[0] = mc_filter[0];
1099 tp->mc_filter[1] = mc_filter[1];
1100 }
1101 } else {
1102 unsigned long flags;
1103 u32 tx_flags = 0x08000000 | 192;
1104
1105 /* Note that only the low-address shortword of setup_frame is valid!
1106 The values are doubled for big-endian architectures. */
4cd24eaf
JP		 1107 if (netdev_mc_count(dev) > 14) {
1108 /* Must use a multicast hash table. */
1da177e4
LT		 1109 build_setup_frame_hash(tp->setup_frame, dev);
1110 tx_flags = 0x08400000 | 192;
1111 } else {
1112 build_setup_frame_perfect(tp->setup_frame, dev);
1113 }
1114
1115 spin_lock_irqsave(&tp->lock, flags);
1116
1117 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1118 /* Same setup recently queued, we need not add it. */
1119 } else {
1120 unsigned int entry;
1121 int dummy = -1;
1122
1123 /* Now add this frame to the Tx list. */
1124
1125 entry = tp->cur_tx++ % TX_RING_SIZE;
1126
1127 if (entry != 0) {
ea8f400c
PC		 1128 /* Avoid a chip errata by prefixing a dummy entry. */
1129 tp->tx_buffers[entry].skb = NULL;
1130 tp->tx_buffers[entry].mapping = 0;
1131 tp->tx_ring[entry].length =
1132 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1133 tp->tx_ring[entry].buffer1 = 0;
1134 /* Must set DescOwned later to avoid race with chip */
1135 dummy = entry;
1136 entry = tp->cur_tx++ % TX_RING_SIZE;
1137
1da177e4
LT		 1138 }
1139
1140 tp->tx_buffers[entry].skb = NULL;
1141 tp->tx_buffers[entry].mapping =
1142 pci_map_single(tp->pdev, tp->setup_frame,
1143 sizeof(tp->setup_frame),
1144 PCI_DMA_TODEVICE);
1145 /* Put the setup frame on the Tx list. */
1146 if (entry == TX_RING_SIZE-1)
1147 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1148 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1149 tp->tx_ring[entry].buffer1 =
1150 cpu_to_le32(tp->tx_buffers[entry].mapping);
1151 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1152 if (dummy >= 0)
1153 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1154 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1155 netif_stop_queue(dev);
1156
1157 /* Trigger an immediate transmit demand. */
1158 iowrite32(0, ioaddr + CSR1);
1159 }
1160
1161 spin_unlock_irqrestore(&tp->lock, flags);
1162 }
1163
1164 iowrite32(csr6, ioaddr + CSR6);
1165}
1166
1167#ifdef CONFIG_TULIP_MWI
1168static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1169 struct net_device *dev)
1170{
1171 struct tulip_private *tp = netdev_priv(dev);
1172 u8 cache;
1173 u16 pci_command;
1174 u32 csr0;
1175
1176 if (tulip_debug > 3)
1177 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1178
1179 tp->csr0 = csr0 = 0;
1180
10c64620
PH		 1181 /* if we have any cache line size at all, we can do MRM and MWI */
1182 csr0 |= MRM | MWI;
1da177e4 1183
10c64620
PH		 1184 /* Enable MWI in the standard PCI command bit.
1185 * Check for the case where MWI is desired but not available
1da177e4 1186 */
10c64620 1187 pci_try_set_mwi(pdev);
1da177e4
LT		 1188
1189 /* read result from hardware (in case bit refused to enable) */
1190 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1191 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1192 csr0 &= ~MWI;
1193
1194 /* if cache line size hardwired to zero, no MWI */
1195 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1196 if ((csr0 & MWI) && (cache == 0)) {
1197 csr0 &= ~MWI;
1198 pci_clear_mwi(pdev);
1199 }
1200
1201 /* assign per-cacheline-size cache alignment and
1202 * burst length values
1203 */
1204 switch (cache) {
1205 case 8:
1206 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1207 break;
1208 case 16:
1209 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1210 break;
1211 case 32:
1212 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1213 break;
1214 default:
1215 cache = 0;
1216 break;
1217 }
1218
1219 /* if we have a good cache line size, we by now have a good
1220 * csr0, so save it and exit
1221 */
1222 if (cache)
1223 goto out;
1224
1225 /* we don't have a good csr0 or cache line size, disable MWI */
1226 if (csr0 & MWI) {
1227 pci_clear_mwi(pdev);
1228 csr0 &= ~MWI;
1229 }
1230
1231 /* sane defaults for burst length and cache alignment
1232 * originally from de4x5 driver
1233 */
1234 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1235
1236out:
1237 tp->csr0 = csr0;
1238 if (tulip_debug > 2)
1239 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1240 pci_name(pdev), cache, csr0);
1241}
1242#endif
1243
1244/*
1245 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1246 * is the DM910X and the on chip ULi devices
1247 */
f3b197ac 1248
1da177e4
LT		 1249static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1250{
1251 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1252 return 1;
1da177e4
LT		 1253 return 0;
1254}
1255
f4266cf3
SH		 1256static const struct net_device_ops tulip_netdev_ops = {
1257 .ndo_open = tulip_open,
1258 .ndo_start_xmit = tulip_start_xmit,
1259 .ndo_tx_timeout = tulip_tx_timeout,
1260 .ndo_stop = tulip_close,
1261 .ndo_get_stats = tulip_get_stats,
1262 .ndo_do_ioctl = private_ioctl,
1263 .ndo_set_multicast_list = set_rx_mode,
1264 .ndo_change_mtu = eth_change_mtu,
1265 .ndo_set_mac_address = eth_mac_addr,
1266 .ndo_validate_addr = eth_validate_addr,
1267#ifdef CONFIG_NET_POLL_CONTROLLER
1268 .ndo_poll_controller = poll_tulip,
1269#endif
1270};
1271
1da177e4
LT		 1272static int __devinit tulip_init_one (struct pci_dev *pdev,
1273 const struct pci_device_id *ent)
1274{
1275 struct tulip_private *tp;
1276 /* See note below on the multiport cards. */
1277 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1278 static struct pci_device_id early_486_chipsets[] = {
1279 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1280 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1281 { },
1282 };
1283 static int last_irq;
1284 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1da177e4
LT		 1285 int i, irq;
1286 unsigned short sum;
1287 unsigned char *ee_data;
1288 struct net_device *dev;
1289 void __iomem *ioaddr;
1290 static int board_idx = -1;
1291 int chip_idx = ent->driver_data;
1292 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1293 unsigned int eeprom_missing = 0;
1294 unsigned int force_csr0 = 0;
1295
1296#ifndef MODULE
d60bec4e
JP		 1297 if (tulip_debug > 0)
1298 printk_once(KERN_INFO "%s", version);
1da177e4
LT		 1299#endif
1300
1301 board_idx++;
1302
1303 /*
1304 * Lan media wire a tulip chip to a wan interface. Needs a very
1305 * different driver (lmc driver)
1306 */
1307
1308 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
d60bec4e 1309 pr_err(PFX "skipping LMC card\n");
1da177e4
LT		 1310 return -ENODEV;
1311 }
1312
1313 /*
4d907069
BH		 1314 * DM910x chips should be handled by the dmfe driver, except
1315 * on-board chips on SPARC systems. Also, early DM9100s need
1316 * software CRC which only the dmfe driver supports.
1da177e4
LT		 1317 */
1318
4d907069
BH		 1319#ifdef CONFIG_TULIP_DM910X
1320 if (chip_idx == DM910X) {
1321 struct device_node *dp;
1322
1323 if (pdev->vendor == 0x1282 && pdev->device == 0x9100 &&
1324 pdev->revision < 0x30) {
d60bec4e 1325 pr_info(PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
4d907069
BH		 1326 return -ENODEV;
1327 }
1328
1329 dp = pci_device_to_OF_node(pdev);
1330 if (!(dp && of_get_property(dp, "local-mac-address", NULL))) {
d60bec4e 1331 pr_info(PFX "skipping DM910x expansion card (use dmfe)\n");
1da177e4
LT		 1332 return -ENODEV;
1333 }
1334 }
4d907069 1335#endif
1da177e4
LT		 1336
1337 /*
1338 * Looks for early PCI chipsets where people report hangs
1339 * without the workarounds being on.
1340 */
1341
1342 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
f3b197ac 1343 aligned. Aries might need this too. The Saturn errata are not
1da177e4
LT		 1344 pretty reading but thankfully it's an old 486 chipset.
1345
1346 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1347 Saturn.
1348 */
1349
1350 if (pci_dev_present(early_486_chipsets)) {
1351 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1352 force_csr0 = 1;
1353 }
1354
1355 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1356 if (chip_idx == AX88140) {
1357 if ((csr0 & 0x3f00) == 0)
1358 csr0 |= 0x2000;
1359 }
1360
1361 /* PNIC doesn't have MWI/MRL/MRM... */
1362 if (chip_idx == LC82C168)
1363 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1364
1365 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1366 if (tulip_uli_dm_quirk(pdev)) {
1367 csr0 &= ~0x01f100ff;
49345103 1368#if defined(CONFIG_SPARC)
1da177e4
LT		 1369 csr0 = (csr0 & ~0xff00) | 0xe000;
1370#endif
1371 }
1372 /*
1373 * And back to business
1374 */
1375
1376 i = pci_enable_device(pdev);
1377 if (i) {
d60bec4e
JP		 1378 pr_err(PFX "Cannot enable tulip board #%d, aborting\n",
1379 board_idx);
1da177e4
LT		 1380 return i;
1381 }
1382
1383 irq = pdev->irq;
1384
1385 /* alloc_etherdev ensures aligned and zeroed private structures */
1386 dev = alloc_etherdev (sizeof (*tp));
1387 if (!dev) {
d60bec4e 1388 pr_err(PFX "ether device alloc failed, aborting\n");
1da177e4
LT		 1389 return -ENOMEM;
1390 }
1391
1da177e4
LT		 1392 SET_NETDEV_DEV(dev, &pdev->dev);
1393 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
d60bec4e
JP		 1394 pr_err(PFX "%s: I/O region (0x%llx@0x%llx) too small, aborting\n",
1395 pci_name(pdev),
1396 (unsigned long long)pci_resource_len (pdev, 0),
1397 (unsigned long long)pci_resource_start (pdev, 0));
1da177e4
LT		 1398 goto err_out_free_netdev;
1399 }
1400
1401 /* grab all resources from both PIO and MMIO regions, as we
1402 * don't want anyone else messing around with our hardware */
d60bec4e 1403 if (pci_request_regions (pdev, DRV_NAME))
1da177e4
LT		 1404 goto err_out_free_netdev;
1405
7f2b1248
GG		 1406 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1407
1da177e4
LT		 1408 if (!ioaddr)
1409 goto err_out_free_res;
1410
1da177e4
LT		 1411 /*
1412 * initialize private data structure 'tp'
1413 * it is zeroed and aligned in alloc_etherdev
1414 */
1415 tp = netdev_priv(dev);
c4028958 1416 tp->dev = dev;
1da177e4
LT		 1417
1418 tp->rx_ring = pci_alloc_consistent(pdev,
1419 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1420 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1421 &tp->rx_ring_dma);
1422 if (!tp->rx_ring)
1423 goto err_out_mtable;
1424 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1425 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1426
1427 tp->chip_id = chip_idx;
1428 tp->flags = tulip_tbl[chip_idx].flags;
1429 tp->pdev = pdev;
1430 tp->base_addr = ioaddr;
44c10138 1431 tp->revision = pdev->revision;
1da177e4
LT		 1432 tp->csr0 = csr0;
1433 spin_lock_init(&tp->lock);
1434 spin_lock_init(&tp->mii_lock);
1435 init_timer(&tp->timer);
1436 tp->timer.data = (unsigned long)dev;
1437 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1438
c4028958 1439 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
0bb3cf72 1440
1da177e4
LT		 1441 dev->base_addr = (unsigned long)ioaddr;
1442
1443#ifdef CONFIG_TULIP_MWI
1444 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1445 tulip_mwi_config (pdev, dev);
1da177e4
LT		 1446#endif
1447
1448 /* Stop the chip's Tx and Rx processes. */
1449 tulip_stop_rxtx(tp);
1450
1451 pci_set_master(pdev);
1452
1453#ifdef CONFIG_GSC
1454 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1455 switch (pdev->subsystem_device) {
1456 default:
1457 break;
1458 case 0x1061:
1459 case 0x1062:
1460 case 0x1063:
1461 case 0x1098:
1462 case 0x1099:
1463 case 0x10EE:
1464 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1465 chip_name = "GSC DS21140 Tulip";
1466 }
1467 }
1468#endif
1469
1470 /* Clear the missed-packet counter. */
1471 ioread32(ioaddr + CSR8);
1472
1473 /* The station address ROM is read byte serially. The register must
1474 be polled, waiting for the value to be read bit serially from the
1475 EEPROM.
1476 */
1477 ee_data = tp->eeprom;
209261c0 1478 memset(ee_data, 0, sizeof(tp->eeprom));
1da177e4
LT		 1479 sum = 0;
1480 if (chip_idx == LC82C168) {
1481 for (i = 0; i < 3; i++) {
1482 int value, boguscnt = 100000;
1483 iowrite32(0x600 | i, ioaddr + 0x98);
ec1d1ebb 1484 do {
1da177e4 1485 value = ioread32(ioaddr + CSR9);
ec1d1ebb 1486 } while (value < 0 && --boguscnt > 0);
6caf52a4 1487 put_unaligned_le16(value, ((__le16 *)dev->dev_addr) + i);
1da177e4
LT		 1488 sum += value & 0xffff;
1489 }
1490 } else if (chip_idx == COMET) {
1491 /* No need to read the EEPROM. */
6caf52a4
HH		 1492 put_unaligned_le32(ioread32(ioaddr + 0xA4), dev->dev_addr);
1493 put_unaligned_le16(ioread32(ioaddr + 0xA8), dev->dev_addr + 4);
1da177e4
LT		 1494 for (i = 0; i < 6; i ++)
1495 sum += dev->dev_addr[i];
1496 } else {
1497 /* A serial EEPROM interface, we read now and sort it out later. */
1498 int sa_offset = 0;
1499 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
209261c0 1500 int ee_max_addr = ((1 << ee_addr_size) - 1) * sizeof(u16);
1da177e4 1501
209261c0
GG		 1502 if (ee_max_addr > sizeof(tp->eeprom))
1503 ee_max_addr = sizeof(tp->eeprom);
1504
1505 for (i = 0; i < ee_max_addr ; i += sizeof(u16)) {
1da177e4
LT		 1506 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1507 ee_data[i] = data & 0xff;
1508 ee_data[i + 1] = data >> 8;
1509 }
1510
1511 /* DEC now has a specification (see Notes) but early board makers
1512 just put the address in the first EEPROM locations. */
1513 /* This does memcmp(ee_data, ee_data+16, 8) */
1514 for (i = 0; i < 8; i ++)
1515 if (ee_data[i] != ee_data[16+i])
1516 sa_offset = 20;
1517 if (chip_idx == CONEXANT) {
1518 /* Check that the tuple type and length is correct. */
1519 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1520 sa_offset = 0x19A;
1521 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1522 ee_data[2] == 0) {
1523 sa_offset = 2; /* Grrr, damn Matrox boards. */
1524 multiport_cnt = 4;
1525 }
1da177e4 1526#ifdef CONFIG_MIPS_COBALT
f3b197ac 1527 if ((pdev->bus->number == 0) &&
1da177e4
LT		 1528 ((PCI_SLOT(pdev->devfn) == 7) ||
1529 (PCI_SLOT(pdev->devfn) == 12))) {
1530 /* Cobalt MAC address in first EEPROM locations. */
1531 sa_offset = 0;
12755c16
RB		 1532 /* Ensure our media table fixup get's applied */
1533 memcpy(ee_data + 16, ee_data, 8);
1da177e4
LT		 1534 }
1535#endif
1536#ifdef CONFIG_GSC
1537 /* Check to see if we have a broken srom */
1538 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1539 /* pci_vendor_id and subsystem_id are swapped */
1540 ee_data[0] = ee_data[2];
1541 ee_data[1] = ee_data[3];
1542 ee_data[2] = 0x61;
1543 ee_data[3] = 0x10;
1544
1545 /* HSC-PCI boards need to be byte-swaped and shifted
1546 * up 1 word. This shift needs to happen at the end
1547 * of the MAC first because of the 2 byte overlap.
1548 */
1549 for (i = 4; i >= 0; i -= 2) {
1550 ee_data[17 + i + 3] = ee_data[17 + i];
1551 ee_data[16 + i + 5] = ee_data[16 + i];
1552 }
1553 }
1554#endif
1555
1556 for (i = 0; i < 6; i ++) {
1557 dev->dev_addr[i] = ee_data[i + sa_offset];
1558 sum += ee_data[i + sa_offset];
1559 }
1560 }
1561 /* Lite-On boards have the address byte-swapped. */
8e95a202
JP		 1562 if ((dev->dev_addr[0] == 0xA0 ||
1563 dev->dev_addr[0] == 0xC0 ||
1564 dev->dev_addr[0] == 0x02) &&
1565 dev->dev_addr[1] == 0x00)
1da177e4
LT		 1566 for (i = 0; i < 6; i+=2) {
1567 char tmp = dev->dev_addr[i];
1568 dev->dev_addr[i] = dev->dev_addr[i+1];
1569 dev->dev_addr[i+1] = tmp;
1570 }
1571 /* On the Zynx 315 Etherarray and other multiport boards only the
1572 first Tulip has an EEPROM.
1573 On Sparc systems the mac address is held in the OBP property
1574 "local-mac-address".
1575 The addresses of the subsequent ports are derived from the first.
1576 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1577 that here as well. */
1578 if (sum == 0 || sum == 6*0xff) {
49345103 1579#if defined(CONFIG_SPARC)
d297c31f
DM		 1580 struct device_node *dp = pci_device_to_OF_node(pdev);
1581 const unsigned char *addr;
1582 int len;
1da177e4
LT		 1583#endif
1584 eeprom_missing = 1;
1585 for (i = 0; i < 5; i++)
1586 dev->dev_addr[i] = last_phys_addr[i];
1587 dev->dev_addr[i] = last_phys_addr[i] + 1;
49345103 1588#if defined(CONFIG_SPARC)
d297c31f
DM		 1589 addr = of_get_property(dp, "local-mac-address", &len);
1590 if (addr && len == 6)
1591 memcpy(dev->dev_addr, addr, 6);
1da177e4 1592#endif
b9c4c609 1593#if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1da177e4
LT		 1594 if (last_irq)
1595 irq = last_irq;
1596#endif
1597 }
1598
1599 for (i = 0; i < 6; i++)
1600 last_phys_addr[i] = dev->dev_addr[i];
1601 last_irq = irq;
1602 dev->irq = irq;
1603
1604 /* The lower four bits are the media type. */
1605 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1606 if (options[board_idx] & MEDIA_MASK)
1607 tp->default_port = options[board_idx] & MEDIA_MASK;
1608 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1609 tp->full_duplex = 1;
1610 if (mtu[board_idx] > 0)
1611 dev->mtu = mtu[board_idx];
1612 }
1613 if (dev->mem_start & MEDIA_MASK)
1614 tp->default_port = dev->mem_start & MEDIA_MASK;
1615 if (tp->default_port) {
d60bec4e
JP		 1616 pr_info(DRV_NAME "%d: Transceiver selection forced to %s\n",
1617 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1da177e4
LT		 1618 tp->medialock = 1;
1619 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1620 tp->full_duplex = 1;
1621 }
1622 if (tp->full_duplex)
1623 tp->full_duplex_lock = 1;
1624
1625 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1626 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1627 tp->mii_advertise = media2advert[tp->default_port - 9];
1628 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1629 }
1630
1631 if (tp->flags & HAS_MEDIA_TABLE) {
d60bec4e 1632 sprintf(dev->name, DRV_NAME "%d", board_idx); /* hack */
1da177e4
LT		 1633 tulip_parse_eeprom(dev);
1634 strcpy(dev->name, "eth%d"); /* un-hack */
1635 }
1636
1637 if ((tp->flags & ALWAYS_CHECK_MII) ||
1638 (tp->mtable && tp->mtable->has_mii) ||
1639 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1640 if (tp->mtable && tp->mtable->has_mii) {
1641 for (i = 0; i < tp->mtable->leafcount; i++)
1642 if (tp->mtable->mleaf[i].media == 11) {
1643 tp->cur_index = i;
1644 tp->saved_if_port = dev->if_port;
1645 tulip_select_media(dev, 2);
1646 dev->if_port = tp->saved_if_port;
1647 break;
1648 }
1649 }
1650
1651 /* Find the connected MII xcvrs.
1652 Doing this in open() would allow detecting external xcvrs
1653 later, but takes much time. */
1654 tulip_find_mii (dev, board_idx);
1655 }
1656
1657 /* The Tulip-specific entries in the device structure. */
f4266cf3 1658 dev->netdev_ops = &tulip_netdev_ops;
1da177e4
LT		 1659 dev->watchdog_timeo = TX_TIMEOUT;
1660#ifdef CONFIG_TULIP_NAPI
bea3348e 1661 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1da177e4
LT		 1662#endif
1663 SET_ETHTOOL_OPS(dev, &ops);
1664
1665 if (register_netdev(dev))
1666 goto err_out_free_ring;
1667
d60bec4e
JP		 1668 pci_set_drvdata(pdev, dev);
1669
1670 dev_info(&dev->dev,
c69f4122 1671#ifdef CONFIG_TULIP_MMIO
d60bec4e 1672 "%s rev %d at MMIO %#llx,%s %pM, IRQ %d\n",
c69f4122 1673#else
d60bec4e 1674 "%s rev %d at Port %#llx,%s %pM, IRQ %d\n",
c69f4122 1675#endif
d60bec4e
JP		 1676 chip_name, pdev->revision,
1677 (unsigned long long)pci_resource_start(pdev, TULIP_BAR),
1678 eeprom_missing ? " EEPROM not present," : "",
1679 dev->dev_addr, irq);
1da177e4
LT		 1680
1681 if (tp->chip_id == PNIC2)
1682 tp->link_change = pnic2_lnk_change;
1683 else if (tp->flags & HAS_NWAY)
1684 tp->link_change = t21142_lnk_change;
1685 else if (tp->flags & HAS_PNICNWAY)
1686 tp->link_change = pnic_lnk_change;
1687
1688 /* Reset the xcvr interface and turn on heartbeat. */
1689 switch (chip_idx) {
1690 case DC21140:
1691 case DM910X:
1da177e4
LT		 1692 default:
1693 if (tp->mtable)
1694 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1695 break;
1696 case DC21142:
1697 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1698 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1699 iowrite32(0x0000, ioaddr + CSR13);
1700 iowrite32(0x0000, ioaddr + CSR14);
1701 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1702 } else
1703 t21142_start_nway(dev);
1704 break;
1705 case PNIC2:
1706 /* just do a reset for sanity sake */
1707 iowrite32(0x0000, ioaddr + CSR13);
1708 iowrite32(0x0000, ioaddr + CSR14);
1709 break;
1710 case LC82C168:
1711 if ( ! tp->mii_cnt) {
1712 tp->nway = 1;
1713 tp->nwayset = 0;
1714 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1715 iowrite32(0x30, ioaddr + CSR12);
1716 iowrite32(0x0001F078, ioaddr + CSR6);
1717 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1718 }
1719 break;
1720 case MX98713:
1721 case COMPEX9881:
1722 iowrite32(0x00000000, ioaddr + CSR6);
1723 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1724 iowrite32(0x00000001, ioaddr + CSR13);
1725 break;
1726 case MX98715:
1727 case MX98725:
1728 iowrite32(0x01a80000, ioaddr + CSR6);
1729 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1730 iowrite32(0x00001000, ioaddr + CSR12);
1731 break;
1732 case COMET:
1733 /* No initialization necessary. */
1734 break;
1735 }
1736
1737 /* put the chip in snooze mode until opened */
1738 tulip_set_power_state (tp, 0, 1);
1739
1740 return 0;
1741
1742err_out_free_ring:
1743 pci_free_consistent (pdev,
1744 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1745 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1746 tp->rx_ring, tp->rx_ring_dma);
1747
1748err_out_mtable:
b4558ea9 1749 kfree (tp->mtable);
1da177e4
LT		 1750 pci_iounmap(pdev, ioaddr);
1751
1752err_out_free_res:
1753 pci_release_regions (pdev);
1754
1755err_out_free_netdev:
1756 free_netdev (dev);
1757 return -ENODEV;
1758}
1759
1760
1761#ifdef CONFIG_PM
1762
1763static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1764{
1765 struct net_device *dev = pci_get_drvdata(pdev);
1766
1fe2cb32
AB		 1767 if (!dev)
1768 return -EINVAL;
1769
56997fa8
GG		 1770 if (!netif_running(dev))
1771 goto save_state;
1772
1773 tulip_down(dev);
1fe2cb32
AB		 1774
1775 netif_device_detach(dev);
1776 free_irq(dev->irq, dev);
1777
56997fa8 1778save_state:
1fe2cb32
AB		 1779 pci_save_state(pdev);
1780 pci_disable_device(pdev);
1781 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1782
1da177e4
LT		 1783 return 0;
1784}
1785
1786
1787static int tulip_resume(struct pci_dev *pdev)
1788{
1789 struct net_device *dev = pci_get_drvdata(pdev);
1fe2cb32 1790 int retval;
1da177e4 1791
1fe2cb32
AB		 1792 if (!dev)
1793 return -EINVAL;
1794
1795 pci_set_power_state(pdev, PCI_D0);
1796 pci_restore_state(pdev);
1797
56997fa8
GG		 1798 if (!netif_running(dev))
1799 return 0;
1800
9f486ae1 1801 if ((retval = pci_enable_device(pdev))) {
d60bec4e 1802 pr_err(PFX "pci_enable_device failed in resume\n");
9f486ae1
VH		 1803 return retval;
1804 }
1fe2cb32 1805
a0607fd3 1806 if ((retval = request_irq(dev->irq, tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
d60bec4e 1807 pr_err(PFX "request_irq failed in resume\n");
1fe2cb32 1808 return retval;
1da177e4 1809 }
1fe2cb32
AB		 1810
1811 netif_device_attach(dev);
1812
1813 if (netif_running(dev))
1814 tulip_up(dev);
1815
1da177e4
LT		 1816 return 0;
1817}
1818
1819#endif /* CONFIG_PM */
1820
1821
1822static void __devexit tulip_remove_one (struct pci_dev *pdev)
1823{
1824 struct net_device *dev = pci_get_drvdata (pdev);
1825 struct tulip_private *tp;
1826
1827 if (!dev)
1828 return;
1829
1830 tp = netdev_priv(dev);
1831 unregister_netdev(dev);
1832 pci_free_consistent (pdev,
1833 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1834 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1835 tp->rx_ring, tp->rx_ring_dma);
b4558ea9 1836 kfree (tp->mtable);
1da177e4
LT		 1837 pci_iounmap(pdev, tp->base_addr);
1838 free_netdev (dev);
1839 pci_release_regions (pdev);
1840 pci_set_drvdata (pdev, NULL);
1841
1842 /* pci_power_off (pdev, -1); */
1843}
1844
1845#ifdef CONFIG_NET_POLL_CONTROLLER
1846/*
1847 * Polling 'interrupt' - used by things like netconsole to send skbs
1848 * without having to re-enable interrupts. It's not called while
1849 * the interrupt routine is executing.
1850 */
1851
1852static void poll_tulip (struct net_device *dev)
1853{
1854 /* disable_irq here is not very nice, but with the lockless
1855 interrupt handler we have no other choice. */
1856 disable_irq(dev->irq);
7d12e780 1857 tulip_interrupt (dev->irq, dev);
1da177e4
LT		 1858 enable_irq(dev->irq);
1859}
1860#endif
1861
1862static struct pci_driver tulip_driver = {
1863 .name = DRV_NAME,
1864 .id_table = tulip_pci_tbl,
1865 .probe = tulip_init_one,
1866 .remove = __devexit_p(tulip_remove_one),
1867#ifdef CONFIG_PM
1868 .suspend = tulip_suspend,
1869 .resume = tulip_resume,
1870#endif /* CONFIG_PM */
1871};
1872
1873
1874static int __init tulip_init (void)
1875{
1876#ifdef MODULE
d60bec4e 1877 pr_info("%s", version);
1da177e4
LT		 1878#endif
1879
1880 /* copy module parms into globals */
1881 tulip_rx_copybreak = rx_copybreak;
1882 tulip_max_interrupt_work = max_interrupt_work;
1883
1884 /* probe for and init boards */
29917620 1885 return pci_register_driver(&tulip_driver);
1da177e4
LT		 1886}
1887
1888
1889static void __exit tulip_cleanup (void)
1890{
1891 pci_unregister_driver (&tulip_driver);
1892}
1893
1894
1895module_init(tulip_init);
1896module_exit(tulip_cleanup);
kernel source for telekom puls (alcatel/mediatek)