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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / tulip / dmfe.c
CommitLineData
1da177e4
LT		 1/*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
113aa838 26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
1da177e4
LT		 27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
113aa838 52 Alan Cox <alan@lxorguk.ukuu.org.uk>
f3b197ac 53 Added new PCI identifiers provided by Clear Zhang at ALi
1da177e4
LT		 54 for their 1563 ethernet device.
55
56 TODO
57
1da177e4
LT		 58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62*/
63
dde7c8ef
JP		 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65
1da177e4
LT		 66#define DRV_NAME "dmfe"
67#define DRV_VERSION "1.36.4"
68#define DRV_RELDATE "2002-01-17"
69
70#include <linux/module.h>
71#include <linux/kernel.h>
72#include <linux/string.h>
73#include <linux/timer.h>
74#include <linux/ptrace.h>
75#include <linux/errno.h>
76#include <linux/ioport.h>
1da177e4
LT		 77#include <linux/interrupt.h>
78#include <linux/pci.h>
cb199d42 79#include <linux/dma-mapping.h>
1da177e4
LT		 80#include <linux/init.h>
81#include <linux/netdevice.h>
82#include <linux/etherdevice.h>
83#include <linux/ethtool.h>
84#include <linux/skbuff.h>
85#include <linux/delay.h>
86#include <linux/spinlock.h>
87#include <linux/crc32.h>
88#include <linux/bitops.h>
89
90#include <asm/processor.h>
91#include <asm/io.h>
92#include <asm/dma.h>
93#include <asm/uaccess.h>
94#include <asm/irq.h>
95
4d907069
BH		 96#ifdef CONFIG_TULIP_DM910X
97#include <linux/of.h>
98#endif
99
1da177e4
LT		 100
101/* Board/System/Debug information/definition ---------------- */
102#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
103#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
104#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
105#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
106
107#define DM9102_IO_SIZE 0x80
108#define DM9102A_IO_SIZE 0x100
109#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
110#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
111#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
112#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
113#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
114#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
115#define TX_BUF_ALLOC 0x600
116#define RX_ALLOC_SIZE 0x620
117#define DM910X_RESET 1
118#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
119#define CR6_DEFAULT 0x00080000 /* HD */
120#define CR7_DEFAULT 0x180c1
121#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
122#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
123#define MAX_PACKET_SIZE 1514
124#define DMFE_MAX_MULTICAST 14
125#define RX_COPY_SIZE 100
126#define MAX_CHECK_PACKET 0x8000
127#define DM9801_NOISE_FLOOR 8
128#define DM9802_NOISE_FLOOR 5
129
f1069046
ML		 130#define DMFE_WOL_LINKCHANGE 0x20000000
131#define DMFE_WOL_SAMPLEPACKET 0x10000000
132#define DMFE_WOL_MAGICPACKET 0x08000000
133
134
1da177e4
LT		 135#define DMFE_10MHF 0
136#define DMFE_100MHF 1
137#define DMFE_10MFD 4
138#define DMFE_100MFD 5
139#define DMFE_AUTO 8
140#define DMFE_1M_HPNA 0x10
141
142#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
143#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
144#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
145#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
146#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
147#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
148
149#define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
150#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
151#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
152
dde7c8ef
JP		 153#define DMFE_DBUG(dbug_now, msg, value) \
154 do { \
155 if (dmfe_debug || (dbug_now)) \
156 pr_err("%s %lx\n", \
157 (msg), (long) (value)); \
f67ba792 158 } while (0)
1da177e4 159
dde7c8ef
JP		 160#define SHOW_MEDIA_TYPE(mode) \
161 pr_info("Change Speed to %sMhz %s duplex\n" , \
162 (mode & 1) ? "100":"10", \
163 (mode & 4) ? "full":"half");
1da177e4
LT		 164
165
166/* CR9 definition: SROM/MII */
167#define CR9_SROM_READ 0x4800
168#define CR9_SRCS 0x1
169#define CR9_SRCLK 0x2
170#define CR9_CRDOUT 0x8
171#define SROM_DATA_0 0x0
172#define SROM_DATA_1 0x4
173#define PHY_DATA_1 0x20000
174#define PHY_DATA_0 0x00000
175#define MDCLKH 0x10000
176
177#define PHY_POWER_DOWN 0x800
178
179#define SROM_V41_CODE 0x14
180
f67ba792
ML		 181#define SROM_CLK_WRITE(data, ioaddr) \
182 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
183 udelay(5); \
184 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
185 udelay(5); \
186 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
187 udelay(5);
188
189#define __CHK_IO_SIZE(pci_id, dev_rev) \
44c10138 190 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
f67ba792 191 DM9102A_IO_SIZE: DM9102_IO_SIZE)
1da177e4 192
44c10138
AK		 193#define CHK_IO_SIZE(pci_dev) \
194 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
195 (pci_dev)->revision))
1da177e4
LT		 196
197/* Sten Check */
198#define DEVICE net_device
199
200/* Structure/enum declaration ------------------------------- */
201struct tx_desc {
a31e40f6 202 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
1da177e4
LT		 203 char *tx_buf_ptr; /* Data for us */
204 struct tx_desc *next_tx_desc;
205} __attribute__(( aligned(32) ));
206
207struct rx_desc {
a31e40f6 208 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
1da177e4
LT		 209 struct sk_buff *rx_skb_ptr; /* Data for us */
210 struct rx_desc *next_rx_desc;
211} __attribute__(( aligned(32) ));
212
213struct dmfe_board_info {
214 u32 chip_id; /* Chip vendor/Device ID */
44c10138 215 u8 chip_revision; /* Chip revision */
ead9bffb 216 struct DEVICE *next_dev; /* next device */
1da177e4
LT		 217 struct pci_dev *pdev; /* PCI device */
218 spinlock_t lock;
219
220 long ioaddr; /* I/O base address */
221 u32 cr0_data;
222 u32 cr5_data;
223 u32 cr6_data;
224 u32 cr7_data;
225 u32 cr15_data;
226
227 /* pointer for memory physical address */
228 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
229 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
230 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
231 dma_addr_t first_tx_desc_dma;
232 dma_addr_t first_rx_desc_dma;
233
234 /* descriptor pointer */
235 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
236 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
237 unsigned char *desc_pool_ptr; /* descriptor pool memory */
238 struct tx_desc *first_tx_desc;
239 struct tx_desc *tx_insert_ptr;
240 struct tx_desc *tx_remove_ptr;
241 struct rx_desc *first_rx_desc;
242 struct rx_desc *rx_insert_ptr;
243 struct rx_desc *rx_ready_ptr; /* packet come pointer */
244 unsigned long tx_packet_cnt; /* transmitted packet count */
245 unsigned long tx_queue_cnt; /* wait to send packet count */
246 unsigned long rx_avail_cnt; /* available rx descriptor count */
247 unsigned long interval_rx_cnt; /* rx packet count a callback time */
248
249 u16 HPNA_command; /* For HPNA register 16 */
250 u16 HPNA_timer; /* For HPNA remote device check */
251 u16 dbug_cnt;
252 u16 NIC_capability; /* NIC media capability */
253 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
254
255 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
256 u8 chip_type; /* Keep DM9102A chip type */
257 u8 media_mode; /* user specify media mode */
258 u8 op_mode; /* real work media mode */
259 u8 phy_addr;
1da177e4
LT		 260 u8 wait_reset; /* Hardware failed, need to reset */
261 u8 dm910x_chk_mode; /* Operating mode check */
262 u8 first_in_callback; /* Flag to record state */
f1069046 263 u8 wol_mode; /* user WOL settings */
1da177e4
LT		 264 struct timer_list timer;
265
1da177e4
LT		 266 /* Driver defined statistic counter */
267 unsigned long tx_fifo_underrun;
268 unsigned long tx_loss_carrier;
269 unsigned long tx_no_carrier;
270 unsigned long tx_late_collision;
271 unsigned long tx_excessive_collision;
272 unsigned long tx_jabber_timeout;
273 unsigned long reset_count;
274 unsigned long reset_cr8;
275 unsigned long reset_fatal;
276 unsigned long reset_TXtimeout;
277
278 /* NIC SROM data */
279 unsigned char srom[128];
280};
281
282enum dmfe_offsets {
283 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
284 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
285 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
286 DCR15 = 0x78
287};
288
289enum dmfe_CR6_bits {
290 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
291 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
292 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
293};
294
295/* Global variable declaration ----------------------------- */
296static int __devinitdata printed_version;
03f54b3d 297static const char version[] __devinitconst =
1da177e4
LT		 298 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
299 DRV_VERSION " (" DRV_RELDATE ")\n";
300
301static int dmfe_debug;
302static unsigned char dmfe_media_mode = DMFE_AUTO;
303static u32 dmfe_cr6_user_set;
304
305/* For module input parameter */
306static int debug;
307static u32 cr6set;
308static unsigned char mode = 8;
309static u8 chkmode = 1;
310static u8 HPNA_mode; /* Default: Low Power/High Speed */
311static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
312static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
313static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
314static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
315 4: TX pause packet */
316
317
318/* function declaration ------------------------------------- */
319static int dmfe_open(struct DEVICE *);
ad096463 320static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
1da177e4 321static int dmfe_stop(struct DEVICE *);
1da177e4 322static void dmfe_set_filter_mode(struct DEVICE *);
7282d491 323static const struct ethtool_ops netdev_ethtool_ops;
1da177e4 324static u16 read_srom_word(long ,int);
7d12e780 325static irqreturn_t dmfe_interrupt(int , void *);
1da177e4
LT		 326#ifdef CONFIG_NET_POLL_CONTROLLER
327static void poll_dmfe (struct net_device *dev);
328#endif
329static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
330static void allocate_rx_buffer(struct dmfe_board_info *);
331static void update_cr6(u32, unsigned long);
4302b67e
JP		 332static void send_filter_frame(struct DEVICE *);
333static void dm9132_id_table(struct DEVICE *);
1da177e4
LT		 334static u16 phy_read(unsigned long, u8, u8, u32);
335static void phy_write(unsigned long, u8, u8, u16, u32);
336static void phy_write_1bit(unsigned long, u32);
337static u16 phy_read_1bit(unsigned long);
338static u8 dmfe_sense_speed(struct dmfe_board_info *);
339static void dmfe_process_mode(struct dmfe_board_info *);
340static void dmfe_timer(unsigned long);
341static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
342static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
343static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
344static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
345static void dmfe_dynamic_reset(struct DEVICE *);
346static void dmfe_free_rxbuffer(struct dmfe_board_info *);
347static void dmfe_init_dm910x(struct DEVICE *);
348static void dmfe_parse_srom(struct dmfe_board_info *);
349static void dmfe_program_DM9801(struct dmfe_board_info *, int);
350static void dmfe_program_DM9802(struct dmfe_board_info *);
351static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
352static void dmfe_set_phyxcer(struct dmfe_board_info *);
353
f67ba792 354/* DM910X network board routine ---------------------------- */
1da177e4 355
2765df58
SH		 356static const struct net_device_ops netdev_ops = {
357 .ndo_open = dmfe_open,
358 .ndo_stop = dmfe_stop,
359 .ndo_start_xmit = dmfe_start_xmit,
360 .ndo_set_multicast_list = dmfe_set_filter_mode,
361 .ndo_change_mtu = eth_change_mtu,
362 .ndo_set_mac_address = eth_mac_addr,
363 .ndo_validate_addr = eth_validate_addr,
364#ifdef CONFIG_NET_POLL_CONTROLLER
365 .ndo_poll_controller = poll_dmfe,
366#endif
367};
368
1da177e4
LT		 369/*
370 * Search DM910X board ,allocate space and register it
371 */
372
373static int __devinit dmfe_init_one (struct pci_dev *pdev,
374 const struct pci_device_id *ent)
375{
376 struct dmfe_board_info *db; /* board information structure */
377 struct net_device *dev;
44c10138 378 u32 pci_pmr;
1da177e4
LT		 379 int i, err;
380
381 DMFE_DBUG(0, "dmfe_init_one()", 0);
382
383 if (!printed_version++)
384 printk(version);
385
4d907069
BH		 386 /*
387 * SPARC on-board DM910x chips should be handled by the main
388 * tulip driver, except for early DM9100s.
389 */
390#ifdef CONFIG_TULIP_DM910X
391 if ((ent->driver_data == PCI_DM9100_ID && pdev->revision >= 0x30) ||
392 ent->driver_data == PCI_DM9102_ID) {
393 struct device_node *dp = pci_device_to_OF_node(pdev);
394
395 if (dp && of_get_property(dp, "local-mac-address", NULL)) {
dde7c8ef 396 pr_info("skipping on-board DM910x (use tulip)\n");
4d907069
BH		 397 return -ENODEV;
398 }
399 }
400#endif
401
1da177e4
LT		 402 /* Init network device */
403 dev = alloc_etherdev(sizeof(*db));
404 if (dev == NULL)
405 return -ENOMEM;
1da177e4
LT		 406 SET_NETDEV_DEV(dev, &pdev->dev);
407
284901a9 408 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
dde7c8ef 409 pr_warning("32-bit PCI DMA not available\n");
1da177e4
LT		 410 err = -ENODEV;
411 goto err_out_free;
412 }
413
414 /* Enable Master/IO access, Disable memory access */
415 err = pci_enable_device(pdev);
416 if (err)
417 goto err_out_free;
418
419 if (!pci_resource_start(pdev, 0)) {
dde7c8ef 420 pr_err("I/O base is zero\n");
1da177e4
LT		 421 err = -ENODEV;
422 goto err_out_disable;
423 }
424
44c10138 425 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
dde7c8ef 426 pr_err("Allocated I/O size too small\n");
1da177e4
LT		 427 err = -ENODEV;
428 goto err_out_disable;
429 }
430
431#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
432
433 /* Set Latency Timer 80h */
434 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
435 Need a PCI quirk.. */
436
437 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
438#endif
439
440 if (pci_request_regions(pdev, DRV_NAME)) {
dde7c8ef 441 pr_err("Failed to request PCI regions\n");
1da177e4
LT		 442 err = -ENODEV;
443 goto err_out_disable;
444 }
445
446 /* Init system & device */
447 db = netdev_priv(dev);
448
449 /* Allocate Tx/Rx descriptor memory */
f67ba792
ML		 450 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
451 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
74d5e8ac
FT		 452 if (!db->desc_pool_ptr)
453 goto err_out_res;
f67ba792
ML		 454
455 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
456 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
74d5e8ac
FT		 457 if (!db->buf_pool_ptr)
458 goto err_out_free_desc;
1da177e4
LT		 459
460 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
461 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
462 db->buf_pool_start = db->buf_pool_ptr;
463 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
464
465 db->chip_id = ent->driver_data;
466 db->ioaddr = pci_resource_start(pdev, 0);
44c10138 467 db->chip_revision = pdev->revision;
f1069046 468 db->wol_mode = 0;
1da177e4
LT		 469
470 db->pdev = pdev;
471
472 dev->base_addr = db->ioaddr;
473 dev->irq = pdev->irq;
474 pci_set_drvdata(pdev, dev);
2765df58 475 dev->netdev_ops = &netdev_ops;
1da177e4 476 dev->ethtool_ops = &netdev_ethtool_ops;
cfa51b9d 477 netif_carrier_off(dev);
1da177e4
LT		 478 spin_lock_init(&db->lock);
479
480 pci_read_config_dword(pdev, 0x50, &pci_pmr);
481 pci_pmr &= 0x70000;
44c10138 482 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
1da177e4
LT		 483 db->chip_type = 1; /* DM9102A E3 */
484 else
485 db->chip_type = 0;
486
487 /* read 64 word srom data */
488 for (i = 0; i < 64; i++)
a31e40f6 489 ((__le16 *) db->srom)[i] =
f67ba792 490 cpu_to_le16(read_srom_word(db->ioaddr, i));
1da177e4
LT		 491
492 /* Set Node address */
493 for (i = 0; i < 6; i++)
494 dev->dev_addr[i] = db->srom[20 + i];
495
496 err = register_netdev (dev);
497 if (err)
74d5e8ac 498 goto err_out_free_buf;
1da177e4 499
dde7c8ef
JP		 500 dev_info(&dev->dev, "Davicom DM%04lx at pci%s, %pM, irq %d\n",
501 ent->driver_data >> 16,
502 pci_name(pdev), dev->dev_addr, dev->irq);
1da177e4
LT		 503
504 pci_set_master(pdev);
505
506 return 0;
507
74d5e8ac
FT		 508err_out_free_buf:
509 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
510 db->buf_pool_ptr, db->buf_pool_dma_ptr);
511err_out_free_desc:
512 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
513 db->desc_pool_ptr, db->desc_pool_dma_ptr);
1da177e4
LT		 514err_out_res:
515 pci_release_regions(pdev);
516err_out_disable:
517 pci_disable_device(pdev);
518err_out_free:
519 pci_set_drvdata(pdev, NULL);
520 free_netdev(dev);
521
522 return err;
523}
524
525
526static void __devexit dmfe_remove_one (struct pci_dev *pdev)
527{
528 struct net_device *dev = pci_get_drvdata(pdev);
529 struct dmfe_board_info *db = netdev_priv(dev);
530
531 DMFE_DBUG(0, "dmfe_remove_one()", 0);
532
533 if (dev) {
4dc68f3d
ML		 534
535 unregister_netdev(dev);
536
1da177e4
LT		 537 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
538 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
539 db->desc_pool_dma_ptr);
540 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
541 db->buf_pool_ptr, db->buf_pool_dma_ptr);
1da177e4
LT		 542 pci_release_regions(pdev);
543 free_netdev(dev); /* free board information */
4dc68f3d 544
1da177e4
LT		 545 pci_set_drvdata(pdev, NULL);
546 }
547
548 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
549}
550
551
552/*
553 * Open the interface.
554 * The interface is opened whenever "ifconfig" actives it.
555 */
556
557static int dmfe_open(struct DEVICE *dev)
558{
559 int ret;
560 struct dmfe_board_info *db = netdev_priv(dev);
561
562 DMFE_DBUG(0, "dmfe_open", 0);
563
a0607fd3 564 ret = request_irq(dev->irq, dmfe_interrupt,
f67ba792 565 IRQF_SHARED, dev->name, dev);
1da177e4
LT		 566 if (ret)
567 return ret;
568
569 /* system variable init */
570 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
571 db->tx_packet_cnt = 0;
572 db->tx_queue_cnt = 0;
573 db->rx_avail_cnt = 0;
1da177e4
LT		 574 db->wait_reset = 0;
575
576 db->first_in_callback = 0;
577 db->NIC_capability = 0xf; /* All capability*/
578 db->PHY_reg4 = 0x1e0;
579
580 /* CR6 operation mode decision */
581 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
44c10138 582 (db->chip_revision >= 0x30) ) {
1da177e4
LT		 583 db->cr6_data |= DMFE_TXTH_256;
584 db->cr0_data = CR0_DEFAULT;
585 db->dm910x_chk_mode=4; /* Enter the normal mode */
586 } else {
587 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
588 db->cr0_data = 0;
589 db->dm910x_chk_mode = 1; /* Enter the check mode */
590 }
591
592 /* Initilize DM910X board */
593 dmfe_init_dm910x(dev);
594
595 /* Active System Interface */
596 netif_wake_queue(dev);
597
598 /* set and active a timer process */
599 init_timer(&db->timer);
600 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
601 db->timer.data = (unsigned long)dev;
602 db->timer.function = &dmfe_timer;
603 add_timer(&db->timer);
604
605 return 0;
606}
607
608
609/* Initilize DM910X board
610 * Reset DM910X board
611 * Initilize TX/Rx descriptor chain structure
612 * Send the set-up frame
613 * Enable Tx/Rx machine
614 */
615
616static void dmfe_init_dm910x(struct DEVICE *dev)
617{
618 struct dmfe_board_info *db = netdev_priv(dev);
619 unsigned long ioaddr = db->ioaddr;
620
621 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
622
623 /* Reset DM910x MAC controller */
624 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
625 udelay(100);
626 outl(db->cr0_data, ioaddr + DCR0);
627 udelay(5);
628
629 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
630 db->phy_addr = 1;
631
632 /* Parser SROM and media mode */
633 dmfe_parse_srom(db);
634 db->media_mode = dmfe_media_mode;
635
636 /* RESET Phyxcer Chip by GPR port bit 7 */
637 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
638 if (db->chip_id == PCI_DM9009_ID) {
639 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
640 mdelay(300); /* Delay 300 ms */
641 }
642 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
643
644 /* Process Phyxcer Media Mode */
645 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
646 dmfe_set_phyxcer(db);
647
648 /* Media Mode Process */
649 if ( !(db->media_mode & DMFE_AUTO) )
650 db->op_mode = db->media_mode; /* Force Mode */
651
652 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
653 dmfe_descriptor_init(db, ioaddr);
654
655 /* Init CR6 to program DM910x operation */
656 update_cr6(db->cr6_data, ioaddr);
657
658 /* Send setup frame */
659 if (db->chip_id == PCI_DM9132_ID)
4302b67e 660 dm9132_id_table(dev); /* DM9132 */
1da177e4 661 else
4302b67e 662 send_filter_frame(dev); /* DM9102/DM9102A */
1da177e4
LT		 663
664 /* Init CR7, interrupt active bit */
665 db->cr7_data = CR7_DEFAULT;
666 outl(db->cr7_data, ioaddr + DCR7);
667
668 /* Init CR15, Tx jabber and Rx watchdog timer */
669 outl(db->cr15_data, ioaddr + DCR15);
670
671 /* Enable DM910X Tx/Rx function */
672 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
673 update_cr6(db->cr6_data, ioaddr);
674}
675
676
677/*
678 * Hardware start transmission.
679 * Send a packet to media from the upper layer.
680 */
681
ad096463
SH		 682static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
683 struct DEVICE *dev)
1da177e4
LT		 684{
685 struct dmfe_board_info *db = netdev_priv(dev);
686 struct tx_desc *txptr;
687 unsigned long flags;
688
689 DMFE_DBUG(0, "dmfe_start_xmit", 0);
690
691 /* Resource flag check */
692 netif_stop_queue(dev);
693
694 /* Too large packet check */
695 if (skb->len > MAX_PACKET_SIZE) {
dde7c8ef 696 pr_err("big packet = %d\n", (u16)skb->len);
1da177e4 697 dev_kfree_skb(skb);
ec634fe3 698 return NETDEV_TX_OK;
1da177e4
LT		 699 }
700
701 spin_lock_irqsave(&db->lock, flags);
702
703 /* No Tx resource check, it never happen nromally */
704 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
705 spin_unlock_irqrestore(&db->lock, flags);
dde7c8ef 706 pr_err("No Tx resource %ld\n", db->tx_queue_cnt);
5b548140 707 return NETDEV_TX_BUSY;
1da177e4
LT		 708 }
709
710 /* Disable NIC interrupt */
711 outl(0, dev->base_addr + DCR7);
712
713 /* transmit this packet */
714 txptr = db->tx_insert_ptr;
d626f62b 715 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
1da177e4
LT		 716 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
717
718 /* Point to next transmit free descriptor */
719 db->tx_insert_ptr = txptr->next_tx_desc;
720
721 /* Transmit Packet Process */
722 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
723 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
724 db->tx_packet_cnt++; /* Ready to send */
725 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
726 dev->trans_start = jiffies; /* saved time stamp */
727 } else {
728 db->tx_queue_cnt++; /* queue TX packet */
729 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
730 }
731
732 /* Tx resource check */
733 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
734 netif_wake_queue(dev);
735
736 /* Restore CR7 to enable interrupt */
737 spin_unlock_irqrestore(&db->lock, flags);
738 outl(db->cr7_data, dev->base_addr + DCR7);
739
740 /* free this SKB */
741 dev_kfree_skb(skb);
742
ec634fe3 743 return NETDEV_TX_OK;
1da177e4
LT		 744}
745
746
747/*
748 * Stop the interface.
749 * The interface is stopped when it is brought.
750 */
751
752static int dmfe_stop(struct DEVICE *dev)
753{
754 struct dmfe_board_info *db = netdev_priv(dev);
755 unsigned long ioaddr = dev->base_addr;
756
757 DMFE_DBUG(0, "dmfe_stop", 0);
758
759 /* disable system */
760 netif_stop_queue(dev);
761
762 /* deleted timer */
763 del_timer_sync(&db->timer);
764
765 /* Reset & stop DM910X board */
766 outl(DM910X_RESET, ioaddr + DCR0);
767 udelay(5);
768 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
769
770 /* free interrupt */
771 free_irq(dev->irq, dev);
772
773 /* free allocated rx buffer */
774 dmfe_free_rxbuffer(db);
775
776#if 0
777 /* show statistic counter */
dde7c8ef
JP		 778 printk("FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
779 db->tx_fifo_underrun, db->tx_excessive_collision,
780 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
781 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
782 db->reset_fatal, db->reset_TXtimeout);
1da177e4
LT		 783#endif
784
785 return 0;
786}
787
788
789/*
790 * DM9102 insterrupt handler
791 * receive the packet to upper layer, free the transmitted packet
792 */
793
7d12e780 794static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
1da177e4
LT		 795{
796 struct DEVICE *dev = dev_id;
797 struct dmfe_board_info *db = netdev_priv(dev);
798 unsigned long ioaddr = dev->base_addr;
799 unsigned long flags;
800
801 DMFE_DBUG(0, "dmfe_interrupt()", 0);
802
1da177e4
LT		 803 spin_lock_irqsave(&db->lock, flags);
804
805 /* Got DM910X status */
806 db->cr5_data = inl(ioaddr + DCR5);
807 outl(db->cr5_data, ioaddr + DCR5);
808 if ( !(db->cr5_data & 0xc1) ) {
809 spin_unlock_irqrestore(&db->lock, flags);
810 return IRQ_HANDLED;
811 }
812
813 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
814 outl(0, ioaddr + DCR7);
815
816 /* Check system status */
817 if (db->cr5_data & 0x2000) {
818 /* system bus error happen */
819 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
820 db->reset_fatal++;
821 db->wait_reset = 1; /* Need to RESET */
822 spin_unlock_irqrestore(&db->lock, flags);
823 return IRQ_HANDLED;
824 }
825
826 /* Received the coming packet */
827 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
828 dmfe_rx_packet(dev, db);
829
830 /* reallocate rx descriptor buffer */
831 if (db->rx_avail_cnt<RX_DESC_CNT)
832 allocate_rx_buffer(db);
833
834 /* Free the transmitted descriptor */
835 if ( db->cr5_data & 0x01)
836 dmfe_free_tx_pkt(dev, db);
837
838 /* Mode Check */
839 if (db->dm910x_chk_mode & 0x2) {
840 db->dm910x_chk_mode = 0x4;
841 db->cr6_data |= 0x100;
842 update_cr6(db->cr6_data, db->ioaddr);
843 }
844
845 /* Restore CR7 to enable interrupt mask */
846 outl(db->cr7_data, ioaddr + DCR7);
847
848 spin_unlock_irqrestore(&db->lock, flags);
849 return IRQ_HANDLED;
850}
851
852
853#ifdef CONFIG_NET_POLL_CONTROLLER
854/*
855 * Polling 'interrupt' - used by things like netconsole to send skbs
856 * without having to re-enable interrupts. It's not called while
857 * the interrupt routine is executing.
858 */
859
860static void poll_dmfe (struct net_device *dev)
861{
862 /* disable_irq here is not very nice, but with the lockless
863 interrupt handler we have no other choice. */
864 disable_irq(dev->irq);
7d12e780 865 dmfe_interrupt (dev->irq, dev);
1da177e4
LT		 866 enable_irq(dev->irq);
867}
868#endif
869
870/*
871 * Free TX resource after TX complete
872 */
873
874static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
875{
876 struct tx_desc *txptr;
877 unsigned long ioaddr = dev->base_addr;
878 u32 tdes0;
879
880 txptr = db->tx_remove_ptr;
881 while(db->tx_packet_cnt) {
882 tdes0 = le32_to_cpu(txptr->tdes0);
dde7c8ef 883 pr_debug("tdes0=%x\n", tdes0);
1da177e4
LT		 884 if (tdes0 & 0x80000000)
885 break;
886
887 /* A packet sent completed */
888 db->tx_packet_cnt--;
2765df58 889 dev->stats.tx_packets++;
1da177e4
LT		 890
891 /* Transmit statistic counter */
892 if ( tdes0 != 0x7fffffff ) {
dde7c8ef 893 pr_debug("tdes0=%x\n", tdes0);
2765df58
SH		 894 dev->stats.collisions += (tdes0 >> 3) & 0xf;
895 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
1da177e4 896 if (tdes0 & TDES0_ERR_MASK) {
2765df58 897 dev->stats.tx_errors++;
1da177e4
LT		 898
899 if (tdes0 & 0x0002) { /* UnderRun */
900 db->tx_fifo_underrun++;
901 if ( !(db->cr6_data & CR6_SFT) ) {
902 db->cr6_data = db->cr6_data | CR6_SFT;
903 update_cr6(db->cr6_data, db->ioaddr);
904 }
905 }
906 if (tdes0 & 0x0100)
907 db->tx_excessive_collision++;
908 if (tdes0 & 0x0200)
909 db->tx_late_collision++;
910 if (tdes0 & 0x0400)
911 db->tx_no_carrier++;
912 if (tdes0 & 0x0800)
913 db->tx_loss_carrier++;
914 if (tdes0 & 0x4000)
915 db->tx_jabber_timeout++;
916 }
917 }
918
919 txptr = txptr->next_tx_desc;
920 }/* End of while */
921
922 /* Update TX remove pointer to next */
923 db->tx_remove_ptr = txptr;
924
925 /* Send the Tx packet in queue */
926 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
927 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
928 db->tx_packet_cnt++; /* Ready to send */
929 db->tx_queue_cnt--;
930 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
931 dev->trans_start = jiffies; /* saved time stamp */
932 }
933
934 /* Resource available check */
935 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
936 netif_wake_queue(dev); /* Active upper layer, send again */
937}
938
939
940/*
941 * Calculate the CRC valude of the Rx packet
942 * flag = 1 : return the reverse CRC (for the received packet CRC)
943 * 0 : return the normal CRC (for Hash Table index)
944 */
945
946static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
947{
948 u32 crc = crc32(~0, Data, Len);
949 if (flag) crc = ~crc;
950 return crc;
951}
952
953
954/*
955 * Receive the come packet and pass to upper layer
956 */
957
958static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
959{
960 struct rx_desc *rxptr;
4dc68f3d 961 struct sk_buff *skb, *newskb;
1da177e4
LT		 962 int rxlen;
963 u32 rdes0;
964
965 rxptr = db->rx_ready_ptr;
966
967 while(db->rx_avail_cnt) {
968 rdes0 = le32_to_cpu(rxptr->rdes0);
969 if (rdes0 & 0x80000000) /* packet owner check */
970 break;
971
972 db->rx_avail_cnt--;
973 db->interval_rx_cnt++;
974
f67ba792
ML		 975 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
976 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
977
1da177e4
LT		 978 if ( (rdes0 & 0x300) != 0x300) {
979 /* A packet without First/Last flag */
980 /* reuse this SKB */
981 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
982 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
983 } else {
984 /* A packet with First/Last flag */
985 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
986
987 /* error summary bit check */
988 if (rdes0 & 0x8000) {
989 /* This is a error packet */
dde7c8ef 990 pr_debug("rdes0: %x\n", rdes0);
2765df58 991 dev->stats.rx_errors++;
1da177e4 992 if (rdes0 & 1)
2765df58 993 dev->stats.rx_fifo_errors++;
1da177e4 994 if (rdes0 & 2)
2765df58 995 dev->stats.rx_crc_errors++;
1da177e4 996 if (rdes0 & 0x80)
2765df58 997 dev->stats.rx_length_errors++;
1da177e4
LT		 998 }
999
1000 if ( !(rdes0 & 0x8000) ||
1001 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
1002 skb = rxptr->rx_skb_ptr;
1003
1004 /* Received Packet CRC check need or not */
1005 if ( (db->dm910x_chk_mode & 1) &&
689be439
DM		 1006 (cal_CRC(skb->data, rxlen, 1) !=
1007 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
1da177e4
LT		 1008 /* Found a error received packet */
1009 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1010 db->dm910x_chk_mode = 3;
1011 } else {
1012 /* Good packet, send to upper layer */
1013 /* Shorst packet used new SKB */
4dc68f3d
ML		 1014 if ((rxlen < RX_COPY_SIZE) &&
1015 ((newskb = dev_alloc_skb(rxlen + 2))
1016 != NULL)) {
1017
1018 skb = newskb;
1da177e4 1019 /* size less than COPY_SIZE, allocate a rxlen SKB */
1da177e4 1020 skb_reserve(skb, 2); /* 16byte align */
d626f62b
ACM		 1021 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
1022 skb_put(skb, rxlen),
1023 rxlen);
1da177e4 1024 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 1025 } else
1da177e4 1026 skb_put(skb, rxlen);
4c13eb66 1027
1da177e4
LT		 1028 skb->protocol = eth_type_trans(skb, dev);
1029 netif_rx(skb);
2765df58
SH		 1030 dev->stats.rx_packets++;
1031 dev->stats.rx_bytes += rxlen;
1da177e4
LT		 1032 }
1033 } else {
1034 /* Reuse SKB buffer when the packet is error */
1035 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1036 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1037 }
1038 }
1039
1040 rxptr = rxptr->next_rx_desc;
1041 }
1042
1043 db->rx_ready_ptr = rxptr;
1044}
1045
1da177e4
LT		 1046/*
1047 * Set DM910X multicast address
1048 */
1049
1050static void dmfe_set_filter_mode(struct DEVICE * dev)
1051{
1052 struct dmfe_board_info *db = netdev_priv(dev);
1053 unsigned long flags;
4cd24eaf 1054 int mc_count = netdev_mc_count(dev);
1da177e4
LT		 1055
1056 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1057 spin_lock_irqsave(&db->lock, flags);
1058
1059 if (dev->flags & IFF_PROMISC) {
1060 DMFE_DBUG(0, "Enable PROM Mode", 0);
1061 db->cr6_data |= CR6_PM | CR6_PBF;
1062 update_cr6(db->cr6_data, db->ioaddr);
1063 spin_unlock_irqrestore(&db->lock, flags);
1064 return;
1065 }
1066
4cd24eaf
JP		 1067 if (dev->flags & IFF_ALLMULTI || mc_count > DMFE_MAX_MULTICAST) {
1068 DMFE_DBUG(0, "Pass all multicast address", mc_count);
1da177e4
LT		 1069 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1070 db->cr6_data |= CR6_PAM;
1071 spin_unlock_irqrestore(&db->lock, flags);
1072 return;
1073 }
1074
4cd24eaf 1075 DMFE_DBUG(0, "Set multicast address", mc_count);
1da177e4 1076 if (db->chip_id == PCI_DM9132_ID)
4302b67e 1077 dm9132_id_table(dev); /* DM9132 */
1da177e4 1078 else
4302b67e 1079 send_filter_frame(dev); /* DM9102/DM9102A */
1da177e4
LT		 1080 spin_unlock_irqrestore(&db->lock, flags);
1081}
1082
f1069046
ML		 1083/*
1084 * Ethtool interace
1085 */
1086
1087static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1da177e4
LT		 1088 struct ethtool_drvinfo *info)
1089{
1090 struct dmfe_board_info *np = netdev_priv(dev);
1091
1092 strcpy(info->driver, DRV_NAME);
1093 strcpy(info->version, DRV_VERSION);
1094 if (np->pdev)
1095 strcpy(info->bus_info, pci_name(np->pdev));
1096 else
1097 sprintf(info->bus_info, "EISA 0x%lx %d",
1098 dev->base_addr, dev->irq);
1099}
1100
f1069046
ML		 1101static int dmfe_ethtool_set_wol(struct net_device *dev,
1102 struct ethtool_wolinfo *wolinfo)
1103{
1104 struct dmfe_board_info *db = netdev_priv(dev);
1105
1106 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1107 WAKE_ARP | WAKE_MAGICSECURE))
1108 return -EOPNOTSUPP;
1109
1110 db->wol_mode = wolinfo->wolopts;
1111 return 0;
1112}
1113
1114static void dmfe_ethtool_get_wol(struct net_device *dev,
1115 struct ethtool_wolinfo *wolinfo)
1116{
1117 struct dmfe_board_info *db = netdev_priv(dev);
1118
1119 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1120 wolinfo->wolopts = db->wol_mode;
1121 return;
1122}
1123
1124
7282d491 1125static const struct ethtool_ops netdev_ethtool_ops = {
f1069046 1126 .get_drvinfo = dmfe_ethtool_get_drvinfo,
cfa51b9d 1127 .get_link = ethtool_op_get_link,
f1069046
ML		 1128 .set_wol = dmfe_ethtool_set_wol,
1129 .get_wol = dmfe_ethtool_get_wol,
1da177e4
LT		 1130};
1131
1132/*
1133 * A periodic timer routine
1134 * Dynamic media sense, allocate Rx buffer...
1135 */
1136
1137static void dmfe_timer(unsigned long data)
1138{
1139 u32 tmp_cr8;
1140 unsigned char tmp_cr12;
1141 struct DEVICE *dev = (struct DEVICE *) data;
1142 struct dmfe_board_info *db = netdev_priv(dev);
1143 unsigned long flags;
1144
cfa51b9d
ML		 1145 int link_ok, link_ok_phy;
1146
1da177e4
LT		 1147 DMFE_DBUG(0, "dmfe_timer()", 0);
1148 spin_lock_irqsave(&db->lock, flags);
1149
1150 /* Media mode process when Link OK before enter this route */
1151 if (db->first_in_callback == 0) {
1152 db->first_in_callback = 1;
1153 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1154 db->cr6_data &= ~0x40000;
1155 update_cr6(db->cr6_data, db->ioaddr);
f67ba792
ML		 1156 phy_write(db->ioaddr,
1157 db->phy_addr, 0, 0x1000, db->chip_id);
1da177e4
LT		 1158 db->cr6_data |= 0x40000;
1159 update_cr6(db->cr6_data, db->ioaddr);
1160 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1161 add_timer(&db->timer);
1162 spin_unlock_irqrestore(&db->lock, flags);
1163 return;
1164 }
1165 }
1166
1167
1168 /* Operating Mode Check */
1169 if ( (db->dm910x_chk_mode & 0x1) &&
2765df58 1170 (dev->stats.rx_packets > MAX_CHECK_PACKET) )
1da177e4
LT		 1171 db->dm910x_chk_mode = 0x4;
1172
1173 /* Dynamic reset DM910X : system error or transmit time-out */
1174 tmp_cr8 = inl(db->ioaddr + DCR8);
1175 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1176 db->reset_cr8++;
1177 db->wait_reset = 1;
1178 }
1179 db->interval_rx_cnt = 0;
1180
1181 /* TX polling kick monitor */
1182 if ( db->tx_packet_cnt &&
1183 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1184 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1185
1186 /* TX Timeout */
1187 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1188 db->reset_TXtimeout++;
1189 db->wait_reset = 1;
dde7c8ef 1190 dev_warn(&dev->dev, "Tx timeout - resetting\n");
1da177e4
LT		 1191 }
1192 }
1193
1194 if (db->wait_reset) {
1195 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1196 db->reset_count++;
1197 dmfe_dynamic_reset(dev);
1198 db->first_in_callback = 0;
1199 db->timer.expires = DMFE_TIMER_WUT;
1200 add_timer(&db->timer);
1201 spin_unlock_irqrestore(&db->lock, flags);
1202 return;
1203 }
1204
1205 /* Link status check, Dynamic media type change */
1206 if (db->chip_id == PCI_DM9132_ID)
1207 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1208 else
1209 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1210
1211 if ( ((db->chip_id == PCI_DM9102_ID) &&
44c10138 1212 (db->chip_revision == 0x30)) ||
1da177e4 1213 ((db->chip_id == PCI_DM9132_ID) &&
44c10138 1214 (db->chip_revision == 0x10)) ) {
1da177e4
LT		 1215 /* DM9102A Chip */
1216 if (tmp_cr12 & 2)
cfa51b9d 1217 link_ok = 0;
1da177e4 1218 else
cfa51b9d 1219 link_ok = 1;
1da177e4 1220 }
cfa51b9d
ML		 1221 else
1222 /*0x43 is used instead of 0x3 because bit 6 should represent
1223 link status of external PHY */
1224 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1225
1226
1227 /* If chip reports that link is failed it could be because external
1228 PHY link status pin is not conected correctly to chip
1229 To be sure ask PHY too.
1230 */
1231
1232 /* need a dummy read because of PHY's register latch*/
1233 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1234 link_ok_phy = (phy_read (db->ioaddr,
1235 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1da177e4 1236
cfa51b9d
ML		 1237 if (link_ok_phy != link_ok) {
1238 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1239 link_ok = link_ok | link_ok_phy;
1240 }
1241
1242 if ( !link_ok && netif_carrier_ok(dev)) {
1da177e4
LT		 1243 /* Link Failed */
1244 DMFE_DBUG(0, "Link Failed", tmp_cr12);
cfa51b9d 1245 netif_carrier_off(dev);
1da177e4
LT		 1246
1247 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1248 /* AUTO or force 1M Homerun/Longrun don't need */
1249 if ( !(db->media_mode & 0x38) )
f67ba792
ML		 1250 phy_write(db->ioaddr, db->phy_addr,
1251 0, 0x1000, db->chip_id);
1da177e4
LT		 1252
1253 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1254 if (db->media_mode & DMFE_AUTO) {
1255 /* 10/100M link failed, used 1M Home-Net */
1256 db->cr6_data|=0x00040000; /* bit18=1, MII */
1257 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1258 update_cr6(db->cr6_data, db->ioaddr);
1259 }
cfa51b9d
ML		 1260 } else if (!netif_carrier_ok(dev)) {
1261
1262 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1263
1264 /* Auto Sense Speed */
1265 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1266 netif_carrier_on(dev);
1267 SHOW_MEDIA_TYPE(db->op_mode);
1da177e4
LT		 1268 }
1269
cfa51b9d
ML		 1270 dmfe_process_mode(db);
1271 }
1272
1da177e4
LT		 1273 /* HPNA remote command check */
1274 if (db->HPNA_command & 0xf00) {
1275 db->HPNA_timer--;
1276 if (!db->HPNA_timer)
1277 dmfe_HPNA_remote_cmd_chk(db);
1278 }
1279
1280 /* Timer active again */
1281 db->timer.expires = DMFE_TIMER_WUT;
1282 add_timer(&db->timer);
1283 spin_unlock_irqrestore(&db->lock, flags);
1284}
1285
1286
1287/*
1288 * Dynamic reset the DM910X board
1289 * Stop DM910X board
1290 * Free Tx/Rx allocated memory
1291 * Reset DM910X board
1292 * Re-initilize DM910X board
1293 */
1294
1295static void dmfe_dynamic_reset(struct DEVICE *dev)
1296{
1297 struct dmfe_board_info *db = netdev_priv(dev);
1298
1299 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1300
1301 /* Sopt MAC controller */
1302 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1303 update_cr6(db->cr6_data, dev->base_addr);
1304 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1305 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1306
1307 /* Disable upper layer interface */
1308 netif_stop_queue(dev);
1309
1310 /* Free Rx Allocate buffer */
1311 dmfe_free_rxbuffer(db);
1312
1313 /* system variable init */
1314 db->tx_packet_cnt = 0;
1315 db->tx_queue_cnt = 0;
1316 db->rx_avail_cnt = 0;
cfa51b9d 1317 netif_carrier_off(dev);
1da177e4
LT		 1318 db->wait_reset = 0;
1319
1320 /* Re-initilize DM910X board */
1321 dmfe_init_dm910x(dev);
1322
1323 /* Restart upper layer interface */
1324 netif_wake_queue(dev);
1325}
1326
1327
1328/*
1329 * free all allocated rx buffer
1330 */
1331
1332static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1333{
1334 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1335
1336 /* free allocated rx buffer */
1337 while (db->rx_avail_cnt) {
1338 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1339 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1340 db->rx_avail_cnt--;
1341 }
1342}
1343
1344
1345/*
1346 * Reuse the SK buffer
1347 */
1348
1349static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1350{
1351 struct rx_desc *rxptr = db->rx_insert_ptr;
1352
1353 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1354 rxptr->rx_skb_ptr = skb;
f67ba792
ML		 1355 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1356 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1357 wmb();
1358 rxptr->rdes0 = cpu_to_le32(0x80000000);
1359 db->rx_avail_cnt++;
1360 db->rx_insert_ptr = rxptr->next_rx_desc;
1361 } else
1362 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1363}
1364
1365
1366/*
1367 * Initialize transmit/Receive descriptor
1368 * Using Chain structure, and allocate Tx/Rx buffer
1369 */
1370
1371static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1372{
1373 struct tx_desc *tmp_tx;
1374 struct rx_desc *tmp_rx;
1375 unsigned char *tmp_buf;
1376 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1377 dma_addr_t tmp_buf_dma;
1378 int i;
1379
1380 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1381
1382 /* tx descriptor start pointer */
1383 db->tx_insert_ptr = db->first_tx_desc;
1384 db->tx_remove_ptr = db->first_tx_desc;
1385 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1386
1387 /* rx descriptor start pointer */
f67ba792
ML		 1388 db->first_rx_desc = (void *)db->first_tx_desc +
1389 sizeof(struct tx_desc) * TX_DESC_CNT;
1390
1391 db->first_rx_desc_dma = db->first_tx_desc_dma +
1392 sizeof(struct tx_desc) * TX_DESC_CNT;
1da177e4
LT		 1393 db->rx_insert_ptr = db->first_rx_desc;
1394 db->rx_ready_ptr = db->first_rx_desc;
1395 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1396
1397 /* Init Transmit chain */
1398 tmp_buf = db->buf_pool_start;
1399 tmp_buf_dma = db->buf_pool_dma_start;
1400 tmp_tx_dma = db->first_tx_desc_dma;
1401 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1402 tmp_tx->tx_buf_ptr = tmp_buf;
1403 tmp_tx->tdes0 = cpu_to_le32(0);
1404 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1405 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1406 tmp_tx_dma += sizeof(struct tx_desc);
1407 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1408 tmp_tx->next_tx_desc = tmp_tx + 1;
1409 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1410 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1411 }
1412 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1413 tmp_tx->next_tx_desc = db->first_tx_desc;
1414
1415 /* Init Receive descriptor chain */
1416 tmp_rx_dma=db->first_rx_desc_dma;
1417 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1418 tmp_rx->rdes0 = cpu_to_le32(0);
1419 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1420 tmp_rx_dma += sizeof(struct rx_desc);
1421 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1422 tmp_rx->next_rx_desc = tmp_rx + 1;
1423 }
1424 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1425 tmp_rx->next_rx_desc = db->first_rx_desc;
1426
1427 /* pre-allocate Rx buffer */
1428 allocate_rx_buffer(db);
1429}
1430
1431
1432/*
1433 * Update CR6 value
1434 * Firstly stop DM910X , then written value and start
1435 */
1436
1437static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1438{
1439 u32 cr6_tmp;
1440
1441 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1442 outl(cr6_tmp, ioaddr + DCR6);
1443 udelay(5);
1444 outl(cr6_data, ioaddr + DCR6);
1445 udelay(5);
1446}
1447
1448
1449/*
1450 * Send a setup frame for DM9132
1451 * This setup frame initilize DM910X address filter mode
1452*/
1453
4302b67e 1454static void dm9132_id_table(struct DEVICE *dev)
1da177e4
LT		 1455{
1456 struct dev_mc_list *mcptr;
1457 u16 * addrptr;
1458 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1459 u32 hash_val;
1460 u16 i, hash_table[4];
1461
1462 DMFE_DBUG(0, "dm9132_id_table()", 0);
1463
1464 /* Node address */
1465 addrptr = (u16 *) dev->dev_addr;
1466 outw(addrptr[0], ioaddr);
1467 ioaddr += 4;
1468 outw(addrptr[1], ioaddr);
1469 ioaddr += 4;
1470 outw(addrptr[2], ioaddr);
1471 ioaddr += 4;
1472
1473 /* Clear Hash Table */
4302b67e 1474 memset(hash_table, 0, sizeof(hash_table));
1da177e4
LT		 1475
1476 /* broadcast address */
1477 hash_table[3] = 0x8000;
1478
1479 /* the multicast address in Hash Table : 64 bits */
4302b67e
JP		 1480 netdev_for_each_mc_addr(mcptr, dev) {
1481 hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1da177e4
LT		 1482 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1483 }
1484
1485 /* Write the hash table to MAC MD table */
1486 for (i = 0; i < 4; i++, ioaddr += 4)
1487 outw(hash_table[i], ioaddr);
1488}
1489
1490
1491/*
1492 * Send a setup frame for DM9102/DM9102A
1493 * This setup frame initilize DM910X address filter mode
1494 */
1495
4302b67e 1496static void send_filter_frame(struct DEVICE *dev)
1da177e4
LT		 1497{
1498 struct dmfe_board_info *db = netdev_priv(dev);
1499 struct dev_mc_list *mcptr;
1500 struct tx_desc *txptr;
1501 u16 * addrptr;
1502 u32 * suptr;
1503 int i;
1504
1505 DMFE_DBUG(0, "send_filter_frame()", 0);
1506
1507 txptr = db->tx_insert_ptr;
1508 suptr = (u32 *) txptr->tx_buf_ptr;
1509
1510 /* Node address */
1511 addrptr = (u16 *) dev->dev_addr;
1512 *suptr++ = addrptr[0];
1513 *suptr++ = addrptr[1];
1514 *suptr++ = addrptr[2];
1515
1516 /* broadcast address */
1517 *suptr++ = 0xffff;
1518 *suptr++ = 0xffff;
1519 *suptr++ = 0xffff;
1520
1521 /* fit the multicast address */
4302b67e 1522 netdev_for_each_mc_addr(mcptr, dev) {
1da177e4
LT		 1523 addrptr = (u16 *) mcptr->dmi_addr;
1524 *suptr++ = addrptr[0];
1525 *suptr++ = addrptr[1];
1526 *suptr++ = addrptr[2];
1527 }
1528
4302b67e 1529 for (i = netdev_mc_count(dev); i < 14; i++) {
1da177e4
LT		 1530 *suptr++ = 0xffff;
1531 *suptr++ = 0xffff;
1532 *suptr++ = 0xffff;
1533 }
1534
1535 /* prepare the setup frame */
1536 db->tx_insert_ptr = txptr->next_tx_desc;
1537 txptr->tdes1 = cpu_to_le32(0x890000c0);
1538
1539 /* Resource Check and Send the setup packet */
1540 if (!db->tx_packet_cnt) {
1541 /* Resource Empty */
1542 db->tx_packet_cnt++;
1543 txptr->tdes0 = cpu_to_le32(0x80000000);
1544 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1545 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1546 update_cr6(db->cr6_data, dev->base_addr);
1547 dev->trans_start = jiffies;
1548 } else
1549 db->tx_queue_cnt++; /* Put in TX queue */
1550}
1551
1552
1553/*
1554 * Allocate rx buffer,
1555 * As possible as allocate maxiumn Rx buffer
1556 */
1557
1558static void allocate_rx_buffer(struct dmfe_board_info *db)
1559{
1560 struct rx_desc *rxptr;
1561 struct sk_buff *skb;
1562
1563 rxptr = db->rx_insert_ptr;
1564
1565 while(db->rx_avail_cnt < RX_DESC_CNT) {
1566 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1567 break;
1568 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
f67ba792
ML		 1569 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1570 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1571 wmb();
1572 rxptr->rdes0 = cpu_to_le32(0x80000000);
1573 rxptr = rxptr->next_rx_desc;
1574 db->rx_avail_cnt++;
1575 }
1576
1577 db->rx_insert_ptr = rxptr;
1578}
1579
1580
1581/*
1582 * Read one word data from the serial ROM
1583 */
1584
1585static u16 read_srom_word(long ioaddr, int offset)
1586{
1587 int i;
1588 u16 srom_data = 0;
1589 long cr9_ioaddr = ioaddr + DCR9;
1590
1591 outl(CR9_SROM_READ, cr9_ioaddr);
1592 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1593
1594 /* Send the Read Command 110b */
1595 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1596 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1597 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1598
1599 /* Send the offset */
1600 for (i = 5; i >= 0; i--) {
1601 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1602 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1603 }
1604
1605 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1606
1607 for (i = 16; i > 0; i--) {
1608 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1609 udelay(5);
f67ba792
ML		 1610 srom_data = (srom_data << 1) |
1611 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1da177e4
LT		 1612 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1613 udelay(5);
1614 }
1615
1616 outl(CR9_SROM_READ, cr9_ioaddr);
1617 return srom_data;
1618}
1619
1620
1621/*
1622 * Auto sense the media mode
1623 */
1624
1625static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1626{
1627 u8 ErrFlag = 0;
1628 u16 phy_mode;
1629
1630 /* CR6 bit18=0, select 10/100M */
1631 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1632
1633 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1634 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1635
1636 if ( (phy_mode & 0x24) == 0x24 ) {
1637 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
f67ba792
ML		 1638 phy_mode = phy_read(db->ioaddr,
1639 db->phy_addr, 7, db->chip_id) & 0xf000;
1da177e4 1640 else /* DM9102/DM9102A */
f67ba792
ML		 1641 phy_mode = phy_read(db->ioaddr,
1642 db->phy_addr, 17, db->chip_id) & 0xf000;
dde7c8ef 1643 pr_debug("Phy_mode %x\n", phy_mode);
1da177e4
LT		 1644 switch (phy_mode) {
1645 case 0x1000: db->op_mode = DMFE_10MHF; break;
1646 case 0x2000: db->op_mode = DMFE_10MFD; break;
1647 case 0x4000: db->op_mode = DMFE_100MHF; break;
1648 case 0x8000: db->op_mode = DMFE_100MFD; break;
1649 default: db->op_mode = DMFE_10MHF;
1650 ErrFlag = 1;
1651 break;
1652 }
1653 } else {
1654 db->op_mode = DMFE_10MHF;
1655 DMFE_DBUG(0, "Link Failed :", phy_mode);
1656 ErrFlag = 1;
1657 }
1658
1659 return ErrFlag;
1660}
1661
1662
1663/*
1664 * Set 10/100 phyxcer capability
1665 * AUTO mode : phyxcer register4 is NIC capability
1666 * Force mode: phyxcer register4 is the force media
1667 */
1668
1669static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1670{
1671 u16 phy_reg;
1672
1673 /* Select 10/100M phyxcer */
1674 db->cr6_data &= ~0x40000;
1675 update_cr6(db->cr6_data, db->ioaddr);
1676
1677 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1678 if (db->chip_id == PCI_DM9009_ID) {
f67ba792
ML		 1679 phy_reg = phy_read(db->ioaddr,
1680 db->phy_addr, 18, db->chip_id) & ~0x1000;
1681
1682 phy_write(db->ioaddr,
1683 db->phy_addr, 18, phy_reg, db->chip_id);
1da177e4
LT		 1684 }
1685
1686 /* Phyxcer capability setting */
1687 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1688
1689 if (db->media_mode & DMFE_AUTO) {
1690 /* AUTO Mode */
1691 phy_reg |= db->PHY_reg4;
1692 } else {
1693 /* Force Mode */
1694 switch(db->media_mode) {
1695 case DMFE_10MHF: phy_reg |= 0x20; break;
1696 case DMFE_10MFD: phy_reg |= 0x40; break;
1697 case DMFE_100MHF: phy_reg |= 0x80; break;
1698 case DMFE_100MFD: phy_reg |= 0x100; break;
1699 }
1700 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1701 }
1702
1703 /* Write new capability to Phyxcer Reg4 */
1704 if ( !(phy_reg & 0x01e0)) {
1705 phy_reg|=db->PHY_reg4;
1706 db->media_mode|=DMFE_AUTO;
1707 }
1708 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1709
1710 /* Restart Auto-Negotiation */
1711 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1712 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1713 if ( !db->chip_type )
1714 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1715}
1716
1717
1718/*
1719 * Process op-mode
1720 * AUTO mode : PHY controller in Auto-negotiation Mode
1721 * Force mode: PHY controller in force mode with HUB
1722 * N-way force capability with SWITCH
1723 */
1724
1725static void dmfe_process_mode(struct dmfe_board_info *db)
1726{
1727 u16 phy_reg;
1728
1729 /* Full Duplex Mode Check */
1730 if (db->op_mode & 0x4)
1731 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1732 else
1733 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1734
1735 /* Transciver Selection */
1736 if (db->op_mode & 0x10) /* 1M HomePNA */
1737 db->cr6_data |= 0x40000;/* External MII select */
1738 else
1739 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1740
1741 update_cr6(db->cr6_data, db->ioaddr);
1742
1743 /* 10/100M phyxcer force mode need */
1744 if ( !(db->media_mode & 0x18)) {
1745 /* Forece Mode */
1746 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1747 if ( !(phy_reg & 0x1) ) {
1748 /* parter without N-Way capability */
1749 phy_reg = 0x0;
1750 switch(db->op_mode) {
1751 case DMFE_10MHF: phy_reg = 0x0; break;
1752 case DMFE_10MFD: phy_reg = 0x100; break;
1753 case DMFE_100MHF: phy_reg = 0x2000; break;
1754 case DMFE_100MFD: phy_reg = 0x2100; break;
1755 }
f67ba792
ML		 1756 phy_write(db->ioaddr,
1757 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1758 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1759 mdelay(20);
f67ba792
ML		 1760 phy_write(db->ioaddr,
1761 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1762 }
1763 }
1764}
1765
1766
1767/*
1768 * Write a word to Phy register
1769 */
1770
f67ba792
ML		 1771static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1772 u16 phy_data, u32 chip_id)
1da177e4
LT		 1773{
1774 u16 i;
1775 unsigned long ioaddr;
1776
1777 if (chip_id == PCI_DM9132_ID) {
1778 ioaddr = iobase + 0x80 + offset * 4;
1779 outw(phy_data, ioaddr);
1780 } else {
1781 /* DM9102/DM9102A Chip */
1782 ioaddr = iobase + DCR9;
1783
1784 /* Send 33 synchronization clock to Phy controller */
1785 for (i = 0; i < 35; i++)
1786 phy_write_1bit(ioaddr, PHY_DATA_1);
1787
1788 /* Send start command(01) to Phy */
1789 phy_write_1bit(ioaddr, PHY_DATA_0);
1790 phy_write_1bit(ioaddr, PHY_DATA_1);
1791
1792 /* Send write command(01) to Phy */
1793 phy_write_1bit(ioaddr, PHY_DATA_0);
1794 phy_write_1bit(ioaddr, PHY_DATA_1);
1795
1796 /* Send Phy address */
1797 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1798 phy_write_1bit(ioaddr,
1799 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1800
1801 /* Send register address */
1802 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1803 phy_write_1bit(ioaddr,
1804 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1805
1806 /* written trasnition */
1807 phy_write_1bit(ioaddr, PHY_DATA_1);
1808 phy_write_1bit(ioaddr, PHY_DATA_0);
1809
1810 /* Write a word data to PHY controller */
1811 for ( i = 0x8000; i > 0; i >>= 1)
f67ba792
ML		 1812 phy_write_1bit(ioaddr,
1813 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1814 }
1815}
1816
1817
1818/*
1819 * Read a word data from phy register
1820 */
1821
1822static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1823{
1824 int i;
1825 u16 phy_data;
1826 unsigned long ioaddr;
1827
1828 if (chip_id == PCI_DM9132_ID) {
1829 /* DM9132 Chip */
1830 ioaddr = iobase + 0x80 + offset * 4;
1831 phy_data = inw(ioaddr);
1832 } else {
1833 /* DM9102/DM9102A Chip */
1834 ioaddr = iobase + DCR9;
1835
1836 /* Send 33 synchronization clock to Phy controller */
1837 for (i = 0; i < 35; i++)
1838 phy_write_1bit(ioaddr, PHY_DATA_1);
1839
1840 /* Send start command(01) to Phy */
1841 phy_write_1bit(ioaddr, PHY_DATA_0);
1842 phy_write_1bit(ioaddr, PHY_DATA_1);
1843
1844 /* Send read command(10) to Phy */
1845 phy_write_1bit(ioaddr, PHY_DATA_1);
1846 phy_write_1bit(ioaddr, PHY_DATA_0);
1847
1848 /* Send Phy address */
1849 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1850 phy_write_1bit(ioaddr,
1851 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1852
1853 /* Send register address */
1854 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1855 phy_write_1bit(ioaddr,
1856 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1857
1858 /* Skip transition state */
1859 phy_read_1bit(ioaddr);
1860
1861 /* read 16bit data */
1862 for (phy_data = 0, i = 0; i < 16; i++) {
1863 phy_data <<= 1;
1864 phy_data |= phy_read_1bit(ioaddr);
1865 }
1866 }
1867
1868 return phy_data;
1869}
1870
1871
1872/*
1873 * Write one bit data to Phy Controller
1874 */
1875
1876static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1877{
1878 outl(phy_data, ioaddr); /* MII Clock Low */
1879 udelay(1);
1880 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1881 udelay(1);
1882 outl(phy_data, ioaddr); /* MII Clock Low */
1883 udelay(1);
1884}
1885
1886
1887/*
1888 * Read one bit phy data from PHY controller
1889 */
1890
1891static u16 phy_read_1bit(unsigned long ioaddr)
1892{
1893 u16 phy_data;
1894
1895 outl(0x50000, ioaddr);
1896 udelay(1);
1897 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1898 outl(0x40000, ioaddr);
1899 udelay(1);
1900
1901 return phy_data;
1902}
1903
1904
1905/*
1906 * Parser SROM and media mode
1907 */
1908
1909static void dmfe_parse_srom(struct dmfe_board_info * db)
1910{
1911 char * srom = db->srom;
1912 int dmfe_mode, tmp_reg;
1913
1914 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1915
1916 /* Init CR15 */
1917 db->cr15_data = CR15_DEFAULT;
1918
1919 /* Check SROM Version */
1920 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1921 /* SROM V4.01 */
1922 /* Get NIC support media mode */
4c93566e 1923 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1da177e4
LT		 1924 db->PHY_reg4 = 0;
1925 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1926 switch( db->NIC_capability & tmp_reg ) {
1927 case 0x1: db->PHY_reg4 |= 0x0020; break;
1928 case 0x2: db->PHY_reg4 |= 0x0040; break;
1929 case 0x4: db->PHY_reg4 |= 0x0080; break;
1930 case 0x8: db->PHY_reg4 |= 0x0100; break;
1931 }
1932 }
1933
1934 /* Media Mode Force or not check */
4c93566e
DM		 1935 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1936 le32_to_cpup((__le32 *) (srom + 36)));
1da177e4
LT		 1937 switch(dmfe_mode) {
1938 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1939 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1940 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1941 case 0x100:
1942 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1943 }
1944
1945 /* Special Function setting */
1946 /* VLAN function */
1947 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1948 db->cr15_data |= 0x40;
1949
1950 /* Flow Control */
1951 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1952 db->cr15_data |= 0x400;
1953
1954 /* TX pause packet */
1955 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1956 db->cr15_data |= 0x9800;
1957 }
1958
1959 /* Parse HPNA parameter */
1960 db->HPNA_command = 1;
1961
1962 /* Accept remote command or not */
1963 if (HPNA_rx_cmd == 0)
1964 db->HPNA_command |= 0x8000;
1965
1966 /* Issue remote command & operation mode */
1967 if (HPNA_tx_cmd == 1)
1968 switch(HPNA_mode) { /* Issue Remote Command */
1969 case 0: db->HPNA_command |= 0x0904; break;
1970 case 1: db->HPNA_command |= 0x0a00; break;
1971 case 2: db->HPNA_command |= 0x0506; break;
1972 case 3: db->HPNA_command |= 0x0602; break;
1973 }
1974 else
1975 switch(HPNA_mode) { /* Don't Issue */
1976 case 0: db->HPNA_command |= 0x0004; break;
1977 case 1: db->HPNA_command |= 0x0000; break;
1978 case 2: db->HPNA_command |= 0x0006; break;
1979 case 3: db->HPNA_command |= 0x0002; break;
1980 }
1981
1982 /* Check DM9801 or DM9802 present or not */
1983 db->HPNA_present = 0;
1984 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1985 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1986 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1987 /* DM9801 or DM9802 present */
1988 db->HPNA_timer = 8;
1989 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1990 /* DM9801 HomeRun */
1991 db->HPNA_present = 1;
1992 dmfe_program_DM9801(db, tmp_reg);
1993 } else {
1994 /* DM9802 LongRun */
1995 db->HPNA_present = 2;
1996 dmfe_program_DM9802(db);
1997 }
1998 }
1999
2000}
2001
2002
2003/*
2004 * Init HomeRun DM9801
2005 */
2006
2007static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
2008{
2009 uint reg17, reg25;
2010
2011 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
2012 switch(HPNA_rev) {
2013 case 0xb900: /* DM9801 E3 */
2014 db->HPNA_command |= 0x1000;
2015 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2016 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2017 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2018 break;
2019 case 0xb901: /* DM9801 E4 */
2020 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2021 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2022 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2023 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2024 break;
2025 case 0xb902: /* DM9801 E5 */
2026 case 0xb903: /* DM9801 E6 */
2027 default:
2028 db->HPNA_command |= 0x1000;
2029 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2030 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2031 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2032 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2033 break;
2034 }
2035 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2036 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2037 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2038}
2039
2040
2041/*
2042 * Init HomeRun DM9802
2043 */
2044
2045static void dmfe_program_DM9802(struct dmfe_board_info * db)
2046{
2047 uint phy_reg;
2048
2049 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2050 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2051 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2052 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2053 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2054}
2055
2056
2057/*
2058 * Check remote HPNA power and speed status. If not correct,
2059 * issue command again.
2060*/
2061
2062static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2063{
2064 uint phy_reg;
2065
2066 /* Got remote device status */
2067 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2068 switch(phy_reg) {
2069 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2070 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2071 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2072 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2073 }
2074
2075 /* Check remote device status match our setting ot not */
2076 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
f67ba792
ML		 2077 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2078 db->chip_id);
1da177e4
LT		 2079 db->HPNA_timer=8;
2080 } else
2081 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2082}
2083
2084
2085
a3aa1884 2086static DEFINE_PCI_DEVICE_TABLE(dmfe_pci_tbl) = {
1da177e4
LT		 2087 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2088 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2089 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2090 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2091 { 0, }
2092};
2093MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2094
2095
bc8a8387
ML		 2096#ifdef CONFIG_PM
2097static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2098{
2099 struct net_device *dev = pci_get_drvdata(pci_dev);
2100 struct dmfe_board_info *db = netdev_priv(dev);
f1069046 2101 u32 tmp;
bc8a8387
ML		 2102
2103 /* Disable upper layer interface */
2104 netif_device_detach(dev);
2105
2106 /* Disable Tx/Rx */
2107 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2108 update_cr6(db->cr6_data, dev->base_addr);
2109
2110 /* Disable Interrupt */
2111 outl(0, dev->base_addr + DCR7);
2112 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
2113
2114 /* Fre RX buffers */
2115 dmfe_free_rxbuffer(db);
2116
f1069046
ML		 2117 /* Enable WOL */
2118 pci_read_config_dword(pci_dev, 0x40, &tmp);
2119 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2120
2121 if (db->wol_mode & WAKE_PHY)
2122 tmp |= DMFE_WOL_LINKCHANGE;
2123 if (db->wol_mode & WAKE_MAGIC)
2124 tmp |= DMFE_WOL_MAGICPACKET;
2125
2126 pci_write_config_dword(pci_dev, 0x40, tmp);
2127
2128 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2129 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2130
bc8a8387 2131 /* Power down device*/
bc8a8387 2132 pci_save_state(pci_dev);
a31e23e1 2133 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
bc8a8387
ML		 2134
2135 return 0;
2136}
2137
2138static int dmfe_resume(struct pci_dev *pci_dev)
2139{
2140 struct net_device *dev = pci_get_drvdata(pci_dev);
f1069046 2141 u32 tmp;
bc8a8387 2142
bc8a8387 2143 pci_set_power_state(pci_dev, PCI_D0);
65809b51 2144 pci_restore_state(pci_dev);
bc8a8387
ML		 2145
2146 /* Re-initilize DM910X board */
2147 dmfe_init_dm910x(dev);
2148
f1069046
ML		 2149 /* Disable WOL */
2150 pci_read_config_dword(pci_dev, 0x40, &tmp);
2151
2152 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2153 pci_write_config_dword(pci_dev, 0x40, tmp);
2154
2155 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2156 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2157
bc8a8387
ML		 2158 /* Restart upper layer interface */
2159 netif_device_attach(dev);
2160
2161 return 0;
2162}
2163#else
2164#define dmfe_suspend NULL
2165#define dmfe_resume NULL
2166#endif
2167
1da177e4
LT		 2168static struct pci_driver dmfe_driver = {
2169 .name = "dmfe",
2170 .id_table = dmfe_pci_tbl,
2171 .probe = dmfe_init_one,
2172 .remove = __devexit_p(dmfe_remove_one),
bc8a8387
ML		 2173 .suspend = dmfe_suspend,
2174 .resume = dmfe_resume
1da177e4
LT		 2175};
2176
2177MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2178MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2179MODULE_LICENSE("GPL");
2180MODULE_VERSION(DRV_VERSION);
2181
2182module_param(debug, int, 0);
2183module_param(mode, byte, 0);
2184module_param(cr6set, int, 0);
2185module_param(chkmode, byte, 0);
2186module_param(HPNA_mode, byte, 0);
2187module_param(HPNA_rx_cmd, byte, 0);
2188module_param(HPNA_tx_cmd, byte, 0);
2189module_param(HPNA_NoiseFloor, byte, 0);
2190module_param(SF_mode, byte, 0);
2191MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
f67ba792
ML		 2192MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2193 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2194
2195MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2196 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
1da177e4
LT		 2197
2198/* Description:
2199 * when user used insmod to add module, system invoked init_module()
2200 * to initilize and register.
2201 */
2202
2203static int __init dmfe_init_module(void)
2204{
2205 int rc;
2206
2207 printk(version);
2208 printed_version = 1;
2209
2210 DMFE_DBUG(0, "init_module() ", debug);
2211
2212 if (debug)
2213 dmfe_debug = debug; /* set debug flag */
2214 if (cr6set)
2215 dmfe_cr6_user_set = cr6set;
2216
2217 switch(mode) {
2218 case DMFE_10MHF:
2219 case DMFE_100MHF:
2220 case DMFE_10MFD:
2221 case DMFE_100MFD:
2222 case DMFE_1M_HPNA:
2223 dmfe_media_mode = mode;
2224 break;
2225 default:dmfe_media_mode = DMFE_AUTO;
2226 break;
2227 }
2228
2229 if (HPNA_mode > 4)
2230 HPNA_mode = 0; /* Default: LP/HS */
2231 if (HPNA_rx_cmd > 1)
2232 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2233 if (HPNA_tx_cmd > 1)
2234 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2235 if (HPNA_NoiseFloor > 15)
2236 HPNA_NoiseFloor = 0;
2237
29917620 2238 rc = pci_register_driver(&dmfe_driver);
1da177e4
LT		 2239 if (rc < 0)
2240 return rc;
2241
2242 return 0;
2243}
2244
2245
2246/*
2247 * Description:
2248 * when user used rmmod to delete module, system invoked clean_module()
2249 * to un-register all registered services.
2250 */
2251
2252static void __exit dmfe_cleanup_module(void)
2253{
2254 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2255 pci_unregister_driver(&dmfe_driver);
2256}
2257
2258module_init(dmfe_init_module);
2259module_exit(dmfe_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)