[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sfc / qt202x_phy.c

/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2006-2009 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */
/*
 * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
 */

#include <linux/slab.h>
#include <linux/timer.h>
#include <linux/delay.h>
#include "efx.h"
#include "mdio_10g.h"
#include "phy.h"
#include "nic.h"

#define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS |		\
			      MDIO_DEVS_PMAPMD |	\
			      MDIO_DEVS_PHYXS)

#define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) |		\
			  (1 << LOOPBACK_PMAPMD) |	\
			  (1 << LOOPBACK_PHYXS_WS))

/****************************************************************************/
/* Quake-specific MDIO registers */
#define MDIO_QUAKE_LED0_REG	(0xD006)

/* QT2025C only */
#define PCS_FW_HEARTBEAT_REG	0xd7ee
#define PCS_FW_HEARTB_LBN	0
#define PCS_FW_HEARTB_WIDTH	8
#define PCS_FW_PRODUCT_CODE_1	0xd7f0
#define PCS_FW_VERSION_1	0xd7f3
#define PCS_FW_BUILD_1		0xd7f6
#define PCS_UC8051_STATUS_REG	0xd7fd
#define PCS_UC_STATUS_LBN	0
#define PCS_UC_STATUS_WIDTH	8
#define PCS_UC_STATUS_FW_SAVE	0x20
#define PMA_PMD_FTX_CTRL2_REG	0xc309
#define PMA_PMD_FTX_STATIC_LBN	13
#define PMA_PMD_VEND1_REG	0xc001
#define PMA_PMD_VEND1_LBTXD_LBN	15
#define PCS_VEND1_REG	   	0xc000
#define PCS_VEND1_LBTXD_LBN	5

void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
{
	int addr = MDIO_QUAKE_LED0_REG + led;
	efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
}

struct qt202x_phy_data {
	enum efx_phy_mode phy_mode;
	bool bug17190_in_bad_state;
	unsigned long bug17190_timer;
	u32 firmware_ver;
};

#define QT2022C2_MAX_RESET_TIME 500
#define QT2022C2_RESET_WAIT 10

#define QT2025C_MAX_HEARTB_TIME (5 * HZ)
#define QT2025C_HEARTB_WAIT 100
#define QT2025C_MAX_FWSTART_TIME (25 * HZ / 10)
#define QT2025C_FWSTART_WAIT 100

#define BUG17190_INTERVAL (2 * HZ)

static int qt2025c_wait_heartbeat(struct efx_nic *efx)
{
	unsigned long timeout = jiffies + QT2025C_MAX_HEARTB_TIME;
	int reg, old_counter = 0;

	/* Wait for firmware heartbeat to start */
	for (;;) {
		int counter;
		reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
		if (reg < 0)
			return reg;
		counter = ((reg >> PCS_FW_HEARTB_LBN) &
			    ((1 << PCS_FW_HEARTB_WIDTH) - 1));
		if (old_counter == 0)
			old_counter = counter;
		else if (counter != old_counter)
			break;
		if (time_after(jiffies, timeout)) {
			/* Some cables have EEPROMs that conflict with the
			 * PHY's on-board EEPROM so it cannot load firmware */
			EFX_ERR(efx, "If an SFP+ direct attach cable is"
				" connected, please check that it complies"
				" with the SFP+ specification\n");
			return -ETIMEDOUT;
		}
		msleep(QT2025C_HEARTB_WAIT);
	}

	return 0;
}

static int qt2025c_wait_fw_status_good(struct efx_nic *efx)
{
	unsigned long timeout = jiffies + QT2025C_MAX_FWSTART_TIME;
	int reg;

	/* Wait for firmware status to look good */
	for (;;) {
		reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
		if (reg < 0)
			return reg;
		if ((reg &
		     ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
		    PCS_UC_STATUS_FW_SAVE)
			break;
		if (time_after(jiffies, timeout))
			return -ETIMEDOUT;
		msleep(QT2025C_FWSTART_WAIT);
	}

	return 0;
}

static void qt2025c_restart_firmware(struct efx_nic *efx)
{
	/* Restart microcontroller execution of firmware from RAM */
	efx_mdio_write(efx, 3, 0xe854, 0x00c0);
	efx_mdio_write(efx, 3, 0xe854, 0x0040);
	msleep(50);
}

static int qt2025c_wait_reset(struct efx_nic *efx)
{
	int rc;

	rc = qt2025c_wait_heartbeat(efx);
	if (rc != 0)
		return rc;

	rc = qt2025c_wait_fw_status_good(efx);
	if (rc == -ETIMEDOUT) {
		/* Bug 17689: occasionally heartbeat starts but firmware status
		 * code never progresses beyond 0x00.  Try again, once, after
		 * restarting execution of the firmware image. */
		EFX_LOG(efx, "bashing QT2025C microcontroller\n");
		qt2025c_restart_firmware(efx);
		rc = qt2025c_wait_heartbeat(efx);
		if (rc != 0)
			return rc;
		rc = qt2025c_wait_fw_status_good(efx);
	}

	return rc;
}

static void qt2025c_firmware_id(struct efx_nic *efx)
{
	struct qt202x_phy_data *phy_data = efx->phy_data;
	u8 firmware_id[9];
	size_t i;

	for (i = 0; i < sizeof(firmware_id); i++)
		firmware_id[i] = efx_mdio_read(efx, MDIO_MMD_PCS,
					       PCS_FW_PRODUCT_CODE_1 + i);
	EFX_INFO(efx, "QT2025C firmware %xr%d v%d.%d.%d.%d [20%02d-%02d-%02d]\n",
		 (firmware_id[0] << 8) | firmware_id[1], firmware_id[2],
		 firmware_id[3] >> 4, firmware_id[3] & 0xf,
		 firmware_id[4], firmware_id[5],
		 firmware_id[6], firmware_id[7], firmware_id[8]);
	phy_data->firmware_ver = ((firmware_id[3] & 0xf0) << 20) |
				 ((firmware_id[3] & 0x0f) << 16) |
				 (firmware_id[4] << 8) | firmware_id[5];
}

static void qt2025c_bug17190_workaround(struct efx_nic *efx)
{
	struct qt202x_phy_data *phy_data = efx->phy_data;

	/* The PHY can get stuck in a state where it reports PHY_XS and PMA/PMD
	 * layers up, but PCS down (no block_lock).  If we notice this state
	 * persisting for a couple of seconds, we switch PMA/PMD loopback
	 * briefly on and then off again, which is normally sufficient to
	 * recover it.
	 */
	if (efx->link_state.up ||
	    !efx_mdio_links_ok(efx, MDIO_DEVS_PMAPMD | MDIO_DEVS_PHYXS)) {
		phy_data->bug17190_in_bad_state = false;
		return;
	}

	if (!phy_data->bug17190_in_bad_state) {
		phy_data->bug17190_in_bad_state = true;
		phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
		return;
	}

	if (time_after_eq(jiffies, phy_data->bug17190_timer)) {
		EFX_LOG(efx, "bashing QT2025C PMA/PMD\n");
		efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
				  MDIO_PMA_CTRL1_LOOPBACK, true);
		msleep(100);
		efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
				  MDIO_PMA_CTRL1_LOOPBACK, false);
		phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
	}
}

static int qt2025c_select_phy_mode(struct efx_nic *efx)
{
	struct qt202x_phy_data *phy_data = efx->phy_data;
	struct falcon_board *board = falcon_board(efx);
	int reg, rc, i;
	uint16_t phy_op_mode;

	/* Only 2.0.1.0+ PHY firmware supports the more optimal SFP+
	 * Self-Configure mode.  Don't attempt any switching if we encounter
	 * older firmware. */
	if (phy_data->firmware_ver < 0x02000100)
		return 0;

	/* In general we will get optimal behaviour in "SFP+ Self-Configure"
	 * mode; however, that powers down most of the PHY when no module is
	 * present, so we must use a different mode (any fixed mode will do)
	 * to be sure that loopbacks will work. */
	phy_op_mode = (efx->loopback_mode == LOOPBACK_NONE) ? 0x0038 : 0x0020;

	/* Only change mode if really necessary */
	reg = efx_mdio_read(efx, 1, 0xc319);
	if ((reg & 0x0038) == phy_op_mode)
		return 0;
	EFX_LOG(efx, "Switching PHY to mode 0x%04x\n", phy_op_mode);

	/* This sequence replicates the register writes configured in the boot
	 * EEPROM (including the differences between board revisions), except
	 * that the operating mode is changed, and the PHY is prevented from
	 * unnecessarily reloading the main firmware image again. */
	efx_mdio_write(efx, 1, 0xc300, 0x0000);
	/* (Note: this portion of the boot EEPROM sequence, which bit-bashes 9
	 * STOPs onto the firmware/module I2C bus to reset it, varies across
	 * board revisions, as the bus is connected to different GPIO/LED
	 * outputs on the PHY.) */
	if (board->major == 0 && board->minor < 2) {
		efx_mdio_write(efx, 1, 0xc303, 0x4498);
		for (i = 0; i < 9; i++) {
			efx_mdio_write(efx, 1, 0xc303, 0x4488);
			efx_mdio_write(efx, 1, 0xc303, 0x4480);
			efx_mdio_write(efx, 1, 0xc303, 0x4490);
			efx_mdio_write(efx, 1, 0xc303, 0x4498);
		}
	} else {
		efx_mdio_write(efx, 1, 0xc303, 0x0920);
		efx_mdio_write(efx, 1, 0xd008, 0x0004);
		for (i = 0; i < 9; i++) {
			efx_mdio_write(efx, 1, 0xc303, 0x0900);
			efx_mdio_write(efx, 1, 0xd008, 0x0005);
			efx_mdio_write(efx, 1, 0xc303, 0x0920);
			efx_mdio_write(efx, 1, 0xd008, 0x0004);
		}
		efx_mdio_write(efx, 1, 0xc303, 0x4900);
	}
	efx_mdio_write(efx, 1, 0xc303, 0x4900);
	efx_mdio_write(efx, 1, 0xc302, 0x0004);
	efx_mdio_write(efx, 1, 0xc316, 0x0013);
	efx_mdio_write(efx, 1, 0xc318, 0x0054);
	efx_mdio_write(efx, 1, 0xc319, phy_op_mode);
	efx_mdio_write(efx, 1, 0xc31a, 0x0098);
	efx_mdio_write(efx, 3, 0x0026, 0x0e00);
	efx_mdio_write(efx, 3, 0x0027, 0x0013);
	efx_mdio_write(efx, 3, 0x0028, 0xa528);
	efx_mdio_write(efx, 1, 0xd006, 0x000a);
	efx_mdio_write(efx, 1, 0xd007, 0x0009);
	efx_mdio_write(efx, 1, 0xd008, 0x0004);
	/* This additional write is not present in the boot EEPROM.  It
	 * prevents the PHY's internal boot ROM doing another pointless (and
	 * slow) reload of the firmware image (the microcontroller's code
	 * memory is not affected by the microcontroller reset). */
	efx_mdio_write(efx, 1, 0xc317, 0x00ff);
	efx_mdio_write(efx, 1, 0xc300, 0x0002);
	msleep(20);

	/* Restart microcontroller execution of firmware from RAM */
	qt2025c_restart_firmware(efx);

	/* Wait for the microcontroller to be ready again */
	rc = qt2025c_wait_reset(efx);
	if (rc < 0) {
		EFX_ERR(efx, "PHY microcontroller reset during mode switch "
				"timed out\n");
		return rc;
	}

	return 0;
}

static int qt202x_reset_phy(struct efx_nic *efx)
{
	int rc;

	if (efx->phy_type == PHY_TYPE_QT2025C) {
		/* Wait for the reset triggered by falcon_reset_hw()
		 * to complete */
		rc = qt2025c_wait_reset(efx);
		if (rc < 0)
			goto fail;
	} else {
		/* Reset the PHYXS MMD. This is documented as doing
		 * a complete soft reset. */
		rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
					QT2022C2_MAX_RESET_TIME /
					QT2022C2_RESET_WAIT,
					QT2022C2_RESET_WAIT);
		if (rc < 0)
			goto fail;
	}

	/* Wait 250ms for the PHY to complete bootup */
	msleep(250);

	falcon_board(efx)->type->init_phy(efx);

	return 0;

 fail:
	EFX_ERR(efx, "PHY reset timed out\n");
	return rc;
}

static int qt202x_phy_probe(struct efx_nic *efx)
{
	struct qt202x_phy_data *phy_data;

	phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
	if (!phy_data)
		return -ENOMEM;
	efx->phy_data = phy_data;
	phy_data->phy_mode = efx->phy_mode;
	phy_data->bug17190_in_bad_state = false;
	phy_data->bug17190_timer = 0;

	efx->mdio.mmds = QT202X_REQUIRED_DEVS;
	efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
	efx->loopback_modes = QT202X_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
	return 0;
}

static int qt202x_phy_init(struct efx_nic *efx)
{
	u32 devid;
	int rc;

	rc = qt202x_reset_phy(efx);
	if (rc) {
		EFX_ERR(efx, "PHY init failed\n");
		return rc;
	}

	devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
	EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
		 devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
		 efx_mdio_id_rev(devid));

	if (efx->phy_type == PHY_TYPE_QT2025C)
		qt2025c_firmware_id(efx);

	return 0;
}

static int qt202x_link_ok(struct efx_nic *efx)
{
	return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
}

static bool qt202x_phy_poll(struct efx_nic *efx)
{
	bool was_up = efx->link_state.up;

	efx->link_state.up = qt202x_link_ok(efx);
	efx->link_state.speed = 10000;
	efx->link_state.fd = true;
	efx->link_state.fc = efx->wanted_fc;

	if (efx->phy_type == PHY_TYPE_QT2025C)
		qt2025c_bug17190_workaround(efx);

	return efx->link_state.up != was_up;
}

static int qt202x_phy_reconfigure(struct efx_nic *efx)
{
	struct qt202x_phy_data *phy_data = efx->phy_data;

	if (efx->phy_type == PHY_TYPE_QT2025C) {
		int rc = qt2025c_select_phy_mode(efx);
		if (rc)
			return rc;

		/* There are several different register bits which can
		 * disable TX (and save power) on direct-attach cables
		 * or optical transceivers, varying somewhat between
		 * firmware versions.  Only 'static mode' appears to
		 * cover everything. */
		mdio_set_flag(
			&efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
			PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
			efx->phy_mode & PHY_MODE_TX_DISABLED ||
			efx->phy_mode & PHY_MODE_LOW_POWER ||
			efx->loopback_mode == LOOPBACK_PCS ||
			efx->loopback_mode == LOOPBACK_PMAPMD);
	} else {
		/* Reset the PHY when moving from tx off to tx on */
		if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
		    (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
			qt202x_reset_phy(efx);

		efx_mdio_transmit_disable(efx);
	}

	efx_mdio_phy_reconfigure(efx);

	phy_data->phy_mode = efx->phy_mode;

	return 0;
}

static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
{
	mdio45_ethtool_gset(&efx->mdio, ecmd);
}

static void qt202x_phy_remove(struct efx_nic *efx)
{
	/* Free the context block */
	kfree(efx->phy_data);
	efx->phy_data = NULL;
}

struct efx_phy_operations falcon_qt202x_phy_ops = {
	.probe		 = qt202x_phy_probe,
	.init		 = qt202x_phy_init,
	.reconfigure	 = qt202x_phy_reconfigure,
	.poll	     	 = qt202x_phy_poll,
	.fini		 = efx_port_dummy_op_void,
	.remove	  	 = qt202x_phy_remove,
	.get_settings	 = qt202x_phy_get_settings,
	.set_settings	 = efx_mdio_set_settings,
	.test_alive	 = efx_mdio_test_alive,
};
Commit	Line	Data
8ceee660 BH	1	/****************************************************************************
8ceee660 BH	2	* Driver for Solarflare Solarstorm network controllers and boards
906bb26c	3	* Copyright 2006-2009 Solarflare Communications Inc.
8ceee660 BH	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published
	7	* by the Free Software Foundation, incorporated herein by reference.
	8	*/
	9	/*
b37b62fe	10	* Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
8ceee660 BH	11	*/
8ceee660 BH	12
5a0e3ad6	13	#include <linux/slab.h>
8ceee660 BH	14	#include <linux/timer.h>
	15	#include <linux/delay.h>
	16	#include "efx.h"
8ceee660	17	#include "mdio_10g.h"
8ceee660	18	#include "phy.h"
744093c9	19	#include "nic.h"
8ceee660	20
b37b62fe BH	21	#define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS \| \
	22	MDIO_DEVS_PMAPMD \| \
	23	MDIO_DEVS_PHYXS)
8ceee660	24
b37b62fe BH	25	#define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) \| \
b37b62fe BH	26	(1 << LOOPBACK_PMAPMD) \| \
e58f69f4	27	(1 << LOOPBACK_PHYXS_WS))
3273c2e8	28
8ceee660 BH	29	/****************************************************************************/
	30	/* Quake-specific MDIO registers */
	31	#define MDIO_QUAKE_LED0_REG (0xD006)
	32
d2d2c373 BH	33	/* QT2025C only */
	34	#define PCS_FW_HEARTBEAT_REG 0xd7ee
	35	#define PCS_FW_HEARTB_LBN 0
	36	#define PCS_FW_HEARTB_WIDTH 8
0d83b2f6 MS	37	#define PCS_FW_PRODUCT_CODE_1 0xd7f0
	38	#define PCS_FW_VERSION_1 0xd7f3
	39	#define PCS_FW_BUILD_1 0xd7f6
d2d2c373 BH	40	#define PCS_UC8051_STATUS_REG 0xd7fd
	41	#define PCS_UC_STATUS_LBN 0
	42	#define PCS_UC_STATUS_WIDTH 8
	43	#define PCS_UC_STATUS_FW_SAVE 0x20
	44	#define PMA_PMD_FTX_CTRL2_REG 0xc309
	45	#define PMA_PMD_FTX_STATIC_LBN 13
	46	#define PMA_PMD_VEND1_REG 0xc001
	47	#define PMA_PMD_VEND1_LBTXD_LBN 15
	48	#define PCS_VEND1_REG 0xc000
	49	#define PCS_VEND1_LBTXD_LBN 5
	50
b37b62fe	51	void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
8ceee660 BH	52	{
8ceee660 BH	53	int addr = MDIO_QUAKE_LED0_REG + led;
68e7f45e	54	efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
8ceee660 BH	55	}
8ceee660 BH	56
b37b62fe	57	struct qt202x_phy_data {
f8b87c17	58	enum efx_phy_mode phy_mode;
17d6aeaf MS	59	bool bug17190_in_bad_state;
17d6aeaf MS	60	unsigned long bug17190_timer;
0d83b2f6	61	u32 firmware_ver;
3273c2e8 BH	62	};
3273c2e8 BH	63
b37b62fe BH	64	#define QT2022C2_MAX_RESET_TIME 500
b37b62fe BH	65	#define QT2022C2_RESET_WAIT 10
8ceee660	66
1a1284ef MS	67	#define QT2025C_MAX_HEARTB_TIME (5 * HZ)
	68	#define QT2025C_HEARTB_WAIT 100
	69	#define QT2025C_MAX_FWSTART_TIME (25 * HZ / 10)
	70	#define QT2025C_FWSTART_WAIT 100
	71
17d6aeaf MS	72	#define BUG17190_INTERVAL (2 * HZ)
17d6aeaf MS	73
1a1284ef	74	static int qt2025c_wait_heartbeat(struct efx_nic *efx)
d2d2c373	75	{
1a1284ef	76	unsigned long timeout = jiffies + QT2025C_MAX_HEARTB_TIME;
d2d2c373 BH	77	int reg, old_counter = 0;
	78
	79	/* Wait for firmware heartbeat to start */
	80	for (;;) {
	81	int counter;
68e7f45e	82	reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
d2d2c373 BH	83	if (reg < 0)
	84	return reg;
	85	counter = ((reg >> PCS_FW_HEARTB_LBN) &
	86	((1 << PCS_FW_HEARTB_WIDTH) - 1));
	87	if (old_counter == 0)
	88	old_counter = counter;
	89	else if (counter != old_counter)
	90	break;
50d6ec55 BH	91	if (time_after(jiffies, timeout)) {
	92	/* Some cables have EEPROMs that conflict with the
	93	* PHY's on-board EEPROM so it cannot load firmware */
	94	EFX_ERR(efx, "If an SFP+ direct attach cable is"
	95	" connected, please check that it complies"
	96	" with the SFP+ specification\n");
d2d2c373	97	return -ETIMEDOUT;
50d6ec55	98	}
1a1284ef	99	msleep(QT2025C_HEARTB_WAIT);
d2d2c373 BH	100	}
d2d2c373 BH	101
1a1284ef MS	102	return 0;
	103	}
	104
	105	static int qt2025c_wait_fw_status_good(struct efx_nic *efx)
	106	{
	107	unsigned long timeout = jiffies + QT2025C_MAX_FWSTART_TIME;
	108	int reg;
	109
d2d2c373 BH	110	/* Wait for firmware status to look good */
d2d2c373 BH	111	for (;;) {
68e7f45e	112	reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
d2d2c373 BH	113	if (reg < 0)
	114	return reg;
	115	if ((reg &
	116	((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
	117	PCS_UC_STATUS_FW_SAVE)
	118	break;
	119	if (time_after(jiffies, timeout))
	120	return -ETIMEDOUT;
1a1284ef	121	msleep(QT2025C_FWSTART_WAIT);
d2d2c373 BH	122	}
	123
	124	return 0;
	125	}
	126
1a1284ef MS	127	static void qt2025c_restart_firmware(struct efx_nic *efx)
	128	{
	129	/* Restart microcontroller execution of firmware from RAM */
	130	efx_mdio_write(efx, 3, 0xe854, 0x00c0);
	131	efx_mdio_write(efx, 3, 0xe854, 0x0040);
	132	msleep(50);
	133	}
	134
	135	static int qt2025c_wait_reset(struct efx_nic *efx)
	136	{
	137	int rc;
	138
	139	rc = qt2025c_wait_heartbeat(efx);
	140	if (rc != 0)
	141	return rc;
	142
	143	rc = qt2025c_wait_fw_status_good(efx);
	144	if (rc == -ETIMEDOUT) {
	145	/* Bug 17689: occasionally heartbeat starts but firmware status
	146	* code never progresses beyond 0x00. Try again, once, after
	147	* restarting execution of the firmware image. */
	148	EFX_LOG(efx, "bashing QT2025C microcontroller\n");
	149	qt2025c_restart_firmware(efx);
	150	rc = qt2025c_wait_heartbeat(efx);
	151	if (rc != 0)
	152	return rc;
	153	rc = qt2025c_wait_fw_status_good(efx);
	154	}
	155
	156	return rc;
	157	}
	158
0d83b2f6 MS	159	static void qt2025c_firmware_id(struct efx_nic *efx)
	160	{
	161	struct qt202x_phy_data *phy_data = efx->phy_data;
	162	u8 firmware_id[9];
	163	size_t i;
	164
	165	for (i = 0; i < sizeof(firmware_id); i++)
	166	firmware_id[i] = efx_mdio_read(efx, MDIO_MMD_PCS,
	167	PCS_FW_PRODUCT_CODE_1 + i);
	168	EFX_INFO(efx, "QT2025C firmware %xr%d v%d.%d.%d.%d [20%02d-%02d-%02d]\n",
	169	(firmware_id[0] << 8) \| firmware_id[1], firmware_id[2],
	170	firmware_id[3] >> 4, firmware_id[3] & 0xf,
	171	firmware_id[4], firmware_id[5],
	172	firmware_id[6], firmware_id[7], firmware_id[8]);
	173	phy_data->firmware_ver = ((firmware_id[3] & 0xf0) << 20) \|
	174	((firmware_id[3] & 0x0f) << 16) \|
	175	(firmware_id[4] << 8) \| firmware_id[5];
	176	}
	177
17d6aeaf MS	178	static void qt2025c_bug17190_workaround(struct efx_nic *efx)
	179	{
	180	struct qt202x_phy_data *phy_data = efx->phy_data;
	181
	182	/* The PHY can get stuck in a state where it reports PHY_XS and PMA/PMD
	183	* layers up, but PCS down (no block_lock). If we notice this state
	184	* persisting for a couple of seconds, we switch PMA/PMD loopback
	185	* briefly on and then off again, which is normally sufficient to
	186	* recover it.
	187	*/
	188	if (efx->link_state.up \|\|
	189	!efx_mdio_links_ok(efx, MDIO_DEVS_PMAPMD \| MDIO_DEVS_PHYXS)) {
	190	phy_data->bug17190_in_bad_state = false;
	191	return;
	192	}
	193
	194	if (!phy_data->bug17190_in_bad_state) {
	195	phy_data->bug17190_in_bad_state = true;
	196	phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
	197	return;
	198	}
	199
	200	if (time_after_eq(jiffies, phy_data->bug17190_timer)) {
	201	EFX_LOG(efx, "bashing QT2025C PMA/PMD\n");
	202	efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
	203	MDIO_PMA_CTRL1_LOOPBACK, true);
	204	msleep(100);
	205	efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
	206	MDIO_PMA_CTRL1_LOOPBACK, false);
	207	phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
	208	}
	209	}
	210
0d83b2f6 MS	211	static int qt2025c_select_phy_mode(struct efx_nic *efx)
	212	{
	213	struct qt202x_phy_data *phy_data = efx->phy_data;
	214	struct falcon_board *board = falcon_board(efx);
	215	int reg, rc, i;
	216	uint16_t phy_op_mode;
	217
	218	/* Only 2.0.1.0+ PHY firmware supports the more optimal SFP+
	219	* Self-Configure mode. Don't attempt any switching if we encounter
	220	* older firmware. */
	221	if (phy_data->firmware_ver < 0x02000100)
	222	return 0;
	223
	224	/* In general we will get optimal behaviour in "SFP+ Self-Configure"
	225	* mode; however, that powers down most of the PHY when no module is
	226	* present, so we must use a different mode (any fixed mode will do)
	227	* to be sure that loopbacks will work. */
	228	phy_op_mode = (efx->loopback_mode == LOOPBACK_NONE) ? 0x0038 : 0x0020;
	229
	230	/* Only change mode if really necessary */
	231	reg = efx_mdio_read(efx, 1, 0xc319);
	232	if ((reg & 0x0038) == phy_op_mode)
	233	return 0;
	234	EFX_LOG(efx, "Switching PHY to mode 0x%04x\n", phy_op_mode);
	235
	236	/* This sequence replicates the register writes configured in the boot
	237	* EEPROM (including the differences between board revisions), except
	238	* that the operating mode is changed, and the PHY is prevented from
	239	* unnecessarily reloading the main firmware image again. */
	240	efx_mdio_write(efx, 1, 0xc300, 0x0000);
	241	/* (Note: this portion of the boot EEPROM sequence, which bit-bashes 9
	242	* STOPs onto the firmware/module I2C bus to reset it, varies across
	243	* board revisions, as the bus is connected to different GPIO/LED
	244	* outputs on the PHY.) */
	245	if (board->major == 0 && board->minor < 2) {
	246	efx_mdio_write(efx, 1, 0xc303, 0x4498);
	247	for (i = 0; i < 9; i++) {
	248	efx_mdio_write(efx, 1, 0xc303, 0x4488);
	249	efx_mdio_write(efx, 1, 0xc303, 0x4480);
	250	efx_mdio_write(efx, 1, 0xc303, 0x4490);
	251	efx_mdio_write(efx, 1, 0xc303, 0x4498);
	252	}
	253	} else {
	254	efx_mdio_write(efx, 1, 0xc303, 0x0920);
	255	efx_mdio_write(efx, 1, 0xd008, 0x0004);
	256	for (i = 0; i < 9; i++) {
	257	efx_mdio_write(efx, 1, 0xc303, 0x0900);
	258	efx_mdio_write(efx, 1, 0xd008, 0x0005);
	259	efx_mdio_write(efx, 1, 0xc303, 0x0920);
	260	efx_mdio_write(efx, 1, 0xd008, 0x0004);
	261	}
	262	efx_mdio_write(efx, 1, 0xc303, 0x4900);
	263	}
	264	efx_mdio_write(efx, 1, 0xc303, 0x4900);
	265	efx_mdio_write(efx, 1, 0xc302, 0x0004);
	266	efx_mdio_write(efx, 1, 0xc316, 0x0013);
	267	efx_mdio_write(efx, 1, 0xc318, 0x0054);
	268	efx_mdio_write(efx, 1, 0xc319, phy_op_mode);
	269	efx_mdio_write(efx, 1, 0xc31a, 0x0098);
	270	efx_mdio_write(efx, 3, 0x0026, 0x0e00);
	271	efx_mdio_write(efx, 3, 0x0027, 0x0013);
	272	efx_mdio_write(efx, 3, 0x0028, 0xa528);
	273	efx_mdio_write(efx, 1, 0xd006, 0x000a);
	274	efx_mdio_write(efx, 1, 0xd007, 0x0009);
275	efx_mdio_write(efx, 1, 0xd008, 0x0004);
276	/* This additional write is not present in the boot EEPROM. It
277	* prevents the PHY's internal boot ROM doing another pointless (and
278	* slow) reload of the firmware image (the microcontroller's code
279	* memory is not affected by the microcontroller reset). */
280	efx_mdio_write(efx, 1, 0xc317, 0x00ff);
281	efx_mdio_write(efx, 1, 0xc300, 0x0002);
282	msleep(20);
283
1a1284ef MS	284	/* Restart microcontroller execution of firmware from RAM */
1a1284ef MS	285	qt2025c_restart_firmware(efx);
0d83b2f6 MS	286
	287	/* Wait for the microcontroller to be ready again */
	288	rc = qt2025c_wait_reset(efx);
	289	if (rc < 0) {
	290	EFX_ERR(efx, "PHY microcontroller reset during mode switch "
	291	"timed out\n");
	292	return rc;
	293	}
	294
	295	return 0;
	296	}
	297
b37b62fe	298	static int qt202x_reset_phy(struct efx_nic *efx)
8ceee660 BH	299	{
	300	int rc;
	301
d2d2c373	302	if (efx->phy_type == PHY_TYPE_QT2025C) {
5afaa753 BH	303	/* Wait for the reset triggered by falcon_reset_hw()
5afaa753 BH	304	* to complete */
d2d2c373 BH	305	rc = qt2025c_wait_reset(efx);
	306	if (rc < 0)
	307	goto fail;
5afaa753 BH	308	} else {
	309	/* Reset the PHYXS MMD. This is documented as doing
	310	* a complete soft reset. */
	311	rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
b37b62fe BH	312	QT2022C2_MAX_RESET_TIME /
	313	QT2022C2_RESET_WAIT,
	314	QT2022C2_RESET_WAIT);
5afaa753 BH	315	if (rc < 0)
5afaa753 BH	316	goto fail;
d2d2c373 BH	317	}
d2d2c373 BH	318
8ceee660 BH	319	/* Wait 250ms for the PHY to complete bootup */
	320	msleep(250);
	321
44838a44	322	falcon_board(efx)->type->init_phy(efx);
8ceee660	323
5e2a911c	324	return 0;
8ceee660 BH	325
8ceee660 BH	326	fail:
f794fd44	327	EFX_ERR(efx, "PHY reset timed out\n");
8ceee660 BH	328	return rc;
	329	}
	330
c1c4f453 BH	331	static int qt202x_phy_probe(struct efx_nic *efx)
c1c4f453 BH	332	{
ff3b00a0 SH	333	struct qt202x_phy_data *phy_data;
	334
	335	phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
	336	if (!phy_data)
	337	return -ENOMEM;
	338	efx->phy_data = phy_data;
	339	phy_data->phy_mode = efx->phy_mode;
17d6aeaf MS	340	phy_data->bug17190_in_bad_state = false;
17d6aeaf MS	341	phy_data->bug17190_timer = 0;
ff3b00a0	342
c1c4f453 BH	343	efx->mdio.mmds = QT202X_REQUIRED_DEVS;
	344	efx->mdio.mode_support = MDIO_SUPPORTS_C45 \| MDIO_EMULATE_C22;
	345	efx->loopback_modes = QT202X_LOOPBACKS \| FALCON_XMAC_LOOPBACKS;
	346	return 0;
	347	}
	348
b37b62fe	349	static int qt202x_phy_init(struct efx_nic *efx)
8ceee660	350	{
47c3d19f	351	u32 devid;
8ceee660 BH	352	int rc;
8ceee660 BH	353
47c3d19f SH	354	rc = qt202x_reset_phy(efx);
	355	if (rc) {
	356	EFX_ERR(efx, "PHY init failed\n");
	357	return rc;
	358	}
	359
47c3d19f	360	devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
3f39a5e9	361	EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
68e7f45e BH	362	devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
68e7f45e BH	363	efx_mdio_id_rev(devid));
8ceee660	364
0d83b2f6 MS	365	if (efx->phy_type == PHY_TYPE_QT2025C)
	366	qt2025c_firmware_id(efx);
	367
3273c2e8	368	return 0;
8ceee660 BH	369	}
8ceee660 BH	370
b37b62fe	371	static int qt202x_link_ok(struct efx_nic *efx)
8ceee660	372	{
b37b62fe	373	return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
8ceee660 BH	374	}
8ceee660 BH	375
fdaa9aed	376	static bool qt202x_phy_poll(struct efx_nic *efx)
8ceee660	377	{
fdaa9aed SH	378	bool was_up = efx->link_state.up;
	379
	380	efx->link_state.up = qt202x_link_ok(efx);
	381	efx->link_state.speed = 10000;
	382	efx->link_state.fd = true;
	383	efx->link_state.fc = efx->wanted_fc;
	384
17d6aeaf MS	385	if (efx->phy_type == PHY_TYPE_QT2025C)
	386	qt2025c_bug17190_workaround(efx);
	387
fdaa9aed	388	return efx->link_state.up != was_up;
8ceee660 BH	389	}
8ceee660 BH	390
d3245b28	391	static int qt202x_phy_reconfigure(struct efx_nic *efx)
8ceee660	392	{
b37b62fe	393	struct qt202x_phy_data *phy_data = efx->phy_data;
3273c2e8	394
d2d2c373	395	if (efx->phy_type == PHY_TYPE_QT2025C) {
0d83b2f6 MS	396	int rc = qt2025c_select_phy_mode(efx);
	397	if (rc)
	398	return rc;
	399
d2d2c373 BH	400	/* There are several different register bits which can
	401	* disable TX (and save power) on direct-attach cables
	402	* or optical transceivers, varying somewhat between
	403	* firmware versions. Only 'static mode' appears to
	404	* cover everything. */
68e7f45e BH	405	mdio_set_flag(
	406	&efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
	407	PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
d2d2c373 BH	408	efx->phy_mode & PHY_MODE_TX_DISABLED \|\|
	409	efx->phy_mode & PHY_MODE_LOW_POWER \|\|
	410	efx->loopback_mode == LOOPBACK_PCS \|\|
	411	efx->loopback_mode == LOOPBACK_PMAPMD);
	412	} else {
	413	/* Reset the PHY when moving from tx off to tx on */
	414	if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
	415	(phy_data->phy_mode & PHY_MODE_TX_DISABLED))
b37b62fe	416	qt202x_reset_phy(efx);
d2d2c373	417
68e7f45e	418	efx_mdio_transmit_disable(efx);
d2d2c373	419	}
3273c2e8	420
68e7f45e	421	efx_mdio_phy_reconfigure(efx);
3273c2e8	422
f8b87c17	423	phy_data->phy_mode = efx->phy_mode;
d3245b28 BH	424
d3245b28 BH	425	return 0;
8ceee660 BH	426	}
8ceee660 BH	427
b37b62fe	428	static void qt202x_phy_get_settings(struct efx_nic efx, struct ethtool_cmd ecmd)
68e7f45e BH	429	{
	430	mdio45_ethtool_gset(&efx->mdio, ecmd);
	431	}
8ceee660	432
ff3b00a0	433	static void qt202x_phy_remove(struct efx_nic *efx)
8ceee660	434	{
3273c2e8 BH	435	/* Free the context block */
	436	kfree(efx->phy_data);
	437	efx->phy_data = NULL;
8ceee660 BH	438	}
8ceee660 BH	439
b37b62fe	440	struct efx_phy_operations falcon_qt202x_phy_ops = {
c1c4f453	441	.probe = qt202x_phy_probe,
b37b62fe BH	442	.init = qt202x_phy_init,
	443	.reconfigure = qt202x_phy_reconfigure,
	444	.poll = qt202x_phy_poll,
ff3b00a0 SH	445	.fini = efx_port_dummy_op_void,
ff3b00a0 SH	446	.remove = qt202x_phy_remove,
b37b62fe	447	.get_settings = qt202x_phy_get_settings,
68e7f45e	448	.set_settings = efx_mdio_set_settings,
4f16c073	449	.test_alive = efx_mdio_test_alive,
8ceee660	450	};