projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: use netdev_mc_count and netdev_mc_empty when appropriate
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
ee5f784a 47#include "ixgbe_dcb_82599.h"
1cdd1ec8 48#include "ixgbe_sriov.h"
9a799d71
AK		 49
50char ixgbe_driver_name[] = "ixgbe";
9c8eb720 51static const char ixgbe_driver_string[] =
b4617240 52 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 53
92eb879f 54#define DRV_VERSION "2.0.62-k2"
9c8eb720 55const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 56static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 57
58static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 59 [board_82598] = &ixgbe_82598_info,
e8e26350 60 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 61};
62
63/* ixgbe_pci_tbl - PCI Device ID Table
64 *
65 * Wildcard entries (PCI_ANY_ID) should come last
66 * Last entry must be all 0s
67 *
68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69 * Class, Class Mask, private data (not used) }
70 */
a3aa1884 71static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
73 board_82598 },
9a799d71 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 77 board_82598 },
0befdb3e
JB		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
79 board_82598 },
3845bec0
PWJ		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
81 board_82598 },
9a799d71 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 83 board_82598 },
8d792cd9
JB		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
85 board_82598 },
c4900be0
DS		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
89 board_82598 },
b95f5fcb
JB		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
91 board_82598 },
c4900be0
DS		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
93 board_82598 },
2f21bdd3
DS		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
95 board_82598 },
e8e26350
PW		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
97 board_82599 },
1fcf03e6
PWJ		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
99 board_82599 },
74757d49
DS		 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
101 board_82599 },
e8e26350
PW		 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
103 board_82599 },
38ad1c8e
DS		 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
105 board_82599 },
dbfec662
DS		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
107 board_82599 },
8911184f
PWJ		 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
109 board_82599 },
312eb931
DS		 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
111 board_82599 },
9a799d71
AK		 112
113 /* required last entry */
114 {0, }
115};
116MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
117
5dd2d332 118#ifdef CONFIG_IXGBE_DCA
bd0362dd 119static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 120 void *p);
bd0362dd
JC		 121static struct notifier_block dca_notifier = {
122 .notifier_call = ixgbe_notify_dca,
123 .next = NULL,
124 .priority = 0
125};
126#endif
127
1cdd1ec8
GR		 128#ifdef CONFIG_PCI_IOV
129static unsigned int max_vfs;
130module_param(max_vfs, uint, 0);
131MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
132 "per physical function");
133#endif /* CONFIG_PCI_IOV */
134
9a799d71
AK		 135MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
136MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
137MODULE_LICENSE("GPL");
138MODULE_VERSION(DRV_VERSION);
139
140#define DEFAULT_DEBUG_LEVEL_SHIFT 3
141
1cdd1ec8
GR		 142static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
143{
144 struct ixgbe_hw *hw = &adapter->hw;
145 u32 gcr;
146 u32 gpie;
147 u32 vmdctl;
148
149#ifdef CONFIG_PCI_IOV
150 /* disable iov and allow time for transactions to clear */
151 pci_disable_sriov(adapter->pdev);
152#endif
153
154 /* turn off device IOV mode */
155 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
156 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
157 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
158 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
159 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
160 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
161
162 /* set default pool back to 0 */
163 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
164 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
165 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
166
167 /* take a breather then clean up driver data */
168 msleep(100);
169 if (adapter->vfinfo)
170 kfree(adapter->vfinfo);
171 adapter->vfinfo = NULL;
172
173 adapter->num_vfs = 0;
174 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
175}
176
5eba3699
AV		 177static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
178{
179 u32 ctrl_ext;
180
181 /* Let firmware take over control of h/w */
182 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 184 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 185}
186
187static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
188{
189 u32 ctrl_ext;
190
191 /* Let firmware know the driver has taken over */
192 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 194 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 195}
9a799d71 196
e8e26350
PW		 197/*
198 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
199 * @adapter: pointer to adapter struct
200 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
201 * @queue: queue to map the corresponding interrupt to
202 * @msix_vector: the vector to map to the corresponding queue
203 *
204 */
205static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
206 u8 queue, u8 msix_vector)
9a799d71
AK		 207{
208 u32 ivar, index;
e8e26350
PW		 209 struct ixgbe_hw *hw = &adapter->hw;
210 switch (hw->mac.type) {
211 case ixgbe_mac_82598EB:
212 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
213 if (direction == -1)
214 direction = 0;
215 index = (((direction * 64) + queue) >> 2) & 0x1F;
216 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
217 ivar &= ~(0xFF << (8 * (queue & 0x3)));
218 ivar |= (msix_vector << (8 * (queue & 0x3)));
219 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
220 break;
221 case ixgbe_mac_82599EB:
222 if (direction == -1) {
223 /* other causes */
224 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
225 index = ((queue & 1) * 8);
226 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
227 ivar &= ~(0xFF << index);
228 ivar |= (msix_vector << index);
229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
230 break;
231 } else {
232 /* tx or rx causes */
233 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
234 index = ((16 * (queue & 1)) + (8 * direction));
235 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
236 ivar &= ~(0xFF << index);
237 ivar |= (msix_vector << index);
238 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
239 break;
240 }
241 default:
242 break;
243 }
9a799d71
AK		 244}
245
fe49f04a
AD		 246static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
247 u64 qmask)
248{
249 u32 mask;
250
251 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
252 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
253 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
254 } else {
255 mask = (qmask & 0xFFFFFFFF);
256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
257 mask = (qmask >> 32);
258 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
259 }
260}
261
9a799d71 262static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 263 struct ixgbe_tx_buffer
264 *tx_buffer_info)
9a799d71 265{
e5a43549
AD		 266 if (tx_buffer_info->dma) {
267 if (tx_buffer_info->mapped_as_page)
268 pci_unmap_page(adapter->pdev,
269 tx_buffer_info->dma,
270 tx_buffer_info->length,
271 PCI_DMA_TODEVICE);
272 else
273 pci_unmap_single(adapter->pdev,
274 tx_buffer_info->dma,
275 tx_buffer_info->length,
276 PCI_DMA_TODEVICE);
277 tx_buffer_info->dma = 0;
278 }
9a799d71
AK		 279 if (tx_buffer_info->skb) {
280 dev_kfree_skb_any(tx_buffer_info->skb);
281 tx_buffer_info->skb = NULL;
282 }
44df32c5 283 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 284 /* tx_buffer_info must be completely set up in the transmit path */
285}
286
26f23d82
YZ		 287/**
288 * ixgbe_tx_is_paused - check if the tx ring is paused
289 * @adapter: the ixgbe adapter
290 * @tx_ring: the corresponding tx_ring
291 *
292 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
293 * corresponding TC of this tx_ring when checking TFCS.
294 *
295 * Returns : true if paused
296 */
297static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
298 struct ixgbe_ring *tx_ring)
299{
26f23d82
YZ		 300 u32 txoff = IXGBE_TFCS_TXOFF;
301
302#ifdef CONFIG_IXGBE_DCB
303 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
30b76832 304 int tc;
26f23d82
YZ		 305 int reg_idx = tx_ring->reg_idx;
306 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
307
6837e895
PW		 308 switch (adapter->hw.mac.type) {
309 case ixgbe_mac_82598EB:
26f23d82
YZ		 310 tc = reg_idx >> 2;
311 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 312 break;
313 case ixgbe_mac_82599EB:
26f23d82
YZ		 314 tc = 0;
315 txoff = IXGBE_TFCS_TXOFF;
316 if (dcb_i == 8) {
317 /* TC0, TC1 */
318 tc = reg_idx >> 5;
319 if (tc == 2) /* TC2, TC3 */
320 tc += (reg_idx - 64) >> 4;
321 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
322 tc += 1 + ((reg_idx - 96) >> 3);
323 } else if (dcb_i == 4) {
324 /* TC0, TC1 */
325 tc = reg_idx >> 6;
326 if (tc == 1) {
327 tc += (reg_idx - 64) >> 5;
328 if (tc == 2) /* TC2, TC3 */
329 tc += (reg_idx - 96) >> 4;
330 }
331 }
6837e895
PW		 332 break;
333 default:
334 tc = 0;
26f23d82
YZ		 335 }
336 txoff <<= tc;
337 }
338#endif
339 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
340}
341
9a799d71 342static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 343 struct ixgbe_ring *tx_ring,
344 unsigned int eop)
9a799d71 345{
e01c31a5 346 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 347
9a799d71 348 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 349 * check with the clearing of time_stamp and movement of eop */
9a799d71 350 adapter->detect_tx_hung = false;
44df32c5 351 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 352 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
26f23d82 353 !ixgbe_tx_is_paused(adapter, tx_ring)) {
9a799d71 354 /* detected Tx unit hang */
e01c31a5
JB		 355 union ixgbe_adv_tx_desc *tx_desc;
356 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 357 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 358 " Tx Queue <%d>\n"
359 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 360 " next_to_use <%x>\n"
361 " next_to_clean <%x>\n"
362 "tx_buffer_info[next_to_clean]\n"
363 " time_stamp <%lx>\n"
e01c31a5
JB		 364 " jiffies <%lx>\n",
365 tx_ring->queue_index,
44df32c5
AD		 366 IXGBE_READ_REG(hw, tx_ring->head),
367 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 368 tx_ring->next_to_use, eop,
369 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 370 return true;
371 }
372
373 return false;
374}
375
b4617240
PW		 376#define IXGBE_MAX_TXD_PWR 14
377#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 378
379/* Tx Descriptors needed, worst case */
380#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
381 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
382#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 383 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 384
e01c31a5
JB		 385static void ixgbe_tx_timeout(struct net_device *netdev);
386
9a799d71
AK		 387/**
388 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 389 * @q_vector: structure containing interrupt and ring information
e01c31a5 390 * @tx_ring: tx ring to clean
9a799d71 391 **/
fe49f04a 392static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 393 struct ixgbe_ring *tx_ring)
9a799d71 394{
fe49f04a 395 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 396 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 397 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
398 struct ixgbe_tx_buffer *tx_buffer_info;
399 unsigned int i, eop, count = 0;
e01c31a5 400 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 401
402 i = tx_ring->next_to_clean;
12207e49
PWJ		 403 eop = tx_ring->tx_buffer_info[i].next_to_watch;
404 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
405
406 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 407 (count < tx_ring->work_limit)) {
12207e49
PWJ		 408 bool cleaned = false;
409 for ( ; !cleaned; count++) {
410 struct sk_buff *skb;
9a799d71
AK		 411 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
412 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 413 cleaned = (i == eop);
e01c31a5 414 skb = tx_buffer_info->skb;
9a799d71 415
12207e49 416 if (cleaned && skb) {
e092be60 417 unsigned int segs, bytecount;
3d8fd385 418 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 419
420 /* gso_segs is currently only valid for tcp */
e092be60 421 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 422#ifdef IXGBE_FCOE
423 /* adjust for FCoE Sequence Offload */
424 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
425 && (skb->protocol == htons(ETH_P_FCOE)) &&
426 skb_is_gso(skb)) {
427 hlen = skb_transport_offset(skb) +
428 sizeof(struct fc_frame_header) +
429 sizeof(struct fcoe_crc_eof);
430 segs = DIV_ROUND_UP(skb->len - hlen,
431 skb_shinfo(skb)->gso_size);
432 }
433#endif /* IXGBE_FCOE */
e092be60 434 /* multiply data chunks by size of headers */
3d8fd385 435 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 436 total_packets += segs;
437 total_bytes += bytecount;
e092be60 438 }
e01c31a5 439
9a799d71 440 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 441 tx_buffer_info);
9a799d71 442
12207e49
PWJ		 443 tx_desc->wb.status = 0;
444
9a799d71
AK		 445 i++;
446 if (i == tx_ring->count)
447 i = 0;
e01c31a5 448 }
12207e49
PWJ		 449
450 eop = tx_ring->tx_buffer_info[i].next_to_watch;
451 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
452 }
453
9a799d71
AK		 454 tx_ring->next_to_clean = i;
455
e092be60 456#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 457 if (unlikely(count && netif_carrier_ok(netdev) &&
458 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 459 /* Make sure that anybody stopping the queue after this
460 * sees the new next_to_clean.
461 */
462 smp_mb();
30eba97a
AV		 463 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
464 !test_bit(__IXGBE_DOWN, &adapter->state)) {
465 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 466 ++tx_ring->restart_queue;
30eba97a 467 }
e092be60 468 }
9a799d71 469
e01c31a5
JB		 470 if (adapter->detect_tx_hung) {
471 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
472 /* schedule immediate reset if we believe we hung */
473 DPRINTK(PROBE, INFO,
474 "tx hang %d detected, resetting adapter\n",
475 adapter->tx_timeout_count + 1);
476 ixgbe_tx_timeout(adapter->netdev);
477 }
478 }
9a799d71 479
e01c31a5 480 /* re-arm the interrupt */
fe49f04a
AD		 481 if (count >= tx_ring->work_limit)
482 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 483
e01c31a5
JB		 484 tx_ring->total_bytes += total_bytes;
485 tx_ring->total_packets += total_packets;
e01c31a5 486 tx_ring->stats.packets += total_packets;
12207e49 487 tx_ring->stats.bytes += total_bytes;
9a1a69ad 488 return (count < tx_ring->work_limit);
9a799d71
AK		 489}
490
5dd2d332 491#ifdef CONFIG_IXGBE_DCA
bd0362dd 492static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 493 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 494{
495 u32 rxctrl;
496 int cpu = get_cpu();
4a0b9ca0 497 int q = rx_ring->reg_idx;
bd0362dd 498
3a581073 499 if (rx_ring->cpu != cpu) {
bd0362dd 500 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 501 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
502 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
503 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
504 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
505 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
506 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
507 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
508 }
bd0362dd
JC		 509 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
510 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 511 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
512 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 513 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 515 rx_ring->cpu = cpu;
bd0362dd
JC		 516 }
517 put_cpu();
518}
519
520static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 521 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 522{
523 u32 txctrl;
524 int cpu = get_cpu();
4a0b9ca0 525 int q = tx_ring->reg_idx;
ee5f784a 526 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 527
3a581073 528 if (tx_ring->cpu != cpu) {
e8e26350 529 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 530 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 531 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
532 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 533 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
534 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 535 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 536 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 537 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
538 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 539 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
540 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
541 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 542 }
3a581073 543 tx_ring->cpu = cpu;
bd0362dd
JC		 544 }
545 put_cpu();
546}
547
548static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
549{
550 int i;
551
552 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
553 return;
554
e35ec126
AD		 555 /* always use CB2 mode, difference is masked in the CB driver */
556 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
557
bd0362dd 558 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 559 adapter->tx_ring[i]->cpu = -1;
560 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 561 }
562 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 563 adapter->rx_ring[i]->cpu = -1;
564 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 565 }
566}
567
568static int __ixgbe_notify_dca(struct device *dev, void *data)
569{
570 struct net_device *netdev = dev_get_drvdata(dev);
571 struct ixgbe_adapter *adapter = netdev_priv(netdev);
572 unsigned long event = *(unsigned long *)data;
573
574 switch (event) {
575 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 576 /* if we're already enabled, don't do it again */
577 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
578 break;
652f093f 579 if (dca_add_requester(dev) == 0) {
96b0e0f6 580 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 581 ixgbe_setup_dca(adapter);
582 break;
583 }
584 /* Fall Through since DCA is disabled. */
585 case DCA_PROVIDER_REMOVE:
586 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
587 dca_remove_requester(dev);
588 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
589 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
590 }
591 break;
592 }
593
652f093f 594 return 0;
bd0362dd
JC		 595}
596
5dd2d332 597#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 598/**
599 * ixgbe_receive_skb - Send a completed packet up the stack
600 * @adapter: board private structure
601 * @skb: packet to send up
177db6ff
MC		 602 * @status: hardware indication of status of receive
603 * @rx_ring: rx descriptor ring (for a specific queue) to setup
604 * @rx_desc: rx descriptor
9a799d71 605 **/
78b6f4ce 606static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 607 struct sk_buff *skb, u8 status,
fdaff1ce 608 struct ixgbe_ring *ring,
177db6ff 609 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 610{
78b6f4ce
HX		 611 struct ixgbe_adapter *adapter = q_vector->adapter;
612 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 613 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
614 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 615
fdaff1ce 616 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 617 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 618 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 619 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 620 else
78b6f4ce 621 napi_gro_receive(napi, skb);
177db6ff 622 } else {
8a62babf 623 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 624 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
625 else
626 netif_rx(skb);
9a799d71
AK		 627 }
628}
629
e59bd25d
AV		 630/**
631 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
632 * @adapter: address of board private structure
633 * @status_err: hardware indication of status of receive
634 * @skb: skb currently being received and modified
635 **/
9a799d71 636static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 637 union ixgbe_adv_rx_desc *rx_desc,
638 struct sk_buff *skb)
9a799d71 639{
8bae1b2b
DS		 640 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
641
9a799d71
AK		 642 skb->ip_summed = CHECKSUM_NONE;
643
712744be
JB		 644 /* Rx csum disabled */
645 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 646 return;
e59bd25d
AV		 647
648 /* if IP and error */
649 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
650 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 651 adapter->hw_csum_rx_error++;
652 return;
653 }
e59bd25d
AV		 654
655 if (!(status_err & IXGBE_RXD_STAT_L4CS))
656 return;
657
658 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 659 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
660
661 /*
662 * 82599 errata, UDP frames with a 0 checksum can be marked as
663 * checksum errors.
664 */
665 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
666 (adapter->hw.mac.type == ixgbe_mac_82599EB))
667 return;
668
e59bd25d
AV		 669 adapter->hw_csum_rx_error++;
670 return;
671 }
672
9a799d71 673 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 674 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 675}
676
e8e26350
PW		 677static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
678 struct ixgbe_ring *rx_ring, u32 val)
679{
680 /*
681 * Force memory writes to complete before letting h/w
682 * know there are new descriptors to fetch. (Only
683 * applicable for weak-ordered memory model archs,
684 * such as IA-64).
685 */
686 wmb();
687 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
688}
689
9a799d71
AK		 690/**
691 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
692 * @adapter: address of board private structure
693 **/
694static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 695 struct ixgbe_ring *rx_ring,
696 int cleaned_count)
9a799d71 697{
9a799d71
AK		 698 struct pci_dev *pdev = adapter->pdev;
699 union ixgbe_adv_rx_desc *rx_desc;
3a581073 700 struct ixgbe_rx_buffer *bi;
9a799d71 701 unsigned int i;
9a799d71
AK		 702
703 i = rx_ring->next_to_use;
3a581073 704 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 705
706 while (cleaned_count--) {
707 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
708
762f4c57 709 if (!bi->page_dma &&
6e455b89 710 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 711 if (!bi->page) {
762f4c57
JB		 712 bi->page = alloc_page(GFP_ATOMIC);
713 if (!bi->page) {
714 adapter->alloc_rx_page_failed++;
715 goto no_buffers;
716 }
717 bi->page_offset = 0;
718 } else {
719 /* use a half page if we're re-using */
720 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 721 }
762f4c57
JB		 722
723 bi->page_dma = pci_map_page(pdev, bi->page,
724 bi->page_offset,
725 (PAGE_SIZE / 2),
726 PCI_DMA_FROMDEVICE);
9a799d71
AK		 727 }
728
3a581073 729 if (!bi->skb) {
5ecc3614 730 struct sk_buff *skb;
7ca3bc58
JB		 731 /* netdev_alloc_skb reserves 32 bytes up front!! */
732 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
733 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 734
735 if (!skb) {
736 adapter->alloc_rx_buff_failed++;
737 goto no_buffers;
738 }
739
7ca3bc58
JB		 740 /* advance the data pointer to the next cache line */
741 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
742 - skb->data));
743
3a581073 744 bi->skb = skb;
4f57ca6e
JB		 745 bi->dma = pci_map_single(pdev, skb->data,
746 rx_ring->rx_buf_len,
3a581073 747 PCI_DMA_FROMDEVICE);
9a799d71
AK		 748 }
749 /* Refresh the desc even if buffer_addrs didn't change because
750 * each write-back erases this info. */
6e455b89 751 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 752 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
753 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 754 } else {
3a581073 755 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 756 }
757
758 i++;
759 if (i == rx_ring->count)
760 i = 0;
3a581073 761 bi = &rx_ring->rx_buffer_info[i];
9a799d71 762 }
7c6e0a43 763
9a799d71
AK		 764no_buffers:
765 if (rx_ring->next_to_use != i) {
766 rx_ring->next_to_use = i;
767 if (i-- == 0)
768 i = (rx_ring->count - 1);
769
e8e26350 770 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 771 }
772}
773
7c6e0a43
JB		 774static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
775{
776 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
777}
778
779static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
780{
781 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
782}
783
f8212f97
AD		 784static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
785{
786 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
787 IXGBE_RXDADV_RSCCNT_MASK) >>
788 IXGBE_RXDADV_RSCCNT_SHIFT;
789}
790
791/**
792 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
793 * @skb: pointer to the last skb in the rsc queue
94b982b2 794 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 795 *
796 * This function changes a queue full of hw rsc buffers into a completed
797 * packet. It uses the ->prev pointers to find the first packet and then
798 * turns it into the frag list owner.
799 **/
94b982b2
MC		 800static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
801 u64 *count)
f8212f97
AD		 802{
803 unsigned int frag_list_size = 0;
804
805 while (skb->prev) {
806 struct sk_buff *prev = skb->prev;
807 frag_list_size += skb->len;
808 skb->prev = NULL;
809 skb = prev;
94b982b2 810 *count += 1;
f8212f97
AD		 811 }
812
813 skb_shinfo(skb)->frag_list = skb->next;
814 skb->next = NULL;
815 skb->len += frag_list_size;
816 skb->data_len += frag_list_size;
817 skb->truesize += frag_list_size;
818 return skb;
819}
820
78b6f4ce 821static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 822 struct ixgbe_ring *rx_ring,
823 int *work_done, int work_to_do)
9a799d71 824{
78b6f4ce 825 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 826 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 827 struct pci_dev *pdev = adapter->pdev;
828 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
829 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
830 struct sk_buff *skb;
f8212f97 831 unsigned int i, rsc_count = 0;
7c6e0a43 832 u32 len, staterr;
177db6ff
MC		 833 u16 hdr_info;
834 bool cleaned = false;
9a799d71 835 int cleaned_count = 0;
d2f4fbe2 836 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 837#ifdef IXGBE_FCOE
838 int ddp_bytes = 0;
839#endif /* IXGBE_FCOE */
9a799d71
AK		 840
841 i = rx_ring->next_to_clean;
9a799d71
AK		 842 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
843 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
844 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 845
846 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 847 u32 upper_len = 0;
9a799d71
AK		 848 if (*work_done >= work_to_do)
849 break;
850 (*work_done)++;
851
6e455b89 852 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 853 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
854 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 855 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 856 if (len > IXGBE_RX_HDR_SIZE)
857 len = IXGBE_RX_HDR_SIZE;
858 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 859 } else {
9a799d71 860 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 861 }
9a799d71
AK		 862
863 cleaned = true;
864 skb = rx_buffer_info->skb;
7ca3bc58 865 prefetch(skb->data);
9a799d71
AK		 866 rx_buffer_info->skb = NULL;
867
21fa4e66 868 if (rx_buffer_info->dma) {
9a799d71 869 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 870 rx_ring->rx_buf_len,
b4617240 871 PCI_DMA_FROMDEVICE);
4f57ca6e 872 rx_buffer_info->dma = 0;
9a799d71
AK		 873 skb_put(skb, len);
874 }
875
876 if (upper_len) {
877 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 878 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 879 rx_buffer_info->page_dma = 0;
880 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 881 rx_buffer_info->page,
882 rx_buffer_info->page_offset,
883 upper_len);
884
885 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
886 (page_count(rx_buffer_info->page) != 1))
887 rx_buffer_info->page = NULL;
888 else
889 get_page(rx_buffer_info->page);
9a799d71
AK		 890
891 skb->len += upper_len;
892 skb->data_len += upper_len;
893 skb->truesize += upper_len;
894 }
895
896 i++;
897 if (i == rx_ring->count)
898 i = 0;
9a799d71
AK		 899
900 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
901 prefetch(next_rxd);
9a799d71 902 cleaned_count++;
f8212f97 903
0c19d6af 904 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 905 rsc_count = ixgbe_get_rsc_count(rx_desc);
906
907 if (rsc_count) {
908 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
909 IXGBE_RXDADV_NEXTP_SHIFT;
910 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 911 } else {
912 next_buffer = &rx_ring->rx_buffer_info[i];
913 }
914
9a799d71 915 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 916 if (skb->prev)
94b982b2
MC		 917 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
918 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
919 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
920 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
921 else
922 rx_ring->rsc_count++;
923 rx_ring->rsc_flush++;
924 }
9a799d71
AK		 925 rx_ring->stats.packets++;
926 rx_ring->stats.bytes += skb->len;
927 } else {
6e455b89 928 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 929 rx_buffer_info->skb = next_buffer->skb;
930 rx_buffer_info->dma = next_buffer->dma;
931 next_buffer->skb = skb;
932 next_buffer->dma = 0;
933 } else {
934 skb->next = next_buffer->skb;
935 skb->next->prev = skb;
936 }
7ca3bc58 937 rx_ring->non_eop_descs++;
9a799d71
AK		 938 goto next_desc;
939 }
940
941 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
942 dev_kfree_skb_irq(skb);
943 goto next_desc;
944 }
945
8bae1b2b 946 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 947
948 /* probably a little skewed due to removing CRC */
949 total_rx_bytes += skb->len;
950 total_rx_packets++;
951
74ce8dd2 952 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 953#ifdef IXGBE_FCOE
954 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 955 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
956 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
957 if (!ddp_bytes)
332d4a7d 958 goto next_desc;
3d8fd385 959 }
332d4a7d 960#endif /* IXGBE_FCOE */
fdaff1ce 961 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 962
963next_desc:
964 rx_desc->wb.upper.status_error = 0;
965
966 /* return some buffers to hardware, one at a time is too slow */
967 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
968 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
969 cleaned_count = 0;
970 }
971
972 /* use prefetched values */
973 rx_desc = next_rxd;
f8212f97 974 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 975
976 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 977 }
978
9a799d71
AK		 979 rx_ring->next_to_clean = i;
980 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
981
982 if (cleaned_count)
983 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
984
3d8fd385
YZ		 985#ifdef IXGBE_FCOE
986 /* include DDPed FCoE data */
987 if (ddp_bytes > 0) {
988 unsigned int mss;
989
990 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
991 sizeof(struct fc_frame_header) -
992 sizeof(struct fcoe_crc_eof);
993 if (mss > 512)
994 mss &= ~511;
995 total_rx_bytes += ddp_bytes;
996 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
997 }
998#endif /* IXGBE_FCOE */
999
f494e8fa
AV		 1000 rx_ring->total_packets += total_rx_packets;
1001 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1002 netdev->stats.rx_bytes += total_rx_bytes;
1003 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1004
9a799d71
AK		 1005 return cleaned;
1006}
1007
021230d4 1008static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1009/**
1010 * ixgbe_configure_msix - Configure MSI-X hardware
1011 * @adapter: board private structure
1012 *
1013 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1014 * interrupts.
1015 **/
1016static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1017{
021230d4
AV		 1018 struct ixgbe_q_vector *q_vector;
1019 int i, j, q_vectors, v_idx, r_idx;
1020 u32 mask;
9a799d71 1021
021230d4 1022 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1023
4df10466
JB		 1024 /*
1025 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1026 * corresponding register.
1027 */
1028 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1029 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 1030 /* XXX for_each_bit(...) */
1031 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1032 adapter->num_rx_queues);
021230d4
AV		 1033
1034 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1035 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1036 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1037 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1038 adapter->num_rx_queues,
1039 r_idx + 1);
021230d4
AV		 1040 }
1041 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1042 adapter->num_tx_queues);
021230d4
AV		 1043
1044 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1045 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1046 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1047 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1048 adapter->num_tx_queues,
1049 r_idx + 1);
021230d4
AV		 1050 }
1051
021230d4 1052 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1053 /* tx only */
1054 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1055 else if (q_vector->rxr_count)
f7554a2b
NS		 1056 /* rx or mixed */
1057 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1058
fe49f04a 1059 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1060 }
1061
e8e26350
PW		 1062 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1063 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1064 v_idx);
1065 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1066 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1067 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1068
41fb9248 1069 /* set up to autoclear timer, and the vectors */
021230d4 1070 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1071 if (adapter->num_vfs)
1072 mask &= ~(IXGBE_EIMS_OTHER |
1073 IXGBE_EIMS_MAILBOX |
1074 IXGBE_EIMS_LSC);
1075 else
1076 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1077 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1078}
1079
f494e8fa
AV		 1080enum latency_range {
1081 lowest_latency = 0,
1082 low_latency = 1,
1083 bulk_latency = 2,
1084 latency_invalid = 255
1085};
1086
1087/**
1088 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1089 * @adapter: pointer to adapter
1090 * @eitr: eitr setting (ints per sec) to give last timeslice
1091 * @itr_setting: current throttle rate in ints/second
1092 * @packets: the number of packets during this measurement interval
1093 * @bytes: the number of bytes during this measurement interval
1094 *
1095 * Stores a new ITR value based on packets and byte
1096 * counts during the last interrupt. The advantage of per interrupt
1097 * computation is faster updates and more accurate ITR for the current
1098 * traffic pattern. Constants in this function were computed
1099 * based on theoretical maximum wire speed and thresholds were set based
1100 * on testing data as well as attempting to minimize response time
1101 * while increasing bulk throughput.
1102 * this functionality is controlled by the InterruptThrottleRate module
1103 * parameter (see ixgbe_param.c)
1104 **/
1105static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1106 u32 eitr, u8 itr_setting,
1107 int packets, int bytes)
f494e8fa
AV		 1108{
1109 unsigned int retval = itr_setting;
1110 u32 timepassed_us;
1111 u64 bytes_perint;
1112
1113 if (packets == 0)
1114 goto update_itr_done;
1115
1116
1117 /* simple throttlerate management
1118 * 0-20MB/s lowest (100000 ints/s)
1119 * 20-100MB/s low (20000 ints/s)
1120 * 100-1249MB/s bulk (8000 ints/s)
1121 */
1122 /* what was last interrupt timeslice? */
1123 timepassed_us = 1000000/eitr;
1124 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1125
1126 switch (itr_setting) {
1127 case lowest_latency:
1128 if (bytes_perint > adapter->eitr_low)
1129 retval = low_latency;
1130 break;
1131 case low_latency:
1132 if (bytes_perint > adapter->eitr_high)
1133 retval = bulk_latency;
1134 else if (bytes_perint <= adapter->eitr_low)
1135 retval = lowest_latency;
1136 break;
1137 case bulk_latency:
1138 if (bytes_perint <= adapter->eitr_high)
1139 retval = low_latency;
1140 break;
1141 }
1142
1143update_itr_done:
1144 return retval;
1145}
1146
509ee935
JB		 1147/**
1148 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1149 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1150 *
1151 * This function is made to be called by ethtool and by the driver
1152 * when it needs to update EITR registers at runtime. Hardware
1153 * specific quirks/differences are taken care of here.
1154 */
fe49f04a 1155void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1156{
fe49f04a 1157 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1158 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1159 int v_idx = q_vector->v_idx;
1160 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1161
509ee935
JB		 1162 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1163 /* must write high and low 16 bits to reset counter */
1164 itr_reg |= (itr_reg << 16);
1165 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1166 /*
1167 * set the WDIS bit to not clear the timer bits and cause an
1168 * immediate assertion of the interrupt
1169 */
1170 itr_reg |= IXGBE_EITR_CNT_WDIS;
1171 }
1172 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1173}
1174
f494e8fa
AV		 1175static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1176{
1177 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1178 u32 new_itr;
1179 u8 current_itr, ret_itr;
fe49f04a 1180 int i, r_idx;
f494e8fa
AV		 1181 struct ixgbe_ring *rx_ring, *tx_ring;
1182
1183 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1184 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1185 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1186 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1187 q_vector->tx_itr,
1188 tx_ring->total_packets,
1189 tx_ring->total_bytes);
f494e8fa
AV		 1190 /* if the result for this queue would decrease interrupt
1191 * rate for this vector then use that result */
30efa5a3 1192 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1193 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1194 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1195 r_idx + 1);
f494e8fa
AV		 1196 }
1197
1198 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1199 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1200 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1201 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1202 q_vector->rx_itr,
1203 rx_ring->total_packets,
1204 rx_ring->total_bytes);
f494e8fa
AV		 1205 /* if the result for this queue would decrease interrupt
1206 * rate for this vector then use that result */
30efa5a3 1207 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1208 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1209 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1210 r_idx + 1);
f494e8fa
AV		 1211 }
1212
30efa5a3 1213 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1214
1215 switch (current_itr) {
1216 /* counts and packets in update_itr are dependent on these numbers */
1217 case lowest_latency:
1218 new_itr = 100000;
1219 break;
1220 case low_latency:
1221 new_itr = 20000; /* aka hwitr = ~200 */
1222 break;
1223 case bulk_latency:
1224 default:
1225 new_itr = 8000;
1226 break;
1227 }
1228
1229 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1230 /* do an exponential smoothing */
1231 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1232
1233 /* save the algorithm value here, not the smoothed one */
1234 q_vector->eitr = new_itr;
fe49f04a
AD		 1235
1236 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1237 }
1238
1239 return;
1240}
1241
0befdb3e
JB		 1242static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1243{
1244 struct ixgbe_hw *hw = &adapter->hw;
1245
1246 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1247 (eicr & IXGBE_EICR_GPI_SDP1)) {
1248 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1249 /* write to clear the interrupt */
1250 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1251 }
1252}
cf8280ee 1253
e8e26350
PW		 1254static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1255{
1256 struct ixgbe_hw *hw = &adapter->hw;
1257
1258 if (eicr & IXGBE_EICR_GPI_SDP1) {
1259 /* Clear the interrupt */
1260 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1261 schedule_work(&adapter->multispeed_fiber_task);
1262 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1263 /* Clear the interrupt */
1264 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1265 schedule_work(&adapter->sfp_config_module_task);
1266 } else {
1267 /* Interrupt isn't for us... */
1268 return;
1269 }
1270}
1271
cf8280ee
JB		 1272static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1273{
1274 struct ixgbe_hw *hw = &adapter->hw;
1275
1276 adapter->lsc_int++;
1277 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1278 adapter->link_check_timeout = jiffies;
1279 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1280 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1281 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1282 schedule_work(&adapter->watchdog_task);
1283 }
1284}
1285
9a799d71
AK		 1286static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1287{
1288 struct net_device *netdev = data;
1289 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1290 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1291 u32 eicr;
1292
1293 /*
1294 * Workaround for Silicon errata. Use clear-by-write instead
1295 * of clear-by-read. Reading with EICS will return the
1296 * interrupt causes without clearing, which later be done
1297 * with the write to EICR.
1298 */
1299 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1300 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1301
cf8280ee
JB		 1302 if (eicr & IXGBE_EICR_LSC)
1303 ixgbe_check_lsc(adapter);
d4f80882 1304
1cdd1ec8
GR		 1305 if (eicr & IXGBE_EICR_MAILBOX)
1306 ixgbe_msg_task(adapter);
1307
e8e26350
PW		 1308 if (hw->mac.type == ixgbe_mac_82598EB)
1309 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1310
c4cf55e5 1311 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1312 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1313
1314 /* Handle Flow Director Full threshold interrupt */
1315 if (eicr & IXGBE_EICR_FLOW_DIR) {
1316 int i;
1317 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1318 /* Disable transmits before FDIR Re-initialization */
1319 netif_tx_stop_all_queues(netdev);
1320 for (i = 0; i < adapter->num_tx_queues; i++) {
1321 struct ixgbe_ring *tx_ring =
4a0b9ca0 1322 adapter->tx_ring[i];
c4cf55e5
PWJ		 1323 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1324 &tx_ring->reinit_state))
1325 schedule_work(&adapter->fdir_reinit_task);
1326 }
1327 }
1328 }
d4f80882
AV		 1329 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1330 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1331
1332 return IRQ_HANDLED;
1333}
1334
fe49f04a
AD		 1335static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1336 u64 qmask)
1337{
1338 u32 mask;
1339
1340 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1341 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1342 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1343 } else {
1344 mask = (qmask & 0xFFFFFFFF);
1345 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1346 mask = (qmask >> 32);
1347 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1348 }
1349 /* skip the flush */
1350}
1351
1352static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1353 u64 qmask)
1354{
1355 u32 mask;
1356
1357 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1358 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1359 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1360 } else {
1361 mask = (qmask & 0xFFFFFFFF);
1362 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1363 mask = (qmask >> 32);
1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1365 }
1366 /* skip the flush */
1367}
1368
9a799d71
AK		 1369static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1370{
021230d4
AV		 1371 struct ixgbe_q_vector *q_vector = data;
1372 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1373 struct ixgbe_ring *tx_ring;
021230d4
AV		 1374 int i, r_idx;
1375
1376 if (!q_vector->txr_count)
1377 return IRQ_HANDLED;
1378
1379 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1380 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1381 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1382 tx_ring->total_bytes = 0;
1383 tx_ring->total_packets = 0;
021230d4 1384 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1385 r_idx + 1);
021230d4 1386 }
9a799d71 1387
9b471446 1388 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1389 napi_schedule(&q_vector->napi);
1390
9a799d71
AK		 1391 return IRQ_HANDLED;
1392}
1393
021230d4
AV		 1394/**
1395 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1396 * @irq: unused
1397 * @data: pointer to our q_vector struct for this interrupt vector
1398 **/
9a799d71
AK		 1399static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1400{
021230d4
AV		 1401 struct ixgbe_q_vector *q_vector = data;
1402 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1403 struct ixgbe_ring *rx_ring;
021230d4 1404 int r_idx;
30efa5a3 1405 int i;
021230d4
AV		 1406
1407 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1408 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1409 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1410 rx_ring->total_bytes = 0;
1411 rx_ring->total_packets = 0;
1412 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1413 r_idx + 1);
1414 }
1415
021230d4
AV		 1416 if (!q_vector->rxr_count)
1417 return IRQ_HANDLED;
1418
021230d4 1419 /* disable interrupts on this vector only */
9b471446 1420 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1421 napi_schedule(&q_vector->napi);
021230d4
AV		 1422
1423 return IRQ_HANDLED;
1424}
1425
1426static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1427{
91281fd3
AD		 1428 struct ixgbe_q_vector *q_vector = data;
1429 struct ixgbe_adapter *adapter = q_vector->adapter;
1430 struct ixgbe_ring *ring;
1431 int r_idx;
1432 int i;
1433
1434 if (!q_vector->txr_count && !q_vector->rxr_count)
1435 return IRQ_HANDLED;
1436
1437 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1438 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1439 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1440 ring->total_bytes = 0;
1441 ring->total_packets = 0;
1442 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1443 r_idx + 1);
1444 }
1445
1446 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1447 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1448 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1449 ring->total_bytes = 0;
1450 ring->total_packets = 0;
1451 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1452 r_idx + 1);
1453 }
1454
9b471446 1455 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1456 napi_schedule(&q_vector->napi);
9a799d71 1457
9a799d71
AK		 1458 return IRQ_HANDLED;
1459}
1460
021230d4
AV		 1461/**
1462 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1463 * @napi: napi struct with our devices info in it
1464 * @budget: amount of work driver is allowed to do this pass, in packets
1465 *
f0848276
JB		 1466 * This function is optimized for cleaning one queue only on a single
1467 * q_vector!!!
021230d4 1468 **/
9a799d71
AK		 1469static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1470{
021230d4 1471 struct ixgbe_q_vector *q_vector =
b4617240 1472 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1473 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1474 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1475 int work_done = 0;
021230d4 1476 long r_idx;
9a799d71 1477
021230d4 1478 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1479 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1480#ifdef CONFIG_IXGBE_DCA
bd0362dd 1481 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1482 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1483#endif
9a799d71 1484
78b6f4ce 1485 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1486
021230d4
AV		 1487 /* If all Rx work done, exit the polling mode */
1488 if (work_done < budget) {
288379f0 1489 napi_complete(napi);
f7554a2b 1490 if (adapter->rx_itr_setting & 1)
f494e8fa 1491 ixgbe_set_itr_msix(q_vector);
9a799d71 1492 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1493 ixgbe_irq_enable_queues(adapter,
1494 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1495 }
1496
1497 return work_done;
1498}
1499
f0848276 1500/**
91281fd3 1501 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1502 * @napi: napi struct with our devices info in it
1503 * @budget: amount of work driver is allowed to do this pass, in packets
1504 *
1505 * This function will clean more than one rx queue associated with a
1506 * q_vector.
1507 **/
91281fd3 1508static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1509{
1510 struct ixgbe_q_vector *q_vector =
1511 container_of(napi, struct ixgbe_q_vector, napi);
1512 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1513 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1514 int work_done = 0, i;
1515 long r_idx;
91281fd3
AD		 1516 bool tx_clean_complete = true;
1517
1518 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1519 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1520 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1521#ifdef CONFIG_IXGBE_DCA
1522 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1523 ixgbe_update_tx_dca(adapter, ring);
1524#endif
1525 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1526 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1527 r_idx + 1);
1528 }
f0848276
JB		 1529
1530 /* attempt to distribute budget to each queue fairly, but don't allow
1531 * the budget to go below 1 because we'll exit polling */
1532 budget /= (q_vector->rxr_count ?: 1);
1533 budget = max(budget, 1);
1534 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1535 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1536 ring = adapter->rx_ring[r_idx];
5dd2d332 1537#ifdef CONFIG_IXGBE_DCA
f0848276 1538 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1539 ixgbe_update_rx_dca(adapter, ring);
f0848276 1540#endif
91281fd3 1541 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1542 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1543 r_idx + 1);
1544 }
1545
1546 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1547 ring = adapter->rx_ring[r_idx];
f0848276 1548 /* If all Rx work done, exit the polling mode */
7f821875 1549 if (work_done < budget) {
288379f0 1550 napi_complete(napi);
f7554a2b 1551 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1552 ixgbe_set_itr_msix(q_vector);
1553 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1554 ixgbe_irq_enable_queues(adapter,
1555 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1556 return 0;
1557 }
1558
1559 return work_done;
1560}
91281fd3
AD		 1561
1562/**
1563 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1564 * @napi: napi struct with our devices info in it
1565 * @budget: amount of work driver is allowed to do this pass, in packets
1566 *
1567 * This function is optimized for cleaning one queue only on a single
1568 * q_vector!!!
1569 **/
1570static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1571{
1572 struct ixgbe_q_vector *q_vector =
1573 container_of(napi, struct ixgbe_q_vector, napi);
1574 struct ixgbe_adapter *adapter = q_vector->adapter;
1575 struct ixgbe_ring *tx_ring = NULL;
1576 int work_done = 0;
1577 long r_idx;
1578
1579 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 1580 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1581#ifdef CONFIG_IXGBE_DCA
1582 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1583 ixgbe_update_tx_dca(adapter, tx_ring);
1584#endif
1585
1586 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1587 work_done = budget;
1588
f7554a2b 1589 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1590 if (work_done < budget) {
1591 napi_complete(napi);
f7554a2b 1592 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1593 ixgbe_set_itr_msix(q_vector);
1594 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1595 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1596 }
1597
1598 return work_done;
1599}
1600
021230d4 1601static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1602 int r_idx)
021230d4 1603{
7a921c93
AD		 1604 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1605
1606 set_bit(r_idx, q_vector->rxr_idx);
1607 q_vector->rxr_count++;
021230d4
AV		 1608}
1609
1610static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1611 int t_idx)
021230d4 1612{
7a921c93
AD		 1613 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1614
1615 set_bit(t_idx, q_vector->txr_idx);
1616 q_vector->txr_count++;
021230d4
AV		 1617}
1618
9a799d71 1619/**
021230d4
AV		 1620 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1621 * @adapter: board private structure to initialize
1622 * @vectors: allotted vector count for descriptor rings
9a799d71 1623 *
021230d4
AV		 1624 * This function maps descriptor rings to the queue-specific vectors
1625 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1626 * one vector per ring/queue, but on a constrained vector budget, we
1627 * group the rings as "efficiently" as possible. You would add new
1628 * mapping configurations in here.
9a799d71 1629 **/
021230d4 1630static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1631 int vectors)
021230d4
AV		 1632{
1633 int v_start = 0;
1634 int rxr_idx = 0, txr_idx = 0;
1635 int rxr_remaining = adapter->num_rx_queues;
1636 int txr_remaining = adapter->num_tx_queues;
1637 int i, j;
1638 int rqpv, tqpv;
1639 int err = 0;
1640
1641 /* No mapping required if MSI-X is disabled. */
1642 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1643 goto out;
9a799d71 1644
021230d4
AV		 1645 /*
1646 * The ideal configuration...
1647 * We have enough vectors to map one per queue.
1648 */
1649 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1650 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1651 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1652
021230d4
AV		 1653 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1654 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1655
9a799d71 1656 goto out;
021230d4 1657 }
9a799d71 1658
021230d4
AV		 1659 /*
1660 * If we don't have enough vectors for a 1-to-1
1661 * mapping, we'll have to group them so there are
1662 * multiple queues per vector.
1663 */
1664 /* Re-adjusting *qpv takes care of the remainder. */
1665 for (i = v_start; i < vectors; i++) {
1666 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1667 for (j = 0; j < rqpv; j++) {
1668 map_vector_to_rxq(adapter, i, rxr_idx);
1669 rxr_idx++;
1670 rxr_remaining--;
1671 }
1672 }
1673 for (i = v_start; i < vectors; i++) {
1674 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1675 for (j = 0; j < tqpv; j++) {
1676 map_vector_to_txq(adapter, i, txr_idx);
1677 txr_idx++;
1678 txr_remaining--;
9a799d71 1679 }
9a799d71
AK		 1680 }
1681
021230d4
AV		 1682out:
1683 return err;
1684}
1685
1686/**
1687 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1688 * @adapter: board private structure
1689 *
1690 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1691 * interrupts from the kernel.
1692 **/
1693static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1694{
1695 struct net_device *netdev = adapter->netdev;
1696 irqreturn_t (*handler)(int, void *);
1697 int i, vector, q_vectors, err;
cb13fc20 1698 int ri=0, ti=0;
021230d4
AV		 1699
1700 /* Decrement for Other and TCP Timer vectors */
1701 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1702
1703 /* Map the Tx/Rx rings to the vectors we were allotted. */
1704 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1705 if (err)
1706 goto out;
1707
1708#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1709 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1710 &ixgbe_msix_clean_many)
021230d4 1711 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1712 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1713
1714 if(handler == &ixgbe_msix_clean_rx) {
1715 sprintf(adapter->name[vector], "%s-%s-%d",
1716 netdev->name, "rx", ri++);
1717 }
1718 else if(handler == &ixgbe_msix_clean_tx) {
1719 sprintf(adapter->name[vector], "%s-%s-%d",
1720 netdev->name, "tx", ti++);
1721 }
1722 else
1723 sprintf(adapter->name[vector], "%s-%s-%d",
1724 netdev->name, "TxRx", vector);
1725
021230d4 1726 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1727 handler, 0, adapter->name[vector],
7a921c93 1728 adapter->q_vector[vector]);
9a799d71
AK		 1729 if (err) {
1730 DPRINTK(PROBE, ERR,
b4617240
PW		 1731 "request_irq failed for MSIX interrupt "
1732 "Error: %d\n", err);
021230d4 1733 goto free_queue_irqs;
9a799d71 1734 }
9a799d71
AK		 1735 }
1736
021230d4
AV		 1737 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1738 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1739 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1740 if (err) {
1741 DPRINTK(PROBE, ERR,
1742 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1743 goto free_queue_irqs;
9a799d71
AK		 1744 }
1745
9a799d71
AK		 1746 return 0;
1747
021230d4
AV		 1748free_queue_irqs:
1749 for (i = vector - 1; i >= 0; i--)
1750 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1751 adapter->q_vector[i]);
021230d4
AV		 1752 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1753 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1754 kfree(adapter->msix_entries);
1755 adapter->msix_entries = NULL;
021230d4 1756out:
9a799d71
AK		 1757 return err;
1758}
1759
f494e8fa
AV		 1760static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1761{
7a921c93 1762 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1763 u8 current_itr;
1764 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 1765 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1766 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 1767
30efa5a3 1768 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1769 q_vector->tx_itr,
1770 tx_ring->total_packets,
1771 tx_ring->total_bytes);
30efa5a3 1772 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1773 q_vector->rx_itr,
1774 rx_ring->total_packets,
1775 rx_ring->total_bytes);
f494e8fa 1776
30efa5a3 1777 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1778
1779 switch (current_itr) {
1780 /* counts and packets in update_itr are dependent on these numbers */
1781 case lowest_latency:
1782 new_itr = 100000;
1783 break;
1784 case low_latency:
1785 new_itr = 20000; /* aka hwitr = ~200 */
1786 break;
1787 case bulk_latency:
1788 new_itr = 8000;
1789 break;
1790 default:
1791 break;
1792 }
1793
1794 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1795 /* do an exponential smoothing */
1796 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1797
1798 /* save the algorithm value here, not the smoothed one */
1799 q_vector->eitr = new_itr;
fe49f04a
AD		 1800
1801 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1802 }
1803
1804 return;
1805}
1806
79aefa45
AD		 1807/**
1808 * ixgbe_irq_enable - Enable default interrupt generation settings
1809 * @adapter: board private structure
1810 **/
1811static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1812{
1813 u32 mask;
835462fc
NS		 1814
1815 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1816 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1817 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1818 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1819 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1820 mask |= IXGBE_EIMS_GPI_SDP1;
1821 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 1822 if (adapter->num_vfs)
1823 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 1824 }
c4cf55e5
PWJ		 1825 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1826 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1827 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1828
79aefa45 1829 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1830 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 1831 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 1832
1833 if (adapter->num_vfs > 32) {
1834 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1836 }
79aefa45 1837}
021230d4 1838
9a799d71 1839/**
021230d4 1840 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1841 * @irq: interrupt number
1842 * @data: pointer to a network interface device structure
9a799d71
AK		 1843 **/
1844static irqreturn_t ixgbe_intr(int irq, void *data)
1845{
1846 struct net_device *netdev = data;
1847 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1848 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1849 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1850 u32 eicr;
1851
54037505
DS		 1852 /*
1853 * Workaround for silicon errata. Mask the interrupts
1854 * before the read of EICR.
1855 */
1856 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1857
021230d4
AV		 1858 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1859 * therefore no explict interrupt disable is necessary */
1860 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1861 if (!eicr) {
1862 /* shared interrupt alert!
1863 * make sure interrupts are enabled because the read will
1864 * have disabled interrupts due to EIAM */
1865 ixgbe_irq_enable(adapter);
9a799d71 1866 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1867 }
9a799d71 1868
cf8280ee
JB		 1869 if (eicr & IXGBE_EICR_LSC)
1870 ixgbe_check_lsc(adapter);
021230d4 1871
e8e26350
PW		 1872 if (hw->mac.type == ixgbe_mac_82599EB)
1873 ixgbe_check_sfp_event(adapter, eicr);
1874
0befdb3e
JB		 1875 ixgbe_check_fan_failure(adapter, eicr);
1876
7a921c93 1877 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 1878 adapter->tx_ring[0]->total_packets = 0;
1879 adapter->tx_ring[0]->total_bytes = 0;
1880 adapter->rx_ring[0]->total_packets = 0;
1881 adapter->rx_ring[0]->total_bytes = 0;
021230d4 1882 /* would disable interrupts here but EIAM disabled it */
7a921c93 1883 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1884 }
1885
1886 return IRQ_HANDLED;
1887}
1888
021230d4
AV		 1889static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1890{
1891 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1892
1893 for (i = 0; i < q_vectors; i++) {
7a921c93 1894 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1895 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1896 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1897 q_vector->rxr_count = 0;
1898 q_vector->txr_count = 0;
1899 }
1900}
1901
9a799d71
AK		 1902/**
1903 * ixgbe_request_irq - initialize interrupts
1904 * @adapter: board private structure
1905 *
1906 * Attempts to configure interrupts using the best available
1907 * capabilities of the hardware and kernel.
1908 **/
021230d4 1909static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1910{
1911 struct net_device *netdev = adapter->netdev;
021230d4 1912 int err;
9a799d71 1913
021230d4
AV		 1914 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1915 err = ixgbe_request_msix_irqs(adapter);
1916 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 1917 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 1918 netdev->name, netdev);
021230d4 1919 } else {
a0607fd3 1920 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 1921 netdev->name, netdev);
9a799d71
AK		 1922 }
1923
9a799d71
AK		 1924 if (err)
1925 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1926
9a799d71
AK		 1927 return err;
1928}
1929
1930static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1931{
1932 struct net_device *netdev = adapter->netdev;
1933
1934 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1935 int i, q_vectors;
9a799d71 1936
021230d4
AV		 1937 q_vectors = adapter->num_msix_vectors;
1938
1939 i = q_vectors - 1;
9a799d71 1940 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1941
021230d4
AV		 1942 i--;
1943 for (; i >= 0; i--) {
1944 free_irq(adapter->msix_entries[i].vector,
7a921c93 1945 adapter->q_vector[i]);
021230d4
AV		 1946 }
1947
1948 ixgbe_reset_q_vectors(adapter);
1949 } else {
1950 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1951 }
1952}
1953
22d5a71b
JB		 1954/**
1955 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1956 * @adapter: board private structure
1957 **/
1958static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1959{
835462fc
NS		 1960 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1961 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1962 } else {
1963 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1964 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1965 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 1966 if (adapter->num_vfs > 32)
1967 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 1968 }
1969 IXGBE_WRITE_FLUSH(&adapter->hw);
1970 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1971 int i;
1972 for (i = 0; i < adapter->num_msix_vectors; i++)
1973 synchronize_irq(adapter->msix_entries[i].vector);
1974 } else {
1975 synchronize_irq(adapter->pdev->irq);
1976 }
1977}
1978
9a799d71
AK		 1979/**
1980 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1981 *
1982 **/
1983static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1984{
9a799d71
AK		 1985 struct ixgbe_hw *hw = &adapter->hw;
1986
021230d4 1987 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 1988 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 1989
e8e26350
PW		 1990 ixgbe_set_ivar(adapter, 0, 0, 0);
1991 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1992
1993 map_vector_to_rxq(adapter, 0, 0);
1994 map_vector_to_txq(adapter, 0, 0);
1995
1996 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1997}
1998
1999/**
3a581073 2000 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2001 * @adapter: board private structure
2002 *
2003 * Configure the Tx unit of the MAC after a reset.
2004 **/
2005static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2006{
12207e49 2007 u64 tdba;
9a799d71 2008 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2009 u32 i, j, tdlen, txctrl;
9a799d71
AK		 2010
2011 /* Setup the HW Tx Head and Tail descriptor pointers */
2012 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2013 struct ixgbe_ring *ring = adapter->tx_ring[i];
e01c31a5
JB		 2014 j = ring->reg_idx;
2015 tdba = ring->dma;
2016 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 2017 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 2018 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 2019 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2020 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2021 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2022 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
4a0b9ca0
PW		 2023 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2024 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
84f62d4b
PWJ		 2025 /*
2026 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 2027 * bookkeeping if things aren't delivered in order.
2028 */
84f62d4b
PWJ		 2029 switch (hw->mac.type) {
2030 case ixgbe_mac_82598EB:
2031 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2032 break;
2033 case ixgbe_mac_82599EB:
2034 default:
2035 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2036 break;
2037 }
021230d4 2038 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 2039 switch (hw->mac.type) {
2040 case ixgbe_mac_82598EB:
2041 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2042 break;
2043 case ixgbe_mac_82599EB:
2044 default:
2045 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2046 break;
2047 }
9a799d71 2048 }
ee5f784a 2049
e8e26350 2050 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a 2051 u32 rttdcs;
1cdd1ec8 2052 u32 mask;
ee5f784a
DS		 2053
2054 /* disable the arbiter while setting MTQC */
2055 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2056 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2057 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2058
1cdd1ec8
GR		 2059 /* set transmit pool layout */
2060 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2061 switch (adapter->flags & mask) {
2062
2063 case (IXGBE_FLAG_SRIOV_ENABLED):
2064 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2065 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2066 break;
2067
2068 case (IXGBE_FLAG_DCB_ENABLED):
2069 /* We enable 8 traffic classes, DCB only */
2070 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2071 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2072 break;
2073
2074 default:
ee5f784a 2075 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1cdd1ec8
GR		 2076 break;
2077 }
ee5f784a
DS		 2078
2079 /* re-eable the arbiter */
2080 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2081 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 2082 }
9a799d71
AK		 2083}
2084
e8e26350 2085#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2086
a6616b42
YZ		 2087static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2088 struct ixgbe_ring *rx_ring)
cc41ac7c 2089{
cc41ac7c 2090 u32 srrctl;
a6616b42 2091 int index;
0cefafad 2092 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2093
a6616b42
YZ		 2094 index = rx_ring->reg_idx;
2095 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2096 unsigned long mask;
0cefafad 2097 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2098 index = index & mask;
cc41ac7c 2099 }
cc41ac7c
JB		 2100 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2101
2102 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2103 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2104
afafd5b0
AD		 2105 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2106 IXGBE_SRRCTL_BSIZEHDR_MASK;
2107
6e455b89 2108 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2109#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2110 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2111#else
2112 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2113#endif
cc41ac7c 2114 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2115 } else {
afafd5b0
AD		 2116 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2117 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2118 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2119 }
e8e26350 2120
cc41ac7c
JB		 2121 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2122}
9a799d71 2123
0cefafad
JB		 2124static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2125{
2126 u32 mrqc = 0;
2127 int mask;
2128
2129 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2130 return mrqc;
2131
2132 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2133#ifdef CONFIG_IXGBE_DCB
2134 | IXGBE_FLAG_DCB_ENABLED
2135#endif
1cdd1ec8 2136 | IXGBE_FLAG_SRIOV_ENABLED
0cefafad
JB		 2137 );
2138
2139 switch (mask) {
2140 case (IXGBE_FLAG_RSS_ENABLED):
2141 mrqc = IXGBE_MRQC_RSSEN;
2142 break;
1cdd1ec8
GR		 2143 case (IXGBE_FLAG_SRIOV_ENABLED):
2144 mrqc = IXGBE_MRQC_VMDQEN;
2145 break;
0cefafad
JB		 2146#ifdef CONFIG_IXGBE_DCB
2147 case (IXGBE_FLAG_DCB_ENABLED):
2148 mrqc = IXGBE_MRQC_RT8TCEN;
2149 break;
2150#endif /* CONFIG_IXGBE_DCB */
2151 default:
2152 break;
2153 }
2154
2155 return mrqc;
2156}
2157
bb5a9ad2
NS		 2158/**
2159 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2160 * @adapter: address of board private structure
2161 * @index: index of ring to set
bb5a9ad2 2162 **/
edd2ea55 2163static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2164{
2165 struct ixgbe_ring *rx_ring;
2166 struct ixgbe_hw *hw = &adapter->hw;
2167 int j;
2168 u32 rscctrl;
edd2ea55 2169 int rx_buf_len;
bb5a9ad2 2170
4a0b9ca0 2171 rx_ring = adapter->rx_ring[index];
bb5a9ad2 2172 j = rx_ring->reg_idx;
edd2ea55 2173 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2174 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2175 rscctrl |= IXGBE_RSCCTL_RSCEN;
2176 /*
2177 * we must limit the number of descriptors so that the
2178 * total size of max desc * buf_len is not greater
2179 * than 65535
2180 */
2181 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2182#if (MAX_SKB_FRAGS > 16)
2183 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2184#elif (MAX_SKB_FRAGS > 8)
2185 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2186#elif (MAX_SKB_FRAGS > 4)
2187 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2188#else
2189 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2190#endif
2191 } else {
2192 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2193 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2194 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2195 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2196 else
2197 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2198 }
2199 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2200}
2201
9a799d71 2202/**
3a581073 2203 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2204 * @adapter: board private structure
2205 *
2206 * Configure the Rx unit of the MAC after a reset.
2207 **/
2208static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2209{
2210 u64 rdba;
2211 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2212 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2213 struct net_device *netdev = adapter->netdev;
2214 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2215 int i, j;
9a799d71 2216 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2217 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2218 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2219 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2220 u32 fctrl, hlreg0;
509ee935 2221 u32 reta = 0, mrqc = 0;
cc41ac7c 2222 u32 rdrxctl;
7c6e0a43 2223 int rx_buf_len;
9a799d71
AK		 2224
2225 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2226 /* Do not use packet split if we're in SR-IOV Mode */
2227 if (!adapter->num_vfs)
2228 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2229
2230 /* Set the RX buffer length according to the mode */
2231 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2232 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2233 if (hw->mac.type == ixgbe_mac_82599EB) {
2234 /* PSRTYPE must be initialized in 82599 */
2235 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2236 IXGBE_PSRTYPE_UDPHDR |
2237 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2238 IXGBE_PSRTYPE_IPV6HDR |
2239 IXGBE_PSRTYPE_L2HDR;
1cdd1ec8
GR		 2240 IXGBE_WRITE_REG(hw,
2241 IXGBE_PSRTYPE(adapter->num_vfs),
2242 psrtype);
e8e26350 2243 }
9a799d71 2244 } else {
0c19d6af 2245 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2246 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2247 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2248 else
7c6e0a43 2249 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2250 }
2251
2252 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2253 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2254 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2255 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2257
2258 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2259 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2260 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2261 else
2262 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2263#ifdef IXGBE_FCOE
f34c5c82 2264 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2265 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2266#endif
9a799d71
AK		 2267 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2268
4a0b9ca0 2269 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2270 /* disable receives while setting up the descriptors */
2271 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2272 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2273
0cefafad
JB		 2274 /*
2275 * Setup the HW Rx Head and Tail Descriptor Pointers and
2276 * the Base and Length of the Rx Descriptor Ring
2277 */
9a799d71 2278 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2279 rx_ring = adapter->rx_ring[i];
a6616b42
YZ		 2280 rdba = rx_ring->dma;
2281 j = rx_ring->reg_idx;
284901a9 2282 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2283 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2284 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2285 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2286 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2287 rx_ring->head = IXGBE_RDH(j);
2288 rx_ring->tail = IXGBE_RDT(j);
2289 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2290
6e455b89
YZ		 2291 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2292 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2293 else
2294 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2295
63f39bd1 2296#ifdef IXGBE_FCOE
f34c5c82 2297 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2298 struct ixgbe_ring_feature *f;
2299 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2300 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2301 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2302 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2303 rx_ring->rx_buf_len =
2304 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2305 }
63f39bd1
YZ		 2306 }
2307
2308#endif /* IXGBE_FCOE */
a6616b42 2309 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2310 }
2311
e8e26350
PW		 2312 if (hw->mac.type == ixgbe_mac_82598EB) {
2313 /*
2314 * For VMDq support of different descriptor types or
2315 * buffer sizes through the use of multiple SRRCTL
2316 * registers, RDRXCTL.MVMEN must be set to 1
2317 *
2318 * also, the manual doesn't mention it clearly but DCA hints
2319 * will only use queue 0's tags unless this bit is set. Side
2320 * effects of setting this bit are only that SRRCTL must be
2321 * fully programmed [0..15]
2322 */
2a41ff81
JB		 2323 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2324 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2325 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2326 }
177db6ff 2327
1cdd1ec8
GR		 2328 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2329 u32 vt_reg_bits;
2330 u32 reg_offset, vf_shift;
2331 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2332 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2333 | IXGBE_VT_CTL_REPLEN;
2334 vt_reg_bits |= (adapter->num_vfs <<
2335 IXGBE_VT_CTL_POOL_SHIFT);
2336 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2337 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2338
2339 vf_shift = adapter->num_vfs % 32;
2340 reg_offset = adapter->num_vfs / 32;
2341 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2342 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2343 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2344 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2345 /* Enable only the PF's pool for Tx/Rx */
2346 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2347 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2348 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2349 ixgbe_set_vmolr(hw, adapter->num_vfs);
2350 }
2351
e8e26350 2352 /* Program MRQC for the distribution of queues */
0cefafad 2353 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2354
021230d4 2355 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2356 /* Fill out redirection table */
021230d4
AV		 2357 for (i = 0, j = 0; i < 128; i++, j++) {
2358 if (j == adapter->ring_feature[RING_F_RSS].indices)
2359 j = 0;
2360 /* reta = 4-byte sliding window of
2361 * 0x00..(indices-1)(indices-1)00..etc. */
2362 reta = (reta << 8) | (j * 0x11);
2363 if ((i & 3) == 3)
2364 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2365 }
2366
2367 /* Fill out hash function seeds */
2368 for (i = 0; i < 10; i++)
7c6e0a43 2369 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2370
2a41ff81
JB		 2371 if (hw->mac.type == ixgbe_mac_82598EB)
2372 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2373 /* Perform hash on these packet types */
2a41ff81
JB		 2374 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2375 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2376 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2377 | IXGBE_MRQC_RSS_FIELD_IPV6
2378 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2379 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2380 }
2a41ff81 2381 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2382
1cdd1ec8
GR		 2383 if (adapter->num_vfs) {
2384 u32 reg;
2385
2386 /* Map PF MAC address in RAR Entry 0 to first pool
2387 * following VFs */
2388 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2389
2390 /* Set up VF register offsets for selected VT Mode, i.e.
2391 * 64 VFs for SR-IOV */
2392 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2393 reg |= IXGBE_GCR_EXT_SRIOV;
2394 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2395 }
2396
021230d4
AV		 2397 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2398
2399 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2400 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2401 /* Disable indicating checksum in descriptor, enables
2402 * RSS hash */
9a799d71 2403 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2404 }
021230d4
AV		 2405 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2406 /* Enable IPv4 payload checksum for UDP fragments
2407 * if PCSD is not set */
2408 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2409 }
2410
2411 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2412
2413 if (hw->mac.type == ixgbe_mac_82599EB) {
2414 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2415 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2416 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2417 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2418 }
f8212f97 2419
0c19d6af 2420 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2421 /* Enable 82599 HW-RSC */
bb5a9ad2 2422 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2423 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2424
f8212f97
AD		 2425 /* Disable RSC for ACK packets */
2426 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2427 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2428 }
9a799d71
AK		 2429}
2430
068c89b0
DS		 2431static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2432{
2433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2434 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2435 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2436
2437 /* add VID to filter table */
1ada1b1b 2438 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2439}
2440
2441static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2442{
2443 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2444 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2445 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2446
2447 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2448 ixgbe_irq_disable(adapter);
2449
2450 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2451
2452 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2453 ixgbe_irq_enable(adapter);
2454
2455 /* remove VID from filter table */
1ada1b1b 2456 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2457}
2458
9a799d71 2459static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2460 struct vlan_group *grp)
9a799d71
AK		 2461{
2462 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2463 u32 ctrl;
e8e26350 2464 int i, j;
9a799d71 2465
d4f80882
AV		 2466 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2467 ixgbe_irq_disable(adapter);
9a799d71
AK		 2468 adapter->vlgrp = grp;
2469
2f90b865
AD		 2470 /*
2471 * For a DCB driver, always enable VLAN tag stripping so we can
2472 * still receive traffic from a DCB-enabled host even if we're
2473 * not in DCB mode.
2474 */
2475 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
dc63d377
AD		 2476
2477 /* Disable CFI check */
2478 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2479
2480 /* enable VLAN tag stripping */
e8e26350 2481 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
dc63d377 2482 ctrl |= IXGBE_VLNCTRL_VME;
e8e26350 2483 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
e8e26350 2484 for (i = 0; i < adapter->num_rx_queues; i++) {
dc63d377 2485 u32 ctrl;
4a0b9ca0 2486 j = adapter->rx_ring[i]->reg_idx;
e8e26350
PW		 2487 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2488 ctrl |= IXGBE_RXDCTL_VME;
2489 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2490 }
9a799d71 2491 }
dc63d377
AD		 2492
2493 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2494
e8e26350 2495 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2496
d4f80882
AV		 2497 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2498 ixgbe_irq_enable(adapter);
9a799d71
AK		 2499}
2500
9a799d71
AK		 2501static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2502{
2503 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2504
2505 if (adapter->vlgrp) {
2506 u16 vid;
2507 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2508 if (!vlan_group_get_device(adapter->vlgrp, vid))
2509 continue;
2510 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2511 }
2512 }
2513}
2514
2c5645cf
CL		 2515static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2516{
2517 struct dev_mc_list *mc_ptr;
2518 u8 *addr = *mc_addr_ptr;
2519 *vmdq = 0;
2520
2521 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2522 if (mc_ptr->next)
2523 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2524 else
2525 *mc_addr_ptr = NULL;
2526
2527 return addr;
2528}
2529
9a799d71 2530/**
2c5645cf 2531 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2532 * @netdev: network interface device structure
2533 *
2c5645cf
CL		 2534 * The set_rx_method entry point is called whenever the unicast/multicast
2535 * address list or the network interface flags are updated. This routine is
2536 * responsible for configuring the hardware for proper unicast, multicast and
2537 * promiscuous mode.
9a799d71 2538 **/
7f870475 2539void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2540{
2541 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2542 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2543 u32 fctrl, vlnctrl;
2c5645cf
CL		 2544 u8 *addr_list = NULL;
2545 int addr_count = 0;
9a799d71
AK		 2546
2547 /* Check for Promiscuous and All Multicast modes */
2548
2549 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2550 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2551
2552 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2553 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2554 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2555 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2556 } else {
746b9f02
PM		 2557 if (netdev->flags & IFF_ALLMULTI) {
2558 fctrl |= IXGBE_FCTRL_MPE;
2559 fctrl &= ~IXGBE_FCTRL_UPE;
2560 } else {
2561 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2562 }
3d01625a 2563 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2564 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2565 }
2566
2567 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2568 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2569
2c5645cf 2570 /* reprogram secondary unicast list */
32e7bfc4 2571 hw->mac.ops.update_uc_addr_list(hw, netdev);
9a799d71 2572
2c5645cf 2573 /* reprogram multicast list */
4cd24eaf 2574 addr_count = netdev_mc_count(netdev);
2c5645cf
CL		 2575 if (addr_count)
2576 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2577 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2578 ixgbe_addr_list_itr);
1cdd1ec8
GR		 2579 if (adapter->num_vfs)
2580 ixgbe_restore_vf_multicasts(adapter);
9a799d71
AK		 2581}
2582
021230d4
AV		 2583static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2584{
2585 int q_idx;
2586 struct ixgbe_q_vector *q_vector;
2587 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2588
2589 /* legacy and MSI only use one vector */
2590 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2591 q_vectors = 1;
2592
2593 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2594 struct napi_struct *napi;
7a921c93 2595 q_vector = adapter->q_vector[q_idx];
f0848276 2596 napi = &q_vector->napi;
91281fd3
AD		 2597 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2598 if (!q_vector->rxr_count || !q_vector->txr_count) {
2599 if (q_vector->txr_count == 1)
2600 napi->poll = &ixgbe_clean_txonly;
2601 else if (q_vector->rxr_count == 1)
2602 napi->poll = &ixgbe_clean_rxonly;
2603 }
2604 }
f0848276
JB		 2605
2606 napi_enable(napi);
021230d4
AV		 2607 }
2608}
2609
2610static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2611{
2612 int q_idx;
2613 struct ixgbe_q_vector *q_vector;
2614 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2615
2616 /* legacy and MSI only use one vector */
2617 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2618 q_vectors = 1;
2619
2620 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2621 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2622 napi_disable(&q_vector->napi);
2623 }
2624}
2625
7a6b6f51 2626#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2627/*
2628 * ixgbe_configure_dcb - Configure DCB hardware
2629 * @adapter: ixgbe adapter struct
2630 *
2631 * This is called by the driver on open to configure the DCB hardware.
2632 * This is also called by the gennetlink interface when reconfiguring
2633 * the DCB state.
2634 */
2635static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2636{
2637 struct ixgbe_hw *hw = &adapter->hw;
2638 u32 txdctl, vlnctrl;
2639 int i, j;
2640
2641 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2642 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2643 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2644
2645 /* reconfigure the hardware */
2646 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2647
2648 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2649 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 2650 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2651 /* PThresh workaround for Tx hang with DFP enabled. */
2652 txdctl |= 32;
2653 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2654 }
2655 /* Enable VLAN tag insert/strip */
2656 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2657 if (hw->mac.type == ixgbe_mac_82598EB) {
2658 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2659 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2660 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2661 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2662 vlnctrl |= IXGBE_VLNCTRL_VFE;
2663 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2664 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2665 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2666 j = adapter->rx_ring[i]->reg_idx;
e8e26350
PW		 2667 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2668 vlnctrl |= IXGBE_RXDCTL_VME;
2669 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2670 }
2671 }
2f90b865
AD		 2672 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2673}
2674
2675#endif
9a799d71
AK		 2676static void ixgbe_configure(struct ixgbe_adapter *adapter)
2677{
2678 struct net_device *netdev = adapter->netdev;
c4cf55e5 2679 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2680 int i;
2681
2c5645cf 2682 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2683
2684 ixgbe_restore_vlan(adapter);
7a6b6f51 2685#ifdef CONFIG_IXGBE_DCB
2f90b865 2686 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 2687 if (hw->mac.type == ixgbe_mac_82598EB)
2688 netif_set_gso_max_size(netdev, 32768);
2689 else
2690 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 2691 ixgbe_configure_dcb(adapter);
2692 } else {
2693 netif_set_gso_max_size(netdev, 65536);
2694 }
2695#else
2696 netif_set_gso_max_size(netdev, 65536);
2697#endif
9a799d71 2698
eacd73f7
YZ		 2699#ifdef IXGBE_FCOE
2700 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2701 ixgbe_configure_fcoe(adapter);
2702
2703#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2704 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2705 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 2706 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 2707 adapter->atr_sample_rate;
2708 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2709 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2710 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2711 }
2712
9a799d71
AK		 2713 ixgbe_configure_tx(adapter);
2714 ixgbe_configure_rx(adapter);
2715 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 2716 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
2717 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 2718}
2719
e8e26350
PW		 2720static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2721{
2722 switch (hw->phy.type) {
2723 case ixgbe_phy_sfp_avago:
2724 case ixgbe_phy_sfp_ftl:
2725 case ixgbe_phy_sfp_intel:
2726 case ixgbe_phy_sfp_unknown:
2727 case ixgbe_phy_tw_tyco:
2728 case ixgbe_phy_tw_unknown:
2729 return true;
2730 default:
2731 return false;
2732 }
2733}
2734
0ecc061d 2735/**
e8e26350
PW		 2736 * ixgbe_sfp_link_config - set up SFP+ link
2737 * @adapter: pointer to private adapter struct
2738 **/
2739static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2740{
2741 struct ixgbe_hw *hw = &adapter->hw;
2742
2743 if (hw->phy.multispeed_fiber) {
2744 /*
2745 * In multispeed fiber setups, the device may not have
2746 * had a physical connection when the driver loaded.
2747 * If that's the case, the initial link configuration
2748 * couldn't get the MAC into 10G or 1G mode, so we'll
2749 * never have a link status change interrupt fire.
2750 * We need to try and force an autonegotiation
2751 * session, then bring up link.
2752 */
2753 hw->mac.ops.setup_sfp(hw);
2754 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2755 schedule_work(&adapter->multispeed_fiber_task);
2756 } else {
2757 /*
2758 * Direct Attach Cu and non-multispeed fiber modules
2759 * still need to be configured properly prior to
2760 * attempting link.
2761 */
2762 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2763 schedule_work(&adapter->sfp_config_module_task);
2764 }
2765}
2766
2767/**
2768 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2769 * @hw: pointer to private hardware struct
2770 *
2771 * Returns 0 on success, negative on failure
2772 **/
e8e26350 2773static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2774{
2775 u32 autoneg;
8620a103 2776 bool negotiation, link_up = false;
0ecc061d
PWJ		 2777 u32 ret = IXGBE_ERR_LINK_SETUP;
2778
2779 if (hw->mac.ops.check_link)
2780 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2781
2782 if (ret)
2783 goto link_cfg_out;
2784
2785 if (hw->mac.ops.get_link_capabilities)
8620a103 2786 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2787 if (ret)
2788 goto link_cfg_out;
2789
8620a103
MC		 2790 if (hw->mac.ops.setup_link)
2791 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2792link_cfg_out:
2793 return ret;
2794}
2795
e8e26350
PW		 2796#define IXGBE_MAX_RX_DESC_POLL 10
2797static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2798 int rxr)
2799{
4a0b9ca0 2800 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 2801 int k;
2802
2803 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2804 if (IXGBE_READ_REG(&adapter->hw,
2805 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2806 break;
2807 else
2808 msleep(1);
2809 }
2810 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2811 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2812 "not set within the polling period\n", rxr);
2813 }
4a0b9ca0
PW		 2814 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
2815 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 2816}
2817
9a799d71
AK		 2818static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2819{
2820 struct net_device *netdev = adapter->netdev;
9a799d71 2821 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2822 int i, j = 0;
e8e26350 2823 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2824 int err;
9a799d71 2825 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2826 u32 txdctl, rxdctl, mhadd;
e8e26350 2827 u32 dmatxctl;
021230d4 2828 u32 gpie;
c9205697 2829 u32 ctrl_ext;
9a799d71 2830
5eba3699
AV		 2831 ixgbe_get_hw_control(adapter);
2832
021230d4
AV		 2833 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2834 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2835 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2836 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2837 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2838 } else {
2839 /* MSI only */
021230d4 2840 gpie = 0;
9a799d71 2841 }
1cdd1ec8
GR		 2842 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2843 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2844 gpie |= IXGBE_GPIE_VTMODE_64;
2845 }
021230d4
AV		 2846 /* XXX: to interrupt immediately for EICS writes, enable this */
2847 /* gpie |= IXGBE_GPIE_EIMEN; */
2848 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2849 }
2850
9b471446
JB		 2851 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2852 /*
2853 * use EIAM to auto-mask when MSI-X interrupt is asserted
2854 * this saves a register write for every interrupt
2855 */
2856 switch (hw->mac.type) {
2857 case ixgbe_mac_82598EB:
2858 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2859 break;
2860 default:
2861 case ixgbe_mac_82599EB:
2862 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2863 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2864 break;
2865 }
2866 } else {
021230d4
AV		 2867 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2868 * specifically only auto mask tx and rx interrupts */
2869 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2870 }
9a799d71 2871
0befdb3e
JB		 2872 /* Enable fan failure interrupt if media type is copper */
2873 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2874 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2875 gpie |= IXGBE_SDP1_GPIEN;
2876 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2877 }
2878
e8e26350
PW		 2879 if (hw->mac.type == ixgbe_mac_82599EB) {
2880 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2881 gpie |= IXGBE_SDP1_GPIEN;
2882 gpie |= IXGBE_SDP2_GPIEN;
2883 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2884 }
2885
63f39bd1
YZ		 2886#ifdef IXGBE_FCOE
2887 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2888 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2889 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2890 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2891
2892#endif /* IXGBE_FCOE */
021230d4 2893 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2894 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2895 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2896 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2897
2898 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2899 }
2900
2901 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2902 j = adapter->tx_ring[i]->reg_idx;
021230d4 2903 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2904 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2905 txdctl |= (8 << 16);
e8e26350
PW		 2906 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2907 }
2908
2909 if (hw->mac.type == ixgbe_mac_82599EB) {
2910 /* DMATXCTL.EN must be set after all Tx queue config is done */
2911 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2912 dmatxctl |= IXGBE_DMATXCTL_TE;
2913 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2914 }
2915 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2916 j = adapter->tx_ring[i]->reg_idx;
e8e26350 2917 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2918 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2919 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 2920 if (hw->mac.type == ixgbe_mac_82599EB) {
2921 int wait_loop = 10;
2922 /* poll for Tx Enable ready */
2923 do {
2924 msleep(1);
2925 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2926 } while (--wait_loop &&
2927 !(txdctl & IXGBE_TXDCTL_ENABLE));
2928 if (!wait_loop)
2929 DPRINTK(DRV, ERR, "Could not enable "
2930 "Tx Queue %d\n", j);
2931 }
9a799d71
AK		 2932 }
2933
e8e26350 2934 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 2935 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 2936 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2937 /* enable PTHRESH=32 descriptors (half the internal cache)
2938 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2939 * this also removes a pesky rx_no_buffer_count increment */
2940 rxdctl |= 0x0020;
9a799d71 2941 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2942 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2943 if (hw->mac.type == ixgbe_mac_82599EB)
2944 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2945 }
2946 /* enable all receives */
2947 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2948 if (hw->mac.type == ixgbe_mac_82598EB)
2949 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2950 else
2951 rxdctl |= IXGBE_RXCTRL_RXEN;
2952 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2953
2954 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2955 ixgbe_configure_msix(adapter);
2956 else
2957 ixgbe_configure_msi_and_legacy(adapter);
2958
2959 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2960 ixgbe_napi_enable_all(adapter);
2961
2962 /* clear any pending interrupts, may auto mask */
2963 IXGBE_READ_REG(hw, IXGBE_EICR);
2964
9a799d71
AK		 2965 ixgbe_irq_enable(adapter);
2966
bf069c97
DS		 2967 /*
2968 * If this adapter has a fan, check to see if we had a failure
2969 * before we enabled the interrupt.
2970 */
2971 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2972 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2973 if (esdp & IXGBE_ESDP_SDP1)
2974 DPRINTK(DRV, CRIT,
2975 "Fan has stopped, replace the adapter\n");
2976 }
2977
e8e26350
PW		 2978 /*
2979 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 2980 * arrived before interrupts were enabled but after probe. Such
2981 * devices wouldn't have their type identified yet. We need to
2982 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 2983 * If we're not hot-pluggable SFP+, we just need to configure link
2984 * and bring it up.
2985 */
19343de2
DS		 2986 if (hw->phy.type == ixgbe_phy_unknown) {
2987 err = hw->phy.ops.identify(hw);
2988 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 2989 /*
2990 * Take the device down and schedule the sfp tasklet
2991 * which will unregister_netdev and log it.
2992 */
19343de2 2993 ixgbe_down(adapter);
5da43c1a 2994 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 2995 return err;
2996 }
e8e26350
PW		 2997 }
2998
2999 if (ixgbe_is_sfp(hw)) {
3000 ixgbe_sfp_link_config(adapter);
3001 } else {
3002 err = ixgbe_non_sfp_link_config(hw);
3003 if (err)
3004 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3005 }
0ecc061d 3006
c4cf55e5
PWJ		 3007 for (i = 0; i < adapter->num_tx_queues; i++)
3008 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 3009 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 3010
1da100bb
PWJ		 3011 /* enable transmits */
3012 netif_tx_start_all_queues(netdev);
3013
9a799d71
AK		 3014 /* bring the link up in the watchdog, this could race with our first
3015 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3016 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3017 adapter->link_check_timeout = jiffies;
9a799d71 3018 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3019
3020 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3021 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3022 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3023 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3024
9a799d71
AK		 3025 return 0;
3026}
3027
d4f80882
AV		 3028void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3029{
3030 WARN_ON(in_interrupt());
3031 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3032 msleep(1);
3033 ixgbe_down(adapter);
3034 ixgbe_up(adapter);
3035 clear_bit(__IXGBE_RESETTING, &adapter->state);
3036}
3037
9a799d71
AK		 3038int ixgbe_up(struct ixgbe_adapter *adapter)
3039{
3040 /* hardware has been reset, we need to reload some things */
3041 ixgbe_configure(adapter);
3042
3043 return ixgbe_up_complete(adapter);
3044}
3045
3046void ixgbe_reset(struct ixgbe_adapter *adapter)
3047{
c44ade9e 3048 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3049 int err;
3050
3051 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3052 switch (err) {
3053 case 0:
3054 case IXGBE_ERR_SFP_NOT_PRESENT:
3055 break;
3056 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3057 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3058 break;
794caeb2
PWJ		 3059 case IXGBE_ERR_EEPROM_VERSION:
3060 /* We are running on a pre-production device, log a warning */
3061 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3062 "adapter/LOM. Please be aware there may be issues "
3063 "associated with your hardware. If you are "
3064 "experiencing problems please contact your Intel or "
3065 "hardware representative who provided you with this "
3066 "hardware.\n");
3067 break;
da4dd0f7
PWJ		 3068 default:
3069 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3070 }
9a799d71
AK		 3071
3072 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3073 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3074 IXGBE_RAH_AV);
9a799d71
AK		 3075}
3076
9a799d71
AK		 3077/**
3078 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3079 * @adapter: board private structure
3080 * @rx_ring: ring to free buffers from
3081 **/
3082static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3083 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3084{
3085 struct pci_dev *pdev = adapter->pdev;
3086 unsigned long size;
3087 unsigned int i;
3088
3089 /* Free all the Rx ring sk_buffs */
3090
3091 for (i = 0; i < rx_ring->count; i++) {
3092 struct ixgbe_rx_buffer *rx_buffer_info;
3093
3094 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3095 if (rx_buffer_info->dma) {
3096 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 3097 rx_ring->rx_buf_len,
3098 PCI_DMA_FROMDEVICE);
9a799d71
AK		 3099 rx_buffer_info->dma = 0;
3100 }
3101 if (rx_buffer_info->skb) {
f8212f97 3102 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3103 rx_buffer_info->skb = NULL;
f8212f97
AD		 3104 do {
3105 struct sk_buff *this = skb;
3106 skb = skb->prev;
3107 dev_kfree_skb(this);
3108 } while (skb);
9a799d71
AK		 3109 }
3110 if (!rx_buffer_info->page)
3111 continue;
4f57ca6e
JB		 3112 if (rx_buffer_info->page_dma) {
3113 pci_unmap_page(pdev, rx_buffer_info->page_dma,
3114 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3115 rx_buffer_info->page_dma = 0;
3116 }
9a799d71
AK		 3117 put_page(rx_buffer_info->page);
3118 rx_buffer_info->page = NULL;
762f4c57 3119 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3120 }
3121
3122 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3123 memset(rx_ring->rx_buffer_info, 0, size);
3124
3125 /* Zero out the descriptor ring */
3126 memset(rx_ring->desc, 0, rx_ring->size);
3127
3128 rx_ring->next_to_clean = 0;
3129 rx_ring->next_to_use = 0;
3130
9891ca7c
JB		 3131 if (rx_ring->head)
3132 writel(0, adapter->hw.hw_addr + rx_ring->head);
3133 if (rx_ring->tail)
3134 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3135}
3136
3137/**
3138 * ixgbe_clean_tx_ring - Free Tx Buffers
3139 * @adapter: board private structure
3140 * @tx_ring: ring to be cleaned
3141 **/
3142static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3143 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3144{
3145 struct ixgbe_tx_buffer *tx_buffer_info;
3146 unsigned long size;
3147 unsigned int i;
3148
3149 /* Free all the Tx ring sk_buffs */
3150
3151 for (i = 0; i < tx_ring->count; i++) {
3152 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3153 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3154 }
3155
3156 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3157 memset(tx_ring->tx_buffer_info, 0, size);
3158
3159 /* Zero out the descriptor ring */
3160 memset(tx_ring->desc, 0, tx_ring->size);
3161
3162 tx_ring->next_to_use = 0;
3163 tx_ring->next_to_clean = 0;
3164
9891ca7c
JB		 3165 if (tx_ring->head)
3166 writel(0, adapter->hw.hw_addr + tx_ring->head);
3167 if (tx_ring->tail)
3168 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3169}
3170
3171/**
021230d4 3172 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3173 * @adapter: board private structure
3174 **/
021230d4 3175static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3176{
3177 int i;
3178
021230d4 3179 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3180 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3181}
3182
3183/**
021230d4 3184 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3185 * @adapter: board private structure
3186 **/
021230d4 3187static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3188{
3189 int i;
3190
021230d4 3191 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3192 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3193}
3194
3195void ixgbe_down(struct ixgbe_adapter *adapter)
3196{
3197 struct net_device *netdev = adapter->netdev;
7f821875 3198 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3199 u32 rxctrl;
7f821875
JB		 3200 u32 txdctl;
3201 int i, j;
9a799d71
AK		 3202
3203 /* signal that we are down to the interrupt handler */
3204 set_bit(__IXGBE_DOWN, &adapter->state);
3205
767081ad
GR		 3206 /* disable receive for all VFs and wait one second */
3207 if (adapter->num_vfs) {
3208 for (i = 0 ; i < adapter->num_vfs; i++)
3209 adapter->vfinfo[i].clear_to_send = 0;
3210
3211 /* ping all the active vfs to let them know we are going down */
3212 ixgbe_ping_all_vfs(adapter);
3213 /* Disable all VFTE/VFRE TX/RX */
3214 ixgbe_disable_tx_rx(adapter);
3215 }
3216
9a799d71 3217 /* disable receives */
7f821875
JB		 3218 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3219 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 3220
3221 netif_tx_disable(netdev);
3222
7f821875 3223 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3224 msleep(10);
3225
7f821875
JB		 3226 netif_tx_stop_all_queues(netdev);
3227
9a799d71
AK		 3228 ixgbe_irq_disable(adapter);
3229
021230d4 3230 ixgbe_napi_disable_all(adapter);
7f821875 3231
0a1f87cb
DS		 3232 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3233 del_timer_sync(&adapter->sfp_timer);
9a799d71 3234 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3235 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3236
c4cf55e5
PWJ		 3237 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3238 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3239 cancel_work_sync(&adapter->fdir_reinit_task);
3240
7f821875
JB		 3241 /* disable transmits in the hardware now that interrupts are off */
3242 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3243 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3244 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3245 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3246 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3247 }
88512539
PW		 3248 /* Disable the Tx DMA engine on 82599 */
3249 if (hw->mac.type == ixgbe_mac_82599EB)
3250 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3251 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3252 ~IXGBE_DMATXCTL_TE));
7f821875 3253
9a799d71 3254 netif_carrier_off(netdev);
9a799d71 3255
9a713e7c
PW		 3256 /* clear n-tuple filters that are cached */
3257 ethtool_ntuple_flush(netdev);
3258
6f4a0e45
PL		 3259 if (!pci_channel_offline(adapter->pdev))
3260 ixgbe_reset(adapter);
9a799d71
AK		 3261 ixgbe_clean_all_tx_rings(adapter);
3262 ixgbe_clean_all_rx_rings(adapter);
3263
5dd2d332 3264#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3265 /* since we reset the hardware DCA settings were cleared */
e35ec126 3266 ixgbe_setup_dca(adapter);
96b0e0f6 3267#endif
9a799d71
AK		 3268}
3269
9a799d71 3270/**
021230d4
AV		 3271 * ixgbe_poll - NAPI Rx polling callback
3272 * @napi: structure for representing this polling device
3273 * @budget: how many packets driver is allowed to clean
3274 *
3275 * This function is used for legacy and MSI, NAPI mode
9a799d71 3276 **/
021230d4 3277static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3278{
9a1a69ad
JB		 3279 struct ixgbe_q_vector *q_vector =
3280 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3281 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3282 int tx_clean_complete, work_done = 0;
9a799d71 3283
5dd2d332 3284#ifdef CONFIG_IXGBE_DCA
bd0362dd 3285 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3286 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3287 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3288 }
3289#endif
3290
4a0b9ca0
PW		 3291 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3292 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3293
9a1a69ad 3294 if (!tx_clean_complete)
d2c7ddd6
DM		 3295 work_done = budget;
3296
53e52c72
DM		 3297 /* If budget not fully consumed, exit the polling mode */
3298 if (work_done < budget) {
288379f0 3299 napi_complete(napi);
f7554a2b 3300 if (adapter->rx_itr_setting & 1)
f494e8fa 3301 ixgbe_set_itr(adapter);
d4f80882 3302 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3303 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3304 }
9a799d71
AK		 3305 return work_done;
3306}
3307
3308/**
3309 * ixgbe_tx_timeout - Respond to a Tx Hang
3310 * @netdev: network interface device structure
3311 **/
3312static void ixgbe_tx_timeout(struct net_device *netdev)
3313{
3314 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3315
3316 /* Do the reset outside of interrupt context */
3317 schedule_work(&adapter->reset_task);
3318}
3319
3320static void ixgbe_reset_task(struct work_struct *work)
3321{
3322 struct ixgbe_adapter *adapter;
3323 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3324
2f90b865
AD		 3325 /* If we're already down or resetting, just bail */
3326 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3327 test_bit(__IXGBE_RESETTING, &adapter->state))
3328 return;
3329
9a799d71
AK		 3330 adapter->tx_timeout_count++;
3331
d4f80882 3332 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3333}
3334
bc97114d
PWJ		 3335#ifdef CONFIG_IXGBE_DCB
3336static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3337{
bc97114d 3338 bool ret = false;
0cefafad 3339 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3340
0cefafad
JB		 3341 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3342 return ret;
3343
3344 f->mask = 0x7 << 3;
3345 adapter->num_rx_queues = f->indices;
3346 adapter->num_tx_queues = f->indices;
3347 ret = true;
2f90b865 3348
bc97114d
PWJ		 3349 return ret;
3350}
3351#endif
3352
4df10466
JB		 3353/**
3354 * ixgbe_set_rss_queues: Allocate queues for RSS
3355 * @adapter: board private structure to initialize
3356 *
3357 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3358 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3359 *
3360 **/
bc97114d
PWJ		 3361static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3362{
3363 bool ret = false;
0cefafad 3364 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3365
3366 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3367 f->mask = 0xF;
3368 adapter->num_rx_queues = f->indices;
3369 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3370 ret = true;
3371 } else {
bc97114d 3372 ret = false;
b9804972
JB		 3373 }
3374
bc97114d
PWJ		 3375 return ret;
3376}
3377
c4cf55e5
PWJ		 3378/**
3379 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3380 * @adapter: board private structure to initialize
3381 *
3382 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3383 * to the original CPU that initiated the Tx session. This runs in addition
3384 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3385 * Rx load across CPUs using RSS.
3386 *
3387 **/
3388static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3389{
3390 bool ret = false;
3391 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3392
3393 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3394 f_fdir->mask = 0;
3395
3396 /* Flow Director must have RSS enabled */
3397 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3398 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3399 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3400 adapter->num_tx_queues = f_fdir->indices;
3401 adapter->num_rx_queues = f_fdir->indices;
3402 ret = true;
3403 } else {
3404 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3405 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3406 }
3407 return ret;
3408}
3409
0331a832
YZ		 3410#ifdef IXGBE_FCOE
3411/**
3412 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3413 * @adapter: board private structure to initialize
3414 *
3415 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3416 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3417 * rx queues out of the max number of rx queues, instead, it is used as the
3418 * index of the first rx queue used by FCoE.
3419 *
3420 **/
3421static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3422{
3423 bool ret = false;
3424 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3425
3426 f->indices = min((int)num_online_cpus(), f->indices);
3427 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3428 adapter->num_rx_queues = 1;
3429 adapter->num_tx_queues = 1;
0331a832
YZ		 3430#ifdef CONFIG_IXGBE_DCB
3431 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6 3432 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
0331a832
YZ		 3433 ixgbe_set_dcb_queues(adapter);
3434 }
3435#endif
3436 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8de8b2e6 3437 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
8faa2a78
YZ		 3438 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3439 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3440 ixgbe_set_fdir_queues(adapter);
3441 else
3442 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3443 }
3444 /* adding FCoE rx rings to the end */
3445 f->mask = adapter->num_rx_queues;
3446 adapter->num_rx_queues += f->indices;
8de8b2e6 3447 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3448
3449 ret = true;
3450 }
3451
3452 return ret;
3453}
3454
3455#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3456/**
3457 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3458 * @adapter: board private structure to initialize
3459 *
3460 * IOV doesn't actually use anything, so just NAK the
3461 * request for now and let the other queue routines
3462 * figure out what to do.
3463 */
3464static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3465{
3466 return false;
3467}
3468
4df10466
JB		 3469/*
3470 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3471 * @adapter: board private structure to initialize
3472 *
3473 * This is the top level queue allocation routine. The order here is very
3474 * important, starting with the "most" number of features turned on at once,
3475 * and ending with the smallest set of features. This way large combinations
3476 * can be allocated if they're turned on, and smaller combinations are the
3477 * fallthrough conditions.
3478 *
3479 **/
bc97114d
PWJ		 3480static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3481{
1cdd1ec8
GR		 3482 /* Start with base case */
3483 adapter->num_rx_queues = 1;
3484 adapter->num_tx_queues = 1;
3485 adapter->num_rx_pools = adapter->num_rx_queues;
3486 adapter->num_rx_queues_per_pool = 1;
3487
3488 if (ixgbe_set_sriov_queues(adapter))
3489 return;
3490
0331a832
YZ		 3491#ifdef IXGBE_FCOE
3492 if (ixgbe_set_fcoe_queues(adapter))
3493 goto done;
3494
3495#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3496#ifdef CONFIG_IXGBE_DCB
3497 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3498 goto done;
bc97114d
PWJ		 3499
3500#endif
c4cf55e5
PWJ		 3501 if (ixgbe_set_fdir_queues(adapter))
3502 goto done;
3503
bc97114d 3504 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3505 goto done;
3506
3507 /* fallback to base case */
3508 adapter->num_rx_queues = 1;
3509 adapter->num_tx_queues = 1;
3510
3511done:
3512 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3513 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3514}
3515
021230d4 3516static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3517 int vectors)
021230d4
AV		 3518{
3519 int err, vector_threshold;
3520
3521 /* We'll want at least 3 (vector_threshold):
3522 * 1) TxQ[0] Cleanup
3523 * 2) RxQ[0] Cleanup
3524 * 3) Other (Link Status Change, etc.)
3525 * 4) TCP Timer (optional)
3526 */
3527 vector_threshold = MIN_MSIX_COUNT;
3528
3529 /* The more we get, the more we will assign to Tx/Rx Cleanup
3530 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3531 * Right now, we simply care about how many we'll get; we'll
3532 * set them up later while requesting irq's.
3533 */
3534 while (vectors >= vector_threshold) {
3535 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3536 vectors);
021230d4
AV		 3537 if (!err) /* Success in acquiring all requested vectors. */
3538 break;
3539 else if (err < 0)
3540 vectors = 0; /* Nasty failure, quit now */
3541 else /* err == number of vectors we should try again with */
3542 vectors = err;
3543 }
3544
3545 if (vectors < vector_threshold) {
3546 /* Can't allocate enough MSI-X interrupts? Oh well.
3547 * This just means we'll go with either a single MSI
3548 * vector or fall back to legacy interrupts.
3549 */
3550 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3551 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3552 kfree(adapter->msix_entries);
3553 adapter->msix_entries = NULL;
021230d4
AV		 3554 } else {
3555 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3556 /*
3557 * Adjust for only the vectors we'll use, which is minimum
3558 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3559 * vectors we were allocated.
3560 */
3561 adapter->num_msix_vectors = min(vectors,
3562 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3563 }
3564}
3565
021230d4 3566/**
bc97114d 3567 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3568 * @adapter: board private structure to initialize
3569 *
bc97114d
PWJ		 3570 * Cache the descriptor ring offsets for RSS to the assigned rings.
3571 *
021230d4 3572 **/
bc97114d 3573static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3574{
bc97114d
PWJ		 3575 int i;
3576 bool ret = false;
3577
3578 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3579 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3580 adapter->rx_ring[i]->reg_idx = i;
bc97114d 3581 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3582 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 3583 ret = true;
3584 } else {
3585 ret = false;
3586 }
3587
3588 return ret;
3589}
3590
3591#ifdef CONFIG_IXGBE_DCB
3592/**
3593 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3594 * @adapter: board private structure to initialize
3595 *
3596 * Cache the descriptor ring offsets for DCB to the assigned rings.
3597 *
3598 **/
3599static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3600{
3601 int i;
3602 bool ret = false;
3603 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3604
3605 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3606 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3607 /* the number of queues is assumed to be symmetric */
3608 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 3609 adapter->rx_ring[i]->reg_idx = i << 3;
3610 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 3611 }
bc97114d 3612 ret = true;
e8e26350 3613 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3614 if (dcb_i == 8) {
3615 /*
3616 * Tx TC0 starts at: descriptor queue 0
3617 * Tx TC1 starts at: descriptor queue 32
3618 * Tx TC2 starts at: descriptor queue 64
3619 * Tx TC3 starts at: descriptor queue 80
3620 * Tx TC4 starts at: descriptor queue 96
3621 * Tx TC5 starts at: descriptor queue 104
3622 * Tx TC6 starts at: descriptor queue 112
3623 * Tx TC7 starts at: descriptor queue 120
3624 *
3625 * Rx TC0-TC7 are offset by 16 queues each
3626 */
3627 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 3628 adapter->tx_ring[i]->reg_idx = i << 5;
3629 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3630 }
3631 for ( ; i < 5; i++) {
4a0b9ca0 3632 adapter->tx_ring[i]->reg_idx =
f92ef202 3633 ((i + 2) << 4);
4a0b9ca0 3634 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3635 }
3636 for ( ; i < dcb_i; i++) {
4a0b9ca0 3637 adapter->tx_ring[i]->reg_idx =
f92ef202 3638 ((i + 8) << 3);
4a0b9ca0 3639 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3640 }
3641
3642 ret = true;
3643 } else if (dcb_i == 4) {
3644 /*
3645 * Tx TC0 starts at: descriptor queue 0
3646 * Tx TC1 starts at: descriptor queue 64
3647 * Tx TC2 starts at: descriptor queue 96
3648 * Tx TC3 starts at: descriptor queue 112
3649 *
3650 * Rx TC0-TC3 are offset by 32 queues each
3651 */
4a0b9ca0
PW		 3652 adapter->tx_ring[0]->reg_idx = 0;
3653 adapter->tx_ring[1]->reg_idx = 64;
3654 adapter->tx_ring[2]->reg_idx = 96;
3655 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 3656 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 3657 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 3658
3659 ret = true;
3660 } else {
3661 ret = false;
e8e26350 3662 }
bc97114d
PWJ		 3663 } else {
3664 ret = false;
021230d4 3665 }
bc97114d
PWJ		 3666 } else {
3667 ret = false;
021230d4 3668 }
bc97114d
PWJ		 3669
3670 return ret;
3671}
3672#endif
3673
c4cf55e5
PWJ		 3674/**
3675 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3676 * @adapter: board private structure to initialize
3677 *
3678 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3679 *
3680 **/
3681static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3682{
3683 int i;
3684 bool ret = false;
3685
3686 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3687 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3688 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3689 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3690 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 3691 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3692 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 3693 ret = true;
3694 }
3695
3696 return ret;
3697}
3698
0331a832
YZ		 3699#ifdef IXGBE_FCOE
3700/**
3701 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3702 * @adapter: board private structure to initialize
3703 *
3704 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3705 *
3706 */
3707static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3708{
8de8b2e6 3709 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3710 bool ret = false;
3711 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3712
3713 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3714#ifdef CONFIG_IXGBE_DCB
3715 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3716 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3717
0331a832 3718 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 3719 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 3720 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
3721 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 3722 /*
3723 * In 82599, the number of Tx queues for each traffic
3724 * class for both 8-TC and 4-TC modes are:
3725 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3726 * 8 TCs: 32 32 16 16 8 8 8 8
3727 * 4 TCs: 64 64 32 32
3728 * We have max 8 queues for FCoE, where 8 the is
3729 * FCoE redirection table size. If TC for FCoE is
3730 * less than or equal to TC3, we have enough queues
3731 * to add max of 8 queues for FCoE, so we start FCoE
3732 * tx descriptor from the next one, i.e., reg_idx + 1.
3733 * If TC for FCoE is above TC3, implying 8 TC mode,
3734 * and we need 8 for FCoE, we have to take all queues
3735 * in that traffic class for FCoE.
3736 */
3737 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3738 fcoe_tx_i--;
0331a832
YZ		 3739 }
3740#endif /* CONFIG_IXGBE_DCB */
3741 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3742 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3743 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3744 ixgbe_cache_ring_fdir(adapter);
3745 else
3746 ixgbe_cache_ring_rss(adapter);
3747
8de8b2e6
YZ		 3748 fcoe_rx_i = f->mask;
3749 fcoe_tx_i = f->mask;
3750 }
3751 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 3752 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
3753 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 3754 }
0331a832
YZ		 3755 ret = true;
3756 }
3757 return ret;
3758}
3759
3760#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3761/**
3762 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3763 * @adapter: board private structure to initialize
3764 *
3765 * SR-IOV doesn't use any descriptor rings but changes the default if
3766 * no other mapping is used.
3767 *
3768 */
3769static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3770{
4a0b9ca0
PW		 3771 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
3772 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 3773 if (adapter->num_vfs)
3774 return true;
3775 else
3776 return false;
3777}
3778
bc97114d
PWJ		 3779/**
3780 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3781 * @adapter: board private structure to initialize
3782 *
3783 * Once we know the feature-set enabled for the device, we'll cache
3784 * the register offset the descriptor ring is assigned to.
3785 *
3786 * Note, the order the various feature calls is important. It must start with
3787 * the "most" features enabled at the same time, then trickle down to the
3788 * least amount of features turned on at once.
3789 **/
3790static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3791{
3792 /* start with default case */
4a0b9ca0
PW		 3793 adapter->rx_ring[0]->reg_idx = 0;
3794 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 3795
1cdd1ec8
GR		 3796 if (ixgbe_cache_ring_sriov(adapter))
3797 return;
3798
0331a832
YZ		 3799#ifdef IXGBE_FCOE
3800 if (ixgbe_cache_ring_fcoe(adapter))
3801 return;
3802
3803#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3804#ifdef CONFIG_IXGBE_DCB
3805 if (ixgbe_cache_ring_dcb(adapter))
3806 return;
3807
3808#endif
c4cf55e5
PWJ		 3809 if (ixgbe_cache_ring_fdir(adapter))
3810 return;
3811
bc97114d
PWJ		 3812 if (ixgbe_cache_ring_rss(adapter))
3813 return;
021230d4
AV		 3814}
3815
9a799d71
AK		 3816/**
3817 * ixgbe_alloc_queues - Allocate memory for all rings
3818 * @adapter: board private structure to initialize
3819 *
3820 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3821 * number of queues at compile-time. The polling_netdev array is
3822 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3823 **/
2f90b865 3824static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3825{
3826 int i;
4a0b9ca0 3827 int orig_node = adapter->node;
9a799d71 3828
021230d4 3829 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 3830 struct ixgbe_ring *ring = adapter->tx_ring[i];
3831 if (orig_node == -1) {
3832 int cur_node = next_online_node(adapter->node);
3833 if (cur_node == MAX_NUMNODES)
3834 cur_node = first_online_node;
3835 adapter->node = cur_node;
3836 }
3837 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3838 adapter->node);
3839 if (!ring)
3840 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3841 if (!ring)
3842 goto err_tx_ring_allocation;
3843 ring->count = adapter->tx_ring_count;
3844 ring->queue_index = i;
3845 ring->numa_node = adapter->node;
3846
3847 adapter->tx_ring[i] = ring;
021230d4 3848 }
b9804972 3849
4a0b9ca0
PW		 3850 /* Restore the adapter's original node */
3851 adapter->node = orig_node;
3852
9a799d71 3853 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 3854 struct ixgbe_ring *ring = adapter->rx_ring[i];
3855 if (orig_node == -1) {
3856 int cur_node = next_online_node(adapter->node);
3857 if (cur_node == MAX_NUMNODES)
3858 cur_node = first_online_node;
3859 adapter->node = cur_node;
3860 }
3861 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3862 adapter->node);
3863 if (!ring)
3864 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3865 if (!ring)
3866 goto err_rx_ring_allocation;
3867 ring->count = adapter->rx_ring_count;
3868 ring->queue_index = i;
3869 ring->numa_node = adapter->node;
3870
3871 adapter->rx_ring[i] = ring;
021230d4
AV		 3872 }
3873
4a0b9ca0
PW		 3874 /* Restore the adapter's original node */
3875 adapter->node = orig_node;
3876
021230d4
AV		 3877 ixgbe_cache_ring_register(adapter);
3878
3879 return 0;
3880
3881err_rx_ring_allocation:
4a0b9ca0
PW		 3882 for (i = 0; i < adapter->num_tx_queues; i++)
3883 kfree(adapter->tx_ring[i]);
021230d4
AV		 3884err_tx_ring_allocation:
3885 return -ENOMEM;
3886}
3887
3888/**
3889 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3890 * @adapter: board private structure to initialize
3891 *
3892 * Attempt to configure the interrupts using the best available
3893 * capabilities of the hardware and the kernel.
3894 **/
feea6a57 3895static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3896{
8be0e467 3897 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3898 int err = 0;
3899 int vector, v_budget;
3900
3901 /*
3902 * It's easy to be greedy for MSI-X vectors, but it really
3903 * doesn't do us much good if we have a lot more vectors
3904 * than CPU's. So let's be conservative and only ask for
342bde1b 3905 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 3906 */
3907 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 3908 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 3909
3910 /*
3911 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3912 * hw.mac->max_msix_vectors vectors. With features
3913 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3914 * descriptor queues supported by our device. Thus, we cap it off in
3915 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3916 */
8be0e467 3917 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3918
3919 /* A failure in MSI-X entry allocation isn't fatal, but it does
3920 * mean we disable MSI-X capabilities of the adapter. */
3921 adapter->msix_entries = kcalloc(v_budget,
b4617240 3922 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3923 if (adapter->msix_entries) {
3924 for (vector = 0; vector < v_budget; vector++)
3925 adapter->msix_entries[vector].entry = vector;
021230d4 3926
7a921c93 3927 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3928
7a921c93
AD		 3929 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3930 goto out;
3931 }
021230d4 3932
7a921c93
AD		 3933 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3934 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3935 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3936 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3937 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 3938 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3939 ixgbe_disable_sriov(adapter);
3940
7a921c93 3941 ixgbe_set_num_queues(adapter);
021230d4 3942
021230d4
AV		 3943 err = pci_enable_msi(adapter->pdev);
3944 if (!err) {
3945 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3946 } else {
3947 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3948 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3949 /* reset err */
3950 err = 0;
3951 }
3952
3953out:
021230d4
AV		 3954 return err;
3955}
3956
7a921c93
AD		 3957/**
3958 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3959 * @adapter: board private structure to initialize
3960 *
3961 * We allocate one q_vector per queue interrupt. If allocation fails we
3962 * return -ENOMEM.
3963 **/
3964static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3965{
3966 int q_idx, num_q_vectors;
3967 struct ixgbe_q_vector *q_vector;
3968 int napi_vectors;
3969 int (*poll)(struct napi_struct *, int);
3970
3971 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3972 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3973 napi_vectors = adapter->num_rx_queues;
91281fd3 3974 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3975 } else {
3976 num_q_vectors = 1;
3977 napi_vectors = 1;
3978 poll = &ixgbe_poll;
3979 }
3980
3981 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 3982 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
3983 GFP_KERNEL, adapter->node);
3984 if (!q_vector)
3985 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
3986 GFP_KERNEL);
7a921c93
AD		 3987 if (!q_vector)
3988 goto err_out;
3989 q_vector->adapter = adapter;
f7554a2b
NS		 3990 if (q_vector->txr_count && !q_vector->rxr_count)
3991 q_vector->eitr = adapter->tx_eitr_param;
3992 else
3993 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 3994 q_vector->v_idx = q_idx;
91281fd3 3995 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3996 adapter->q_vector[q_idx] = q_vector;
3997 }
3998
3999 return 0;
4000
4001err_out:
4002 while (q_idx) {
4003 q_idx--;
4004 q_vector = adapter->q_vector[q_idx];
4005 netif_napi_del(&q_vector->napi);
4006 kfree(q_vector);
4007 adapter->q_vector[q_idx] = NULL;
4008 }
4009 return -ENOMEM;
4010}
4011
4012/**
4013 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4014 * @adapter: board private structure to initialize
4015 *
4016 * This function frees the memory allocated to the q_vectors. In addition if
4017 * NAPI is enabled it will delete any references to the NAPI struct prior
4018 * to freeing the q_vector.
4019 **/
4020static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4021{
4022 int q_idx, num_q_vectors;
7a921c93 4023
91281fd3 4024 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4025 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4026 else
7a921c93 4027 num_q_vectors = 1;
7a921c93
AD		 4028
4029 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4030 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4031 adapter->q_vector[q_idx] = NULL;
91281fd3 4032 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4033 kfree(q_vector);
4034 }
4035}
4036
7b25cdba 4037static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4038{
4039 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4040 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4041 pci_disable_msix(adapter->pdev);
4042 kfree(adapter->msix_entries);
4043 adapter->msix_entries = NULL;
4044 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4045 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4046 pci_disable_msi(adapter->pdev);
4047 }
4048 return;
4049}
4050
4051/**
4052 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4053 * @adapter: board private structure to initialize
4054 *
4055 * We determine which interrupt scheme to use based on...
4056 * - Kernel support (MSI, MSI-X)
4057 * - which can be user-defined (via MODULE_PARAM)
4058 * - Hardware queue count (num_*_queues)
4059 * - defined by miscellaneous hardware support/features (RSS, etc.)
4060 **/
2f90b865 4061int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4062{
4063 int err;
4064
4065 /* Number of supported queues */
4066 ixgbe_set_num_queues(adapter);
4067
021230d4
AV		 4068 err = ixgbe_set_interrupt_capability(adapter);
4069 if (err) {
4070 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4071 goto err_set_interrupt;
9a799d71
AK		 4072 }
4073
7a921c93
AD		 4074 err = ixgbe_alloc_q_vectors(adapter);
4075 if (err) {
4076 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4077 "vectors\n");
4078 goto err_alloc_q_vectors;
4079 }
4080
4081 err = ixgbe_alloc_queues(adapter);
4082 if (err) {
4083 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4084 goto err_alloc_queues;
4085 }
4086
021230d4 4087 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 4088 "Tx Queue count = %u\n",
4089 (adapter->num_rx_queues > 1) ? "Enabled" :
4090 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4091
4092 set_bit(__IXGBE_DOWN, &adapter->state);
4093
9a799d71 4094 return 0;
021230d4 4095
7a921c93
AD		 4096err_alloc_queues:
4097 ixgbe_free_q_vectors(adapter);
4098err_alloc_q_vectors:
4099 ixgbe_reset_interrupt_capability(adapter);
021230d4 4100err_set_interrupt:
7a921c93
AD		 4101 return err;
4102}
4103
4104/**
4105 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4106 * @adapter: board private structure to clear interrupt scheme on
4107 *
4108 * We go through and clear interrupt specific resources and reset the structure
4109 * to pre-load conditions
4110 **/
4111void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4112{
4a0b9ca0
PW		 4113 int i;
4114
4115 for (i = 0; i < adapter->num_tx_queues; i++) {
4116 kfree(adapter->tx_ring[i]);
4117 adapter->tx_ring[i] = NULL;
4118 }
4119 for (i = 0; i < adapter->num_rx_queues; i++) {
4120 kfree(adapter->rx_ring[i]);
4121 adapter->rx_ring[i] = NULL;
4122 }
7a921c93
AD		 4123
4124 ixgbe_free_q_vectors(adapter);
4125 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4126}
4127
c4900be0
DS		 4128/**
4129 * ixgbe_sfp_timer - worker thread to find a missing module
4130 * @data: pointer to our adapter struct
4131 **/
4132static void ixgbe_sfp_timer(unsigned long data)
4133{
4134 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4135
4df10466
JB		 4136 /*
4137 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4138 * delays that sfp+ detection requires
4139 */
4140 schedule_work(&adapter->sfp_task);
4141}
4142
4143/**
4144 * ixgbe_sfp_task - worker thread to find a missing module
4145 * @work: pointer to work_struct containing our data
4146 **/
4147static void ixgbe_sfp_task(struct work_struct *work)
4148{
4149 struct ixgbe_adapter *adapter = container_of(work,
4150 struct ixgbe_adapter,
4151 sfp_task);
4152 struct ixgbe_hw *hw = &adapter->hw;
4153
4154 if ((hw->phy.type == ixgbe_phy_nl) &&
4155 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4156 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4157 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4158 goto reschedule;
4159 ret = hw->phy.ops.reset(hw);
4160 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4161 dev_err(&adapter->pdev->dev, "failed to initialize "
4162 "because an unsupported SFP+ module type "
4163 "was detected.\n"
4164 "Reload the driver after installing a "
4165 "supported module.\n");
c4900be0
DS		 4166 unregister_netdev(adapter->netdev);
4167 } else {
4168 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4169 hw->phy.sfp_type);
4170 }
4171 /* don't need this routine any more */
4172 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4173 }
4174 return;
4175reschedule:
4176 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4177 mod_timer(&adapter->sfp_timer,
4178 round_jiffies(jiffies + (2 * HZ)));
4179}
4180
9a799d71
AK		 4181/**
4182 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4183 * @adapter: board private structure to initialize
4184 *
4185 * ixgbe_sw_init initializes the Adapter private data structure.
4186 * Fields are initialized based on PCI device information and
4187 * OS network device settings (MTU size).
4188 **/
4189static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4190{
4191 struct ixgbe_hw *hw = &adapter->hw;
4192 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4193 struct net_device *dev = adapter->netdev;
021230d4 4194 unsigned int rss;
7a6b6f51 4195#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4196 int j;
4197 struct tc_configuration *tc;
4198#endif
021230d4 4199
c44ade9e
JB		 4200 /* PCI config space info */
4201
4202 hw->vendor_id = pdev->vendor;
4203 hw->device_id = pdev->device;
4204 hw->revision_id = pdev->revision;
4205 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4206 hw->subsystem_device_id = pdev->subsystem_device;
4207
021230d4
AV		 4208 /* Set capability flags */
4209 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4210 adapter->ring_feature[RING_F_RSS].indices = rss;
4211 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4212 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4213 if (hw->mac.type == ixgbe_mac_82598EB) {
4214 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4215 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4216 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4217 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4218 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4219 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4220 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9a713e7c
PW		 4221 if (dev->features & NETIF_F_NTUPLE) {
4222 /* Flow Director perfect filter enabled */
4223 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4224 adapter->atr_sample_rate = 0;
4225 spin_lock_init(&adapter->fdir_perfect_lock);
4226 } else {
4227 /* Flow Director hash filters enabled */
4228 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4229 adapter->atr_sample_rate = 20;
4230 }
c4cf55e5
PWJ		 4231 adapter->ring_feature[RING_F_FDIR].indices =
4232 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4233 adapter->fdir_pballoc = 0;
eacd73f7 4234#ifdef IXGBE_FCOE
0d551589
YZ		 4235 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4236 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4237 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4238#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4239 /* Default traffic class to use for FCoE */
4240 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
61a0f421 4241#endif
eacd73f7 4242#endif /* IXGBE_FCOE */
f8212f97 4243 }
2f90b865 4244
7a6b6f51 4245#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4246 /* Configure DCB traffic classes */
4247 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4248 tc = &adapter->dcb_cfg.tc_config[j];
4249 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4250 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4251 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4252 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4253 tc->dcb_pfc = pfc_disabled;
4254 }
4255 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4256 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4257 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4258 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4259 adapter->dcb_cfg.round_robin_enable = false;
4260 adapter->dcb_set_bitmap = 0x00;
4261 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4262 adapter->ring_feature[RING_F_DCB].indices);
4263
4264#endif
9a799d71
AK		 4265
4266 /* default flow control settings */
cd7664f6 4267 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4268 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4269#ifdef CONFIG_DCB
4270 adapter->last_lfc_mode = hw->fc.current_mode;
4271#endif
2b9ade93
JB		 4272 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4273 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4274 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4275 hw->fc.send_xon = true;
71fd570b 4276 hw->fc.disable_fc_autoneg = false;
9a799d71 4277
30efa5a3 4278 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4279 adapter->rx_itr_setting = 1;
4280 adapter->rx_eitr_param = 20000;
4281 adapter->tx_itr_setting = 1;
4282 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4283
4284 /* set defaults for eitr in MegaBytes */
4285 adapter->eitr_low = 10;
4286 adapter->eitr_high = 20;
4287
4288 /* set default ring sizes */
4289 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4290 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4291
9a799d71 4292 /* initialize eeprom parameters */
c44ade9e 4293 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 4294 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4295 return -EIO;
4296 }
4297
021230d4 4298 /* enable rx csum by default */
9a799d71
AK		 4299 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4300
1a6c14a2
JB		 4301 /* get assigned NUMA node */
4302 adapter->node = dev_to_node(&pdev->dev);
4303
9a799d71
AK		 4304 set_bit(__IXGBE_DOWN, &adapter->state);
4305
4306 return 0;
4307}
4308
4309/**
4310 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4311 * @adapter: board private structure
3a581073 4312 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4313 *
4314 * Return 0 on success, negative on failure
4315 **/
4316int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4317 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4318{
4319 struct pci_dev *pdev = adapter->pdev;
4320 int size;
4321
3a581073 4322 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4323 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4324 if (!tx_ring->tx_buffer_info)
4325 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4326 if (!tx_ring->tx_buffer_info)
4327 goto err;
3a581073 4328 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4329
4330 /* round up to nearest 4K */
12207e49 4331 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4332 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4333
3a581073
JB		 4334 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4335 &tx_ring->dma);
e01c31a5
JB		 4336 if (!tx_ring->desc)
4337 goto err;
9a799d71 4338
3a581073
JB		 4339 tx_ring->next_to_use = 0;
4340 tx_ring->next_to_clean = 0;
4341 tx_ring->work_limit = tx_ring->count;
9a799d71 4342 return 0;
e01c31a5
JB		 4343
4344err:
4345 vfree(tx_ring->tx_buffer_info);
4346 tx_ring->tx_buffer_info = NULL;
4347 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4348 "descriptor ring\n");
4349 return -ENOMEM;
9a799d71
AK		 4350}
4351
69888674
AD		 4352/**
4353 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4354 * @adapter: board private structure
4355 *
4356 * If this function returns with an error, then it's possible one or
4357 * more of the rings is populated (while the rest are not). It is the
4358 * callers duty to clean those orphaned rings.
4359 *
4360 * Return 0 on success, negative on failure
4361 **/
4362static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4363{
4364 int i, err = 0;
4365
4366 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4367 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4368 if (!err)
4369 continue;
4370 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4371 break;
4372 }
4373
4374 return err;
4375}
4376
9a799d71
AK		 4377/**
4378 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4379 * @adapter: board private structure
3a581073 4380 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4381 *
4382 * Returns 0 on success, negative on failure
4383 **/
4384int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4385 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4386{
4387 struct pci_dev *pdev = adapter->pdev;
021230d4 4388 int size;
9a799d71 4389
3a581073 4390 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4391 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4392 if (!rx_ring->rx_buffer_info)
4393 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4394 if (!rx_ring->rx_buffer_info) {
9a799d71 4395 DPRINTK(PROBE, ERR,
b4617240 4396 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4397 goto alloc_failed;
9a799d71 4398 }
3a581073 4399 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4400
9a799d71 4401 /* Round up to nearest 4K */
3a581073
JB		 4402 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4403 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4404
3a581073 4405 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 4406
3a581073 4407 if (!rx_ring->desc) {
9a799d71 4408 DPRINTK(PROBE, ERR,
b4617240 4409 "Memory allocation failed for the rx desc ring\n");
3a581073 4410 vfree(rx_ring->rx_buffer_info);
177db6ff 4411 goto alloc_failed;
9a799d71
AK		 4412 }
4413
3a581073
JB		 4414 rx_ring->next_to_clean = 0;
4415 rx_ring->next_to_use = 0;
9a799d71
AK		 4416
4417 return 0;
177db6ff
MC		 4418
4419alloc_failed:
177db6ff 4420 return -ENOMEM;
9a799d71
AK		 4421}
4422
69888674
AD		 4423/**
4424 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4425 * @adapter: board private structure
4426 *
4427 * If this function returns with an error, then it's possible one or
4428 * more of the rings is populated (while the rest are not). It is the
4429 * callers duty to clean those orphaned rings.
4430 *
4431 * Return 0 on success, negative on failure
4432 **/
4433
4434static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4435{
4436 int i, err = 0;
4437
4438 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4439 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 4440 if (!err)
4441 continue;
4442 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4443 break;
4444 }
4445
4446 return err;
4447}
4448
9a799d71
AK		 4449/**
4450 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4451 * @adapter: board private structure
4452 * @tx_ring: Tx descriptor ring for a specific queue
4453 *
4454 * Free all transmit software resources
4455 **/
c431f97e
JB		 4456void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4457 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4458{
4459 struct pci_dev *pdev = adapter->pdev;
4460
4461 ixgbe_clean_tx_ring(adapter, tx_ring);
4462
4463 vfree(tx_ring->tx_buffer_info);
4464 tx_ring->tx_buffer_info = NULL;
4465
4466 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4467
4468 tx_ring->desc = NULL;
4469}
4470
4471/**
4472 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4473 * @adapter: board private structure
4474 *
4475 * Free all transmit software resources
4476 **/
4477static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4478{
4479 int i;
4480
4481 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 4482 if (adapter->tx_ring[i]->desc)
4483 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 4484}
4485
4486/**
b4617240 4487 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4488 * @adapter: board private structure
4489 * @rx_ring: ring to clean the resources from
4490 *
4491 * Free all receive software resources
4492 **/
c431f97e
JB		 4493void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4494 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4495{
4496 struct pci_dev *pdev = adapter->pdev;
4497
4498 ixgbe_clean_rx_ring(adapter, rx_ring);
4499
4500 vfree(rx_ring->rx_buffer_info);
4501 rx_ring->rx_buffer_info = NULL;
4502
4503 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4504
4505 rx_ring->desc = NULL;
4506}
4507
4508/**
4509 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4510 * @adapter: board private structure
4511 *
4512 * Free all receive software resources
4513 **/
4514static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4515{
4516 int i;
4517
4518 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 4519 if (adapter->rx_ring[i]->desc)
4520 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 4521}
4522
9a799d71
AK		 4523/**
4524 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4525 * @netdev: network interface device structure
4526 * @new_mtu: new value for maximum frame size
4527 *
4528 * Returns 0 on success, negative on failure
4529 **/
4530static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4531{
4532 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4533 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4534
42c783c5
JB		 4535 /* MTU < 68 is an error and causes problems on some kernels */
4536 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4537 return -EINVAL;
4538
021230d4 4539 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4540 netdev->mtu, new_mtu);
021230d4 4541 /* must set new MTU before calling down or up */
9a799d71
AK		 4542 netdev->mtu = new_mtu;
4543
d4f80882
AV		 4544 if (netif_running(netdev))
4545 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4546
4547 return 0;
4548}
4549
4550/**
4551 * ixgbe_open - Called when a network interface is made active
4552 * @netdev: network interface device structure
4553 *
4554 * Returns 0 on success, negative value on failure
4555 *
4556 * The open entry point is called when a network interface is made
4557 * active by the system (IFF_UP). At this point all resources needed
4558 * for transmit and receive operations are allocated, the interrupt
4559 * handler is registered with the OS, the watchdog timer is started,
4560 * and the stack is notified that the interface is ready.
4561 **/
4562static int ixgbe_open(struct net_device *netdev)
4563{
4564 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4565 int err;
4bebfaa5
AK		 4566
4567 /* disallow open during test */
4568 if (test_bit(__IXGBE_TESTING, &adapter->state))
4569 return -EBUSY;
9a799d71 4570
54386467
JB		 4571 netif_carrier_off(netdev);
4572
9a799d71
AK		 4573 /* allocate transmit descriptors */
4574 err = ixgbe_setup_all_tx_resources(adapter);
4575 if (err)
4576 goto err_setup_tx;
4577
9a799d71
AK		 4578 /* allocate receive descriptors */
4579 err = ixgbe_setup_all_rx_resources(adapter);
4580 if (err)
4581 goto err_setup_rx;
4582
4583 ixgbe_configure(adapter);
4584
021230d4 4585 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4586 if (err)
4587 goto err_req_irq;
4588
9a799d71
AK		 4589 err = ixgbe_up_complete(adapter);
4590 if (err)
4591 goto err_up;
4592
d55b53ff
JK		 4593 netif_tx_start_all_queues(netdev);
4594
9a799d71
AK		 4595 return 0;
4596
4597err_up:
5eba3699 4598 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4599 ixgbe_free_irq(adapter);
4600err_req_irq:
9a799d71 4601err_setup_rx:
a20a1199 4602 ixgbe_free_all_rx_resources(adapter);
9a799d71 4603err_setup_tx:
a20a1199 4604 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4605 ixgbe_reset(adapter);
4606
4607 return err;
4608}
4609
4610/**
4611 * ixgbe_close - Disables a network interface
4612 * @netdev: network interface device structure
4613 *
4614 * Returns 0, this is not allowed to fail
4615 *
4616 * The close entry point is called when an interface is de-activated
4617 * by the OS. The hardware is still under the drivers control, but
4618 * needs to be disabled. A global MAC reset is issued to stop the
4619 * hardware, and all transmit and receive resources are freed.
4620 **/
4621static int ixgbe_close(struct net_device *netdev)
4622{
4623 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4624
4625 ixgbe_down(adapter);
4626 ixgbe_free_irq(adapter);
4627
4628 ixgbe_free_all_tx_resources(adapter);
4629 ixgbe_free_all_rx_resources(adapter);
4630
5eba3699 4631 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4632
4633 return 0;
4634}
4635
b3c8b4ba
AD		 4636#ifdef CONFIG_PM
4637static int ixgbe_resume(struct pci_dev *pdev)
4638{
4639 struct net_device *netdev = pci_get_drvdata(pdev);
4640 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4641 u32 err;
4642
4643 pci_set_power_state(pdev, PCI_D0);
4644 pci_restore_state(pdev);
656ab817
DS		 4645 /*
4646 * pci_restore_state clears dev->state_saved so call
4647 * pci_save_state to restore it.
4648 */
4649 pci_save_state(pdev);
9ce77666 4650
4651 err = pci_enable_device_mem(pdev);
b3c8b4ba 4652 if (err) {
69888674 4653 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4654 "suspend\n");
4655 return err;
4656 }
4657 pci_set_master(pdev);
4658
dd4d8ca6 4659 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4660
4661 err = ixgbe_init_interrupt_scheme(adapter);
4662 if (err) {
4663 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4664 "device\n");
4665 return err;
4666 }
4667
b3c8b4ba
AD		 4668 ixgbe_reset(adapter);
4669
495dce12
WJP		 4670 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4671
b3c8b4ba
AD		 4672 if (netif_running(netdev)) {
4673 err = ixgbe_open(adapter->netdev);
4674 if (err)
4675 return err;
4676 }
4677
4678 netif_device_attach(netdev);
4679
4680 return 0;
4681}
b3c8b4ba 4682#endif /* CONFIG_PM */
9d8d05ae
RW		 4683
4684static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4685{
4686 struct net_device *netdev = pci_get_drvdata(pdev);
4687 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4688 struct ixgbe_hw *hw = &adapter->hw;
4689 u32 ctrl, fctrl;
4690 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4691#ifdef CONFIG_PM
4692 int retval = 0;
4693#endif
4694
4695 netif_device_detach(netdev);
4696
4697 if (netif_running(netdev)) {
4698 ixgbe_down(adapter);
4699 ixgbe_free_irq(adapter);
4700 ixgbe_free_all_tx_resources(adapter);
4701 ixgbe_free_all_rx_resources(adapter);
4702 }
7a921c93 4703 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4704
4705#ifdef CONFIG_PM
4706 retval = pci_save_state(pdev);
4707 if (retval)
4708 return retval;
4df10466 4709
b3c8b4ba 4710#endif
e8e26350
PW		 4711 if (wufc) {
4712 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4713
e8e26350
PW		 4714 /* turn on all-multi mode if wake on multicast is enabled */
4715 if (wufc & IXGBE_WUFC_MC) {
4716 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4717 fctrl |= IXGBE_FCTRL_MPE;
4718 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4719 }
4720
4721 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4722 ctrl |= IXGBE_CTRL_GIO_DIS;
4723 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4724
4725 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4726 } else {
4727 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4728 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4729 }
4730
dd4d8ca6
DS		 4731 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4732 pci_wake_from_d3(pdev, true);
4733 else
4734 pci_wake_from_d3(pdev, false);
b3c8b4ba 4735
9d8d05ae
RW		 4736 *enable_wake = !!wufc;
4737
b3c8b4ba
AD		 4738 ixgbe_release_hw_control(adapter);
4739
4740 pci_disable_device(pdev);
4741
9d8d05ae
RW		 4742 return 0;
4743}
4744
4745#ifdef CONFIG_PM
4746static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4747{
4748 int retval;
4749 bool wake;
4750
4751 retval = __ixgbe_shutdown(pdev, &wake);
4752 if (retval)
4753 return retval;
4754
4755 if (wake) {
4756 pci_prepare_to_sleep(pdev);
4757 } else {
4758 pci_wake_from_d3(pdev, false);
4759 pci_set_power_state(pdev, PCI_D3hot);
4760 }
b3c8b4ba
AD		 4761
4762 return 0;
4763}
9d8d05ae 4764#endif /* CONFIG_PM */
b3c8b4ba
AD		 4765
4766static void ixgbe_shutdown(struct pci_dev *pdev)
4767{
9d8d05ae
RW		 4768 bool wake;
4769
4770 __ixgbe_shutdown(pdev, &wake);
4771
4772 if (system_state == SYSTEM_POWER_OFF) {
4773 pci_wake_from_d3(pdev, wake);
4774 pci_set_power_state(pdev, PCI_D3hot);
4775 }
b3c8b4ba
AD		 4776}
4777
9a799d71
AK		 4778/**
4779 * ixgbe_update_stats - Update the board statistics counters.
4780 * @adapter: board private structure
4781 **/
4782void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4783{
2d86f139 4784 struct net_device *netdev = adapter->netdev;
9a799d71 4785 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4786 u64 total_mpc = 0;
4787 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 4788 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 4789
94b982b2 4790 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 4791 u64 rsc_count = 0;
94b982b2 4792 u64 rsc_flush = 0;
d51019a4
PW		 4793 for (i = 0; i < 16; i++)
4794 adapter->hw_rx_no_dma_resources +=
4795 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 4796 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4797 rsc_count += adapter->rx_ring[i]->rsc_count;
4798 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 4799 }
4800 adapter->rsc_total_count = rsc_count;
4801 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 4802 }
4803
7ca3bc58
JB		 4804 /* gather some stats to the adapter struct that are per queue */
4805 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4806 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 4807 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 4808
4809 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4810 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 4811 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 4812
9a799d71 4813 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4814 for (i = 0; i < 8; i++) {
4815 /* for packet buffers not used, the register should read 0 */
4816 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4817 missed_rx += mpc;
4818 adapter->stats.mpc[i] += mpc;
4819 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4820 if (hw->mac.type == ixgbe_mac_82598EB)
4821 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4822 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4823 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4824 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4825 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4826 if (hw->mac.type == ixgbe_mac_82599EB) {
4827 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4828 IXGBE_PXONRXCNT(i));
4829 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4830 IXGBE_PXOFFRXCNT(i));
4831 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4832 } else {
4833 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4834 IXGBE_PXONRXC(i));
4835 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4836 IXGBE_PXOFFRXC(i));
4837 }
2f90b865
AD		 4838 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4839 IXGBE_PXONTXC(i));
2f90b865 4840 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4841 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4842 }
4843 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4844 /* work around hardware counting issue */
4845 adapter->stats.gprc -= missed_rx;
4846
4847 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 4848 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 4849 u64 tmp;
e8e26350 4850 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 4851 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4852 adapter->stats.gorc += (tmp << 32);
e8e26350 4853 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 4854 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4855 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 4856 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4857 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4858 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4859 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4860 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4861 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4862#ifdef IXGBE_FCOE
4863 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4864 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4865 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4866 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4867 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4868 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4869#endif /* IXGBE_FCOE */
e8e26350
PW		 4870 } else {
4871 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4872 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4873 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4874 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4875 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4876 }
9a799d71
AK		 4877 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4878 adapter->stats.bprc += bprc;
4879 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4880 if (hw->mac.type == ixgbe_mac_82598EB)
4881 adapter->stats.mprc -= bprc;
9a799d71
AK		 4882 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4883 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4884 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4885 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4886 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4887 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4888 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4889 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4890 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4891 adapter->stats.lxontxc += lxon;
4892 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4893 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4894 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4895 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4896 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4897 /*
4898 * 82598 errata - tx of flow control packets is included in tx counters
4899 */
4900 xon_off_tot = lxon + lxoff;
4901 adapter->stats.gptc -= xon_off_tot;
4902 adapter->stats.mptc -= xon_off_tot;
4903 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4904 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4905 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4906 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4907 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4908 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4909 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4910 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4911 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4912 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4913 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4914 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4915 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4916
4917 /* Fill out the OS statistics structure */
2d86f139 4918 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 4919
4920 /* Rx Errors */
2d86f139 4921 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 4922 adapter->stats.rlec;
2d86f139
AK		 4923 netdev->stats.rx_dropped = 0;
4924 netdev->stats.rx_length_errors = adapter->stats.rlec;
4925 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4926 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4927}
4928
4929/**
4930 * ixgbe_watchdog - Timer Call-back
4931 * @data: pointer to adapter cast into an unsigned long
4932 **/
4933static void ixgbe_watchdog(unsigned long data)
4934{
4935 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4936 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4937 u64 eics = 0;
4938 int i;
cf8280ee 4939
fe49f04a
AD		 4940 /*
4941 * Do the watchdog outside of interrupt context due to the lovely
4942 * delays that some of the newer hardware requires
4943 */
22d5a71b 4944
fe49f04a
AD		 4945 if (test_bit(__IXGBE_DOWN, &adapter->state))
4946 goto watchdog_short_circuit;
22d5a71b 4947
fe49f04a
AD		 4948 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4949 /*
4950 * for legacy and MSI interrupts don't set any bits
4951 * that are enabled for EIAM, because this operation
4952 * would set *both* EIMS and EICS for any bit in EIAM
4953 */
4954 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4955 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4956 goto watchdog_reschedule;
4957 }
4958
4959 /* get one bit for every active tx/rx interrupt vector */
4960 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4961 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4962 if (qv->rxr_count || qv->txr_count)
4963 eics |= ((u64)1 << i);
cf8280ee 4964 }
9a799d71 4965
fe49f04a
AD		 4966 /* Cause software interrupt to ensure rx rings are cleaned */
4967 ixgbe_irq_rearm_queues(adapter, eics);
4968
4969watchdog_reschedule:
4970 /* Reset the timer */
4971 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4972
4973watchdog_short_circuit:
cf8280ee
JB		 4974 schedule_work(&adapter->watchdog_task);
4975}
4976
e8e26350
PW		 4977/**
4978 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4979 * @work: pointer to work_struct containing our data
4980 **/
4981static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4982{
4983 struct ixgbe_adapter *adapter = container_of(work,
4984 struct ixgbe_adapter,
4985 multispeed_fiber_task);
4986 struct ixgbe_hw *hw = &adapter->hw;
4987 u32 autoneg;
8620a103 4988 bool negotiation;
e8e26350
PW		 4989
4990 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 4991 autoneg = hw->phy.autoneg_advertised;
4992 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103
MC		 4993 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4994 if (hw->mac.ops.setup_link)
4995 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 4996 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4997 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4998}
4999
5000/**
5001 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5002 * @work: pointer to work_struct containing our data
5003 **/
5004static void ixgbe_sfp_config_module_task(struct work_struct *work)
5005{
5006 struct ixgbe_adapter *adapter = container_of(work,
5007 struct ixgbe_adapter,
5008 sfp_config_module_task);
5009 struct ixgbe_hw *hw = &adapter->hw;
5010 u32 err;
5011
5012 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5013
5014 /* Time for electrical oscillations to settle down */
5015 msleep(100);
e8e26350 5016 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5017
e8e26350 5018 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5019 dev_err(&adapter->pdev->dev, "failed to initialize because "
5020 "an unsupported SFP+ module type was detected.\n"
5021 "Reload the driver after installing a supported "
5022 "module.\n");
63d6e1d8 5023 unregister_netdev(adapter->netdev);
e8e26350
PW		 5024 return;
5025 }
5026 hw->mac.ops.setup_sfp(hw);
5027
8d1c3c07 5028 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5029 /* This will also work for DA Twinax connections */
5030 schedule_work(&adapter->multispeed_fiber_task);
5031 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5032}
5033
c4cf55e5
PWJ		 5034/**
5035 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5036 * @work: pointer to work_struct containing our data
5037 **/
5038static void ixgbe_fdir_reinit_task(struct work_struct *work)
5039{
5040 struct ixgbe_adapter *adapter = container_of(work,
5041 struct ixgbe_adapter,
5042 fdir_reinit_task);
5043 struct ixgbe_hw *hw = &adapter->hw;
5044 int i;
5045
5046 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5047 for (i = 0; i < adapter->num_tx_queues; i++)
5048 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5049 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5
PWJ		 5050 } else {
5051 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
5052 "ignored adding FDIR ATR filters \n");
5053 }
5054 /* Done FDIR Re-initialization, enable transmits */
5055 netif_tx_start_all_queues(adapter->netdev);
5056}
5057
10eec955
JF		 5058static DEFINE_MUTEX(ixgbe_watchdog_lock);
5059
cf8280ee 5060/**
69888674
AD		 5061 * ixgbe_watchdog_task - worker thread to bring link up
5062 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5063 **/
5064static void ixgbe_watchdog_task(struct work_struct *work)
5065{
5066 struct ixgbe_adapter *adapter = container_of(work,
5067 struct ixgbe_adapter,
5068 watchdog_task);
5069 struct net_device *netdev = adapter->netdev;
5070 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5071 u32 link_speed;
5072 bool link_up;
bc59fcda
NS		 5073 int i;
5074 struct ixgbe_ring *tx_ring;
5075 int some_tx_pending = 0;
cf8280ee 5076
10eec955
JF		 5077 mutex_lock(&ixgbe_watchdog_lock);
5078
5079 link_up = adapter->link_up;
5080 link_speed = adapter->link_speed;
cf8280ee
JB		 5081
5082 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5083 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5084 if (link_up) {
5085#ifdef CONFIG_DCB
5086 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5087 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5088 hw->mac.ops.fc_enable(hw, i);
264857b8 5089 } else {
620fa036 5090 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5091 }
5092#else
620fa036 5093 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5094#endif
5095 }
5096
cf8280ee
JB		 5097 if (link_up ||
5098 time_after(jiffies, (adapter->link_check_timeout +
5099 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5100 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5101 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5102 }
5103 adapter->link_up = link_up;
5104 adapter->link_speed = link_speed;
5105 }
9a799d71
AK		 5106
5107 if (link_up) {
5108 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5109 bool flow_rx, flow_tx;
5110
5111 if (hw->mac.type == ixgbe_mac_82599EB) {
5112 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5113 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5114 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5115 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5116 } else {
5117 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5118 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5119 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5120 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5121 }
5122
a46e534b
JK		 5123 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5124 "Flow Control: %s\n",
5125 netdev->name,
5126 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5127 "10 Gbps" :
5128 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5129 "1 Gbps" : "unknown speed")),
e8e26350
PW		 5130 ((flow_rx && flow_tx) ? "RX/TX" :
5131 (flow_rx ? "RX" :
5132 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5133
5134 netif_carrier_on(netdev);
9a799d71
AK		 5135 } else {
5136 /* Force detection of hung controller */
5137 adapter->detect_tx_hung = true;
5138 }
5139 } else {
cf8280ee
JB		 5140 adapter->link_up = false;
5141 adapter->link_speed = 0;
9a799d71 5142 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 5143 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5144 netdev->name);
9a799d71 5145 netif_carrier_off(netdev);
9a799d71
AK		 5146 }
5147 }
5148
bc59fcda
NS		 5149 if (!netif_carrier_ok(netdev)) {
5150 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5151 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5152 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5153 some_tx_pending = 1;
5154 break;
5155 }
5156 }
5157
5158 if (some_tx_pending) {
5159 /* We've lost link, so the controller stops DMA,
5160 * but we've got queued Tx work that's never going
5161 * to get done, so reset controller to flush Tx.
5162 * (Do the reset outside of interrupt context).
5163 */
5164 schedule_work(&adapter->reset_task);
5165 }
5166 }
5167
9a799d71 5168 ixgbe_update_stats(adapter);
10eec955 5169 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5170}
5171
9a799d71 5172static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5173 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5174 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5175{
5176 struct ixgbe_adv_tx_context_desc *context_desc;
5177 unsigned int i;
5178 int err;
5179 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5180 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5181 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5182
5183 if (skb_is_gso(skb)) {
5184 if (skb_header_cloned(skb)) {
5185 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5186 if (err)
5187 return err;
5188 }
5189 l4len = tcp_hdrlen(skb);
5190 *hdr_len += l4len;
5191
8327d000 5192 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5193 struct iphdr *iph = ip_hdr(skb);
5194 iph->tot_len = 0;
5195 iph->check = 0;
5196 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5197 iph->daddr, 0,
5198 IPPROTO_TCP,
5199 0);
8e1e8a47 5200 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5201 ipv6_hdr(skb)->payload_len = 0;
5202 tcp_hdr(skb)->check =
5203 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5204 &ipv6_hdr(skb)->daddr,
5205 0, IPPROTO_TCP, 0);
9a799d71
AK		 5206 }
5207
5208 i = tx_ring->next_to_use;
5209
5210 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5211 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5212
5213 /* VLAN MACLEN IPLEN */
5214 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5215 vlan_macip_lens |=
5216 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5217 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5218 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5219 *hdr_len += skb_network_offset(skb);
5220 vlan_macip_lens |=
5221 (skb_transport_header(skb) - skb_network_header(skb));
5222 *hdr_len +=
5223 (skb_transport_header(skb) - skb_network_header(skb));
5224 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5225 context_desc->seqnum_seed = 0;
5226
5227 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5228 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5229 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5230
8327d000 5231 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5232 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5233 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5234 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5235
5236 /* MSS L4LEN IDX */
9f8cdf4f 5237 mss_l4len_idx =
9a799d71
AK		 5238 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5239 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5240 /* use index 1 for TSO */
5241 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5242 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5243
5244 tx_buffer_info->time_stamp = jiffies;
5245 tx_buffer_info->next_to_watch = i;
5246
5247 i++;
5248 if (i == tx_ring->count)
5249 i = 0;
5250 tx_ring->next_to_use = i;
5251
5252 return true;
5253 }
5254 return false;
5255}
5256
5257static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5258 struct ixgbe_ring *tx_ring,
5259 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5260{
5261 struct ixgbe_adv_tx_context_desc *context_desc;
5262 unsigned int i;
5263 struct ixgbe_tx_buffer *tx_buffer_info;
5264 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5265
5266 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5267 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5268 i = tx_ring->next_to_use;
5269 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5270 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5271
5272 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5273 vlan_macip_lens |=
5274 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5275 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5276 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5277 if (skb->ip_summed == CHECKSUM_PARTIAL)
5278 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5279 skb_network_header(skb));
9a799d71
AK		 5280
5281 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5282 context_desc->seqnum_seed = 0;
5283
5284 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5285 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5286
5287 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5288 __be16 protocol;
5289
5290 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5291 const struct vlan_ethhdr *vhdr =
5292 (const struct vlan_ethhdr *)skb->data;
5293
5294 protocol = vhdr->h_vlan_encapsulated_proto;
5295 } else {
5296 protocol = skb->protocol;
5297 }
5298
5299 switch (protocol) {
09640e63 5300 case cpu_to_be16(ETH_P_IP):
9a799d71 5301 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5302 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5303 type_tucmd_mlhl |=
b4617240 5304 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5305 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5306 type_tucmd_mlhl |=
5307 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5308 break;
09640e63 5309 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5310 /* XXX what about other V6 headers?? */
5311 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5312 type_tucmd_mlhl |=
b4617240 5313 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5314 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5315 type_tucmd_mlhl |=
5316 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5317 break;
41825d71
AK		 5318 default:
5319 if (unlikely(net_ratelimit())) {
5320 DPRINTK(PROBE, WARNING,
5321 "partial checksum but proto=%x!\n",
5322 skb->protocol);
5323 }
5324 break;
5325 }
9a799d71
AK		 5326 }
5327
5328 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5329 /* use index zero for tx checksum offload */
9a799d71
AK		 5330 context_desc->mss_l4len_idx = 0;
5331
5332 tx_buffer_info->time_stamp = jiffies;
5333 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5334
9a799d71
AK		 5335 i++;
5336 if (i == tx_ring->count)
5337 i = 0;
5338 tx_ring->next_to_use = i;
5339
5340 return true;
5341 }
9f8cdf4f 5342
9a799d71
AK		 5343 return false;
5344}
5345
5346static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5347 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5348 struct sk_buff *skb, u32 tx_flags,
5349 unsigned int first)
9a799d71 5350{
e5a43549 5351 struct pci_dev *pdev = adapter->pdev;
9a799d71 5352 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5353 unsigned int len;
5354 unsigned int total = skb->len;
9a799d71
AK		 5355 unsigned int offset = 0, size, count = 0, i;
5356 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5357 unsigned int f;
9a799d71
AK		 5358
5359 i = tx_ring->next_to_use;
5360
eacd73f7
YZ		 5361 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5362 /* excluding fcoe_crc_eof for FCoE */
5363 total -= sizeof(struct fcoe_crc_eof);
5364
5365 len = min(skb_headlen(skb), total);
9a799d71
AK		 5366 while (len) {
5367 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5368 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5369
5370 tx_buffer_info->length = size;
e5a43549
AD		 5371 tx_buffer_info->mapped_as_page = false;
5372 tx_buffer_info->dma = pci_map_single(pdev,
5373 skb->data + offset,
5374 size, PCI_DMA_TODEVICE);
5375 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5376 goto dma_error;
9a799d71
AK		 5377 tx_buffer_info->time_stamp = jiffies;
5378 tx_buffer_info->next_to_watch = i;
5379
5380 len -= size;
eacd73f7 5381 total -= size;
9a799d71
AK		 5382 offset += size;
5383 count++;
44df32c5
AD		 5384
5385 if (len) {
5386 i++;
5387 if (i == tx_ring->count)
5388 i = 0;
5389 }
9a799d71
AK		 5390 }
5391
5392 for (f = 0; f < nr_frags; f++) {
5393 struct skb_frag_struct *frag;
5394
5395 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5396 len = min((unsigned int)frag->size, total);
e5a43549 5397 offset = frag->page_offset;
9a799d71
AK		 5398
5399 while (len) {
44df32c5
AD		 5400 i++;
5401 if (i == tx_ring->count)
5402 i = 0;
5403
9a799d71
AK		 5404 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5405 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5406
5407 tx_buffer_info->length = size;
e5a43549
AD		 5408 tx_buffer_info->dma = pci_map_page(adapter->pdev,
5409 frag->page,
5410 offset, size,
5411 PCI_DMA_TODEVICE);
5412 tx_buffer_info->mapped_as_page = true;
5413 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5414 goto dma_error;
9a799d71
AK		 5415 tx_buffer_info->time_stamp = jiffies;
5416 tx_buffer_info->next_to_watch = i;
5417
5418 len -= size;
eacd73f7 5419 total -= size;
9a799d71
AK		 5420 offset += size;
5421 count++;
9a799d71 5422 }
eacd73f7
YZ		 5423 if (total == 0)
5424 break;
9a799d71 5425 }
44df32c5 5426
9a799d71
AK		 5427 tx_ring->tx_buffer_info[i].skb = skb;
5428 tx_ring->tx_buffer_info[first].next_to_watch = i;
5429
e5a43549
AD		 5430 return count;
5431
5432dma_error:
5433 dev_err(&pdev->dev, "TX DMA map failed\n");
5434
5435 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5436 tx_buffer_info->dma = 0;
5437 tx_buffer_info->time_stamp = 0;
5438 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5439 if (count)
5440 count--;
e5a43549
AD		 5441
5442 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5443 while (count--) {
5444 if (i==0)
e5a43549 5445 i += tx_ring->count;
c1fa347f 5446 i--;
e5a43549
AD		 5447 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5448 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5449 }
5450
e44d38e1 5451 return 0;
9a799d71
AK		 5452}
5453
5454static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5455 struct ixgbe_ring *tx_ring,
5456 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5457{
5458 union ixgbe_adv_tx_desc *tx_desc = NULL;
5459 struct ixgbe_tx_buffer *tx_buffer_info;
5460 u32 olinfo_status = 0, cmd_type_len = 0;
5461 unsigned int i;
5462 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5463
5464 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5465
5466 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5467
5468 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5469 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5470
5471 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5472 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5473
5474 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5475 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5476
4eeae6fd
PW		 5477 /* use index 1 context for tso */
5478 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5479 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5480 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5481 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5482
5483 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5484 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5485 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5486
eacd73f7
YZ		 5487 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5488 olinfo_status |= IXGBE_ADVTXD_CC;
5489 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5490 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5491 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5492 }
5493
9a799d71
AK		 5494 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5495
5496 i = tx_ring->next_to_use;
5497 while (count--) {
5498 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5499 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5500 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5501 tx_desc->read.cmd_type_len =
b4617240 5502 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5503 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5504 i++;
5505 if (i == tx_ring->count)
5506 i = 0;
5507 }
5508
5509 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5510
5511 /*
5512 * Force memory writes to complete before letting h/w
5513 * know there are new descriptors to fetch. (Only
5514 * applicable for weak-ordered memory model archs,
5515 * such as IA-64).
5516 */
5517 wmb();
5518
5519 tx_ring->next_to_use = i;
5520 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5521}
5522
c4cf55e5
PWJ		 5523static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5524 int queue, u32 tx_flags)
5525{
5526 /* Right now, we support IPv4 only */
5527 struct ixgbe_atr_input atr_input;
5528 struct tcphdr *th;
c4cf55e5
PWJ		 5529 struct iphdr *iph = ip_hdr(skb);
5530 struct ethhdr *eth = (struct ethhdr *)skb->data;
5531 u16 vlan_id, src_port, dst_port, flex_bytes;
5532 u32 src_ipv4_addr, dst_ipv4_addr;
5533 u8 l4type = 0;
5534
5535 /* check if we're UDP or TCP */
5536 if (iph->protocol == IPPROTO_TCP) {
5537 th = tcp_hdr(skb);
5538 src_port = th->source;
5539 dst_port = th->dest;
5540 l4type |= IXGBE_ATR_L4TYPE_TCP;
5541 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5542 } else {
5543 /* Unsupported L4 header, just bail here */
5544 return;
5545 }
5546
5547 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5548
5549 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5550 IXGBE_TX_FLAGS_VLAN_SHIFT;
5551 src_ipv4_addr = iph->saddr;
5552 dst_ipv4_addr = iph->daddr;
5553 flex_bytes = eth->h_proto;
5554
5555 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5556 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5557 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5558 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5559 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5560 /* src and dst are inverted, think how the receiver sees them */
5561 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5562 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5563
5564 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5565 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5566}
5567
e092be60 5568static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5569 struct ixgbe_ring *tx_ring, int size)
e092be60 5570{
30eba97a 5571 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5572 /* Herbert's original patch had:
5573 * smp_mb__after_netif_stop_queue();
5574 * but since that doesn't exist yet, just open code it. */
5575 smp_mb();
5576
5577 /* We need to check again in a case another CPU has just
5578 * made room available. */
5579 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5580 return -EBUSY;
5581
5582 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5583 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 5584 ++tx_ring->restart_queue;
e092be60
AV		 5585 return 0;
5586}
5587
5588static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5589 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5590{
5591 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5592 return 0;
5593 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5594}
5595
09a3b1f8
SH		 5596static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5597{
5598 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 5599 int txq = smp_processor_id();
09a3b1f8 5600
fdd3d631
KK		 5601 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5602 while (unlikely(txq >= dev->real_num_tx_queues))
5603 txq -= dev->real_num_tx_queues;
5f715823 5604 return txq;
fdd3d631 5605 }
c4cf55e5 5606
5f715823
YZ		 5607#ifdef IXGBE_FCOE
5608 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5609 (skb->protocol == htons(ETH_P_FCOE))) {
5610 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5611 txq += adapter->ring_feature[RING_F_FCOE].mask;
5612 return txq;
5613 }
5614#endif
09a3b1f8 5615 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
36e89d73 5616 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
09a3b1f8
SH		 5617
5618 return skb_tx_hash(dev, skb);
5619}
5620
3b29a56d
SH		 5621static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5622 struct net_device *netdev)
9a799d71
AK		 5623{
5624 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5625 struct ixgbe_ring *tx_ring;
60d51134 5626 struct netdev_queue *txq;
9a799d71
AK		 5627 unsigned int first;
5628 unsigned int tx_flags = 0;
30eba97a 5629 u8 hdr_len = 0;
5f715823 5630 int tso;
9a799d71
AK		 5631 int count = 0;
5632 unsigned int f;
9f8cdf4f 5633
9f8cdf4f
JB		 5634 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5635 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5636 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5637 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 5638 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 5639 }
5640 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5641 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5642 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
60127865 5643 if (skb->priority != TC_PRIO_CONTROL) {
5f715823 5644 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
60127865
LL		 5645 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5646 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5647 } else {
5648 skb->queue_mapping =
5649 adapter->ring_feature[RING_F_DCB].indices-1;
5650 }
9a799d71 5651 }
eacd73f7 5652
4a0b9ca0 5653 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 5654
eacd73f7 5655 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
09ad1cc0 5656 (skb->protocol == htons(ETH_P_FCOE))) {
eacd73f7 5657 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 5658#ifdef IXGBE_FCOE
61a0f421
YZ		 5659#ifdef CONFIG_IXGBE_DCB
5660 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5661 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5662 tx_flags |= ((adapter->fcoe.up << 13)
5663 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5664#endif
09ad1cc0
YZ		 5665#endif
5666 }
eacd73f7 5667 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5668 if (skb_is_gso(skb) ||
5669 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5670 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5671 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5672 count++;
5673
9f8cdf4f
JB		 5674 count += TXD_USE_COUNT(skb_headlen(skb));
5675 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5676 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5677
e092be60 5678 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5679 adapter->tx_busy++;
9a799d71
AK		 5680 return NETDEV_TX_BUSY;
5681 }
9a799d71 5682
9a799d71 5683 first = tx_ring->next_to_use;
eacd73f7
YZ		 5684 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5685#ifdef IXGBE_FCOE
5686 /* setup tx offload for FCoE */
5687 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5688 if (tso < 0) {
5689 dev_kfree_skb_any(skb);
5690 return NETDEV_TX_OK;
5691 }
5692 if (tso)
5693 tx_flags |= IXGBE_TX_FLAGS_FSO;
5694#endif /* IXGBE_FCOE */
5695 } else {
5696 if (skb->protocol == htons(ETH_P_IP))
5697 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5698 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5699 if (tso < 0) {
5700 dev_kfree_skb_any(skb);
5701 return NETDEV_TX_OK;
5702 }
9a799d71 5703
eacd73f7
YZ		 5704 if (tso)
5705 tx_flags |= IXGBE_TX_FLAGS_TSO;
5706 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5707 (skb->ip_summed == CHECKSUM_PARTIAL))
5708 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5709 }
9a799d71 5710
eacd73f7 5711 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5712 if (count) {
c4cf55e5
PWJ		 5713 /* add the ATR filter if ATR is on */
5714 if (tx_ring->atr_sample_rate) {
5715 ++tx_ring->atr_count;
5716 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5717 test_bit(__IXGBE_FDIR_INIT_DONE,
5718 &tx_ring->reinit_state)) {
5719 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5720 tx_flags);
5721 tx_ring->atr_count = 0;
5722 }
5723 }
60d51134
ED		 5724 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5725 txq->tx_bytes += skb->len;
5726 txq->tx_packets++;
44df32c5
AD		 5727 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5728 hdr_len);
44df32c5 5729 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5730
44df32c5
AD		 5731 } else {
5732 dev_kfree_skb_any(skb);
5733 tx_ring->tx_buffer_info[first].time_stamp = 0;
5734 tx_ring->next_to_use = first;
5735 }
9a799d71
AK		 5736
5737 return NETDEV_TX_OK;
5738}
5739
9a799d71
AK		 5740/**
5741 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5742 * @netdev: network interface device structure
5743 * @p: pointer to an address structure
5744 *
5745 * Returns 0 on success, negative on failure
5746 **/
5747static int ixgbe_set_mac(struct net_device *netdev, void *p)
5748{
5749 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5750 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5751 struct sockaddr *addr = p;
5752
5753 if (!is_valid_ether_addr(addr->sa_data))
5754 return -EADDRNOTAVAIL;
5755
5756 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5757 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5758
1cdd1ec8
GR		 5759 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5760 IXGBE_RAH_AV);
9a799d71
AK		 5761
5762 return 0;
5763}
5764
6b73e10d
BH		 5765static int
5766ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5767{
5768 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5769 struct ixgbe_hw *hw = &adapter->hw;
5770 u16 value;
5771 int rc;
5772
5773 if (prtad != hw->phy.mdio.prtad)
5774 return -EINVAL;
5775 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5776 if (!rc)
5777 rc = value;
5778 return rc;
5779}
5780
5781static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5782 u16 addr, u16 value)
5783{
5784 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5785 struct ixgbe_hw *hw = &adapter->hw;
5786
5787 if (prtad != hw->phy.mdio.prtad)
5788 return -EINVAL;
5789 return hw->phy.ops.write_reg(hw, addr, devad, value);
5790}
5791
5792static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5793{
5794 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5795
5796 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5797}
5798
0365e6e4
PW		 5799/**
5800 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5801 * netdev->dev_addrs
0365e6e4
PW		 5802 * @netdev: network interface device structure
5803 *
5804 * Returns non-zero on failure
5805 **/
5806static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5807{
5808 int err = 0;
5809 struct ixgbe_adapter *adapter = netdev_priv(dev);
5810 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5811
5812 if (is_valid_ether_addr(mac->san_addr)) {
5813 rtnl_lock();
5814 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5815 rtnl_unlock();
5816 }
5817 return err;
5818}
5819
5820/**
5821 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5822 * netdev->dev_addrs
0365e6e4
PW		 5823 * @netdev: network interface device structure
5824 *
5825 * Returns non-zero on failure
5826 **/
5827static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5828{
5829 int err = 0;
5830 struct ixgbe_adapter *adapter = netdev_priv(dev);
5831 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5832
5833 if (is_valid_ether_addr(mac->san_addr)) {
5834 rtnl_lock();
5835 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5836 rtnl_unlock();
5837 }
5838 return err;
5839}
5840
9a799d71
AK		 5841#ifdef CONFIG_NET_POLL_CONTROLLER
5842/*
5843 * Polling 'interrupt' - used by things like netconsole to send skbs
5844 * without having to re-enable interrupts. It's not called while
5845 * the interrupt routine is executing.
5846 */
5847static void ixgbe_netpoll(struct net_device *netdev)
5848{
5849 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5850 int i;
9a799d71 5851
1a647bd2
AD		 5852 /* if interface is down do nothing */
5853 if (test_bit(__IXGBE_DOWN, &adapter->state))
5854 return;
5855
9a799d71 5856 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5857 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5858 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5859 for (i = 0; i < num_q_vectors; i++) {
5860 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5861 ixgbe_msix_clean_many(0, q_vector);
5862 }
5863 } else {
5864 ixgbe_intr(adapter->pdev->irq, netdev);
5865 }
9a799d71 5866 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5867}
5868#endif
5869
0edc3527
SH		 5870static const struct net_device_ops ixgbe_netdev_ops = {
5871 .ndo_open = ixgbe_open,
5872 .ndo_stop = ixgbe_close,
00829823 5873 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5874 .ndo_select_queue = ixgbe_select_queue,
e90d400c 5875 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5876 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5877 .ndo_validate_addr = eth_validate_addr,
5878 .ndo_set_mac_address = ixgbe_set_mac,
5879 .ndo_change_mtu = ixgbe_change_mtu,
5880 .ndo_tx_timeout = ixgbe_tx_timeout,
5881 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5882 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5883 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5884 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5885#ifdef CONFIG_NET_POLL_CONTROLLER
5886 .ndo_poll_controller = ixgbe_netpoll,
5887#endif
332d4a7d
YZ		 5888#ifdef IXGBE_FCOE
5889 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5890 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5891 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5892 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 5893 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 5894#endif /* IXGBE_FCOE */
0edc3527
SH		 5895};
5896
1cdd1ec8
GR		 5897static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
5898 const struct ixgbe_info *ii)
5899{
5900#ifdef CONFIG_PCI_IOV
5901 struct ixgbe_hw *hw = &adapter->hw;
5902 int err;
5903
5904 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
5905 return;
5906
5907 /* The 82599 supports up to 64 VFs per physical function
5908 * but this implementation limits allocation to 63 so that
5909 * basic networking resources are still available to the
5910 * physical function
5911 */
5912 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
5913 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
5914 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
5915 if (err) {
5916 DPRINTK(PROBE, ERR,
5917 "Failed to enable PCI sriov: %d\n", err);
5918 goto err_novfs;
5919 }
5920 /* If call to enable VFs succeeded then allocate memory
5921 * for per VF control structures.
5922 */
5923 adapter->vfinfo =
5924 kcalloc(adapter->num_vfs,
5925 sizeof(struct vf_data_storage), GFP_KERNEL);
5926 if (adapter->vfinfo) {
5927 /* Now that we're sure SR-IOV is enabled
5928 * and memory allocated set up the mailbox parameters
5929 */
5930 ixgbe_init_mbx_params_pf(hw);
5931 memcpy(&hw->mbx.ops, ii->mbx_ops,
5932 sizeof(hw->mbx.ops));
5933
5934 /* Disable RSC when in SR-IOV mode */
5935 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
5936 IXGBE_FLAG2_RSC_ENABLED);
5937 return;
5938 }
5939
5940 /* Oh oh */
5941 DPRINTK(PROBE, ERR,
5942 "Unable to allocate memory for VF "
5943 "Data Storage - SRIOV disabled\n");
5944 pci_disable_sriov(adapter->pdev);
5945
5946err_novfs:
5947 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
5948 adapter->num_vfs = 0;
5949#endif /* CONFIG_PCI_IOV */
5950}
5951
9a799d71
AK		 5952/**
5953 * ixgbe_probe - Device Initialization Routine
5954 * @pdev: PCI device information struct
5955 * @ent: entry in ixgbe_pci_tbl
5956 *
5957 * Returns 0 on success, negative on failure
5958 *
5959 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5960 * The OS initialization, configuring of the adapter private structure,
5961 * and a hardware reset occur.
5962 **/
5963static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5964 const struct pci_device_id *ent)
9a799d71
AK		 5965{
5966 struct net_device *netdev;
5967 struct ixgbe_adapter *adapter = NULL;
5968 struct ixgbe_hw *hw;
5969 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5970 static int cards_found;
5971 int i, err, pci_using_dac;
eacd73f7
YZ		 5972#ifdef IXGBE_FCOE
5973 u16 device_caps;
5974#endif
c44ade9e 5975 u32 part_num, eec;
9a799d71 5976
9ce77666 5977 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5978 if (err)
5979 return err;
5980
6a35528a
YH		 5981 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5982 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5983 pci_using_dac = 1;
5984 } else {
284901a9 5985 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5986 if (err) {
284901a9 5987 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5988 if (err) {
b4617240
PW		 5989 dev_err(&pdev->dev, "No usable DMA "
5990 "configuration, aborting\n");
9a799d71
AK		 5991 goto err_dma;
5992 }
5993 }
5994 pci_using_dac = 0;
5995 }
5996
9ce77666 5997 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5998 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5999 if (err) {
9ce77666 6000 dev_err(&pdev->dev,
6001 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6002 goto err_pci_reg;
6003 }
6004
19d5afd4 6005 pci_enable_pcie_error_reporting(pdev);
6fabd715 6006
9a799d71 6007 pci_set_master(pdev);
fb3b27bc 6008 pci_save_state(pdev);
9a799d71 6009
30eba97a 6010 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 6011 if (!netdev) {
6012 err = -ENOMEM;
6013 goto err_alloc_etherdev;
6014 }
6015
9a799d71
AK		 6016 SET_NETDEV_DEV(netdev, &pdev->dev);
6017
6018 pci_set_drvdata(pdev, netdev);
6019 adapter = netdev_priv(netdev);
6020
6021 adapter->netdev = netdev;
6022 adapter->pdev = pdev;
6023 hw = &adapter->hw;
6024 hw->back = adapter;
6025 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6026
05857980
JK		 6027 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6028 pci_resource_len(pdev, 0));
9a799d71
AK		 6029 if (!hw->hw_addr) {
6030 err = -EIO;
6031 goto err_ioremap;
6032 }
6033
6034 for (i = 1; i <= 5; i++) {
6035 if (pci_resource_len(pdev, i) == 0)
6036 continue;
6037 }
6038
0edc3527 6039 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6040 ixgbe_set_ethtool_ops(netdev);
9a799d71 6041 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6042 strcpy(netdev->name, pci_name(pdev));
6043
9a799d71
AK		 6044 adapter->bd_number = cards_found;
6045
9a799d71
AK		 6046 /* Setup hw api */
6047 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6048 hw->mac.type = ii->mac;
9a799d71 6049
c44ade9e
JB		 6050 /* EEPROM */
6051 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6052 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6053 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6054 if (!(eec & (1 << 8)))
6055 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6056
6057 /* PHY */
6058 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6059 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6060 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6061 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6062 hw->phy.mdio.mmds = 0;
6063 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6064 hw->phy.mdio.dev = netdev;
6065 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6066 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6067
6068 /* set up this timer and work struct before calling get_invariants
6069 * which might start the timer
6070 */
6071 init_timer(&adapter->sfp_timer);
6072 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6073 adapter->sfp_timer.data = (unsigned long) adapter;
6074
6075 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6076
e8e26350
PW		 6077 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6078 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6079
6080 /* a new SFP+ module arrival, called from GPI SDP2 context */
6081 INIT_WORK(&adapter->sfp_config_module_task,
6082 ixgbe_sfp_config_module_task);
6083
8ca783ab 6084 ii->get_invariants(hw);
9a799d71
AK		 6085
6086 /* setup the private structure */
6087 err = ixgbe_sw_init(adapter);
6088 if (err)
6089 goto err_sw_init;
6090
bf069c97
DS		 6091 /*
6092 * If there is a fan on this device and it has failed log the
6093 * failure.
6094 */
6095 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6096 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6097 if (esdp & IXGBE_ESDP_SDP1)
6098 DPRINTK(PROBE, CRIT,
6099 "Fan has stopped, replace the adapter\n");
6100 }
6101
c44ade9e
JB		 6102 /* reset_hw fills in the perm_addr as well */
6103 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 6104 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6105 hw->mac.type == ixgbe_mac_82598EB) {
6106 /*
6107 * Start a kernel thread to watch for a module to arrive.
6108 * Only do this for 82598, since 82599 will generate
6109 * interrupts on module arrival.
6110 */
6111 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6112 mod_timer(&adapter->sfp_timer,
6113 round_jiffies(jiffies + (2 * HZ)));
6114 err = 0;
6115 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 6116 dev_err(&adapter->pdev->dev, "failed to initialize because "
6117 "an unsupported SFP+ module type was detected.\n"
6118 "Reload the driver after installing a supported "
6119 "module.\n");
04f165ef
PW		 6120 goto err_sw_init;
6121 } else if (err) {
c44ade9e
JB		 6122 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6123 goto err_sw_init;
6124 }
6125
1cdd1ec8
GR		 6126 ixgbe_probe_vf(adapter, ii);
6127
9a799d71 6128 netdev->features = NETIF_F_SG |
b4617240
PW		 6129 NETIF_F_IP_CSUM |
6130 NETIF_F_HW_VLAN_TX |
6131 NETIF_F_HW_VLAN_RX |
6132 NETIF_F_HW_VLAN_FILTER;
9a799d71 6133
e9990a9c 6134 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6135 netdev->features |= NETIF_F_TSO;
9a799d71 6136 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6137 netdev->features |= NETIF_F_GRO;
ad31c402 6138
45a5ead0
JB		 6139 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6140 netdev->features |= NETIF_F_SCTP_CSUM;
6141
ad31c402
JK		 6142 netdev->vlan_features |= NETIF_F_TSO;
6143 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6144 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6145 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6146 netdev->vlan_features |= NETIF_F_SG;
6147
1cdd1ec8
GR		 6148 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6149 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6150 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6151 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6152 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6153
7a6b6f51 6154#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6155 netdev->dcbnl_ops = &dcbnl_ops;
6156#endif
6157
eacd73f7 6158#ifdef IXGBE_FCOE
0d551589 6159 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6160 if (hw->mac.ops.get_device_caps) {
6161 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6162 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6163 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6164 }
6165 }
6166#endif /* IXGBE_FCOE */
9a799d71
AK		 6167 if (pci_using_dac)
6168 netdev->features |= NETIF_F_HIGHDMA;
6169
0c19d6af 6170 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6171 netdev->features |= NETIF_F_LRO;
6172
9a799d71 6173 /* make sure the EEPROM is good */
c44ade9e 6174 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 6175 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6176 err = -EIO;
6177 goto err_eeprom;
6178 }
6179
6180 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6181 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6182
c44ade9e
JB		 6183 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6184 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 6185 err = -EIO;
6186 goto err_eeprom;
6187 }
6188
6189 init_timer(&adapter->watchdog_timer);
6190 adapter->watchdog_timer.function = &ixgbe_watchdog;
6191 adapter->watchdog_timer.data = (unsigned long)adapter;
6192
6193 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6194 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6195
021230d4
AV		 6196 err = ixgbe_init_interrupt_scheme(adapter);
6197 if (err)
6198 goto err_sw_init;
9a799d71 6199
e8e26350
PW		 6200 switch (pdev->device) {
6201 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6202 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6203 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 6204 /* Enable ACPI wakeup in GRC */
6205 IXGBE_WRITE_REG(hw, IXGBE_GRC,
6206 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 6207 break;
6208 default:
6209 adapter->wol = 0;
6210 break;
6211 }
e8e26350
PW		 6212 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6213
04f165ef
PW		 6214 /* pick up the PCI bus settings for reporting later */
6215 hw->mac.ops.get_bus_info(hw);
6216
9a799d71 6217 /* print bus type/speed/width info */
7c510e4b 6218 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6219 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6220 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6221 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6222 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6223 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6224 "Unknown"),
7c510e4b 6225 netdev->dev_addr);
c44ade9e 6226 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 6227 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6228 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6229 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6230 (part_num >> 8), (part_num & 0xff));
6231 else
6232 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6233 hw->mac.type, hw->phy.type,
6234 (part_num >> 8), (part_num & 0xff));
9a799d71 6235
e8e26350 6236 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 6237 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 6238 "this card is not sufficient for optimal "
6239 "performance.\n");
0c254d86 6240 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 6241 "PCI-Express slot is required.\n");
0c254d86
AK		 6242 }
6243
34b0368c
PWJ		 6244 /* save off EEPROM version number */
6245 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6246
9a799d71 6247 /* reset the hardware with the new settings */
794caeb2 6248 err = hw->mac.ops.start_hw(hw);
c44ade9e 6249
794caeb2
PWJ		 6250 if (err == IXGBE_ERR_EEPROM_VERSION) {
6251 /* We are running on a pre-production device, log a warning */
6252 dev_warn(&pdev->dev, "This device is a pre-production "
6253 "adapter/LOM. Please be aware there may be issues "
6254 "associated with your hardware. If you are "
6255 "experiencing problems please contact your Intel or "
6256 "hardware representative who provided you with this "
6257 "hardware.\n");
6258 }
9a799d71
AK		 6259 strcpy(netdev->name, "eth%d");
6260 err = register_netdev(netdev);
6261 if (err)
6262 goto err_register;
6263
54386467
JB		 6264 /* carrier off reporting is important to ethtool even BEFORE open */
6265 netif_carrier_off(netdev);
6266
c4cf55e5
PWJ		 6267 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6268 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6269 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6270
5dd2d332 6271#ifdef CONFIG_IXGBE_DCA
652f093f 6272 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6273 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6274 ixgbe_setup_dca(adapter);
6275 }
6276#endif
1cdd1ec8
GR		 6277 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6278 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6279 adapter->num_vfs);
6280 for (i = 0; i < adapter->num_vfs; i++)
6281 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6282 }
6283
0365e6e4
PW		 6284 /* add san mac addr to netdev */
6285 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 6286
6287 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6288 cards_found++;
6289 return 0;
6290
6291err_register:
5eba3699 6292 ixgbe_release_hw_control(adapter);
7a921c93 6293 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6294err_sw_init:
6295err_eeprom:
1cdd1ec8
GR		 6296 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6297 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6298 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6299 del_timer_sync(&adapter->sfp_timer);
6300 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6301 cancel_work_sync(&adapter->multispeed_fiber_task);
6302 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6303 iounmap(hw->hw_addr);
6304err_ioremap:
6305 free_netdev(netdev);
6306err_alloc_etherdev:
9ce77666 6307 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6308 IORESOURCE_MEM));
9a799d71
AK		 6309err_pci_reg:
6310err_dma:
6311 pci_disable_device(pdev);
6312 return err;
6313}
6314
6315/**
6316 * ixgbe_remove - Device Removal Routine
6317 * @pdev: PCI device information struct
6318 *
6319 * ixgbe_remove is called by the PCI subsystem to alert the driver
6320 * that it should release a PCI device. The could be caused by a
6321 * Hot-Plug event, or because the driver is going to be removed from
6322 * memory.
6323 **/
6324static void __devexit ixgbe_remove(struct pci_dev *pdev)
6325{
6326 struct net_device *netdev = pci_get_drvdata(pdev);
6327 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6328
6329 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6330 /* clear the module not found bit to make sure the worker won't
6331 * reschedule
6332 */
6333 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6334 del_timer_sync(&adapter->watchdog_timer);
6335
c4900be0
DS		 6336 del_timer_sync(&adapter->sfp_timer);
6337 cancel_work_sync(&adapter->watchdog_task);
6338 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6339 cancel_work_sync(&adapter->multispeed_fiber_task);
6340 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6341 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6342 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6343 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6344 flush_scheduled_work();
6345
5dd2d332 6346#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6347 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6348 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6349 dca_remove_requester(&pdev->dev);
6350 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6351 }
6352
6353#endif
332d4a7d
YZ		 6354#ifdef IXGBE_FCOE
6355 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6356 ixgbe_cleanup_fcoe(adapter);
6357
6358#endif /* IXGBE_FCOE */
0365e6e4
PW		 6359
6360 /* remove the added san mac */
6361 ixgbe_del_sanmac_netdev(netdev);
6362
c4900be0
DS		 6363 if (netdev->reg_state == NETREG_REGISTERED)
6364 unregister_netdev(netdev);
9a799d71 6365
1cdd1ec8
GR		 6366 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6367 ixgbe_disable_sriov(adapter);
6368
7a921c93 6369 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6370
021230d4 6371 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6372
6373 iounmap(adapter->hw.hw_addr);
9ce77666 6374 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6375 IORESOURCE_MEM));
9a799d71 6376
021230d4 6377 DPRINTK(PROBE, INFO, "complete\n");
021230d4 6378
9a799d71
AK		 6379 free_netdev(netdev);
6380
19d5afd4 6381 pci_disable_pcie_error_reporting(pdev);
6fabd715 6382
9a799d71
AK		 6383 pci_disable_device(pdev);
6384}
6385
6386/**
6387 * ixgbe_io_error_detected - called when PCI error is detected
6388 * @pdev: Pointer to PCI device
6389 * @state: The current pci connection state
6390 *
6391 * This function is called after a PCI bus error affecting
6392 * this device has been detected.
6393 */
6394static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6395 pci_channel_state_t state)
9a799d71
AK		 6396{
6397 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6398 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6399
6400 netif_device_detach(netdev);
6401
3044b8d1
BL		 6402 if (state == pci_channel_io_perm_failure)
6403 return PCI_ERS_RESULT_DISCONNECT;
6404
9a799d71
AK		 6405 if (netif_running(netdev))
6406 ixgbe_down(adapter);
6407 pci_disable_device(pdev);
6408
b4617240 6409 /* Request a slot reset. */
9a799d71
AK		 6410 return PCI_ERS_RESULT_NEED_RESET;
6411}
6412
6413/**
6414 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6415 * @pdev: Pointer to PCI device
6416 *
6417 * Restart the card from scratch, as if from a cold-boot.
6418 */
6419static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6420{
6421 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6422 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 6423 pci_ers_result_t result;
6424 int err;
9a799d71 6425
9ce77666 6426 if (pci_enable_device_mem(pdev)) {
9a799d71 6427 DPRINTK(PROBE, ERR,
b4617240 6428 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 6429 result = PCI_ERS_RESULT_DISCONNECT;
6430 } else {
6431 pci_set_master(pdev);
6432 pci_restore_state(pdev);
c0e1f68b 6433 pci_save_state(pdev);
9a799d71 6434
dd4d8ca6 6435 pci_wake_from_d3(pdev, false);
9a799d71 6436
6fabd715 6437 ixgbe_reset(adapter);
88512539 6438 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 6439 result = PCI_ERS_RESULT_RECOVERED;
6440 }
6441
6442 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6443 if (err) {
6444 dev_err(&pdev->dev,
6445 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6446 /* non-fatal, continue */
6447 }
9a799d71 6448
6fabd715 6449 return result;
9a799d71
AK		 6450}
6451
6452/**
6453 * ixgbe_io_resume - called when traffic can start flowing again.
6454 * @pdev: Pointer to PCI device
6455 *
6456 * This callback is called when the error recovery driver tells us that
6457 * its OK to resume normal operation.
6458 */
6459static void ixgbe_io_resume(struct pci_dev *pdev)
6460{
6461 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6462 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6463
6464 if (netif_running(netdev)) {
6465 if (ixgbe_up(adapter)) {
6466 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6467 return;
6468 }
6469 }
6470
6471 netif_device_attach(netdev);
9a799d71
AK		 6472}
6473
6474static struct pci_error_handlers ixgbe_err_handler = {
6475 .error_detected = ixgbe_io_error_detected,
6476 .slot_reset = ixgbe_io_slot_reset,
6477 .resume = ixgbe_io_resume,
6478};
6479
6480static struct pci_driver ixgbe_driver = {
6481 .name = ixgbe_driver_name,
6482 .id_table = ixgbe_pci_tbl,
6483 .probe = ixgbe_probe,
6484 .remove = __devexit_p(ixgbe_remove),
6485#ifdef CONFIG_PM
6486 .suspend = ixgbe_suspend,
6487 .resume = ixgbe_resume,
6488#endif
6489 .shutdown = ixgbe_shutdown,
6490 .err_handler = &ixgbe_err_handler
6491};
6492
6493/**
6494 * ixgbe_init_module - Driver Registration Routine
6495 *
6496 * ixgbe_init_module is the first routine called when the driver is
6497 * loaded. All it does is register with the PCI subsystem.
6498 **/
6499static int __init ixgbe_init_module(void)
6500{
6501 int ret;
6502 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6503 ixgbe_driver_string, ixgbe_driver_version);
6504
6505 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6506
5dd2d332 6507#ifdef CONFIG_IXGBE_DCA
bd0362dd 6508 dca_register_notify(&dca_notifier);
bd0362dd 6509#endif
5dd2d332 6510
9a799d71
AK		 6511 ret = pci_register_driver(&ixgbe_driver);
6512 return ret;
6513}
b4617240 6514
9a799d71
AK		 6515module_init(ixgbe_init_module);
6516
6517/**
6518 * ixgbe_exit_module - Driver Exit Cleanup Routine
6519 *
6520 * ixgbe_exit_module is called just before the driver is removed
6521 * from memory.
6522 **/
6523static void __exit ixgbe_exit_module(void)
6524{
5dd2d332 6525#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6526 dca_unregister_notify(&dca_notifier);
6527#endif
9a799d71
AK		 6528 pci_unregister_driver(&ixgbe_driver);
6529}
bd0362dd 6530
5dd2d332 6531#ifdef CONFIG_IXGBE_DCA
bd0362dd 6532static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6533 void *p)
bd0362dd
JC		 6534{
6535 int ret_val;
6536
6537 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6538 __ixgbe_notify_dca);
bd0362dd
JC		 6539
6540 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6541}
b453368d 6542
5dd2d332 6543#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6544#ifdef DEBUG
6545/**
6546 * ixgbe_get_hw_dev_name - return device name string
6547 * used by hardware layer to print debugging information
6548 **/
6549char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6550{
6551 struct ixgbe_adapter *adapter = hw->back;
6552 return adapter->netdev->name;
6553}
bd0362dd 6554
b453368d 6555#endif
9a799d71
AK		 6556module_exit(ixgbe_exit_module);
6557
6558/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)