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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / igb / e1000_82575.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* e1000_82575
29 * e1000_82576
30 */
31
32#include <linux/types.h>
2d064c06 33#include <linux/if_ether.h>
9d5c8243
AK		 34
35#include "e1000_mac.h"
36#include "e1000_82575.h"
37
38static s32 igb_get_invariants_82575(struct e1000_hw *);
39static s32 igb_acquire_phy_82575(struct e1000_hw *);
40static void igb_release_phy_82575(struct e1000_hw *);
41static s32 igb_acquire_nvm_82575(struct e1000_hw *);
42static void igb_release_nvm_82575(struct e1000_hw *);
43static s32 igb_check_for_link_82575(struct e1000_hw *);
44static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45static s32 igb_init_hw_82575(struct e1000_hw *);
46static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
bb2ac47b
AD		 48static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
49static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
9d5c8243 50static s32 igb_reset_hw_82575(struct e1000_hw *);
bb2ac47b 51static s32 igb_reset_hw_82580(struct e1000_hw *);
9d5c8243
AK		 52static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
53static s32 igb_setup_copper_link_82575(struct e1000_hw *);
2fb02a26 54static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
9d5c8243
AK		 55static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
56static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
57static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
9d5c8243
AK		 58static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
59 u16 *);
60static s32 igb_get_phy_id_82575(struct e1000_hw *);
61static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
62static bool igb_sgmii_active_82575(struct e1000_hw *);
63static s32 igb_reset_init_script_82575(struct e1000_hw *);
64static s32 igb_read_mac_addr_82575(struct e1000_hw *);
009bc06e 65static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
9d5c8243 66
bb2ac47b
AD		 67static const u16 e1000_82580_rxpbs_table[] =
68 { 36, 72, 144, 1, 2, 4, 8, 16,
69 35, 70, 140 };
70#define E1000_82580_RXPBS_TABLE_SIZE \
71 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
72
9d5c8243
AK		 73static s32 igb_get_invariants_82575(struct e1000_hw *hw)
74{
75 struct e1000_phy_info *phy = &hw->phy;
76 struct e1000_nvm_info *nvm = &hw->nvm;
77 struct e1000_mac_info *mac = &hw->mac;
c1889bfe 78 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
9d5c8243
AK		 79 u32 eecd;
80 s32 ret_val;
81 u16 size;
82 u32 ctrl_ext = 0;
83
84 switch (hw->device_id) {
85 case E1000_DEV_ID_82575EB_COPPER:
86 case E1000_DEV_ID_82575EB_FIBER_SERDES:
87 case E1000_DEV_ID_82575GB_QUAD_COPPER:
88 mac->type = e1000_82575;
89 break;
2d064c06 90 case E1000_DEV_ID_82576:
9eb2341d 91 case E1000_DEV_ID_82576_NS:
747d49ba 92 case E1000_DEV_ID_82576_NS_SERDES:
2d064c06
AD		 93 case E1000_DEV_ID_82576_FIBER:
94 case E1000_DEV_ID_82576_SERDES:
c8ea5ea9 95 case E1000_DEV_ID_82576_QUAD_COPPER:
b894fa26 96 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
4703bf73 97 case E1000_DEV_ID_82576_SERDES_QUAD:
2d064c06
AD		 98 mac->type = e1000_82576;
99 break;
bb2ac47b
AD		 100 case E1000_DEV_ID_82580_COPPER:
101 case E1000_DEV_ID_82580_FIBER:
102 case E1000_DEV_ID_82580_SERDES:
103 case E1000_DEV_ID_82580_SGMII:
104 case E1000_DEV_ID_82580_COPPER_DUAL:
105 mac->type = e1000_82580;
106 break;
9d5c8243
AK		 107 default:
108 return -E1000_ERR_MAC_INIT;
109 break;
110 }
111
9d5c8243
AK		 112 /* Set media type */
113 /*
114 * The 82575 uses bits 22:23 for link mode. The mode can be changed
115 * based on the EEPROM. We cannot rely upon device ID. There
116 * is no distinguishable difference between fiber and internal
117 * SerDes mode on the 82575. There can be an external PHY attached
118 * on the SGMII interface. For this, we'll set sgmii_active to true.
119 */
120 phy->media_type = e1000_media_type_copper;
121 dev_spec->sgmii_active = false;
122
123 ctrl_ext = rd32(E1000_CTRL_EXT);
2fb02a26
AD		 124 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
125 case E1000_CTRL_EXT_LINK_MODE_SGMII:
9d5c8243
AK		 126 dev_spec->sgmii_active = true;
127 ctrl_ext |= E1000_CTRL_I2C_ENA;
2fb02a26 128 break;
bb2ac47b 129 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
2fb02a26
AD		 130 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
131 hw->phy.media_type = e1000_media_type_internal_serdes;
132 ctrl_ext |= E1000_CTRL_I2C_ENA;
133 break;
134 default:
9d5c8243 135 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
2fb02a26 136 break;
9d5c8243 137 }
2fb02a26 138
9d5c8243
AK		 139 wr32(E1000_CTRL_EXT, ctrl_ext);
140
bb2ac47b
AD		 141 /*
142 * if using i2c make certain the MDICNFG register is cleared to prevent
143 * communications from being misrouted to the mdic registers
144 */
145 if ((ctrl_ext & E1000_CTRL_I2C_ENA) && (hw->mac.type == e1000_82580))
146 wr32(E1000_MDICNFG, 0);
147
9d5c8243
AK		 148 /* Set mta register count */
149 mac->mta_reg_count = 128;
150 /* Set rar entry count */
151 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
2d064c06
AD		 152 if (mac->type == e1000_82576)
153 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
bb2ac47b
AD		 154 if (mac->type == e1000_82580)
155 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
156 /* reset */
157 if (mac->type == e1000_82580)
158 mac->ops.reset_hw = igb_reset_hw_82580;
159 else
160 mac->ops.reset_hw = igb_reset_hw_82575;
9d5c8243
AK		 161 /* Set if part includes ASF firmware */
162 mac->asf_firmware_present = true;
163 /* Set if manageability features are enabled. */
164 mac->arc_subsystem_valid =
165 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
166 ? true : false;
167
168 /* physical interface link setup */
169 mac->ops.setup_physical_interface =
170 (hw->phy.media_type == e1000_media_type_copper)
171 ? igb_setup_copper_link_82575
2fb02a26 172 : igb_setup_serdes_link_82575;
9d5c8243
AK		 173
174 /* NVM initialization */
175 eecd = rd32(E1000_EECD);
176
177 nvm->opcode_bits = 8;
178 nvm->delay_usec = 1;
179 switch (nvm->override) {
180 case e1000_nvm_override_spi_large:
181 nvm->page_size = 32;
182 nvm->address_bits = 16;
183 break;
184 case e1000_nvm_override_spi_small:
185 nvm->page_size = 8;
186 nvm->address_bits = 8;
187 break;
188 default:
189 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
190 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
191 break;
192 }
193
194 nvm->type = e1000_nvm_eeprom_spi;
195
196 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
197 E1000_EECD_SIZE_EX_SHIFT);
198
199 /*
200 * Added to a constant, "size" becomes the left-shift value
201 * for setting word_size.
202 */
203 size += NVM_WORD_SIZE_BASE_SHIFT;
5c3cad75
JK		 204
205 /* EEPROM access above 16k is unsupported */
206 if (size > 14)
207 size = 14;
9d5c8243
AK		 208 nvm->word_size = 1 << size;
209
a0c98605
AD		 210 /* if 82576 then initialize mailbox parameters */
211 if (mac->type == e1000_82576)
212 igb_init_mbx_params_pf(hw);
213
9d5c8243
AK		 214 /* setup PHY parameters */
215 if (phy->media_type != e1000_media_type_copper) {
216 phy->type = e1000_phy_none;
217 return 0;
218 }
219
220 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
221 phy->reset_delay_us = 100;
222
223 /* PHY function pointers */
224 if (igb_sgmii_active_82575(hw)) {
a8d2a0c2
AD		 225 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
226 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
227 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
bb2ac47b
AD		 228 } else if (hw->mac.type == e1000_82580) {
229 phy->ops.reset = igb_phy_hw_reset;
230 phy->ops.read_reg = igb_read_phy_reg_82580;
231 phy->ops.write_reg = igb_write_phy_reg_82580;
9d5c8243 232 } else {
a8d2a0c2
AD		 233 phy->ops.reset = igb_phy_hw_reset;
234 phy->ops.read_reg = igb_read_phy_reg_igp;
235 phy->ops.write_reg = igb_write_phy_reg_igp;
9d5c8243
AK		 236 }
237
19e588e7
AD		 238 /* set lan id */
239 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
240 E1000_STATUS_FUNC_SHIFT;
241
9d5c8243
AK		 242 /* Set phy->phy_addr and phy->id. */
243 ret_val = igb_get_phy_id_82575(hw);
244 if (ret_val)
245 return ret_val;
246
247 /* Verify phy id and set remaining function pointers */
248 switch (phy->id) {
249 case M88E1111_I_PHY_ID:
250 phy->type = e1000_phy_m88;
251 phy->ops.get_phy_info = igb_get_phy_info_m88;
252 phy->ops.get_cable_length = igb_get_cable_length_m88;
253 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
254 break;
255 case IGP03E1000_E_PHY_ID:
256 phy->type = e1000_phy_igp_3;
257 phy->ops.get_phy_info = igb_get_phy_info_igp;
258 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
259 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
260 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
261 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
262 break;
bb2ac47b
AD		 263 case I82580_I_PHY_ID:
264 phy->type = e1000_phy_82580;
265 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
266 phy->ops.get_cable_length = igb_get_cable_length_82580;
267 phy->ops.get_phy_info = igb_get_phy_info_82580;
268 break;
9d5c8243
AK		 269 default:
270 return -E1000_ERR_PHY;
271 }
272
273 return 0;
274}
275
276/**
733596be 277 * igb_acquire_phy_82575 - Acquire rights to access PHY
9d5c8243
AK		 278 * @hw: pointer to the HW structure
279 *
280 * Acquire access rights to the correct PHY. This is a
281 * function pointer entry point called by the api module.
282 **/
283static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
284{
008c3422 285 u16 mask = E1000_SWFW_PHY0_SM;
9d5c8243 286
008c3422
AD		 287 if (hw->bus.func == E1000_FUNC_1)
288 mask = E1000_SWFW_PHY1_SM;
9d5c8243
AK		 289
290 return igb_acquire_swfw_sync_82575(hw, mask);
291}
292
293/**
733596be 294 * igb_release_phy_82575 - Release rights to access PHY
9d5c8243
AK		 295 * @hw: pointer to the HW structure
296 *
297 * A wrapper to release access rights to the correct PHY. This is a
298 * function pointer entry point called by the api module.
299 **/
300static void igb_release_phy_82575(struct e1000_hw *hw)
301{
008c3422
AD		 302 u16 mask = E1000_SWFW_PHY0_SM;
303
304 if (hw->bus.func == E1000_FUNC_1)
305 mask = E1000_SWFW_PHY1_SM;
9d5c8243 306
9d5c8243
AK		 307 igb_release_swfw_sync_82575(hw, mask);
308}
309
310/**
733596be 311 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
9d5c8243
AK		 312 * @hw: pointer to the HW structure
313 * @offset: register offset to be read
314 * @data: pointer to the read data
315 *
316 * Reads the PHY register at offset using the serial gigabit media independent
317 * interface and stores the retrieved information in data.
318 **/
319static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
320 u16 *data)
321{
bf6f7a92 322 s32 ret_val = -E1000_ERR_PARAM;
9d5c8243
AK		 323
324 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 325 hw_dbg("PHY Address %u is out of range\n", offset);
bf6f7a92 326 goto out;
9d5c8243
AK		 327 }
328
bf6f7a92
AD		 329 ret_val = hw->phy.ops.acquire(hw);
330 if (ret_val)
331 goto out;
9d5c8243 332
bf6f7a92 333 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
9d5c8243 334
bf6f7a92
AD		 335 hw->phy.ops.release(hw);
336
337out:
338 return ret_val;
9d5c8243
AK		 339}
340
341/**
733596be 342 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
9d5c8243
AK		 343 * @hw: pointer to the HW structure
344 * @offset: register offset to write to
345 * @data: data to write at register offset
346 *
347 * Writes the data to PHY register at the offset using the serial gigabit
348 * media independent interface.
349 **/
350static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
351 u16 data)
352{
bf6f7a92
AD		 353 s32 ret_val = -E1000_ERR_PARAM;
354
9d5c8243
AK		 355
356 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 357 hw_dbg("PHY Address %d is out of range\n", offset);
bf6f7a92 358 goto out;
9d5c8243
AK		 359 }
360
bf6f7a92
AD		 361 ret_val = hw->phy.ops.acquire(hw);
362 if (ret_val)
363 goto out;
9d5c8243 364
bf6f7a92 365 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
9d5c8243 366
bf6f7a92
AD		 367 hw->phy.ops.release(hw);
368
369out:
370 return ret_val;
9d5c8243
AK		 371}
372
373/**
733596be 374 * igb_get_phy_id_82575 - Retrieve PHY addr and id
9d5c8243
AK		 375 * @hw: pointer to the HW structure
376 *
652fff32 377 * Retrieves the PHY address and ID for both PHY's which do and do not use
9d5c8243
AK		 378 * sgmi interface.
379 **/
380static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
381{
382 struct e1000_phy_info *phy = &hw->phy;
383 s32 ret_val = 0;
384 u16 phy_id;
2fb02a26 385 u32 ctrl_ext;
9d5c8243
AK		 386
387 /*
388 * For SGMII PHYs, we try the list of possible addresses until
389 * we find one that works. For non-SGMII PHYs
390 * (e.g. integrated copper PHYs), an address of 1 should
391 * work. The result of this function should mean phy->phy_addr
392 * and phy->id are set correctly.
393 */
394 if (!(igb_sgmii_active_82575(hw))) {
395 phy->addr = 1;
396 ret_val = igb_get_phy_id(hw);
397 goto out;
398 }
399
2fb02a26
AD		 400 /* Power on sgmii phy if it is disabled */
401 ctrl_ext = rd32(E1000_CTRL_EXT);
402 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
403 wrfl();
404 msleep(300);
405
9d5c8243
AK		 406 /*
407 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
408 * Therefore, we need to test 1-7
409 */
410 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
411 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
412 if (ret_val == 0) {
652fff32
AK		 413 hw_dbg("Vendor ID 0x%08X read at address %u\n",
414 phy_id, phy->addr);
9d5c8243
AK		 415 /*
416 * At the time of this writing, The M88 part is
417 * the only supported SGMII PHY product.
418 */
419 if (phy_id == M88_VENDOR)
420 break;
421 } else {
652fff32 422 hw_dbg("PHY address %u was unreadable\n", phy->addr);
9d5c8243
AK		 423 }
424 }
425
426 /* A valid PHY type couldn't be found. */
427 if (phy->addr == 8) {
428 phy->addr = 0;
429 ret_val = -E1000_ERR_PHY;
430 goto out;
2fb02a26
AD		 431 } else {
432 ret_val = igb_get_phy_id(hw);
9d5c8243
AK		 433 }
434
2fb02a26
AD		 435 /* restore previous sfp cage power state */
436 wr32(E1000_CTRL_EXT, ctrl_ext);
9d5c8243
AK		 437
438out:
439 return ret_val;
440}
441
442/**
733596be 443 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
9d5c8243
AK		 444 * @hw: pointer to the HW structure
445 *
446 * Resets the PHY using the serial gigabit media independent interface.
447 **/
448static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
449{
450 s32 ret_val;
451
452 /*
453 * This isn't a true "hard" reset, but is the only reset
454 * available to us at this time.
455 */
456
652fff32 457 hw_dbg("Soft resetting SGMII attached PHY...\n");
9d5c8243
AK		 458
459 /*
460 * SFP documentation requires the following to configure the SPF module
461 * to work on SGMII. No further documentation is given.
462 */
a8d2a0c2 463 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
9d5c8243
AK		 464 if (ret_val)
465 goto out;
466
467 ret_val = igb_phy_sw_reset(hw);
468
469out:
470 return ret_val;
471}
472
473/**
733596be 474 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
9d5c8243
AK		 475 * @hw: pointer to the HW structure
476 * @active: true to enable LPLU, false to disable
477 *
478 * Sets the LPLU D0 state according to the active flag. When
479 * activating LPLU this function also disables smart speed
480 * and vice versa. LPLU will not be activated unless the
481 * device autonegotiation advertisement meets standards of
482 * either 10 or 10/100 or 10/100/1000 at all duplexes.
483 * This is a function pointer entry point only called by
484 * PHY setup routines.
485 **/
486static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
487{
488 struct e1000_phy_info *phy = &hw->phy;
489 s32 ret_val;
490 u16 data;
491
a8d2a0c2 492 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
9d5c8243
AK		 493 if (ret_val)
494 goto out;
495
496 if (active) {
497 data |= IGP02E1000_PM_D0_LPLU;
a8d2a0c2 498 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 499 data);
9d5c8243
AK		 500 if (ret_val)
501 goto out;
502
503 /* When LPLU is enabled, we should disable SmartSpeed */
a8d2a0c2 504 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 505 &data);
9d5c8243 506 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 507 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 508 data);
9d5c8243
AK		 509 if (ret_val)
510 goto out;
511 } else {
512 data &= ~IGP02E1000_PM_D0_LPLU;
a8d2a0c2 513 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 514 data);
9d5c8243
AK		 515 /*
516 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
517 * during Dx states where the power conservation is most
518 * important. During driver activity we should enable
519 * SmartSpeed, so performance is maintained.
520 */
521 if (phy->smart_speed == e1000_smart_speed_on) {
a8d2a0c2 522 ret_val = phy->ops.read_reg(hw,
652fff32 523 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 524 if (ret_val)
525 goto out;
526
527 data |= IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 528 ret_val = phy->ops.write_reg(hw,
652fff32 529 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 530 if (ret_val)
531 goto out;
532 } else if (phy->smart_speed == e1000_smart_speed_off) {
a8d2a0c2 533 ret_val = phy->ops.read_reg(hw,
652fff32 534 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 535 if (ret_val)
536 goto out;
537
538 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 539 ret_val = phy->ops.write_reg(hw,
652fff32 540 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 541 if (ret_val)
542 goto out;
543 }
544 }
545
546out:
547 return ret_val;
548}
549
550/**
733596be 551 * igb_acquire_nvm_82575 - Request for access to EEPROM
9d5c8243
AK		 552 * @hw: pointer to the HW structure
553 *
652fff32 554 * Acquire the necessary semaphores for exclusive access to the EEPROM.
9d5c8243
AK		 555 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
556 * Return successful if access grant bit set, else clear the request for
557 * EEPROM access and return -E1000_ERR_NVM (-1).
558 **/
559static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
560{
561 s32 ret_val;
562
563 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
564 if (ret_val)
565 goto out;
566
567 ret_val = igb_acquire_nvm(hw);
568
569 if (ret_val)
570 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
571
572out:
573 return ret_val;
574}
575
576/**
733596be 577 * igb_release_nvm_82575 - Release exclusive access to EEPROM
9d5c8243
AK		 578 * @hw: pointer to the HW structure
579 *
580 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
581 * then release the semaphores acquired.
582 **/
583static void igb_release_nvm_82575(struct e1000_hw *hw)
584{
585 igb_release_nvm(hw);
586 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
587}
588
589/**
733596be 590 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
9d5c8243
AK		 591 * @hw: pointer to the HW structure
592 * @mask: specifies which semaphore to acquire
593 *
594 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
595 * will also specify which port we're acquiring the lock for.
596 **/
597static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
598{
599 u32 swfw_sync;
600 u32 swmask = mask;
601 u32 fwmask = mask << 16;
602 s32 ret_val = 0;
603 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
604
605 while (i < timeout) {
606 if (igb_get_hw_semaphore(hw)) {
607 ret_val = -E1000_ERR_SWFW_SYNC;
608 goto out;
609 }
610
611 swfw_sync = rd32(E1000_SW_FW_SYNC);
612 if (!(swfw_sync & (fwmask | swmask)))
613 break;
614
615 /*
616 * Firmware currently using resource (fwmask)
617 * or other software thread using resource (swmask)
618 */
619 igb_put_hw_semaphore(hw);
620 mdelay(5);
621 i++;
622 }
623
624 if (i == timeout) {
652fff32 625 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
9d5c8243
AK		 626 ret_val = -E1000_ERR_SWFW_SYNC;
627 goto out;
628 }
629
630 swfw_sync |= swmask;
631 wr32(E1000_SW_FW_SYNC, swfw_sync);
632
633 igb_put_hw_semaphore(hw);
634
635out:
636 return ret_val;
637}
638
639/**
733596be 640 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
9d5c8243
AK		 641 * @hw: pointer to the HW structure
642 * @mask: specifies which semaphore to acquire
643 *
644 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
645 * will also specify which port we're releasing the lock for.
646 **/
647static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
648{
649 u32 swfw_sync;
650
651 while (igb_get_hw_semaphore(hw) != 0);
652 /* Empty */
653
654 swfw_sync = rd32(E1000_SW_FW_SYNC);
655 swfw_sync &= ~mask;
656 wr32(E1000_SW_FW_SYNC, swfw_sync);
657
658 igb_put_hw_semaphore(hw);
659}
660
661/**
733596be 662 * igb_get_cfg_done_82575 - Read config done bit
9d5c8243
AK		 663 * @hw: pointer to the HW structure
664 *
665 * Read the management control register for the config done bit for
666 * completion status. NOTE: silicon which is EEPROM-less will fail trying
667 * to read the config done bit, so an error is *ONLY* logged and returns
668 * 0. If we were to return with error, EEPROM-less silicon
669 * would not be able to be reset or change link.
670 **/
671static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
672{
673 s32 timeout = PHY_CFG_TIMEOUT;
674 s32 ret_val = 0;
675 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
676
677 if (hw->bus.func == 1)
678 mask = E1000_NVM_CFG_DONE_PORT_1;
bb2ac47b
AD		 679 else if (hw->bus.func == E1000_FUNC_2)
680 mask = E1000_NVM_CFG_DONE_PORT_2;
681 else if (hw->bus.func == E1000_FUNC_3)
682 mask = E1000_NVM_CFG_DONE_PORT_3;
9d5c8243
AK		 683
684 while (timeout) {
685 if (rd32(E1000_EEMNGCTL) & mask)
686 break;
687 msleep(1);
688 timeout--;
689 }
690 if (!timeout)
652fff32 691 hw_dbg("MNG configuration cycle has not completed.\n");
9d5c8243
AK		 692
693 /* If EEPROM is not marked present, init the PHY manually */
694 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
695 (hw->phy.type == e1000_phy_igp_3))
696 igb_phy_init_script_igp3(hw);
697
698 return ret_val;
699}
700
701/**
733596be 702 * igb_check_for_link_82575 - Check for link
9d5c8243
AK		 703 * @hw: pointer to the HW structure
704 *
705 * If sgmii is enabled, then use the pcs register to determine link, otherwise
706 * use the generic interface for determining link.
707 **/
708static s32 igb_check_for_link_82575(struct e1000_hw *hw)
709{
710 s32 ret_val;
711 u16 speed, duplex;
712
70d92f86 713 if (hw->phy.media_type != e1000_media_type_copper) {
9d5c8243 714 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
2d064c06 715 &duplex);
5d0932a5
AD		 716 /*
717 * Use this flag to determine if link needs to be checked or
718 * not. If we have link clear the flag so that we do not
719 * continue to check for link.
720 */
721 hw->mac.get_link_status = !hw->mac.serdes_has_link;
722 } else {
9d5c8243 723 ret_val = igb_check_for_copper_link(hw);
5d0932a5 724 }
9d5c8243
AK		 725
726 return ret_val;
727}
70d92f86 728
88a268c1
NN		 729/**
730 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
731 * @hw: pointer to the HW structure
732 **/
733void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
734{
735 u32 reg;
736
737
738 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
739 !igb_sgmii_active_82575(hw))
740 return;
741
742 /* Enable PCS to turn on link */
743 reg = rd32(E1000_PCS_CFG0);
744 reg |= E1000_PCS_CFG_PCS_EN;
745 wr32(E1000_PCS_CFG0, reg);
746
747 /* Power up the laser */
748 reg = rd32(E1000_CTRL_EXT);
749 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
750 wr32(E1000_CTRL_EXT, reg);
751
752 /* flush the write to verify completion */
753 wrfl();
754 msleep(1);
755}
756
9d5c8243 757/**
733596be 758 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
9d5c8243
AK		 759 * @hw: pointer to the HW structure
760 * @speed: stores the current speed
761 * @duplex: stores the current duplex
762 *
652fff32 763 * Using the physical coding sub-layer (PCS), retrieve the current speed and
9d5c8243
AK		 764 * duplex, then store the values in the pointers provided.
765 **/
766static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
767 u16 *duplex)
768{
769 struct e1000_mac_info *mac = &hw->mac;
770 u32 pcs;
771
772 /* Set up defaults for the return values of this function */
773 mac->serdes_has_link = false;
774 *speed = 0;
775 *duplex = 0;
776
777 /*
778 * Read the PCS Status register for link state. For non-copper mode,
779 * the status register is not accurate. The PCS status register is
780 * used instead.
781 */
782 pcs = rd32(E1000_PCS_LSTAT);
783
784 /*
785 * The link up bit determines when link is up on autoneg. The sync ok
786 * gets set once both sides sync up and agree upon link. Stable link
787 * can be determined by checking for both link up and link sync ok
788 */
789 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
790 mac->serdes_has_link = true;
791
792 /* Detect and store PCS speed */
793 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
794 *speed = SPEED_1000;
795 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
796 *speed = SPEED_100;
797 } else {
798 *speed = SPEED_10;
799 }
800
801 /* Detect and store PCS duplex */
802 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
803 *duplex = FULL_DUPLEX;
804 } else {
805 *duplex = HALF_DUPLEX;
806 }
807 }
808
809 return 0;
810}
811
2d064c06 812/**
2fb02a26 813 * igb_shutdown_serdes_link_82575 - Remove link during power down
9d5c8243 814 * @hw: pointer to the HW structure
9d5c8243 815 *
2d064c06
AD		 816 * In the case of fiber serdes, shut down optics and PCS on driver unload
817 * when management pass thru is not enabled.
9d5c8243 818 **/
2fb02a26 819void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 820{
2d064c06
AD		 821 u32 reg;
822
53c992fa 823 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
2fb02a26 824 igb_sgmii_active_82575(hw))
2d064c06
AD		 825 return;
826
53c992fa 827 if (!igb_enable_mng_pass_thru(hw)) {
2d064c06
AD		 828 /* Disable PCS to turn off link */
829 reg = rd32(E1000_PCS_CFG0);
830 reg &= ~E1000_PCS_CFG_PCS_EN;
831 wr32(E1000_PCS_CFG0, reg);
832
833 /* shutdown the laser */
834 reg = rd32(E1000_CTRL_EXT);
2fb02a26 835 reg |= E1000_CTRL_EXT_SDP3_DATA;
2d064c06
AD		 836 wr32(E1000_CTRL_EXT, reg);
837
838 /* flush the write to verify completion */
839 wrfl();
840 msleep(1);
841 }
9d5c8243
AK		 842}
843
844/**
733596be 845 * igb_reset_hw_82575 - Reset hardware
9d5c8243
AK		 846 * @hw: pointer to the HW structure
847 *
848 * This resets the hardware into a known state. This is a
849 * function pointer entry point called by the api module.
850 **/
851static s32 igb_reset_hw_82575(struct e1000_hw *hw)
852{
853 u32 ctrl, icr;
854 s32 ret_val;
855
856 /*
857 * Prevent the PCI-E bus from sticking if there is no TLP connection
858 * on the last TLP read/write transaction when MAC is reset.
859 */
860 ret_val = igb_disable_pcie_master(hw);
861 if (ret_val)
652fff32 862 hw_dbg("PCI-E Master disable polling has failed.\n");
9d5c8243 863
009bc06e
AD		 864 /* set the completion timeout for interface */
865 ret_val = igb_set_pcie_completion_timeout(hw);
866 if (ret_val) {
867 hw_dbg("PCI-E Set completion timeout has failed.\n");
868 }
869
652fff32 870 hw_dbg("Masking off all interrupts\n");
9d5c8243
AK		 871 wr32(E1000_IMC, 0xffffffff);
872
873 wr32(E1000_RCTL, 0);
874 wr32(E1000_TCTL, E1000_TCTL_PSP);
875 wrfl();
876
877 msleep(10);
878
879 ctrl = rd32(E1000_CTRL);
880
652fff32 881 hw_dbg("Issuing a global reset to MAC\n");
9d5c8243
AK		 882 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
883
884 ret_val = igb_get_auto_rd_done(hw);
885 if (ret_val) {
886 /*
887 * When auto config read does not complete, do not
888 * return with an error. This can happen in situations
889 * where there is no eeprom and prevents getting link.
890 */
652fff32 891 hw_dbg("Auto Read Done did not complete\n");
9d5c8243
AK		 892 }
893
894 /* If EEPROM is not present, run manual init scripts */
895 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
896 igb_reset_init_script_82575(hw);
897
898 /* Clear any pending interrupt events. */
899 wr32(E1000_IMC, 0xffffffff);
900 icr = rd32(E1000_ICR);
901
5ac16659
AD		 902 /* Install any alternate MAC address into RAR0 */
903 ret_val = igb_check_alt_mac_addr(hw);
9d5c8243
AK		 904
905 return ret_val;
906}
907
908/**
733596be 909 * igb_init_hw_82575 - Initialize hardware
9d5c8243
AK		 910 * @hw: pointer to the HW structure
911 *
912 * This inits the hardware readying it for operation.
913 **/
914static s32 igb_init_hw_82575(struct e1000_hw *hw)
915{
916 struct e1000_mac_info *mac = &hw->mac;
917 s32 ret_val;
918 u16 i, rar_count = mac->rar_entry_count;
919
920 /* Initialize identification LED */
921 ret_val = igb_id_led_init(hw);
922 if (ret_val) {
652fff32 923 hw_dbg("Error initializing identification LED\n");
9d5c8243
AK		 924 /* This is not fatal and we should not stop init due to this */
925 }
926
927 /* Disabling VLAN filtering */
652fff32 928 hw_dbg("Initializing the IEEE VLAN\n");
9d5c8243
AK		 929 igb_clear_vfta(hw);
930
931 /* Setup the receive address */
5ac16659
AD		 932 igb_init_rx_addrs(hw, rar_count);
933
9d5c8243 934 /* Zero out the Multicast HASH table */
652fff32 935 hw_dbg("Zeroing the MTA\n");
9d5c8243
AK		 936 for (i = 0; i < mac->mta_reg_count; i++)
937 array_wr32(E1000_MTA, i, 0);
938
68d480c4
AD		 939 /* Zero out the Unicast HASH table */
940 hw_dbg("Zeroing the UTA\n");
941 for (i = 0; i < mac->uta_reg_count; i++)
942 array_wr32(E1000_UTA, i, 0);
943
9d5c8243
AK		 944 /* Setup link and flow control */
945 ret_val = igb_setup_link(hw);
946
947 /*
948 * Clear all of the statistics registers (clear on read). It is
949 * important that we do this after we have tried to establish link
950 * because the symbol error count will increment wildly if there
951 * is no link.
952 */
953 igb_clear_hw_cntrs_82575(hw);
954
955 return ret_val;
956}
957
958/**
733596be 959 * igb_setup_copper_link_82575 - Configure copper link settings
9d5c8243
AK		 960 * @hw: pointer to the HW structure
961 *
962 * Configures the link for auto-neg or forced speed and duplex. Then we check
963 * for link, once link is established calls to configure collision distance
964 * and flow control are called.
965 **/
966static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
967{
12645a19 968 u32 ctrl;
9d5c8243 969 s32 ret_val;
9d5c8243
AK		 970
971 ctrl = rd32(E1000_CTRL);
972 ctrl |= E1000_CTRL_SLU;
973 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
974 wr32(E1000_CTRL, ctrl);
975
2fb02a26
AD		 976 ret_val = igb_setup_serdes_link_82575(hw);
977 if (ret_val)
978 goto out;
979
980 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
bb2ac47b
AD		 981 /* allow time for SFP cage time to power up phy */
982 msleep(300);
983
2fb02a26
AD		 984 ret_val = hw->phy.ops.reset(hw);
985 if (ret_val) {
986 hw_dbg("Error resetting the PHY.\n");
987 goto out;
988 }
989 }
9d5c8243
AK		 990 switch (hw->phy.type) {
991 case e1000_phy_m88:
992 ret_val = igb_copper_link_setup_m88(hw);
993 break;
994 case e1000_phy_igp_3:
995 ret_val = igb_copper_link_setup_igp(hw);
9d5c8243 996 break;
bb2ac47b
AD		 997 case e1000_phy_82580:
998 ret_val = igb_copper_link_setup_82580(hw);
999 break;
9d5c8243
AK		 1000 default:
1001 ret_val = -E1000_ERR_PHY;
1002 break;
1003 }
1004
1005 if (ret_val)
1006 goto out;
1007
81fadd81 1008 ret_val = igb_setup_copper_link(hw);
9d5c8243
AK		 1009out:
1010 return ret_val;
1011}
1012
1013/**
70d92f86 1014 * igb_setup_serdes_link_82575 - Setup link for serdes
9d5c8243
AK		 1015 * @hw: pointer to the HW structure
1016 *
70d92f86
AD		 1017 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1018 * used on copper connections where the serialized gigabit media independent
1019 * interface (sgmii), or serdes fiber is being used. Configures the link
1020 * for auto-negotiation or forces speed/duplex.
9d5c8243 1021 **/
2fb02a26 1022static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1023{
bb2ac47b
AD		 1024 u32 ctrl_ext, ctrl_reg, reg;
1025 bool pcs_autoneg;
2fb02a26
AD		 1026
1027 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1028 !igb_sgmii_active_82575(hw))
1029 return 0;
9d5c8243
AK		 1030
1031 /*
1032 * On the 82575, SerDes loopback mode persists until it is
1033 * explicitly turned off or a power cycle is performed. A read to
1034 * the register does not indicate its status. Therefore, we ensure
1035 * loopback mode is disabled during initialization.
1036 */
1037 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1038
2fb02a26 1039 /* power on the sfp cage if present */
bb2ac47b
AD		 1040 ctrl_ext = rd32(E1000_CTRL_EXT);
1041 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1042 wr32(E1000_CTRL_EXT, ctrl_ext);
2fb02a26
AD		 1043
1044 ctrl_reg = rd32(E1000_CTRL);
1045 ctrl_reg |= E1000_CTRL_SLU;
1046
1047 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1048 /* set both sw defined pins */
1049 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1050
1051 /* Set switch control to serdes energy detect */
1052 reg = rd32(E1000_CONNSW);
1053 reg |= E1000_CONNSW_ENRGSRC;
1054 wr32(E1000_CONNSW, reg);
1055 }
1056
1057 reg = rd32(E1000_PCS_LCTL);
1058
bb2ac47b
AD		 1059 /* default pcs_autoneg to the same setting as mac autoneg */
1060 pcs_autoneg = hw->mac.autoneg;
2fb02a26 1061
bb2ac47b
AD		 1062 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1063 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1064 /* sgmii mode lets the phy handle forcing speed/duplex */
1065 pcs_autoneg = true;
1066 /* autoneg time out should be disabled for SGMII mode */
2fb02a26 1067 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
bb2ac47b
AD		 1068 break;
1069 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1070 /* disable PCS autoneg and support parallel detect only */
1071 pcs_autoneg = false;
1072 default:
1073 /*
1074 * non-SGMII modes only supports a speed of 1000/Full for the
1075 * link so it is best to just force the MAC and let the pcs
1076 * link either autoneg or be forced to 1000/Full
1077 */
2fb02a26
AD		 1078 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1079 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
bb2ac47b
AD		 1080
1081 /* set speed of 1000/Full if speed/duplex is forced */
1082 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1083 break;
921aa749
AD		 1084 }
1085
2fb02a26 1086 wr32(E1000_CTRL, ctrl_reg);
9d5c8243
AK		 1087
1088 /*
1089 * New SerDes mode allows for forcing speed or autonegotiating speed
1090 * at 1gb. Autoneg should be default set by most drivers. This is the
1091 * mode that will be compatible with older link partners and switches.
1092 * However, both are supported by the hardware and some drivers/tools.
1093 */
9d5c8243
AK		 1094 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1095 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1096
2fb02a26
AD		 1097 /*
1098 * We force flow control to prevent the CTRL register values from being
1099 * overwritten by the autonegotiated flow control values
1100 */
1101 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1102
bb2ac47b 1103 if (pcs_autoneg) {
9d5c8243 1104 /* Set PCS register for autoneg */
bb2ac47b 1105 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
70d92f86 1106 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
bb2ac47b 1107 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1108 } else {
bb2ac47b 1109 /* Set PCS register for forced link */
d68caec6 1110 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
bb2ac47b
AD		 1111
1112 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1113 }
726c09e7 1114
9d5c8243
AK		 1115 wr32(E1000_PCS_LCTL, reg);
1116
2fb02a26
AD		 1117 if (!igb_sgmii_active_82575(hw))
1118 igb_force_mac_fc(hw);
9d5c8243 1119
2fb02a26 1120 return 0;
9d5c8243
AK		 1121}
1122
1123/**
733596be 1124 * igb_sgmii_active_82575 - Return sgmii state
9d5c8243
AK		 1125 * @hw: pointer to the HW structure
1126 *
1127 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1128 * which can be enabled for use in the embedded applications. Simply
1129 * return the current state of the sgmii interface.
1130 **/
1131static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1132{
c1889bfe 1133 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
c1889bfe 1134 return dev_spec->sgmii_active;
9d5c8243
AK		 1135}
1136
1137/**
733596be 1138 * igb_reset_init_script_82575 - Inits HW defaults after reset
9d5c8243
AK		 1139 * @hw: pointer to the HW structure
1140 *
1141 * Inits recommended HW defaults after a reset when there is no EEPROM
1142 * detected. This is only for the 82575.
1143 **/
1144static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1145{
1146 if (hw->mac.type == e1000_82575) {
652fff32 1147 hw_dbg("Running reset init script for 82575\n");
9d5c8243
AK		 1148 /* SerDes configuration via SERDESCTRL */
1149 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1150 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1151 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1152 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1153
1154 /* CCM configuration via CCMCTL register */
1155 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1156 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1157
1158 /* PCIe lanes configuration */
1159 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1160 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1161 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1162 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1163
1164 /* PCIe PLL Configuration */
1165 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1166 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1167 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1168 }
1169
1170 return 0;
1171}
1172
1173/**
733596be 1174 * igb_read_mac_addr_82575 - Read device MAC address
9d5c8243
AK		 1175 * @hw: pointer to the HW structure
1176 **/
1177static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1178{
1179 s32 ret_val = 0;
1180
22896639
AD		 1181 /*
1182 * If there's an alternate MAC address place it in RAR0
1183 * so that it will override the Si installed default perm
1184 * address.
1185 */
1186 ret_val = igb_check_alt_mac_addr(hw);
1187 if (ret_val)
1188 goto out;
1189
1190 ret_val = igb_read_mac_addr(hw);
9d5c8243 1191
22896639 1192out:
9d5c8243
AK		 1193 return ret_val;
1194}
1195
88a268c1
NN		 1196/**
1197 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1198 * @hw: pointer to the HW structure
1199 *
1200 * In the case of a PHY power down to save power, or to turn off link during a
1201 * driver unload, or wake on lan is not enabled, remove the link.
1202 **/
1203void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1204{
1205 /* If the management interface is not enabled, then power down */
1206 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1207 igb_power_down_phy_copper(hw);
1208
1209 return;
1210}
1211
9d5c8243 1212/**
733596be 1213 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
9d5c8243
AK		 1214 * @hw: pointer to the HW structure
1215 *
1216 * Clears the hardware counters by reading the counter registers.
1217 **/
1218static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1219{
9d5c8243
AK		 1220 igb_clear_hw_cntrs_base(hw);
1221
cc9073bb
AD		 1222 rd32(E1000_PRC64);
1223 rd32(E1000_PRC127);
1224 rd32(E1000_PRC255);
1225 rd32(E1000_PRC511);
1226 rd32(E1000_PRC1023);
1227 rd32(E1000_PRC1522);
1228 rd32(E1000_PTC64);
1229 rd32(E1000_PTC127);
1230 rd32(E1000_PTC255);
1231 rd32(E1000_PTC511);
1232 rd32(E1000_PTC1023);
1233 rd32(E1000_PTC1522);
1234
1235 rd32(E1000_ALGNERRC);
1236 rd32(E1000_RXERRC);
1237 rd32(E1000_TNCRS);
1238 rd32(E1000_CEXTERR);
1239 rd32(E1000_TSCTC);
1240 rd32(E1000_TSCTFC);
1241
1242 rd32(E1000_MGTPRC);
1243 rd32(E1000_MGTPDC);
1244 rd32(E1000_MGTPTC);
1245
1246 rd32(E1000_IAC);
1247 rd32(E1000_ICRXOC);
1248
1249 rd32(E1000_ICRXPTC);
1250 rd32(E1000_ICRXATC);
1251 rd32(E1000_ICTXPTC);
1252 rd32(E1000_ICTXATC);
1253 rd32(E1000_ICTXQEC);
1254 rd32(E1000_ICTXQMTC);
1255 rd32(E1000_ICRXDMTC);
1256
1257 rd32(E1000_CBTMPC);
1258 rd32(E1000_HTDPMC);
1259 rd32(E1000_CBRMPC);
1260 rd32(E1000_RPTHC);
1261 rd32(E1000_HGPTC);
1262 rd32(E1000_HTCBDPC);
1263 rd32(E1000_HGORCL);
1264 rd32(E1000_HGORCH);
1265 rd32(E1000_HGOTCL);
1266 rd32(E1000_HGOTCH);
1267 rd32(E1000_LENERRS);
9d5c8243
AK		 1268
1269 /* This register should not be read in copper configurations */
2fb02a26
AD		 1270 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1271 igb_sgmii_active_82575(hw))
cc9073bb 1272 rd32(E1000_SCVPC);
9d5c8243
AK		 1273}
1274
662d7205
AD		 1275/**
1276 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1277 * @hw: pointer to the HW structure
1278 *
1279 * After rx enable if managability is enabled then there is likely some
1280 * bad data at the start of the fifo and possibly in the DMA fifo. This
1281 * function clears the fifos and flushes any packets that came in as rx was
1282 * being enabled.
1283 **/
1284void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1285{
1286 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1287 int i, ms_wait;
1288
1289 if (hw->mac.type != e1000_82575 ||
1290 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1291 return;
1292
1293 /* Disable all RX queues */
1294 for (i = 0; i < 4; i++) {
1295 rxdctl[i] = rd32(E1000_RXDCTL(i));
1296 wr32(E1000_RXDCTL(i),
1297 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1298 }
1299 /* Poll all queues to verify they have shut down */
1300 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1301 msleep(1);
1302 rx_enabled = 0;
1303 for (i = 0; i < 4; i++)
1304 rx_enabled |= rd32(E1000_RXDCTL(i));
1305 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1306 break;
1307 }
1308
1309 if (ms_wait == 10)
1310 hw_dbg("Queue disable timed out after 10ms\n");
1311
1312 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1313 * incoming packets are rejected. Set enable and wait 2ms so that
1314 * any packet that was coming in as RCTL.EN was set is flushed
1315 */
1316 rfctl = rd32(E1000_RFCTL);
1317 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1318
1319 rlpml = rd32(E1000_RLPML);
1320 wr32(E1000_RLPML, 0);
1321
1322 rctl = rd32(E1000_RCTL);
1323 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1324 temp_rctl |= E1000_RCTL_LPE;
1325
1326 wr32(E1000_RCTL, temp_rctl);
1327 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1328 wrfl();
1329 msleep(2);
1330
1331 /* Enable RX queues that were previously enabled and restore our
1332 * previous state
1333 */
1334 for (i = 0; i < 4; i++)
1335 wr32(E1000_RXDCTL(i), rxdctl[i]);
1336 wr32(E1000_RCTL, rctl);
1337 wrfl();
1338
1339 wr32(E1000_RLPML, rlpml);
1340 wr32(E1000_RFCTL, rfctl);
1341
1342 /* Flush receive errors generated by workaround */
1343 rd32(E1000_ROC);
1344 rd32(E1000_RNBC);
1345 rd32(E1000_MPC);
1346}
1347
009bc06e
AD		 1348/**
1349 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1350 * @hw: pointer to the HW structure
1351 *
1352 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1353 * however the hardware default for these parts is 500us to 1ms which is less
1354 * than the 10ms recommended by the pci-e spec. To address this we need to
1355 * increase the value to either 10ms to 200ms for capability version 1 config,
1356 * or 16ms to 55ms for version 2.
1357 **/
1358static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1359{
1360 u32 gcr = rd32(E1000_GCR);
1361 s32 ret_val = 0;
1362 u16 pcie_devctl2;
1363
1364 /* only take action if timeout value is defaulted to 0 */
1365 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1366 goto out;
1367
1368 /*
1369 * if capababilities version is type 1 we can write the
1370 * timeout of 10ms to 200ms through the GCR register
1371 */
1372 if (!(gcr & E1000_GCR_CAP_VER2)) {
1373 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1374 goto out;
1375 }
1376
1377 /*
1378 * for version 2 capabilities we need to write the config space
1379 * directly in order to set the completion timeout value for
1380 * 16ms to 55ms
1381 */
1382 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1383 &pcie_devctl2);
1384 if (ret_val)
1385 goto out;
1386
1387 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1388
1389 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1390 &pcie_devctl2);
1391out:
1392 /* disable completion timeout resend */
1393 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1394
1395 wr32(E1000_GCR, gcr);
1396 return ret_val;
1397}
1398
4ae196df
AD		 1399/**
1400 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1401 * @hw: pointer to the hardware struct
1402 * @enable: state to enter, either enabled or disabled
1403 *
1404 * enables/disables L2 switch loopback functionality.
1405 **/
1406void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1407{
1408 u32 dtxswc = rd32(E1000_DTXSWC);
1409
1410 if (enable)
1411 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1412 else
1413 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1414
1415 wr32(E1000_DTXSWC, dtxswc);
1416}
1417
1418/**
1419 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1420 * @hw: pointer to the hardware struct
1421 * @enable: state to enter, either enabled or disabled
1422 *
1423 * enables/disables replication of packets across multiple pools.
1424 **/
1425void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1426{
1427 u32 vt_ctl = rd32(E1000_VT_CTL);
1428
1429 if (enable)
1430 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1431 else
1432 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1433
1434 wr32(E1000_VT_CTL, vt_ctl);
1435}
1436
bb2ac47b
AD		 1437/**
1438 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1439 * @hw: pointer to the HW structure
1440 * @offset: register offset to be read
1441 * @data: pointer to the read data
1442 *
1443 * Reads the MDI control register in the PHY at offset and stores the
1444 * information read to data.
1445 **/
1446static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1447{
1448 u32 mdicnfg = 0;
1449 s32 ret_val;
1450
1451
1452 ret_val = hw->phy.ops.acquire(hw);
1453 if (ret_val)
1454 goto out;
1455
1456 /*
1457 * We config the phy address in MDICNFG register now. Same bits
1458 * as before. The values in MDIC can be written but will be
1459 * ignored. This allows us to call the old function after
1460 * configuring the PHY address in the new register
1461 */
1462 mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1463 wr32(E1000_MDICNFG, mdicnfg);
1464
1465 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1466
1467 hw->phy.ops.release(hw);
1468
1469out:
1470 return ret_val;
1471}
1472
1473/**
1474 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1475 * @hw: pointer to the HW structure
1476 * @offset: register offset to write to
1477 * @data: data to write to register at offset
1478 *
1479 * Writes data to MDI control register in the PHY at offset.
1480 **/
1481static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1482{
1483 u32 mdicnfg = 0;
1484 s32 ret_val;
1485
1486
1487 ret_val = hw->phy.ops.acquire(hw);
1488 if (ret_val)
1489 goto out;
1490
1491 /*
1492 * We config the phy address in MDICNFG register now. Same bits
1493 * as before. The values in MDIC can be written but will be
1494 * ignored. This allows us to call the old function after
1495 * configuring the PHY address in the new register
1496 */
1497 mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1498 wr32(E1000_MDICNFG, mdicnfg);
1499
1500 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1501
1502 hw->phy.ops.release(hw);
1503
1504out:
1505 return ret_val;
1506}
1507
1508/**
1509 * igb_reset_hw_82580 - Reset hardware
1510 * @hw: pointer to the HW structure
1511 *
1512 * This resets function or entire device (all ports, etc.)
1513 * to a known state.
1514 **/
1515static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1516{
1517 s32 ret_val = 0;
1518 /* BH SW mailbox bit in SW_FW_SYNC */
1519 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1520 u32 ctrl, icr;
1521 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1522
1523
1524 hw->dev_spec._82575.global_device_reset = false;
1525
1526 /* Get current control state. */
1527 ctrl = rd32(E1000_CTRL);
1528
1529 /*
1530 * Prevent the PCI-E bus from sticking if there is no TLP connection
1531 * on the last TLP read/write transaction when MAC is reset.
1532 */
1533 ret_val = igb_disable_pcie_master(hw);
1534 if (ret_val)
1535 hw_dbg("PCI-E Master disable polling has failed.\n");
1536
1537 hw_dbg("Masking off all interrupts\n");
1538 wr32(E1000_IMC, 0xffffffff);
1539 wr32(E1000_RCTL, 0);
1540 wr32(E1000_TCTL, E1000_TCTL_PSP);
1541 wrfl();
1542
1543 msleep(10);
1544
1545 /* Determine whether or not a global dev reset is requested */
1546 if (global_device_reset &&
1547 igb_acquire_swfw_sync_82575(hw, swmbsw_mask))
1548 global_device_reset = false;
1549
1550 if (global_device_reset &&
1551 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1552 ctrl |= E1000_CTRL_DEV_RST;
1553 else
1554 ctrl |= E1000_CTRL_RST;
1555
1556 wr32(E1000_CTRL, ctrl);
1557
1558 /* Add delay to insure DEV_RST has time to complete */
1559 if (global_device_reset)
1560 msleep(5);
1561
1562 ret_val = igb_get_auto_rd_done(hw);
1563 if (ret_val) {
1564 /*
1565 * When auto config read does not complete, do not
1566 * return with an error. This can happen in situations
1567 * where there is no eeprom and prevents getting link.
1568 */
1569 hw_dbg("Auto Read Done did not complete\n");
1570 }
1571
1572 /* If EEPROM is not present, run manual init scripts */
1573 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1574 igb_reset_init_script_82575(hw);
1575
1576 /* clear global device reset status bit */
1577 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
1578
1579 /* Clear any pending interrupt events. */
1580 wr32(E1000_IMC, 0xffffffff);
1581 icr = rd32(E1000_ICR);
1582
1583 /* Install any alternate MAC address into RAR0 */
1584 ret_val = igb_check_alt_mac_addr(hw);
1585
1586 /* Release semaphore */
1587 if (global_device_reset)
1588 igb_release_swfw_sync_82575(hw, swmbsw_mask);
1589
1590 return ret_val;
1591}
1592
1593/**
1594 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1595 * @data: data received by reading RXPBS register
1596 *
1597 * The 82580 uses a table based approach for packet buffer allocation sizes.
1598 * This function converts the retrieved value into the correct table value
1599 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1600 * 0x0 36 72 144 1 2 4 8 16
1601 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1602 */
1603u16 igb_rxpbs_adjust_82580(u32 data)
1604{
1605 u16 ret_val = 0;
1606
1607 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1608 ret_val = e1000_82580_rxpbs_table[data];
1609
1610 return ret_val;
1611}
1612
9d5c8243 1613static struct e1000_mac_operations e1000_mac_ops_82575 = {
9d5c8243
AK		 1614 .init_hw = igb_init_hw_82575,
1615 .check_for_link = igb_check_for_link_82575,
2d064c06 1616 .rar_set = igb_rar_set,
9d5c8243
AK		 1617 .read_mac_addr = igb_read_mac_addr_82575,
1618 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1619};
1620
1621static struct e1000_phy_operations e1000_phy_ops_82575 = {
a8d2a0c2 1622 .acquire = igb_acquire_phy_82575,
9d5c8243 1623 .get_cfg_done = igb_get_cfg_done_82575,
a8d2a0c2 1624 .release = igb_release_phy_82575,
9d5c8243
AK		 1625};
1626
1627static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
312c75ae
AD		 1628 .acquire = igb_acquire_nvm_82575,
1629 .read = igb_read_nvm_eerd,
1630 .release = igb_release_nvm_82575,
1631 .write = igb_write_nvm_spi,
9d5c8243
AK		 1632};
1633
1634const struct e1000_info e1000_82575_info = {
1635 .get_invariants = igb_get_invariants_82575,
1636 .mac_ops = &e1000_mac_ops_82575,
1637 .phy_ops = &e1000_phy_ops_82575,
1638 .nvm_ops = &e1000_nvm_ops_82575,
1639};
1640
kernel source for telekom puls (alcatel/mediatek)