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baycom: Drop __TIME__ usage
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / hamradio / baycom_ser_hdx.c
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1da177e4
LT		 1/*****************************************************************************/
2
3/*
4 * baycom_ser_hdx.c -- baycom ser12 halfduplex radio modem driver.
5 *
6 * Copyright (C) 1996-2000 Thomas Sailer (sailer@ife.ee.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Please note that the GPL allows you to use the driver, NOT the radio.
23 * In order to use the radio, you need a license from the communications
24 * authority of your country.
25 *
26 *
27 * Supported modems
28 *
29 * ser12: This is a very simple 1200 baud AFSK modem. The modem consists only
30 * of a modulator/demodulator chip, usually a TI TCM3105. The computer
31 * is responsible for regenerating the receiver bit clock, as well as
32 * for handling the HDLC protocol. The modem connects to a serial port,
33 * hence the name. Since the serial port is not used as an async serial
34 * port, the kernel driver for serial ports cannot be used, and this
35 * driver only supports standard serial hardware (8250, 16450, 16550A)
36 *
37 *
38 * Command line options (insmod command line)
39 *
40 * mode ser12 hardware DCD
41 * ser12* software DCD
42 * ser12@ hardware/software DCD, i.e. no explicit DCD signal but hardware
43 * mutes audio input to the modem
44 * ser12+ hardware DCD, inverted signal at DCD pin
45 * iobase base address of the port; common values are 0x3f8, 0x2f8, 0x3e8, 0x2e8
46 * irq interrupt line of the port; common values are 4,3
47 *
48 *
49 * History:
50 * 0.1 26.06.1996 Adapted from baycom.c and made network driver interface
51 * 18.10.1996 Changed to new user space access routines (copy_{to,from}_user)
52 * 0.3 26.04.1997 init code/data tagged
53 * 0.4 08.07.1997 alternative ser12 decoding algorithm (uses delta CTS ints)
54 * 0.5 11.11.1997 ser12/par96 split into separate files
55 * 0.6 14.04.1998 cleanups
56 * 0.7 03.08.1999 adapt to Linus' new __setup/__initcall
57 * 0.8 10.08.1999 use module_init/module_exit
58 * 0.9 12.02.2000 adapted to softnet driver interface
59 * 0.10 03.07.2000 fix interface name handling
60 */
61
62/*****************************************************************************/
63
d43c36dc 64#include <linux/capability.h>
1da177e4
LT		 65#include <linux/module.h>
66#include <linux/ioport.h>
67#include <linux/string.h>
68#include <linux/init.h>
69#include <asm/uaccess.h>
70#include <asm/io.h>
71#include <linux/hdlcdrv.h>
72#include <linux/baycom.h>
cd8749b4 73#include <linux/jiffies.h>
1da177e4
LT		 74
75/* --------------------------------------------------------------------- */
76
77#define BAYCOM_DEBUG
78
79/* --------------------------------------------------------------------- */
80
81static const char bc_drvname[] = "baycom_ser_hdx";
82static const char bc_drvinfo[] = KERN_INFO "baycom_ser_hdx: (C) 1996-2000 Thomas Sailer, HB9JNX/AE4WA\n"
c1afba3c 83"baycom_ser_hdx: version 0.10\n";
1da177e4
LT		 84
85/* --------------------------------------------------------------------- */
86
87#define NR_PORTS 4
88
89static struct net_device *baycom_device[NR_PORTS];
90
91/* --------------------------------------------------------------------- */
92
93#define RBR(iobase) (iobase+0)
94#define THR(iobase) (iobase+0)
95#define IER(iobase) (iobase+1)
96#define IIR(iobase) (iobase+2)
97#define FCR(iobase) (iobase+2)
98#define LCR(iobase) (iobase+3)
99#define MCR(iobase) (iobase+4)
100#define LSR(iobase) (iobase+5)
101#define MSR(iobase) (iobase+6)
102#define SCR(iobase) (iobase+7)
103#define DLL(iobase) (iobase+0)
104#define DLM(iobase) (iobase+1)
105
106#define SER12_EXTENT 8
107
108/* ---------------------------------------------------------------------- */
109/*
110 * Information that need to be kept for each board.
111 */
112
113struct baycom_state {
114 struct hdlcdrv_state hdrv;
115
116 int opt_dcd;
117
118 struct modem_state {
119 short arb_divider;
120 unsigned char flags;
121 unsigned int shreg;
122 struct modem_state_ser12 {
123 unsigned char tx_bit;
124 int dcd_sum0, dcd_sum1, dcd_sum2;
125 unsigned char last_sample;
126 unsigned char last_rxbit;
127 unsigned int dcd_shreg;
128 unsigned int dcd_time;
129 unsigned int bit_pll;
130 unsigned char interm_sample;
131 } ser12;
132 } modem;
133
134#ifdef BAYCOM_DEBUG
135 struct debug_vals {
136 unsigned long last_jiffies;
137 unsigned cur_intcnt;
138 unsigned last_intcnt;
139 int cur_pllcorr;
140 int last_pllcorr;
141 } debug_vals;
142#endif /* BAYCOM_DEBUG */
143};
144
145/* --------------------------------------------------------------------- */
146
147static inline void baycom_int_freq(struct baycom_state *bc)
148{
149#ifdef BAYCOM_DEBUG
150 unsigned long cur_jiffies = jiffies;
151 /*
152 * measure the interrupt frequency
153 */
154 bc->debug_vals.cur_intcnt++;
cd8749b4 155 if (time_after_eq(cur_jiffies, bc->debug_vals.last_jiffies + HZ)) {
1da177e4
LT		 156 bc->debug_vals.last_jiffies = cur_jiffies;
157 bc->debug_vals.last_intcnt = bc->debug_vals.cur_intcnt;
158 bc->debug_vals.cur_intcnt = 0;
159 bc->debug_vals.last_pllcorr = bc->debug_vals.cur_pllcorr;
160 bc->debug_vals.cur_pllcorr = 0;
161 }
162#endif /* BAYCOM_DEBUG */
163}
164
165/* --------------------------------------------------------------------- */
166/*
167 * ===================== SER12 specific routines =========================
168 */
169
170static inline void ser12_set_divisor(struct net_device *dev,
171 unsigned char divisor)
172{
173 outb(0x81, LCR(dev->base_addr)); /* DLAB = 1 */
174 outb(divisor, DLL(dev->base_addr));
175 outb(0, DLM(dev->base_addr));
176 outb(0x01, LCR(dev->base_addr)); /* word length = 6 */
177 /*
178 * make sure the next interrupt is generated;
179 * 0 must be used to power the modem; the modem draws its
180 * power from the TxD line
181 */
182 outb(0x00, THR(dev->base_addr));
183 /*
184 * it is important not to set the divider while transmitting;
185 * this reportedly makes some UARTs generating interrupts
186 * in the hundredthousands per second region
187 * Reported by: Ignacio.Arenaza@studi.epfl.ch (Ignacio Arenaza Nuno)
188 */
189}
190
191/* --------------------------------------------------------------------- */
192
193/*
194 * must call the TX arbitrator every 10ms
195 */
196#define SER12_ARB_DIVIDER(bc) (bc->opt_dcd ? 24 : 36)
197
198#define SER12_DCD_INTERVAL(bc) (bc->opt_dcd ? 12 : 240)
199
200static inline void ser12_tx(struct net_device *dev, struct baycom_state *bc)
201{
202 /* one interrupt per channel bit */
203 ser12_set_divisor(dev, 12);
204 /*
205 * first output the last bit (!) then call HDLC transmitter,
206 * since this may take quite long
207 */
208 outb(0x0e | (!!bc->modem.ser12.tx_bit), MCR(dev->base_addr));
209 if (bc->modem.shreg <= 1)
210 bc->modem.shreg = 0x10000 | hdlcdrv_getbits(&bc->hdrv);
211 bc->modem.ser12.tx_bit = !(bc->modem.ser12.tx_bit ^
212 (bc->modem.shreg & 1));
213 bc->modem.shreg >>= 1;
214}
215
216/* --------------------------------------------------------------------- */
217
218static inline void ser12_rx(struct net_device *dev, struct baycom_state *bc)
219{
220 unsigned char cur_s;
221 /*
222 * do demodulator
223 */
224 cur_s = inb(MSR(dev->base_addr)) & 0x10; /* the CTS line */
225 hdlcdrv_channelbit(&bc->hdrv, cur_s);
226 bc->modem.ser12.dcd_shreg = (bc->modem.ser12.dcd_shreg << 1) |
227 (cur_s != bc->modem.ser12.last_sample);
228 bc->modem.ser12.last_sample = cur_s;
229 if(bc->modem.ser12.dcd_shreg & 1) {
230 if (!bc->opt_dcd) {
231 unsigned int dcdspos, dcdsneg;
232
233 dcdspos = dcdsneg = 0;
234 dcdspos += ((bc->modem.ser12.dcd_shreg >> 1) & 1);
235 if (!(bc->modem.ser12.dcd_shreg & 0x7ffffffe))
236 dcdspos += 2;
237 dcdsneg += ((bc->modem.ser12.dcd_shreg >> 2) & 1);
238 dcdsneg += ((bc->modem.ser12.dcd_shreg >> 3) & 1);
239 dcdsneg += ((bc->modem.ser12.dcd_shreg >> 4) & 1);
240
241 bc->modem.ser12.dcd_sum0 += 16*dcdspos - dcdsneg;
242 } else
243 bc->modem.ser12.dcd_sum0--;
244 }
245 if(!bc->modem.ser12.dcd_time) {
246 hdlcdrv_setdcd(&bc->hdrv, (bc->modem.ser12.dcd_sum0 +
247 bc->modem.ser12.dcd_sum1 +
248 bc->modem.ser12.dcd_sum2) < 0);
249 bc->modem.ser12.dcd_sum2 = bc->modem.ser12.dcd_sum1;
250 bc->modem.ser12.dcd_sum1 = bc->modem.ser12.dcd_sum0;
251 /* offset to ensure DCD off on silent input */
252 bc->modem.ser12.dcd_sum0 = 2;
253 bc->modem.ser12.dcd_time = SER12_DCD_INTERVAL(bc);
254 }
255 bc->modem.ser12.dcd_time--;
256 if (!bc->opt_dcd) {
257 /*
258 * PLL code for the improved software DCD algorithm
259 */
260 if (bc->modem.ser12.interm_sample) {
261 /*
262 * intermediate sample; set timing correction to normal
263 */
264 ser12_set_divisor(dev, 4);
265 } else {
266 /*
267 * do PLL correction and call HDLC receiver
268 */
269 switch (bc->modem.ser12.dcd_shreg & 7) {
270 case 1: /* transition too late */
271 ser12_set_divisor(dev, 5);
272#ifdef BAYCOM_DEBUG
273 bc->debug_vals.cur_pllcorr++;
274#endif /* BAYCOM_DEBUG */
275 break;
276 case 4: /* transition too early */
277 ser12_set_divisor(dev, 3);
278#ifdef BAYCOM_DEBUG
279 bc->debug_vals.cur_pllcorr--;
280#endif /* BAYCOM_DEBUG */
281 break;
282 default:
283 ser12_set_divisor(dev, 4);
284 break;
285 }
286 bc->modem.shreg >>= 1;
287 if (bc->modem.ser12.last_sample ==
288 bc->modem.ser12.last_rxbit)
289 bc->modem.shreg |= 0x10000;
290 bc->modem.ser12.last_rxbit =
291 bc->modem.ser12.last_sample;
292 }
293 if (++bc->modem.ser12.interm_sample >= 3)
294 bc->modem.ser12.interm_sample = 0;
295 /*
296 * DCD stuff
297 */
298 if (bc->modem.ser12.dcd_shreg & 1) {
299 unsigned int dcdspos, dcdsneg;
300
301 dcdspos = dcdsneg = 0;
302 dcdspos += ((bc->modem.ser12.dcd_shreg >> 1) & 1);
303 dcdspos += (!(bc->modem.ser12.dcd_shreg & 0x7ffffffe))
304 << 1;
305 dcdsneg += ((bc->modem.ser12.dcd_shreg >> 2) & 1);
306 dcdsneg += ((bc->modem.ser12.dcd_shreg >> 3) & 1);
307 dcdsneg += ((bc->modem.ser12.dcd_shreg >> 4) & 1);
308
309 bc->modem.ser12.dcd_sum0 += 16*dcdspos - dcdsneg;
310 }
311 } else {
312 /*
313 * PLL algorithm for the hardware squelch DCD algorithm
314 */
315 if (bc->modem.ser12.interm_sample) {
316 /*
317 * intermediate sample; set timing correction to normal
318 */
319 ser12_set_divisor(dev, 6);
320 } else {
321 /*
322 * do PLL correction and call HDLC receiver
323 */
324 switch (bc->modem.ser12.dcd_shreg & 3) {
325 case 1: /* transition too late */
326 ser12_set_divisor(dev, 7);
327#ifdef BAYCOM_DEBUG
328 bc->debug_vals.cur_pllcorr++;
329#endif /* BAYCOM_DEBUG */
330 break;
331 case 2: /* transition too early */
332 ser12_set_divisor(dev, 5);
333#ifdef BAYCOM_DEBUG
334 bc->debug_vals.cur_pllcorr--;
335#endif /* BAYCOM_DEBUG */
336 break;
337 default:
338 ser12_set_divisor(dev, 6);
339 break;
340 }
341 bc->modem.shreg >>= 1;
342 if (bc->modem.ser12.last_sample ==
343 bc->modem.ser12.last_rxbit)
344 bc->modem.shreg |= 0x10000;
345 bc->modem.ser12.last_rxbit =
346 bc->modem.ser12.last_sample;
347 }
348 bc->modem.ser12.interm_sample = !bc->modem.ser12.interm_sample;
349 /*
350 * DCD stuff
351 */
352 bc->modem.ser12.dcd_sum0 -= (bc->modem.ser12.dcd_shreg & 1);
353 }
354 outb(0x0d, MCR(dev->base_addr)); /* transmitter off */
355 if (bc->modem.shreg & 1) {
356 hdlcdrv_putbits(&bc->hdrv, bc->modem.shreg >> 1);
357 bc->modem.shreg = 0x10000;
358 }
359 if(!bc->modem.ser12.dcd_time) {
360 if (bc->opt_dcd & 1)
361 hdlcdrv_setdcd(&bc->hdrv, !((inb(MSR(dev->base_addr)) ^ bc->opt_dcd) & 0x80));
362 else
363 hdlcdrv_setdcd(&bc->hdrv, (bc->modem.ser12.dcd_sum0 +
364 bc->modem.ser12.dcd_sum1 +
365 bc->modem.ser12.dcd_sum2) < 0);
366 bc->modem.ser12.dcd_sum2 = bc->modem.ser12.dcd_sum1;
367 bc->modem.ser12.dcd_sum1 = bc->modem.ser12.dcd_sum0;
368 /* offset to ensure DCD off on silent input */
369 bc->modem.ser12.dcd_sum0 = 2;
370 bc->modem.ser12.dcd_time = SER12_DCD_INTERVAL(bc);
371 }
372 bc->modem.ser12.dcd_time--;
373}
374
375/* --------------------------------------------------------------------- */
376
7d12e780 377static irqreturn_t ser12_interrupt(int irq, void *dev_id)
1da177e4
LT		 378{
379 struct net_device *dev = (struct net_device *)dev_id;
380 struct baycom_state *bc = netdev_priv(dev);
381 unsigned char iir;
382
383 if (!dev || !bc || bc->hdrv.magic != HDLCDRV_MAGIC)
384 return IRQ_NONE;
385 /* fast way out */
386 if ((iir = inb(IIR(dev->base_addr))) & 1)
387 return IRQ_NONE;
388 baycom_int_freq(bc);
389 do {
390 switch (iir & 6) {
391 case 6:
392 inb(LSR(dev->base_addr));
393 break;
394
395 case 4:
396 inb(RBR(dev->base_addr));
397 break;
398
399 case 2:
400 /*
401 * check if transmitter active
402 */
403 if (hdlcdrv_ptt(&bc->hdrv))
404 ser12_tx(dev, bc);
405 else {
406 ser12_rx(dev, bc);
407 bc->modem.arb_divider--;
408 }
409 outb(0x00, THR(dev->base_addr));
410 break;
411
412 default:
413 inb(MSR(dev->base_addr));
414 break;
415 }
416 iir = inb(IIR(dev->base_addr));
417 } while (!(iir & 1));
418 if (bc->modem.arb_divider <= 0) {
419 bc->modem.arb_divider = SER12_ARB_DIVIDER(bc);
420 local_irq_enable();
421 hdlcdrv_arbitrate(dev, &bc->hdrv);
422 }
423 local_irq_enable();
424 hdlcdrv_transmitter(dev, &bc->hdrv);
425 hdlcdrv_receiver(dev, &bc->hdrv);
426 local_irq_disable();
427 return IRQ_HANDLED;
428}
429
430/* --------------------------------------------------------------------- */
431
432enum uart { c_uart_unknown, c_uart_8250,
433 c_uart_16450, c_uart_16550, c_uart_16550A};
434static const char *uart_str[] = {
435 "unknown", "8250", "16450", "16550", "16550A"
436};
437
438static enum uart ser12_check_uart(unsigned int iobase)
439{
440 unsigned char b1,b2,b3;
441 enum uart u;
442 enum uart uart_tab[] =
443 { c_uart_16450, c_uart_unknown, c_uart_16550, c_uart_16550A };
444
445 b1 = inb(MCR(iobase));
446 outb(b1 | 0x10, MCR(iobase)); /* loopback mode */
447 b2 = inb(MSR(iobase));
448 outb(0x1a, MCR(iobase));
449 b3 = inb(MSR(iobase)) & 0xf0;
450 outb(b1, MCR(iobase)); /* restore old values */
451 outb(b2, MSR(iobase));
452 if (b3 != 0x90)
453 return c_uart_unknown;
454 inb(RBR(iobase));
455 inb(RBR(iobase));
456 outb(0x01, FCR(iobase)); /* enable FIFOs */
457 u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];
458 if (u == c_uart_16450) {
459 outb(0x5a, SCR(iobase));
460 b1 = inb(SCR(iobase));
461 outb(0xa5, SCR(iobase));
462 b2 = inb(SCR(iobase));
463 if ((b1 != 0x5a) || (b2 != 0xa5))
464 u = c_uart_8250;
465 }
466 return u;
467}
468
469/* --------------------------------------------------------------------- */
470
471static int ser12_open(struct net_device *dev)
472{
473 struct baycom_state *bc = netdev_priv(dev);
474 enum uart u;
475
476 if (!dev || !bc)
477 return -ENXIO;
478 if (!dev->base_addr || dev->base_addr > 0x1000-SER12_EXTENT ||
479 dev->irq < 2 || dev->irq > 15)
480 return -ENXIO;
481 if (!request_region(dev->base_addr, SER12_EXTENT, "baycom_ser12"))
482 return -EACCES;
483 memset(&bc->modem, 0, sizeof(bc->modem));
484 bc->hdrv.par.bitrate = 1200;
485 if ((u = ser12_check_uart(dev->base_addr)) == c_uart_unknown) {
486 release_region(dev->base_addr, SER12_EXTENT);
487 return -EIO;
488 }
489 outb(0, FCR(dev->base_addr)); /* disable FIFOs */
490 outb(0x0d, MCR(dev->base_addr));
491 outb(0, IER(dev->base_addr));
1fb9df5d 492 if (request_irq(dev->irq, ser12_interrupt, IRQF_DISABLED | IRQF_SHARED,
1da177e4
LT		 493 "baycom_ser12", dev)) {
494 release_region(dev->base_addr, SER12_EXTENT);
495 return -EBUSY;
496 }
497 /*
498 * enable transmitter empty interrupt
499 */
500 outb(2, IER(dev->base_addr));
501 /*
502 * set the SIO to 6 Bits/character and 19200 or 28800 baud, so that
503 * we get exactly (hopefully) 2 or 3 interrupts per radio symbol,
504 * depending on the usage of the software DCD routine
505 */
506 ser12_set_divisor(dev, bc->opt_dcd ? 6 : 4);
507 printk(KERN_INFO "%s: ser12 at iobase 0x%lx irq %u uart %s\n",
508 bc_drvname, dev->base_addr, dev->irq, uart_str[u]);
509 return 0;
510}
511
512/* --------------------------------------------------------------------- */
513
514static int ser12_close(struct net_device *dev)
515{
516 struct baycom_state *bc = netdev_priv(dev);
517
518 if (!dev || !bc)
519 return -EINVAL;
520 /*
521 * disable interrupts
522 */
523 outb(0, IER(dev->base_addr));
524 outb(1, MCR(dev->base_addr));
525 free_irq(dev->irq, dev);
526 release_region(dev->base_addr, SER12_EXTENT);
527 printk(KERN_INFO "%s: close ser12 at iobase 0x%lx irq %u\n",
528 bc_drvname, dev->base_addr, dev->irq);
529 return 0;
530}
531
532/* --------------------------------------------------------------------- */
533/*
534 * ===================== hdlcdrv driver interface =========================
535 */
536
537/* --------------------------------------------------------------------- */
538
539static int baycom_ioctl(struct net_device *dev, struct ifreq *ifr,
540 struct hdlcdrv_ioctl *hi, int cmd);
541
542/* --------------------------------------------------------------------- */
543
544static struct hdlcdrv_ops ser12_ops = {
545 .drvname = bc_drvname,
546 .drvinfo = bc_drvinfo,
547 .open = ser12_open,
548 .close = ser12_close,
549 .ioctl = baycom_ioctl,
550};
551
552/* --------------------------------------------------------------------- */
553
554static int baycom_setmode(struct baycom_state *bc, const char *modestr)
555{
556 if (strchr(modestr, '*'))
557 bc->opt_dcd = 0;
558 else if (strchr(modestr, '+'))
559 bc->opt_dcd = -1;
560 else if (strchr(modestr, '@'))
561 bc->opt_dcd = -2;
562 else
563 bc->opt_dcd = 1;
564 return 0;
565}
566
567/* --------------------------------------------------------------------- */
568
569static int baycom_ioctl(struct net_device *dev, struct ifreq *ifr,
570 struct hdlcdrv_ioctl *hi, int cmd)
571{
572 struct baycom_state *bc;
573 struct baycom_ioctl bi;
574
575 if (!dev)
576 return -EINVAL;
577
578 bc = netdev_priv(dev);
579 BUG_ON(bc->hdrv.magic != HDLCDRV_MAGIC);
580
581 if (cmd != SIOCDEVPRIVATE)
582 return -ENOIOCTLCMD;
583 switch (hi->cmd) {
584 default:
585 break;
586
587 case HDLCDRVCTL_GETMODE:
588 strcpy(hi->data.modename, "ser12");
589 if (bc->opt_dcd <= 0)
590 strcat(hi->data.modename, (!bc->opt_dcd) ? "*" : (bc->opt_dcd == -2) ? "@" : "+");
591 if (copy_to_user(ifr->ifr_data, hi, sizeof(struct hdlcdrv_ioctl)))
592 return -EFAULT;
593 return 0;
594
595 case HDLCDRVCTL_SETMODE:
596 if (netif_running(dev) || !capable(CAP_NET_ADMIN))
597 return -EACCES;
598 hi->data.modename[sizeof(hi->data.modename)-1] = '\0';
599 return baycom_setmode(bc, hi->data.modename);
600
601 case HDLCDRVCTL_MODELIST:
602 strcpy(hi->data.modename, "ser12");
603 if (copy_to_user(ifr->ifr_data, hi, sizeof(struct hdlcdrv_ioctl)))
604 return -EFAULT;
605 return 0;
606
607 case HDLCDRVCTL_MODEMPARMASK:
608 return HDLCDRV_PARMASK_IOBASE | HDLCDRV_PARMASK_IRQ;
609
610 }
611
612 if (copy_from_user(&bi, ifr->ifr_data, sizeof(bi)))
613 return -EFAULT;
614 switch (bi.cmd) {
615 default:
616 return -ENOIOCTLCMD;
617
618#ifdef BAYCOM_DEBUG
619 case BAYCOMCTL_GETDEBUG:
620 bi.data.dbg.debug1 = bc->hdrv.ptt_keyed;
621 bi.data.dbg.debug2 = bc->debug_vals.last_intcnt;
622 bi.data.dbg.debug3 = bc->debug_vals.last_pllcorr;
623 break;
624#endif /* BAYCOM_DEBUG */
625
626 }
627 if (copy_to_user(ifr->ifr_data, &bi, sizeof(bi)))
628 return -EFAULT;
629 return 0;
630
631}
632
633/* --------------------------------------------------------------------- */
634
635/*
636 * command line settable parameters
637 */
638static char *mode[NR_PORTS] = { "ser12*", };
639static int iobase[NR_PORTS] = { 0x3f8, };
640static int irq[NR_PORTS] = { 4, };
641
642module_param_array(mode, charp, NULL, 0);
643MODULE_PARM_DESC(mode, "baycom operating mode; * for software DCD");
644module_param_array(iobase, int, NULL, 0);
645MODULE_PARM_DESC(iobase, "baycom io base address");
646module_param_array(irq, int, NULL, 0);
647MODULE_PARM_DESC(irq, "baycom irq number");
648
649MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
650MODULE_DESCRIPTION("Baycom ser12 half duplex amateur radio modem driver");
651MODULE_LICENSE("GPL");
652
653/* --------------------------------------------------------------------- */
654
655static int __init init_baycomserhdx(void)
656{
657 int i, found = 0;
658 char set_hw = 1;
659
660 printk(bc_drvinfo);
661 /*
662 * register net devices
663 */
664 for (i = 0; i < NR_PORTS; i++) {
665 struct net_device *dev;
666 struct baycom_state *bc;
667 char ifname[IFNAMSIZ];
668
669 sprintf(ifname, "bcsh%d", i);
670
671 if (!mode[i])
672 set_hw = 0;
673 if (!set_hw)
674 iobase[i] = irq[i] = 0;
675
676 dev = hdlcdrv_register(&ser12_ops,
677 sizeof(struct baycom_state),
678 ifname, iobase[i], irq[i], 0);
679 if (IS_ERR(dev))
680 break;
681
682 bc = netdev_priv(dev);
683 if (set_hw && baycom_setmode(bc, mode[i]))
684 set_hw = 0;
685 found++;
686 baycom_device[i] = dev;
687 }
688
689 if (!found)
690 return -ENXIO;
691 return 0;
692}
693
694static void __exit cleanup_baycomserhdx(void)
695{
696 int i;
697
698 for(i = 0; i < NR_PORTS; i++) {
699 struct net_device *dev = baycom_device[i];
700
701 if (dev)
702 hdlcdrv_unregister(dev);
703 }
704}
705
706module_init(init_baycomserhdx);
707module_exit(cleanup_baycomserhdx);
708
709/* --------------------------------------------------------------------- */
710
711#ifndef MODULE
712
713/*
714 * format: baycom_ser_hdx=io,irq,mode
715 * mode: ser12 hardware DCD
716 * ser12* software DCD
717 * ser12@ hardware/software DCD, i.e. no explicit DCD signal but hardware
718 * mutes audio input to the modem
719 * ser12+ hardware DCD, inverted signal at DCD pin
720 */
721
722static int __init baycom_ser_hdx_setup(char *str)
723{
724 static unsigned nr_dev;
725 int ints[3];
726
727 if (nr_dev >= NR_PORTS)
728 return 0;
729 str = get_options(str, 3, ints);
730 if (ints[0] < 2)
731 return 0;
732 mode[nr_dev] = str;
733 iobase[nr_dev] = ints[1];
734 irq[nr_dev] = ints[2];
735 nr_dev++;
736 return 1;
737}
738
739__setup("baycom_ser_hdx=", baycom_ser_hdx_setup);
740
741#endif /* MODULE */
742/* --------------------------------------------------------------------- */
kernel source for telekom puls (alcatel/mediatek)