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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / mellanox / mlx4 / port.c
CommitLineData
2a2336f8
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/errno.h>
34#include <linux/if_ether.h>
ee40fa06 35#include <linux/export.h>
2a2336f8
YP		 36
37#include <linux/mlx4/cmd.h>
38
39#include "mlx4.h"
40
41#define MLX4_MAC_VALID (1ull << 63)
42#define MLX4_MAC_MASK 0xffffffffffffULL
43
44#define MLX4_VLAN_VALID (1u << 31)
45#define MLX4_VLAN_MASK 0xfff
46
93ece0c1
EE		 47#define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL
48#define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL
49#define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL
50#define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL
51
2a2336f8
YP		 52void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table)
53{
54 int i;
55
56 mutex_init(&table->mutex);
57 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
58 table->entries[i] = 0;
59 table->refs[i] = 0;
60 }
61 table->max = 1 << dev->caps.log_num_macs;
62 table->total = 0;
63}
64
65void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table)
66{
67 int i;
68
69 mutex_init(&table->mutex);
70 for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
71 table->entries[i] = 0;
72 table->refs[i] = 0;
73 }
e72ebf5a 74 table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR;
2a2336f8
YP		 75 table->total = 0;
76}
77
ffe455ad 78static int mlx4_uc_steer_add(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn)
2a2336f8 79{
1679200f
YP		 80 struct mlx4_qp qp;
81 u8 gid[16] = {0};
2ab573c5 82 __be64 be_mac;
1679200f
YP		 83 int err;
84
1679200f
YP		 85 qp.qpn = *qpn;
86
87 mac &= 0xffffffffffffULL;
2ab573c5
YP		 88 be_mac = cpu_to_be64(mac << 16);
89 memcpy(&gid[10], &be_mac, ETH_ALEN);
1679200f 90 gid[5] = port;
1679200f 91
ffe455ad
EE		 92 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
93 if (err)
94 mlx4_warn(dev, "Failed Attaching Unicast\n");
1679200f
YP		 95
96 return err;
97}
98
99static void mlx4_uc_steer_release(struct mlx4_dev *dev, u8 port,
ffe455ad 100 u64 mac, int qpn)
1679200f
YP		 101{
102 struct mlx4_qp qp;
103 u8 gid[16] = {0};
2ab573c5 104 __be64 be_mac;
1679200f
YP		 105
106 qp.qpn = qpn;
107 mac &= 0xffffffffffffULL;
2ab573c5
YP		 108 be_mac = cpu_to_be64(mac << 16);
109 memcpy(&gid[10], &be_mac, ETH_ALEN);
1679200f 110 gid[5] = port;
1679200f 111
ffe455ad
EE		 112 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
113}
114
115static int validate_index(struct mlx4_dev *dev,
116 struct mlx4_mac_table *table, int index)
117{
118 int err = 0;
119
120 if (index < 0 || index >= table->max || !table->entries[index]) {
121 mlx4_warn(dev, "No valid Mac entry for the given index\n");
122 err = -EINVAL;
123 }
124 return err;
125}
126
127static int find_index(struct mlx4_dev *dev,
128 struct mlx4_mac_table *table, u64 mac)
129{
130 int i;
131
132 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
133 if ((mac & MLX4_MAC_MASK) ==
134 (MLX4_MAC_MASK & be64_to_cpu(table->entries[i])))
135 return i;
136 }
137 /* Mac not found */
138 return -EINVAL;
1679200f
YP		 139}
140
ffe455ad 141int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn)
1679200f
YP		 142{
143 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1679200f 144 struct mlx4_mac_entry *entry;
ffe455ad
EE		 145 int index = 0;
146 int err = 0;
2a2336f8 147
ffe455ad
EE		 148 mlx4_dbg(dev, "Registering MAC: 0x%llx for adding\n",
149 (unsigned long long) mac);
150 index = mlx4_register_mac(dev, port, mac);
151 if (index < 0) {
152 err = index;
153 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
154 (unsigned long long) mac);
155 return err;
156 }
0f6740c7 157
ffe455ad
EE		 158 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER)) {
159 *qpn = info->base_qpn + index;
160 return 0;
161 }
162
163 err = mlx4_qp_reserve_range(dev, 1, 1, qpn);
164 mlx4_dbg(dev, "Reserved qp %d\n", *qpn);
165 if (err) {
166 mlx4_err(dev, "Failed to reserve qp for mac registration\n");
167 goto qp_err;
168 }
169
170 err = mlx4_uc_steer_add(dev, port, mac, qpn);
171 if (err)
172 goto steer_err;
173
174 entry = kmalloc(sizeof *entry, GFP_KERNEL);
175 if (!entry) {
176 err = -ENOMEM;
177 goto alloc_err;
178 }
179 entry->mac = mac;
180 err = radix_tree_insert(&info->mac_tree, *qpn, entry);
181 if (err)
182 goto insert_err;
183 return 0;
184
185insert_err:
186 kfree(entry);
187
188alloc_err:
189 mlx4_uc_steer_release(dev, port, mac, *qpn);
190
191steer_err:
192 mlx4_qp_release_range(dev, *qpn, 1);
0f6740c7 193
ffe455ad
EE		 194qp_err:
195 mlx4_unregister_mac(dev, port, mac);
196 return err;
197}
198EXPORT_SYMBOL_GPL(mlx4_get_eth_qp);
199
200void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn)
201{
202 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
203 struct mlx4_mac_entry *entry;
204
205 mlx4_dbg(dev, "Registering MAC: 0x%llx for deleting\n",
206 (unsigned long long) mac);
207 mlx4_unregister_mac(dev, port, mac);
208
209 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER) {
210 entry = radix_tree_lookup(&info->mac_tree, qpn);
211 if (entry) {
212 mlx4_dbg(dev, "Releasing qp: port %d, mac 0x%llx,"
213 " qpn %d\n", port,
214 (unsigned long long) mac, qpn);
215 mlx4_uc_steer_release(dev, port, entry->mac, qpn);
216 mlx4_qp_release_range(dev, qpn, 1);
217 radix_tree_delete(&info->mac_tree, qpn);
0f6740c7 218 kfree(entry);
0f6740c7 219 }
1679200f 220 }
ffe455ad
EE		 221}
222EXPORT_SYMBOL_GPL(mlx4_put_eth_qp);
223
224static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port,
225 __be64 *entries)
226{
227 struct mlx4_cmd_mailbox *mailbox;
228 u32 in_mod;
229 int err;
230
231 mailbox = mlx4_alloc_cmd_mailbox(dev);
232 if (IS_ERR(mailbox))
233 return PTR_ERR(mailbox);
234
235 memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE);
236
237 in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port;
0f6740c7 238
ffe455ad
EE		 239 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
240 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
241
242 mlx4_free_cmd_mailbox(dev, mailbox);
243 return err;
244}
245
246int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
247{
248 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
249 struct mlx4_mac_table *table = &info->mac_table;
250 int i, err = 0;
251 int free = -1;
252
253 mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d\n",
254 (unsigned long long) mac, port);
0f6740c7 255
2a2336f8 256 mutex_lock(&table->mutex);
ffe455ad
EE		 257 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
258 if (free < 0 && !table->entries[i]) {
2a2336f8
YP		 259 free = i;
260 continue;
261 }
262
263 if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
ffe455ad
EE		 264 /* MAC already registered, Must not have duplicates */
265 err = -EEXIST;
2a2336f8
YP		 266 goto out;
267 }
268 }
0926f910 269
2a2336f8
YP		 270 mlx4_dbg(dev, "Free MAC index is %d\n", free);
271
272 if (table->total == table->max) {
273 /* No free mac entries */
274 err = -ENOSPC;
275 goto out;
276 }
277
278 /* Register new MAC */
2a2336f8
YP		 279 table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID);
280
281 err = mlx4_set_port_mac_table(dev, port, table->entries);
282 if (unlikely(err)) {
ffe455ad
EE		 283 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
284 (unsigned long long) mac);
2a2336f8
YP		 285 table->entries[free] = 0;
286 goto out;
287 }
288
ffe455ad 289 err = free;
2a2336f8
YP		 290 ++table->total;
291out:
292 mutex_unlock(&table->mutex);
293 return err;
294}
ffe455ad 295EXPORT_SYMBOL_GPL(__mlx4_register_mac);
2a2336f8 296
ffe455ad 297int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
2a2336f8 298{
ffe455ad
EE		 299 u64 out_param;
300 int err;
2a2336f8 301
ffe455ad
EE		 302 if (mlx4_is_mfunc(dev)) {
303 set_param_l(&out_param, port);
304 err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
305 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
306 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
307 if (err)
308 return err;
1679200f 309
ffe455ad 310 return get_param_l(&out_param);
1679200f 311 }
ffe455ad 312 return __mlx4_register_mac(dev, port, mac);
1679200f 313}
ffe455ad
EE		 314EXPORT_SYMBOL_GPL(mlx4_register_mac);
315
1679200f 316
ffe455ad 317void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
1679200f
YP		 318{
319 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
320 struct mlx4_mac_table *table = &info->mac_table;
ffe455ad 321 int index;
1679200f 322
ffe455ad 323 index = find_index(dev, table, mac);
1679200f
YP		 324
325 mutex_lock(&table->mutex);
326
327 if (validate_index(dev, table, index))
328 goto out;
329
ffe455ad
EE		 330 table->entries[index] = 0;
331 mlx4_set_port_mac_table(dev, port, table->entries);
332 --table->total;
2a2336f8
YP		 333out:
334 mutex_unlock(&table->mutex);
335}
ffe455ad
EE		 336EXPORT_SYMBOL_GPL(__mlx4_unregister_mac);
337
338void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
339{
340 u64 out_param;
ffe455ad
EE		 341
342 if (mlx4_is_mfunc(dev)) {
343 set_param_l(&out_param, port);
162344ed
OG		 344 (void) mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
345 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
346 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
ffe455ad
EE		 347 return;
348 }
349 __mlx4_unregister_mac(dev, port, mac);
350 return;
351}
2a2336f8
YP		 352EXPORT_SYMBOL_GPL(mlx4_unregister_mac);
353
ffe455ad 354int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac)
1679200f
YP		 355{
356 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
357 struct mlx4_mac_table *table = &info->mac_table;
1679200f 358 struct mlx4_mac_entry *entry;
ffe455ad
EE		 359 int index = qpn - info->base_qpn;
360 int err = 0;
1679200f 361
ccf86321 362 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER) {
1679200f
YP		 363 entry = radix_tree_lookup(&info->mac_tree, qpn);
364 if (!entry)
365 return -EINVAL;
ffe455ad
EE		 366 mlx4_uc_steer_release(dev, port, entry->mac, qpn);
367 mlx4_unregister_mac(dev, port, entry->mac);
1679200f 368 entry->mac = new_mac;
ffe455ad
EE		 369 mlx4_register_mac(dev, port, new_mac);
370 err = mlx4_uc_steer_add(dev, port, entry->mac, &qpn);
371 return err;
1679200f
YP		 372 }
373
ffe455ad 374 /* CX1 doesn't support multi-functions */
1679200f
YP		 375 mutex_lock(&table->mutex);
376
377 err = validate_index(dev, table, index);
378 if (err)
379 goto out;
380
381 table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID);
382
383 err = mlx4_set_port_mac_table(dev, port, table->entries);
384 if (unlikely(err)) {
ffe455ad
EE		 385 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
386 (unsigned long long) new_mac);
1679200f
YP		 387 table->entries[index] = 0;
388 }
389out:
390 mutex_unlock(&table->mutex);
391 return err;
392}
393EXPORT_SYMBOL_GPL(mlx4_replace_mac);
ffe455ad 394
2a2336f8
YP		 395static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port,
396 __be32 *entries)
397{
398 struct mlx4_cmd_mailbox *mailbox;
399 u32 in_mod;
400 int err;
401
402 mailbox = mlx4_alloc_cmd_mailbox(dev);
403 if (IS_ERR(mailbox))
404 return PTR_ERR(mailbox);
405
406 memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE);
407 in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port;
408 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
f9baff50 409 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
2a2336f8
YP		 410
411 mlx4_free_cmd_mailbox(dev, mailbox);
412
413 return err;
414}
415
4c3eb3ca
EC		 416int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx)
417{
418 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
419 int i;
420
421 for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) {
422 if (table->refs[i] &&
423 (vid == (MLX4_VLAN_MASK &
424 be32_to_cpu(table->entries[i])))) {
425 /* VLAN already registered, increase reference count */
426 *idx = i;
427 return 0;
428 }
429 }
430
431 return -ENOENT;
432}
433EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan);
434
ffe455ad
EE		 435static int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan,
436 int *index)
2a2336f8
YP		 437{
438 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
439 int i, err = 0;
440 int free = -1;
441
442 mutex_lock(&table->mutex);
e72ebf5a
YP		 443
444 if (table->total == table->max) {
445 /* No free vlan entries */
446 err = -ENOSPC;
447 goto out;
448 }
449
2a2336f8
YP		 450 for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) {
451 if (free < 0 && (table->refs[i] == 0)) {
452 free = i;
453 continue;
454 }
455
456 if (table->refs[i] &&
457 (vlan == (MLX4_VLAN_MASK &
458 be32_to_cpu(table->entries[i])))) {
25985edc 459 /* Vlan already registered, increase references count */
2a2336f8
YP		 460 *index = i;
461 ++table->refs[i];
462 goto out;
463 }
464 }
465
0926f910
EC		 466 if (free < 0) {
467 err = -ENOMEM;
468 goto out;
469 }
470
ffe455ad 471 /* Register new VLAN */
2a2336f8
YP		 472 table->refs[free] = 1;
473 table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID);
474
475 err = mlx4_set_port_vlan_table(dev, port, table->entries);
476 if (unlikely(err)) {
477 mlx4_warn(dev, "Failed adding vlan: %u\n", vlan);
478 table->refs[free] = 0;
479 table->entries[free] = 0;
480 goto out;
481 }
482
483 *index = free;
484 ++table->total;
485out:
486 mutex_unlock(&table->mutex);
487 return err;
488}
ffe455ad
EE		 489
490int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index)
491{
492 u64 out_param;
493 int err;
494
495 if (mlx4_is_mfunc(dev)) {
496 set_param_l(&out_param, port);
497 err = mlx4_cmd_imm(dev, vlan, &out_param, RES_VLAN,
498 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
499 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
500 if (!err)
501 *index = get_param_l(&out_param);
502
503 return err;
504 }
505 return __mlx4_register_vlan(dev, port, vlan, index);
506}
2a2336f8
YP		 507EXPORT_SYMBOL_GPL(mlx4_register_vlan);
508
ffe455ad 509static void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index)
2a2336f8
YP		 510{
511 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
512
513 if (index < MLX4_VLAN_REGULAR) {
514 mlx4_warn(dev, "Trying to free special vlan index %d\n", index);
515 return;
516 }
517
518 mutex_lock(&table->mutex);
519 if (!table->refs[index]) {
520 mlx4_warn(dev, "No vlan entry for index %d\n", index);
521 goto out;
522 }
523 if (--table->refs[index]) {
524 mlx4_dbg(dev, "Have more references for index %d,"
525 "no need to modify vlan table\n", index);
526 goto out;
527 }
528 table->entries[index] = 0;
529 mlx4_set_port_vlan_table(dev, port, table->entries);
530 --table->total;
531out:
532 mutex_unlock(&table->mutex);
533}
ffe455ad
EE		 534
535void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index)
536{
537 u64 in_param;
538 int err;
539
540 if (mlx4_is_mfunc(dev)) {
541 set_param_l(&in_param, port);
542 err = mlx4_cmd(dev, in_param, RES_VLAN, RES_OP_RESERVE_AND_MAP,
543 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
544 MLX4_CMD_WRAPPED);
545 if (!err)
546 mlx4_warn(dev, "Failed freeing vlan at index:%d\n",
547 index);
548
549 return;
550 }
551 __mlx4_unregister_vlan(dev, port, index);
552}
2a2336f8 553EXPORT_SYMBOL_GPL(mlx4_unregister_vlan);
7ff93f8b 554
9a5aa622
JM		 555int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps)
556{
557 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
558 u8 *inbuf, *outbuf;
559 int err;
560
561 inmailbox = mlx4_alloc_cmd_mailbox(dev);
562 if (IS_ERR(inmailbox))
563 return PTR_ERR(inmailbox);
564
565 outmailbox = mlx4_alloc_cmd_mailbox(dev);
566 if (IS_ERR(outmailbox)) {
567 mlx4_free_cmd_mailbox(dev, inmailbox);
568 return PTR_ERR(outmailbox);
569 }
570
571 inbuf = inmailbox->buf;
572 outbuf = outmailbox->buf;
573 memset(inbuf, 0, 256);
574 memset(outbuf, 0, 256);
575 inbuf[0] = 1;
576 inbuf[1] = 1;
577 inbuf[2] = 1;
578 inbuf[3] = 1;
579 *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015);
580 *(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
581
582 err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
f9baff50
JM		 583 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
584 MLX4_CMD_NATIVE);
9a5aa622
JM		 585 if (!err)
586 *caps = *(__be32 *) (outbuf + 84);
587 mlx4_free_cmd_mailbox(dev, inmailbox);
588 mlx4_free_cmd_mailbox(dev, outmailbox);
589 return err;
590}
591
ffe455ad
EE		 592static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod,
593 u8 op_mod, struct mlx4_cmd_mailbox *inbox)
594{
595 struct mlx4_priv *priv = mlx4_priv(dev);
596 struct mlx4_port_info *port_info;
597 struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
598 struct mlx4_slave_state *slave_st = &master->slave_state[slave];
599 struct mlx4_set_port_rqp_calc_context *qpn_context;
600 struct mlx4_set_port_general_context *gen_context;
601 int reset_qkey_viols;
602 int port;
603 int is_eth;
604 u32 in_modifier;
605 u32 promisc;
606 u16 mtu, prev_mtu;
607 int err;
608 int i;
609 __be32 agg_cap_mask;
610 __be32 slave_cap_mask;
611 __be32 new_cap_mask;
612
613 port = in_mod & 0xff;
614 in_modifier = in_mod >> 8;
615 is_eth = op_mod;
616 port_info = &priv->port[port];
617
618 /* Slaves cannot perform SET_PORT operations except changing MTU */
619 if (is_eth) {
620 if (slave != dev->caps.function &&
621 in_modifier != MLX4_SET_PORT_GENERAL) {
622 mlx4_warn(dev, "denying SET_PORT for slave:%d\n",
623 slave);
624 return -EINVAL;
625 }
626 switch (in_modifier) {
627 case MLX4_SET_PORT_RQP_CALC:
628 qpn_context = inbox->buf;
629 qpn_context->base_qpn =
630 cpu_to_be32(port_info->base_qpn);
631 qpn_context->n_mac = 0x7;
632 promisc = be32_to_cpu(qpn_context->promisc) >>
633 SET_PORT_PROMISC_SHIFT;
634 qpn_context->promisc = cpu_to_be32(
635 promisc << SET_PORT_PROMISC_SHIFT |
636 port_info->base_qpn);
637 promisc = be32_to_cpu(qpn_context->mcast) >>
638 SET_PORT_MC_PROMISC_SHIFT;
639 qpn_context->mcast = cpu_to_be32(
640 promisc << SET_PORT_MC_PROMISC_SHIFT |
641 port_info->base_qpn);
642 break;
643 case MLX4_SET_PORT_GENERAL:
644 gen_context = inbox->buf;
645 /* Mtu is configured as the max MTU among all the
646 * the functions on the port. */
647 mtu = be16_to_cpu(gen_context->mtu);
648 mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port]);
649 prev_mtu = slave_st->mtu[port];
650 slave_st->mtu[port] = mtu;
651 if (mtu > master->max_mtu[port])
652 master->max_mtu[port] = mtu;
653 if (mtu < prev_mtu && prev_mtu ==
654 master->max_mtu[port]) {
655 slave_st->mtu[port] = mtu;
656 master->max_mtu[port] = mtu;
657 for (i = 0; i < dev->num_slaves; i++) {
658 master->max_mtu[port] =
659 max(master->max_mtu[port],
660 master->slave_state[i].mtu[port]);
661 }
662 }
663
664 gen_context->mtu = cpu_to_be16(master->max_mtu[port]);
665 break;
666 }
667 return mlx4_cmd(dev, inbox->dma, in_mod, op_mod,
668 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
669 MLX4_CMD_NATIVE);
670 }
671
672 /* For IB, we only consider:
673 * - The capability mask, which is set to the aggregate of all
674 * slave function capabilities
675 * - The QKey violatin counter - reset according to each request.
676 */
677
678 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
679 reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40;
680 new_cap_mask = ((__be32 *) inbox->buf)[2];
681 } else {
682 reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1;
683 new_cap_mask = ((__be32 *) inbox->buf)[1];
684 }
685
686 agg_cap_mask = 0;
687 slave_cap_mask =
688 priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
689 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask;
690 for (i = 0; i < dev->num_slaves; i++)
691 agg_cap_mask |=
692 priv->mfunc.master.slave_state[i].ib_cap_mask[port];
693
694 /* only clear mailbox for guests. Master may be setting
695 * MTU or PKEY table size
696 */
697 if (slave != dev->caps.function)
698 memset(inbox->buf, 0, 256);
699 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
edc4a67e 700 *(u8 *) inbox->buf |= !!reset_qkey_viols << 6;
ffe455ad
EE		 701 ((__be32 *) inbox->buf)[2] = agg_cap_mask;
702 } else {
edc4a67e 703 ((u8 *) inbox->buf)[3] |= !!reset_qkey_viols;
ffe455ad
EE		 704 ((__be32 *) inbox->buf)[1] = agg_cap_mask;
705 }
706
707 err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
708 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
709 if (err)
710 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] =
711 slave_cap_mask;
712 return err;
713}
714
715int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
716 struct mlx4_vhcr *vhcr,
717 struct mlx4_cmd_mailbox *inbox,
718 struct mlx4_cmd_mailbox *outbox,
719 struct mlx4_cmd_info *cmd)
720{
721 return mlx4_common_set_port(dev, slave, vhcr->in_modifier,
722 vhcr->op_modifier, inbox);
723}
724
096335b3
OG		 725/* bit locations for set port command with zero op modifier */
726enum {
727 MLX4_SET_PORT_VL_CAP = 4, /* bits 7:4 */
728 MLX4_SET_PORT_MTU_CAP = 12, /* bits 15:12 */
729 MLX4_CHANGE_PORT_VL_CAP = 21,
730 MLX4_CHANGE_PORT_MTU_CAP = 22,
731};
732
7ff93f8b
YP		 733int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port)
734{
735 struct mlx4_cmd_mailbox *mailbox;
096335b3 736 int err, vl_cap;
7ff93f8b 737
352b09ed
RD		 738 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
739 return 0;
740
7ff93f8b
YP		 741 mailbox = mlx4_alloc_cmd_mailbox(dev);
742 if (IS_ERR(mailbox))
743 return PTR_ERR(mailbox);
744
745 memset(mailbox->buf, 0, 256);
793730bf
YP		 746
747 ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port];
096335b3
OG		 748
749 /* IB VL CAP enum isn't used by the firmware, just numerical values */
750 for (vl_cap = 8; vl_cap >= 1; vl_cap >>= 1) {
751 ((__be32 *) mailbox->buf)[0] = cpu_to_be32(
752 (1 << MLX4_CHANGE_PORT_MTU_CAP) |
753 (1 << MLX4_CHANGE_PORT_VL_CAP) |
754 (dev->caps.port_ib_mtu[port] << MLX4_SET_PORT_MTU_CAP) |
755 (vl_cap << MLX4_SET_PORT_VL_CAP));
756 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT,
757 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
758 if (err != -ENOMEM)
759 break;
760 }
7ff93f8b
YP		 761
762 mlx4_free_cmd_mailbox(dev, mailbox);
763 return err;
764}
ffe455ad 765
cb9ffb76 766int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
ffe455ad
EE		 767 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
768{
769 struct mlx4_cmd_mailbox *mailbox;
770 struct mlx4_set_port_general_context *context;
771 int err;
772 u32 in_mod;
773
774 mailbox = mlx4_alloc_cmd_mailbox(dev);
775 if (IS_ERR(mailbox))
776 return PTR_ERR(mailbox);
777 context = mailbox->buf;
778 memset(context, 0, sizeof *context);
779
780 context->flags = SET_PORT_GEN_ALL_VALID;
781 context->mtu = cpu_to_be16(mtu);
782 context->pptx = (pptx * (!pfctx)) << 7;
783 context->pfctx = pfctx;
784 context->pprx = (pprx * (!pfcrx)) << 7;
785 context->pfcrx = pfcrx;
786
787 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
788 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
789 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
790
791 mlx4_free_cmd_mailbox(dev, mailbox);
792 return err;
793}
794EXPORT_SYMBOL(mlx4_SET_PORT_general);
795
cb9ffb76 796int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
ffe455ad
EE		 797 u8 promisc)
798{
799 struct mlx4_cmd_mailbox *mailbox;
800 struct mlx4_set_port_rqp_calc_context *context;
801 int err;
802 u32 in_mod;
803 u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
804 MCAST_DIRECT : MCAST_DEFAULT;
805
806 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER &&
807 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER)
808 return 0;
809
810 mailbox = mlx4_alloc_cmd_mailbox(dev);
811 if (IS_ERR(mailbox))
812 return PTR_ERR(mailbox);
813 context = mailbox->buf;
814 memset(context, 0, sizeof *context);
815
816 context->base_qpn = cpu_to_be32(base_qpn);
817 context->n_mac = dev->caps.log_num_macs;
818 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
819 base_qpn);
820 context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
821 base_qpn);
822 context->intra_no_vlan = 0;
823 context->no_vlan = MLX4_NO_VLAN_IDX;
824 context->intra_vlan_miss = 0;
825 context->vlan_miss = MLX4_VLAN_MISS_IDX;
826
827 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
828 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
829 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
830
831 mlx4_free_cmd_mailbox(dev, mailbox);
832 return err;
833}
834EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc);
835
e5395e92
AV		 836int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc)
837{
838 struct mlx4_cmd_mailbox *mailbox;
839 struct mlx4_set_port_prio2tc_context *context;
840 int err;
841 u32 in_mod;
842 int i;
843
844 mailbox = mlx4_alloc_cmd_mailbox(dev);
845 if (IS_ERR(mailbox))
846 return PTR_ERR(mailbox);
847 context = mailbox->buf;
848 memset(context, 0, sizeof *context);
849
850 for (i = 0; i < MLX4_NUM_UP; i += 2)
851 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1];
852
853 in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port;
854 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
855 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
856
857 mlx4_free_cmd_mailbox(dev, mailbox);
858 return err;
859}
860EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC);
861
862int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
863 u8 *pg, u16 *ratelimit)
864{
865 struct mlx4_cmd_mailbox *mailbox;
866 struct mlx4_set_port_scheduler_context *context;
867 int err;
868 u32 in_mod;
869 int i;
870
871 mailbox = mlx4_alloc_cmd_mailbox(dev);
872 if (IS_ERR(mailbox))
873 return PTR_ERR(mailbox);
874 context = mailbox->buf;
875 memset(context, 0, sizeof *context);
876
877 for (i = 0; i < MLX4_NUM_TC; i++) {
878 struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i];
879 u16 r = ratelimit && ratelimit[i] ? ratelimit[i] :
880 MLX4_RATELIMIT_DEFAULT;
881
882 tc->pg = htons(pg[i]);
883 tc->bw_precentage = htons(tc_tx_bw[i]);
884
885 tc->max_bw_units = htons(MLX4_RATELIMIT_UNITS);
886 tc->max_bw_value = htons(r);
887 }
888
889 in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port;
890 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
891 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
892
893 mlx4_free_cmd_mailbox(dev, mailbox);
894 return err;
895}
896EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER);
897
ffe455ad
EE		 898int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
899 struct mlx4_vhcr *vhcr,
900 struct mlx4_cmd_mailbox *inbox,
901 struct mlx4_cmd_mailbox *outbox,
902 struct mlx4_cmd_info *cmd)
903{
904 int err = 0;
905
906 return err;
907}
908
909int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
910 u64 mac, u64 clear, u8 mode)
911{
912 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
913 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B,
914 MLX4_CMD_WRAPPED);
915}
916EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR);
917
918int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
919 struct mlx4_vhcr *vhcr,
920 struct mlx4_cmd_mailbox *inbox,
921 struct mlx4_cmd_mailbox *outbox,
922 struct mlx4_cmd_info *cmd)
923{
924 int err = 0;
925
926 return err;
927}
928
929int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave,
930 u32 in_mod, struct mlx4_cmd_mailbox *outbox)
931{
932 return mlx4_cmd_box(dev, 0, outbox->dma, in_mod, 0,
933 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
934 MLX4_CMD_NATIVE);
935}
936
937int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
938 struct mlx4_vhcr *vhcr,
939 struct mlx4_cmd_mailbox *inbox,
940 struct mlx4_cmd_mailbox *outbox,
941 struct mlx4_cmd_info *cmd)
942{
35fb9afb
EE		 943 if (slave != dev->caps.function)
944 return 0;
ffe455ad
EE		 945 return mlx4_common_dump_eth_stats(dev, slave,
946 vhcr->in_modifier, outbox);
947}
93ece0c1
EE		 948
949void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap)
950{
951 if (!mlx4_is_mfunc(dev)) {
952 *stats_bitmap = 0;
953 return;
954 }
955
956 *stats_bitmap = (MLX4_STATS_TRAFFIC_COUNTERS_MASK |
957 MLX4_STATS_TRAFFIC_DROPS_MASK |
958 MLX4_STATS_PORT_COUNTERS_MASK);
959
960 if (mlx4_is_master(dev))
961 *stats_bitmap |= MLX4_STATS_ERROR_COUNTERS_MASK;
962}
963EXPORT_SYMBOL(mlx4_set_stats_bitmap);
kernel source for telekom puls (alcatel/mediatek)