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d339b133 RC |
1 | /* |
2 | * PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580 | |
3 | * | |
4 | * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | #include <linux/module.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/pci.h> | |
ba59814b | 23 | #include <linux/ptp_classify.h> |
d339b133 RC |
24 | |
25 | #include "igb.h" | |
26 | ||
27 | #define INCVALUE_MASK 0x7fffffff | |
28 | #define ISGN 0x80000000 | |
29 | ||
30 | /* | |
7ebae817 RC |
31 | * The 82580 timesync updates the system timer every 8ns by 8ns, |
32 | * and this update value cannot be reprogrammed. | |
33 | * | |
d339b133 RC |
34 | * Neither the 82576 nor the 82580 offer registers wide enough to hold |
35 | * nanoseconds time values for very long. For the 82580, SYSTIM always | |
36 | * counts nanoseconds, but the upper 24 bits are not availible. The | |
37 | * frequency is adjusted by changing the 32 bit fractional nanoseconds | |
38 | * register, TIMINCA. | |
39 | * | |
40 | * For the 82576, the SYSTIM register time unit is affect by the | |
41 | * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this | |
42 | * field are needed to provide the nominal 16 nanosecond period, | |
43 | * leaving 19 bits for fractional nanoseconds. | |
44 | * | |
7ebae817 RC |
45 | * We scale the NIC clock cycle by a large factor so that relatively |
46 | * small clock corrections can be added or subtracted at each clock | |
47 | * tick. The drawbacks of a large factor are a) that the clock | |
48 | * register overflows more quickly (not such a big deal) and b) that | |
49 | * the increment per tick has to fit into 24 bits. As a result we | |
50 | * need to use a shift of 19 so we can fit a value of 16 into the | |
51 | * TIMINCA register. | |
52 | * | |
d339b133 RC |
53 | * |
54 | * SYSTIMH SYSTIML | |
55 | * +--------------+ +---+---+------+ | |
56 | * 82576 | 32 | | 8 | 5 | 19 | | |
57 | * +--------------+ +---+---+------+ | |
58 | * \________ 45 bits _______/ fract | |
59 | * | |
60 | * +----------+---+ +--------------+ | |
61 | * 82580 | 24 | 8 | | 32 | | |
62 | * +----------+---+ +--------------+ | |
63 | * reserved \______ 40 bits _____/ | |
64 | * | |
65 | * | |
66 | * The 45 bit 82576 SYSTIM overflows every | |
67 | * 2^45 * 10^-9 / 3600 = 9.77 hours. | |
68 | * | |
69 | * The 40 bit 82580 SYSTIM overflows every | |
70 | * 2^40 * 10^-9 / 60 = 18.3 minutes. | |
71 | */ | |
72 | ||
a79f4f88 | 73 | #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9) |
428f1f71 | 74 | #define IGB_PTP_TX_TIMEOUT (HZ * 15) |
a79f4f88 MV |
75 | #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT) |
76 | #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1) | |
77 | #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT) | |
78 | #define IGB_NBITS_82580 40 | |
d339b133 RC |
79 | |
80 | /* | |
81 | * SYSTIM read access for the 82576 | |
82 | */ | |
83 | ||
a79f4f88 | 84 | static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc) |
d339b133 | 85 | { |
d339b133 RC |
86 | struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); |
87 | struct e1000_hw *hw = &igb->hw; | |
a79f4f88 MV |
88 | u64 val; |
89 | u32 lo, hi; | |
d339b133 RC |
90 | |
91 | lo = rd32(E1000_SYSTIML); | |
92 | hi = rd32(E1000_SYSTIMH); | |
93 | ||
94 | val = ((u64) hi) << 32; | |
95 | val |= lo; | |
96 | ||
97 | return val; | |
98 | } | |
99 | ||
100 | /* | |
101 | * SYSTIM read access for the 82580 | |
102 | */ | |
103 | ||
a79f4f88 | 104 | static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc) |
d339b133 | 105 | { |
d339b133 RC |
106 | struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); |
107 | struct e1000_hw *hw = &igb->hw; | |
a79f4f88 MV |
108 | u64 val; |
109 | u32 lo, hi, jk; | |
d339b133 | 110 | |
7ebae817 RC |
111 | /* |
112 | * The timestamp latches on lowest register read. For the 82580 | |
113 | * the lowest register is SYSTIMR instead of SYSTIML. However we only | |
114 | * need to provide nanosecond resolution, so we just ignore it. | |
115 | */ | |
d339b133 RC |
116 | jk = rd32(E1000_SYSTIMR); |
117 | lo = rd32(E1000_SYSTIML); | |
118 | hi = rd32(E1000_SYSTIMH); | |
119 | ||
120 | val = ((u64) hi) << 32; | |
121 | val |= lo; | |
122 | ||
123 | return val; | |
124 | } | |
125 | ||
e57b8bdb MV |
126 | /* |
127 | * SYSTIM read access for I210/I211 | |
128 | */ | |
129 | ||
130 | static void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts) | |
131 | { | |
132 | struct e1000_hw *hw = &adapter->hw; | |
133 | u32 sec, nsec, jk; | |
134 | ||
135 | /* | |
136 | * The timestamp latches on lowest register read. For I210/I211, the | |
137 | * lowest register is SYSTIMR. Since we only need to provide nanosecond | |
138 | * resolution, we can ignore it. | |
139 | */ | |
140 | jk = rd32(E1000_SYSTIMR); | |
141 | nsec = rd32(E1000_SYSTIML); | |
142 | sec = rd32(E1000_SYSTIMH); | |
143 | ||
144 | ts->tv_sec = sec; | |
145 | ts->tv_nsec = nsec; | |
146 | } | |
147 | ||
148 | static void igb_ptp_write_i210(struct igb_adapter *adapter, | |
149 | const struct timespec *ts) | |
150 | { | |
151 | struct e1000_hw *hw = &adapter->hw; | |
152 | ||
153 | /* | |
154 | * Writing the SYSTIMR register is not necessary as it only provides | |
155 | * sub-nanosecond resolution. | |
156 | */ | |
157 | wr32(E1000_SYSTIML, ts->tv_nsec); | |
158 | wr32(E1000_SYSTIMH, ts->tv_sec); | |
159 | } | |
160 | ||
a79f4f88 MV |
161 | /** |
162 | * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp | |
163 | * @adapter: board private structure | |
164 | * @hwtstamps: timestamp structure to update | |
165 | * @systim: unsigned 64bit system time value. | |
166 | * | |
167 | * We need to convert the system time value stored in the RX/TXSTMP registers | |
168 | * into a hwtstamp which can be used by the upper level timestamping functions. | |
169 | * | |
170 | * The 'tmreg_lock' spinlock is used to protect the consistency of the | |
171 | * system time value. This is needed because reading the 64 bit time | |
172 | * value involves reading two (or three) 32 bit registers. The first | |
173 | * read latches the value. Ditto for writing. | |
174 | * | |
175 | * In addition, here have extended the system time with an overflow | |
176 | * counter in software. | |
177 | **/ | |
178 | static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, | |
179 | struct skb_shared_hwtstamps *hwtstamps, | |
180 | u64 systim) | |
181 | { | |
182 | unsigned long flags; | |
183 | u64 ns; | |
184 | ||
185 | switch (adapter->hw.mac.type) { | |
e57b8bdb MV |
186 | case e1000_82576: |
187 | case e1000_82580: | |
188 | case e1000_i350: | |
189 | spin_lock_irqsave(&adapter->tmreg_lock, flags); | |
190 | ||
191 | ns = timecounter_cyc2time(&adapter->tc, systim); | |
192 | ||
193 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); | |
194 | ||
195 | memset(hwtstamps, 0, sizeof(*hwtstamps)); | |
196 | hwtstamps->hwtstamp = ns_to_ktime(ns); | |
197 | break; | |
a79f4f88 MV |
198 | case e1000_i210: |
199 | case e1000_i211: | |
e57b8bdb MV |
200 | memset(hwtstamps, 0, sizeof(*hwtstamps)); |
201 | /* Upper 32 bits contain s, lower 32 bits contain ns. */ | |
202 | hwtstamps->hwtstamp = ktime_set(systim >> 32, | |
203 | systim & 0xFFFFFFFF); | |
a79f4f88 MV |
204 | break; |
205 | default: | |
e57b8bdb | 206 | break; |
a79f4f88 | 207 | } |
a79f4f88 MV |
208 | } |
209 | ||
d339b133 RC |
210 | /* |
211 | * PTP clock operations | |
212 | */ | |
213 | ||
a79f4f88 | 214 | static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) |
d339b133 | 215 | { |
a79f4f88 MV |
216 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
217 | ptp_caps); | |
218 | struct e1000_hw *hw = &igb->hw; | |
219 | int neg_adj = 0; | |
d339b133 RC |
220 | u64 rate; |
221 | u32 incvalue; | |
d339b133 RC |
222 | |
223 | if (ppb < 0) { | |
224 | neg_adj = 1; | |
225 | ppb = -ppb; | |
226 | } | |
227 | rate = ppb; | |
228 | rate <<= 14; | |
229 | rate = div_u64(rate, 1953125); | |
230 | ||
231 | incvalue = 16 << IGB_82576_TSYNC_SHIFT; | |
232 | ||
233 | if (neg_adj) | |
234 | incvalue -= rate; | |
235 | else | |
236 | incvalue += rate; | |
237 | ||
238 | wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
a79f4f88 | 243 | static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb) |
d339b133 | 244 | { |
a79f4f88 MV |
245 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
246 | ptp_caps); | |
247 | struct e1000_hw *hw = &igb->hw; | |
248 | int neg_adj = 0; | |
d339b133 RC |
249 | u64 rate; |
250 | u32 inca; | |
d339b133 RC |
251 | |
252 | if (ppb < 0) { | |
253 | neg_adj = 1; | |
254 | ppb = -ppb; | |
255 | } | |
256 | rate = ppb; | |
257 | rate <<= 26; | |
258 | rate = div_u64(rate, 1953125); | |
259 | ||
260 | inca = rate & INCVALUE_MASK; | |
261 | if (neg_adj) | |
262 | inca |= ISGN; | |
263 | ||
264 | wr32(E1000_TIMINCA, inca); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
e57b8bdb | 269 | static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) |
d339b133 | 270 | { |
a79f4f88 MV |
271 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
272 | ptp_caps); | |
d339b133 | 273 | unsigned long flags; |
a79f4f88 | 274 | s64 now; |
d339b133 RC |
275 | |
276 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
277 | ||
278 | now = timecounter_read(&igb->tc); | |
279 | now += delta; | |
280 | timecounter_init(&igb->tc, &igb->cc, now); | |
281 | ||
282 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
e57b8bdb MV |
287 | static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) |
288 | { | |
289 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
290 | ptp_caps); | |
291 | unsigned long flags; | |
292 | struct timespec now, then = ns_to_timespec(delta); | |
293 | ||
294 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
295 | ||
296 | igb_ptp_read_i210(igb, &now); | |
297 | now = timespec_add(now, then); | |
298 | igb_ptp_write_i210(igb, (const struct timespec *)&now); | |
299 | ||
300 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
305 | static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp, | |
306 | struct timespec *ts) | |
d339b133 | 307 | { |
a79f4f88 MV |
308 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
309 | ptp_caps); | |
310 | unsigned long flags; | |
d339b133 RC |
311 | u64 ns; |
312 | u32 remainder; | |
d339b133 RC |
313 | |
314 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
315 | ||
316 | ns = timecounter_read(&igb->tc); | |
317 | ||
318 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
319 | ||
320 | ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder); | |
321 | ts->tv_nsec = remainder; | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
e57b8bdb MV |
326 | static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp, |
327 | struct timespec *ts) | |
328 | { | |
329 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
330 | ptp_caps); | |
331 | unsigned long flags; | |
332 | ||
333 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
334 | ||
335 | igb_ptp_read_i210(igb, ts); | |
336 | ||
337 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, | |
343 | const struct timespec *ts) | |
d339b133 | 344 | { |
a79f4f88 MV |
345 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
346 | ptp_caps); | |
d339b133 | 347 | unsigned long flags; |
a79f4f88 | 348 | u64 ns; |
d339b133 RC |
349 | |
350 | ns = ts->tv_sec * 1000000000ULL; | |
351 | ns += ts->tv_nsec; | |
352 | ||
353 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
354 | ||
355 | timecounter_init(&igb->tc, &igb->cc, ns); | |
356 | ||
357 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
e57b8bdb MV |
362 | static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, |
363 | const struct timespec *ts) | |
364 | { | |
365 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
366 | ptp_caps); | |
367 | unsigned long flags; | |
368 | ||
369 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
370 | ||
371 | igb_ptp_write_i210(igb, ts); | |
372 | ||
373 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
a79f4f88 MV |
378 | static int igb_ptp_enable(struct ptp_clock_info *ptp, |
379 | struct ptp_clock_request *rq, int on) | |
d339b133 RC |
380 | { |
381 | return -EOPNOTSUPP; | |
382 | } | |
383 | ||
1f6e8178 MV |
384 | /** |
385 | * igb_ptp_tx_work | |
386 | * @work: pointer to work struct | |
387 | * | |
388 | * This work function polls the TSYNCTXCTL valid bit to determine when a | |
389 | * timestamp has been taken for the current stored skb. | |
390 | */ | |
391 | void igb_ptp_tx_work(struct work_struct *work) | |
392 | { | |
393 | struct igb_adapter *adapter = container_of(work, struct igb_adapter, | |
394 | ptp_tx_work); | |
395 | struct e1000_hw *hw = &adapter->hw; | |
396 | u32 tsynctxctl; | |
397 | ||
398 | if (!adapter->ptp_tx_skb) | |
399 | return; | |
400 | ||
428f1f71 MV |
401 | if (time_is_before_jiffies(adapter->ptp_tx_start + |
402 | IGB_PTP_TX_TIMEOUT)) { | |
403 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
404 | adapter->ptp_tx_skb = NULL; | |
405 | adapter->tx_hwtstamp_timeouts++; | |
406 | dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang"); | |
407 | return; | |
408 | } | |
409 | ||
1f6e8178 MV |
410 | tsynctxctl = rd32(E1000_TSYNCTXCTL); |
411 | if (tsynctxctl & E1000_TSYNCTXCTL_VALID) | |
412 | igb_ptp_tx_hwtstamp(adapter); | |
413 | else | |
414 | /* reschedule to check later */ | |
415 | schedule_work(&adapter->ptp_tx_work); | |
416 | } | |
417 | ||
a79f4f88 | 418 | static void igb_ptp_overflow_check(struct work_struct *work) |
d339b133 | 419 | { |
a79f4f88 MV |
420 | struct igb_adapter *igb = |
421 | container_of(work, struct igb_adapter, ptp_overflow_work.work); | |
422 | struct timespec ts; | |
423 | ||
e57b8bdb | 424 | igb->ptp_caps.gettime(&igb->ptp_caps, &ts); |
a79f4f88 MV |
425 | |
426 | pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec); | |
427 | ||
428 | schedule_delayed_work(&igb->ptp_overflow_work, | |
429 | IGB_SYSTIM_OVERFLOW_PERIOD); | |
d339b133 RC |
430 | } |
431 | ||
fc580751 MV |
432 | /** |
433 | * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched | |
434 | * @adapter: private network adapter structure | |
435 | * | |
436 | * This watchdog task is scheduled to detect error case where hardware has | |
437 | * dropped an Rx packet that was timestamped when the ring is full. The | |
438 | * particular error is rare but leaves the device in a state unable to timestamp | |
439 | * any future packets. | |
440 | */ | |
441 | void igb_ptp_rx_hang(struct igb_adapter *adapter) | |
442 | { | |
443 | struct e1000_hw *hw = &adapter->hw; | |
444 | struct igb_ring *rx_ring; | |
445 | u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); | |
446 | unsigned long rx_event; | |
447 | int n; | |
448 | ||
449 | if (hw->mac.type != e1000_82576) | |
450 | return; | |
451 | ||
452 | /* If we don't have a valid timestamp in the registers, just update the | |
453 | * timeout counter and exit | |
454 | */ | |
455 | if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { | |
456 | adapter->last_rx_ptp_check = jiffies; | |
457 | return; | |
458 | } | |
459 | ||
460 | /* Determine the most recent watchdog or rx_timestamp event */ | |
461 | rx_event = adapter->last_rx_ptp_check; | |
462 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
463 | rx_ring = adapter->rx_ring[n]; | |
464 | if (time_after(rx_ring->last_rx_timestamp, rx_event)) | |
465 | rx_event = rx_ring->last_rx_timestamp; | |
466 | } | |
467 | ||
468 | /* Only need to read the high RXSTMP register to clear the lock */ | |
469 | if (time_is_before_jiffies(rx_event + 5 * HZ)) { | |
470 | rd32(E1000_RXSTMPH); | |
471 | adapter->last_rx_ptp_check = jiffies; | |
472 | adapter->rx_hwtstamp_cleared++; | |
473 | dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang"); | |
474 | } | |
475 | } | |
476 | ||
a79f4f88 MV |
477 | /** |
478 | * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp | |
1f6e8178 | 479 | * @adapter: Board private structure. |
a79f4f88 MV |
480 | * |
481 | * If we were asked to do hardware stamping and such a time stamp is | |
482 | * available, then it must have been for this skb here because we only | |
483 | * allow only one such packet into the queue. | |
484 | */ | |
1f6e8178 | 485 | void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) |
d339b133 | 486 | { |
a79f4f88 MV |
487 | struct e1000_hw *hw = &adapter->hw; |
488 | struct skb_shared_hwtstamps shhwtstamps; | |
489 | u64 regval; | |
d339b133 | 490 | |
a79f4f88 MV |
491 | regval = rd32(E1000_TXSTMPL); |
492 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | |
d339b133 | 493 | |
a79f4f88 | 494 | igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); |
1f6e8178 MV |
495 | skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); |
496 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
497 | adapter->ptp_tx_skb = NULL; | |
a79f4f88 MV |
498 | } |
499 | ||
b534550a AD |
500 | /** |
501 | * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp | |
502 | * @q_vector: Pointer to interrupt specific structure | |
503 | * @va: Pointer to address containing Rx buffer | |
504 | * @skb: Buffer containing timestamp and packet | |
505 | * | |
506 | * This function is meant to retrieve a timestamp from the first buffer of an | |
507 | * incoming frame. The value is stored in little endian format starting on | |
508 | * byte 8. | |
509 | */ | |
510 | void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, | |
511 | unsigned char *va, | |
512 | struct sk_buff *skb) | |
513 | { | |
ac61d515 | 514 | __le64 *regval = (__le64 *)va; |
b534550a AD |
515 | |
516 | /* | |
517 | * The timestamp is recorded in little endian format. | |
518 | * DWORD: 0 1 2 3 | |
519 | * Field: Reserved Reserved SYSTIML SYSTIMH | |
520 | */ | |
521 | igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb), | |
522 | le64_to_cpu(regval[1])); | |
523 | } | |
524 | ||
525 | /** | |
526 | * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register | |
527 | * @q_vector: Pointer to interrupt specific structure | |
528 | * @skb: Buffer containing timestamp and packet | |
529 | * | |
530 | * This function is meant to retrieve a timestamp from the internal registers | |
531 | * of the adapter and store it in the skb. | |
532 | */ | |
533 | void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, | |
a79f4f88 MV |
534 | struct sk_buff *skb) |
535 | { | |
536 | struct igb_adapter *adapter = q_vector->adapter; | |
537 | struct e1000_hw *hw = &adapter->hw; | |
538 | u64 regval; | |
539 | ||
a79f4f88 MV |
540 | /* |
541 | * If this bit is set, then the RX registers contain the time stamp. No | |
542 | * other packet will be time stamped until we read these registers, so | |
543 | * read the registers to make them available again. Because only one | |
544 | * packet can be time stamped at a time, we know that the register | |
545 | * values must belong to this one here and therefore we don't need to | |
546 | * compare any of the additional attributes stored for it. | |
547 | * | |
548 | * If nothing went wrong, then it should have a shared tx_flags that we | |
549 | * can turn into a skb_shared_hwtstamps. | |
550 | */ | |
b534550a AD |
551 | if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) |
552 | return; | |
553 | ||
554 | regval = rd32(E1000_RXSTMPL); | |
555 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | |
a79f4f88 MV |
556 | |
557 | igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); | |
558 | } | |
559 | ||
560 | /** | |
561 | * igb_ptp_hwtstamp_ioctl - control hardware time stamping | |
562 | * @netdev: | |
563 | * @ifreq: | |
564 | * @cmd: | |
565 | * | |
566 | * Outgoing time stamping can be enabled and disabled. Play nice and | |
567 | * disable it when requested, although it shouldn't case any overhead | |
568 | * when no packet needs it. At most one packet in the queue may be | |
569 | * marked for time stamping, otherwise it would be impossible to tell | |
570 | * for sure to which packet the hardware time stamp belongs. | |
571 | * | |
572 | * Incoming time stamping has to be configured via the hardware | |
573 | * filters. Not all combinations are supported, in particular event | |
574 | * type has to be specified. Matching the kind of event packet is | |
575 | * not supported, with the exception of "all V2 events regardless of | |
576 | * level 2 or 4". | |
577 | * | |
578 | **/ | |
579 | int igb_ptp_hwtstamp_ioctl(struct net_device *netdev, | |
580 | struct ifreq *ifr, int cmd) | |
581 | { | |
582 | struct igb_adapter *adapter = netdev_priv(netdev); | |
583 | struct e1000_hw *hw = &adapter->hw; | |
584 | struct hwtstamp_config config; | |
585 | u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; | |
586 | u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
587 | u32 tsync_rx_cfg = 0; | |
588 | bool is_l4 = false; | |
589 | bool is_l2 = false; | |
590 | u32 regval; | |
591 | ||
592 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
593 | return -EFAULT; | |
594 | ||
595 | /* reserved for future extensions */ | |
596 | if (config.flags) | |
597 | return -EINVAL; | |
598 | ||
599 | switch (config.tx_type) { | |
600 | case HWTSTAMP_TX_OFF: | |
601 | tsync_tx_ctl = 0; | |
602 | case HWTSTAMP_TX_ON: | |
603 | break; | |
604 | default: | |
605 | return -ERANGE; | |
606 | } | |
607 | ||
608 | switch (config.rx_filter) { | |
609 | case HWTSTAMP_FILTER_NONE: | |
610 | tsync_rx_ctl = 0; | |
611 | break; | |
a79f4f88 MV |
612 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
613 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
614 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; | |
615 | is_l4 = true; | |
616 | break; | |
617 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
618 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
619 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; | |
620 | is_l4 = true; | |
621 | break; | |
3e961a06 MV |
622 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
623 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
624 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
625 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
a79f4f88 MV |
626 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: |
627 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3e961a06 | 628 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
a79f4f88 MV |
629 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: |
630 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
a79f4f88 MV |
631 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; |
632 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
633 | is_l2 = true; | |
634 | is_l4 = true; | |
635 | break; | |
3e961a06 MV |
636 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
637 | case HWTSTAMP_FILTER_ALL: | |
638 | /* 82576 cannot timestamp all packets, which it needs to do to | |
639 | * support both V1 Sync and Delay_Req messages | |
640 | */ | |
641 | if (hw->mac.type != e1000_82576) { | |
642 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; | |
643 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
644 | break; | |
645 | } | |
646 | /* fall through */ | |
a79f4f88 | 647 | default: |
3e961a06 | 648 | config.rx_filter = HWTSTAMP_FILTER_NONE; |
a79f4f88 MV |
649 | return -ERANGE; |
650 | } | |
651 | ||
652 | if (hw->mac.type == e1000_82575) { | |
653 | if (tsync_rx_ctl | tsync_tx_ctl) | |
654 | return -EINVAL; | |
655 | return 0; | |
656 | } | |
657 | ||
658 | /* | |
659 | * Per-packet timestamping only works if all packets are | |
660 | * timestamped, so enable timestamping in all packets as | |
661 | * long as one rx filter was configured. | |
662 | */ | |
663 | if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { | |
664 | tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
665 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; | |
3e961a06 MV |
666 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
667 | is_l2 = true; | |
668 | is_l4 = true; | |
e57b8bdb MV |
669 | |
670 | if ((hw->mac.type == e1000_i210) || | |
671 | (hw->mac.type == e1000_i211)) { | |
672 | regval = rd32(E1000_RXPBS); | |
673 | regval |= E1000_RXPBS_CFG_TS_EN; | |
674 | wr32(E1000_RXPBS, regval); | |
675 | } | |
a79f4f88 MV |
676 | } |
677 | ||
678 | /* enable/disable TX */ | |
679 | regval = rd32(E1000_TSYNCTXCTL); | |
680 | regval &= ~E1000_TSYNCTXCTL_ENABLED; | |
681 | regval |= tsync_tx_ctl; | |
682 | wr32(E1000_TSYNCTXCTL, regval); | |
683 | ||
684 | /* enable/disable RX */ | |
685 | regval = rd32(E1000_TSYNCRXCTL); | |
686 | regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); | |
687 | regval |= tsync_rx_ctl; | |
688 | wr32(E1000_TSYNCRXCTL, regval); | |
689 | ||
690 | /* define which PTP packets are time stamped */ | |
691 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); | |
692 | ||
693 | /* define ethertype filter for timestamped packets */ | |
694 | if (is_l2) | |
695 | wr32(E1000_ETQF(3), | |
696 | (E1000_ETQF_FILTER_ENABLE | /* enable filter */ | |
697 | E1000_ETQF_1588 | /* enable timestamping */ | |
698 | ETH_P_1588)); /* 1588 eth protocol type */ | |
699 | else | |
700 | wr32(E1000_ETQF(3), 0); | |
701 | ||
a79f4f88 MV |
702 | /* L4 Queue Filter[3]: filter by destination port and protocol */ |
703 | if (is_l4) { | |
704 | u32 ftqf = (IPPROTO_UDP /* UDP */ | |
705 | | E1000_FTQF_VF_BP /* VF not compared */ | |
706 | | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ | |
707 | | E1000_FTQF_MASK); /* mask all inputs */ | |
708 | ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ | |
709 | ||
ba59814b | 710 | wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); |
a79f4f88 MV |
711 | wr32(E1000_IMIREXT(3), |
712 | (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); | |
713 | if (hw->mac.type == e1000_82576) { | |
714 | /* enable source port check */ | |
ba59814b | 715 | wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); |
a79f4f88 MV |
716 | ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; |
717 | } | |
718 | wr32(E1000_FTQF(3), ftqf); | |
719 | } else { | |
720 | wr32(E1000_FTQF(3), E1000_FTQF_MASK); | |
721 | } | |
722 | wrfl(); | |
723 | ||
724 | /* clear TX/RX time stamp registers, just to be sure */ | |
e57b8bdb | 725 | regval = rd32(E1000_TXSTMPL); |
a79f4f88 | 726 | regval = rd32(E1000_TXSTMPH); |
e57b8bdb | 727 | regval = rd32(E1000_RXSTMPL); |
a79f4f88 MV |
728 | regval = rd32(E1000_RXSTMPH); |
729 | ||
730 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
731 | -EFAULT : 0; | |
d339b133 RC |
732 | } |
733 | ||
734 | void igb_ptp_init(struct igb_adapter *adapter) | |
735 | { | |
736 | struct e1000_hw *hw = &adapter->hw; | |
201987e3 | 737 | struct net_device *netdev = adapter->netdev; |
d339b133 RC |
738 | |
739 | switch (hw->mac.type) { | |
e57b8bdb MV |
740 | case e1000_82576: |
741 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); | |
742 | adapter->ptp_caps.owner = THIS_MODULE; | |
75517d92 | 743 | adapter->ptp_caps.max_adj = 999999881; |
e57b8bdb MV |
744 | adapter->ptp_caps.n_ext_ts = 0; |
745 | adapter->ptp_caps.pps = 0; | |
746 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; | |
747 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; | |
748 | adapter->ptp_caps.gettime = igb_ptp_gettime_82576; | |
749 | adapter->ptp_caps.settime = igb_ptp_settime_82576; | |
750 | adapter->ptp_caps.enable = igb_ptp_enable; | |
751 | adapter->cc.read = igb_ptp_read_82576; | |
752 | adapter->cc.mask = CLOCKSOURCE_MASK(64); | |
753 | adapter->cc.mult = 1; | |
754 | adapter->cc.shift = IGB_82576_TSYNC_SHIFT; | |
755 | /* Dial the nominal frequency. */ | |
756 | wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); | |
757 | break; | |
d339b133 | 758 | case e1000_82580: |
e57b8bdb | 759 | case e1000_i350: |
201987e3 | 760 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
a79f4f88 | 761 | adapter->ptp_caps.owner = THIS_MODULE; |
a79f4f88 MV |
762 | adapter->ptp_caps.max_adj = 62499999; |
763 | adapter->ptp_caps.n_ext_ts = 0; | |
764 | adapter->ptp_caps.pps = 0; | |
765 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; | |
e57b8bdb MV |
766 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; |
767 | adapter->ptp_caps.gettime = igb_ptp_gettime_82576; | |
768 | adapter->ptp_caps.settime = igb_ptp_settime_82576; | |
a79f4f88 MV |
769 | adapter->ptp_caps.enable = igb_ptp_enable; |
770 | adapter->cc.read = igb_ptp_read_82580; | |
771 | adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580); | |
772 | adapter->cc.mult = 1; | |
773 | adapter->cc.shift = 0; | |
d339b133 RC |
774 | /* Enable the timer functions by clearing bit 31. */ |
775 | wr32(E1000_TSAUXC, 0x0); | |
776 | break; | |
e57b8bdb MV |
777 | case e1000_i210: |
778 | case e1000_i211: | |
201987e3 | 779 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
a79f4f88 | 780 | adapter->ptp_caps.owner = THIS_MODULE; |
e57b8bdb | 781 | adapter->ptp_caps.max_adj = 62499999; |
a79f4f88 MV |
782 | adapter->ptp_caps.n_ext_ts = 0; |
783 | adapter->ptp_caps.pps = 0; | |
e57b8bdb MV |
784 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; |
785 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; | |
786 | adapter->ptp_caps.gettime = igb_ptp_gettime_i210; | |
787 | adapter->ptp_caps.settime = igb_ptp_settime_i210; | |
a79f4f88 | 788 | adapter->ptp_caps.enable = igb_ptp_enable; |
e57b8bdb MV |
789 | /* Enable the timer functions by clearing bit 31. */ |
790 | wr32(E1000_TSAUXC, 0x0); | |
d339b133 | 791 | break; |
d339b133 RC |
792 | default: |
793 | adapter->ptp_clock = NULL; | |
794 | return; | |
795 | } | |
796 | ||
797 | wrfl(); | |
798 | ||
e57b8bdb MV |
799 | spin_lock_init(&adapter->tmreg_lock); |
800 | INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); | |
d339b133 | 801 | |
e57b8bdb MV |
802 | /* Initialize the clock and overflow work for devices that need it. */ |
803 | if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { | |
804 | struct timespec ts = ktime_to_timespec(ktime_get_real()); | |
d339b133 | 805 | |
e57b8bdb MV |
806 | igb_ptp_settime_i210(&adapter->ptp_caps, &ts); |
807 | } else { | |
808 | timecounter_init(&adapter->tc, &adapter->cc, | |
809 | ktime_to_ns(ktime_get_real())); | |
d339b133 | 810 | |
e57b8bdb MV |
811 | INIT_DELAYED_WORK(&adapter->ptp_overflow_work, |
812 | igb_ptp_overflow_check); | |
1f6e8178 | 813 | |
e57b8bdb MV |
814 | schedule_delayed_work(&adapter->ptp_overflow_work, |
815 | IGB_SYSTIM_OVERFLOW_PERIOD); | |
816 | } | |
d339b133 | 817 | |
1f6e8178 MV |
818 | /* Initialize the time sync interrupts for devices that support it. */ |
819 | if (hw->mac.type >= e1000_82580) { | |
820 | wr32(E1000_TSIM, E1000_TSIM_TXTS); | |
821 | wr32(E1000_IMS, E1000_IMS_TS); | |
822 | } | |
823 | ||
1ef76158 RC |
824 | adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, |
825 | &adapter->pdev->dev); | |
d339b133 RC |
826 | if (IS_ERR(adapter->ptp_clock)) { |
827 | adapter->ptp_clock = NULL; | |
828 | dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); | |
1f6e8178 | 829 | } else { |
d339b133 RC |
830 | dev_info(&adapter->pdev->dev, "added PHC on %s\n", |
831 | adapter->netdev->name); | |
1f6e8178 MV |
832 | adapter->flags |= IGB_FLAG_PTP; |
833 | } | |
d339b133 RC |
834 | } |
835 | ||
a79f4f88 MV |
836 | /** |
837 | * igb_ptp_stop - Disable PTP device and stop the overflow check. | |
838 | * @adapter: Board private structure. | |
839 | * | |
840 | * This function stops the PTP support and cancels the delayed work. | |
841 | **/ | |
842 | void igb_ptp_stop(struct igb_adapter *adapter) | |
d339b133 | 843 | { |
d3eef8c8 | 844 | switch (adapter->hw.mac.type) { |
d3eef8c8 | 845 | case e1000_82576: |
1f6e8178 MV |
846 | case e1000_82580: |
847 | case e1000_i350: | |
a79f4f88 | 848 | cancel_delayed_work_sync(&adapter->ptp_overflow_work); |
d3eef8c8 | 849 | break; |
1f6e8178 MV |
850 | case e1000_i210: |
851 | case e1000_i211: | |
852 | /* No delayed work to cancel. */ | |
853 | break; | |
d3eef8c8 CW |
854 | default: |
855 | return; | |
856 | } | |
d339b133 | 857 | |
1f6e8178 | 858 | cancel_work_sync(&adapter->ptp_tx_work); |
badc26dd MV |
859 | if (adapter->ptp_tx_skb) { |
860 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
861 | adapter->ptp_tx_skb = NULL; | |
862 | } | |
1f6e8178 | 863 | |
d339b133 RC |
864 | if (adapter->ptp_clock) { |
865 | ptp_clock_unregister(adapter->ptp_clock); | |
866 | dev_info(&adapter->pdev->dev, "removed PHC on %s\n", | |
867 | adapter->netdev->name); | |
1f6e8178 | 868 | adapter->flags &= ~IGB_FLAG_PTP; |
d339b133 RC |
869 | } |
870 | } | |
1f6e8178 MV |
871 | |
872 | /** | |
873 | * igb_ptp_reset - Re-enable the adapter for PTP following a reset. | |
874 | * @adapter: Board private structure. | |
875 | * | |
876 | * This function handles the reset work required to re-enable the PTP device. | |
877 | **/ | |
878 | void igb_ptp_reset(struct igb_adapter *adapter) | |
879 | { | |
880 | struct e1000_hw *hw = &adapter->hw; | |
881 | ||
882 | if (!(adapter->flags & IGB_FLAG_PTP)) | |
883 | return; | |
884 | ||
885 | switch (adapter->hw.mac.type) { | |
886 | case e1000_82576: | |
887 | /* Dial the nominal frequency. */ | |
888 | wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); | |
889 | break; | |
890 | case e1000_82580: | |
891 | case e1000_i350: | |
892 | case e1000_i210: | |
893 | case e1000_i211: | |
894 | /* Enable the timer functions and interrupts. */ | |
895 | wr32(E1000_TSAUXC, 0x0); | |
896 | wr32(E1000_TSIM, E1000_TSIM_TXTS); | |
897 | wr32(E1000_IMS, E1000_IMS_TS); | |
898 | break; | |
899 | default: | |
900 | /* No work to do. */ | |
901 | return; | |
902 | } | |
903 | ||
e57b8bdb MV |
904 | /* Re-initialize the timer. */ |
905 | if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { | |
906 | struct timespec ts = ktime_to_timespec(ktime_get_real()); | |
907 | ||
908 | igb_ptp_settime_i210(&adapter->ptp_caps, &ts); | |
909 | } else { | |
910 | timecounter_init(&adapter->tc, &adapter->cc, | |
911 | ktime_to_ns(ktime_get_real())); | |
912 | } | |
1f6e8178 | 913 | } |