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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / epic100.c
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1da177e4
LT		 1/* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2/*
3 Written/copyright 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the SMC83c170/175 "EPIC" series, as used on the
13 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Information and updates available at
21 http://www.scyld.com/network/epic100.html
36e1e847 22 [this link no longer provides anything useful -jgarzik]
1da177e4
LT		 23
24 ---------------------------------------------------------------------
f3b197ac 25
1da177e4
LT		 26*/
27
28#define DRV_NAME "epic100"
d5b20697
AG		 29#define DRV_VERSION "2.1"
30#define DRV_RELDATE "Sept 11, 2006"
1da177e4
LT		 31
32/* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36
37/* Used to pass the full-duplex flag, etc. */
38#define MAX_UNITS 8 /* More are supported, limit only on options */
39static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
40static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
41
42/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
43 Setting to > 1518 effectively disables this feature. */
44static int rx_copybreak;
45
46/* Operational parameters that are set at compile time. */
47
48/* Keep the ring sizes a power of two for operational efficiency.
49 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
50 Making the Tx ring too large decreases the effectiveness of channel
51 bonding and packet priority.
52 There are no ill effects from too-large receive rings. */
53#define TX_RING_SIZE 256
54#define TX_QUEUE_LEN 240 /* Limit ring entries actually used. */
55#define RX_RING_SIZE 256
56#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc)
57#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc)
58
59/* Operational parameters that usually are not changed. */
60/* Time in jiffies before concluding the transmitter is hung. */
61#define TX_TIMEOUT (2*HZ)
62
63#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
64
65/* Bytes transferred to chip before transmission starts. */
66/* Initial threshold, increased on underflow, rounded down to 4 byte units. */
67#define TX_FIFO_THRESH 256
68#define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
69
1da177e4
LT		 70#include <linux/module.h>
71#include <linux/kernel.h>
72#include <linux/string.h>
73#include <linux/timer.h>
74#include <linux/errno.h>
75#include <linux/ioport.h>
76#include <linux/slab.h>
77#include <linux/interrupt.h>
78#include <linux/pci.h>
79#include <linux/delay.h>
80#include <linux/netdevice.h>
81#include <linux/etherdevice.h>
82#include <linux/skbuff.h>
83#include <linux/init.h>
84#include <linux/spinlock.h>
85#include <linux/ethtool.h>
86#include <linux/mii.h>
87#include <linux/crc32.h>
88#include <linux/bitops.h>
89#include <asm/io.h>
90#include <asm/uaccess.h>
91
92/* These identify the driver base version and may not be removed. */
93static char version[] __devinitdata =
94DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>\n";
95static char version2[] __devinitdata =
1da177e4
LT		 96" (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
97
98MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
99MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
100MODULE_LICENSE("GPL");
101
102module_param(debug, int, 0);
103module_param(rx_copybreak, int, 0);
104module_param_array(options, int, NULL, 0);
105module_param_array(full_duplex, int, NULL, 0);
106MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)");
107MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
108MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames");
109MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)");
110
111/*
112 Theory of Operation
113
114I. Board Compatibility
115
116This device driver is designed for the SMC "EPIC/100", the SMC
117single-chip Ethernet controllers for PCI. This chip is used on
118the SMC EtherPower II boards.
119
120II. Board-specific settings
121
122PCI bus devices are configured by the system at boot time, so no jumpers
123need to be set on the board. The system BIOS will assign the
124PCI INTA signal to a (preferably otherwise unused) system IRQ line.
125Note: Kernel versions earlier than 1.3.73 do not support shared PCI
126interrupt lines.
127
128III. Driver operation
129
130IIIa. Ring buffers
131
132IVb. References
133
9ebfd492
AV		 134http://www.smsc.com/main/tools/discontinued/83c171.pdf
135http://www.smsc.com/main/tools/discontinued/83c175.pdf
1da177e4
LT		 136http://scyld.com/expert/NWay.html
137http://www.national.com/pf/DP/DP83840A.html
138
139IVc. Errata
140
141*/
142
143
1da177e4
LT		 144enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
145
146#define EPIC_TOTAL_SIZE 0x100
147#define USE_IO_OPS 1
1da177e4
LT		 148
149typedef enum {
150 SMSC_83C170_0,
151 SMSC_83C170,
152 SMSC_83C175,
153} chip_t;
154
155
156struct epic_chip_info {
157 const char *name;
1da177e4
LT		 158 int drv_flags; /* Driver use, intended as capability flags. */
159};
160
161
162/* indexed by chip_t */
f71e1309 163static const struct epic_chip_info pci_id_tbl[] = {
36e1e847
JG		 164 { "SMSC EPIC/100 83c170", TYPE2_INTR | NO_MII | MII_PWRDWN },
165 { "SMSC EPIC/100 83c170", TYPE2_INTR },
166 { "SMSC EPIC/C 83c175", TYPE2_INTR | MII_PWRDWN },
1da177e4
LT		 167};
168
169
a3aa1884 170static DEFINE_PCI_DEVICE_TABLE(epic_pci_tbl) = {
1da177e4
LT		 171 { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
172 { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
173 { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
174 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
175 { 0,}
176};
177MODULE_DEVICE_TABLE (pci, epic_pci_tbl);
178
f3b197ac 179
1da177e4
LT		 180#ifndef USE_IO_OPS
181#undef inb
182#undef inw
183#undef inl
184#undef outb
185#undef outw
186#undef outl
187#define inb readb
188#define inw readw
189#define inl readl
190#define outb writeb
191#define outw writew
192#define outl writel
193#endif
194
195/* Offsets to registers, using the (ugh) SMC names. */
196enum epic_registers {
197 COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
198 PCIBurstCnt=0x18,
199 TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
200 MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
201 LAN0=64, /* MAC address. */
202 MC0=80, /* Multicast filter table. */
203 RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
204 PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
205};
206
207/* Interrupt register bits, using my own meaningful names. */
208enum IntrStatus {
209 TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
210 PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
211 RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
212 TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
213 RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
214};
215enum CommandBits {
216 StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
217 StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
218};
219
220#define EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */
221
222#define EpicNapiEvent (TxEmpty | TxDone | \
223 RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull)
224#define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent)
225
f71e1309 226static const u16 media2miictl[16] = {
1da177e4
LT		 227 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
228 0, 0, 0, 0, 0, 0, 0, 0 };
229
9ebfd492
AV		 230/*
231 * The EPIC100 Rx and Tx buffer descriptors. Note that these
232 * really ARE host-endian; it's not a misannotation. We tell
233 * the card to byteswap them internally on big-endian hosts -
234 * look for #ifdef CONFIG_BIG_ENDIAN in epic_open().
235 */
1da177e4
LT		 236
237struct epic_tx_desc {
238 u32 txstatus;
239 u32 bufaddr;
240 u32 buflength;
241 u32 next;
242};
243
244struct epic_rx_desc {
245 u32 rxstatus;
246 u32 bufaddr;
247 u32 buflength;
248 u32 next;
249};
250
251enum desc_status_bits {
252 DescOwn=0x8000,
253};
254
255#define PRIV_ALIGN 15 /* Required alignment mask */
256struct epic_private {
257 struct epic_rx_desc *rx_ring;
258 struct epic_tx_desc *tx_ring;
259 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
260 struct sk_buff* tx_skbuff[TX_RING_SIZE];
261 /* The addresses of receive-in-place skbuffs. */
262 struct sk_buff* rx_skbuff[RX_RING_SIZE];
263
264 dma_addr_t tx_ring_dma;
265 dma_addr_t rx_ring_dma;
266
267 /* Ring pointers. */
268 spinlock_t lock; /* Group with Tx control cache line. */
269 spinlock_t napi_lock;
bea3348e 270 struct napi_struct napi;
1da177e4
LT		 271 unsigned int reschedule_in_poll;
272 unsigned int cur_tx, dirty_tx;
273
274 unsigned int cur_rx, dirty_rx;
275 u32 irq_mask;
276 unsigned int rx_buf_sz; /* Based on MTU+slack. */
277
278 struct pci_dev *pci_dev; /* PCI bus location. */
279 int chip_id, chip_flags;
280
281 struct net_device_stats stats;
282 struct timer_list timer; /* Media selection timer. */
283 int tx_threshold;
284 unsigned char mc_filter[8];
285 signed char phys[4]; /* MII device addresses. */
286 u16 advertising; /* NWay media advertisement */
287 int mii_phy_cnt;
288 struct mii_if_info mii;
289 unsigned int tx_full:1; /* The Tx queue is full. */
290 unsigned int default_port:4; /* Last dev->if_port value. */
291};
292
293static int epic_open(struct net_device *dev);
294static int read_eeprom(long ioaddr, int location);
295static int mdio_read(struct net_device *dev, int phy_id, int location);
296static void mdio_write(struct net_device *dev, int phy_id, int loc, int val);
297static void epic_restart(struct net_device *dev);
298static void epic_timer(unsigned long data);
299static void epic_tx_timeout(struct net_device *dev);
300static void epic_init_ring(struct net_device *dev);
61357325
SH		 301static netdev_tx_t epic_start_xmit(struct sk_buff *skb,
302 struct net_device *dev);
1da177e4 303static int epic_rx(struct net_device *dev, int budget);
bea3348e 304static int epic_poll(struct napi_struct *napi, int budget);
7d12e780 305static irqreturn_t epic_interrupt(int irq, void *dev_instance);
1da177e4 306static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
7282d491 307static const struct ethtool_ops netdev_ethtool_ops;
1da177e4
LT		 308static int epic_close(struct net_device *dev);
309static struct net_device_stats *epic_get_stats(struct net_device *dev);
310static void set_rx_mode(struct net_device *dev);
311
805524cb
SH		 312static const struct net_device_ops epic_netdev_ops = {
313 .ndo_open = epic_open,
314 .ndo_stop = epic_close,
315 .ndo_start_xmit = epic_start_xmit,
316 .ndo_tx_timeout = epic_tx_timeout,
317 .ndo_get_stats = epic_get_stats,
318 .ndo_set_multicast_list = set_rx_mode,
319 .ndo_do_ioctl = netdev_ioctl,
320 .ndo_change_mtu = eth_change_mtu,
321 .ndo_set_mac_address = eth_mac_addr,
322 .ndo_validate_addr = eth_validate_addr,
323};
1da177e4
LT		 324
325static int __devinit epic_init_one (struct pci_dev *pdev,
326 const struct pci_device_id *ent)
327{
328 static int card_idx = -1;
329 long ioaddr;
330 int chip_idx = (int) ent->driver_data;
331 int irq;
332 struct net_device *dev;
333 struct epic_private *ep;
334 int i, ret, option = 0, duplex = 0;
335 void *ring_space;
336 dma_addr_t ring_dma;
337
338/* when built into the kernel, we only print version if device is found */
339#ifndef MODULE
340 static int printed_version;
341 if (!printed_version++)
ad361c98 342 printk(KERN_INFO "%s%s", version, version2);
1da177e4 343#endif
f3b197ac 344
1da177e4 345 card_idx++;
f3b197ac 346
1da177e4
LT		 347 ret = pci_enable_device(pdev);
348 if (ret)
349 goto out;
350 irq = pdev->irq;
351
36e1e847 352 if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) {
9b91cf9d 353 dev_err(&pdev->dev, "no PCI region space\n");
1da177e4
LT		 354 ret = -ENODEV;
355 goto err_out_disable;
356 }
f3b197ac 357
1da177e4
LT		 358 pci_set_master(pdev);
359
360 ret = pci_request_regions(pdev, DRV_NAME);
361 if (ret < 0)
362 goto err_out_disable;
363
364 ret = -ENOMEM;
365
366 dev = alloc_etherdev(sizeof (*ep));
367 if (!dev) {
9b91cf9d 368 dev_err(&pdev->dev, "no memory for eth device\n");
1da177e4
LT		 369 goto err_out_free_res;
370 }
1da177e4
LT		 371 SET_NETDEV_DEV(dev, &pdev->dev);
372
373#ifdef USE_IO_OPS
374 ioaddr = pci_resource_start (pdev, 0);
375#else
376 ioaddr = pci_resource_start (pdev, 1);
275f165f 377 ioaddr = (long) pci_ioremap_bar(pdev, 1);
1da177e4 378 if (!ioaddr) {
9b91cf9d 379 dev_err(&pdev->dev, "ioremap failed\n");
1da177e4
LT		 380 goto err_out_free_netdev;
381 }
382#endif
383
384 pci_set_drvdata(pdev, dev);
4cf1653a 385 ep = netdev_priv(dev);
1da177e4
LT		 386 ep->mii.dev = dev;
387 ep->mii.mdio_read = mdio_read;
388 ep->mii.mdio_write = mdio_write;
389 ep->mii.phy_id_mask = 0x1f;
390 ep->mii.reg_num_mask = 0x1f;
391
392 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
393 if (!ring_space)
394 goto err_out_iounmap;
395 ep->tx_ring = (struct epic_tx_desc *)ring_space;
396 ep->tx_ring_dma = ring_dma;
397
398 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
399 if (!ring_space)
400 goto err_out_unmap_tx;
401 ep->rx_ring = (struct epic_rx_desc *)ring_space;
402 ep->rx_ring_dma = ring_dma;
403
404 if (dev->mem_start) {
405 option = dev->mem_start;
406 duplex = (dev->mem_start & 16) ? 1 : 0;
407 } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
408 if (options[card_idx] >= 0)
409 option = options[card_idx];
410 if (full_duplex[card_idx] >= 0)
411 duplex = full_duplex[card_idx];
412 }
413
414 dev->base_addr = ioaddr;
415 dev->irq = irq;
416
417 spin_lock_init(&ep->lock);
418 spin_lock_init(&ep->napi_lock);
419 ep->reschedule_in_poll = 0;
420
421 /* Bring the chip out of low-power mode. */
422 outl(0x4200, ioaddr + GENCTL);
423 /* Magic?! If we don't set this bit the MII interface won't work. */
424 /* This magic is documented in SMSC app note 7.15 */
425 for (i = 16; i > 0; i--)
426 outl(0x0008, ioaddr + TEST1);
427
428 /* Turn on the MII transceiver. */
429 outl(0x12, ioaddr + MIICfg);
430 if (chip_idx == 1)
431 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
432 outl(0x0200, ioaddr + GENCTL);
433
434 /* Note: the '175 does not have a serial EEPROM. */
435 for (i = 0; i < 3; i++)
9ebfd492 436 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(inw(ioaddr + LAN0 + i*4));
1da177e4
LT		 437
438 if (debug > 2) {
2e8a538d 439 dev_printk(KERN_DEBUG, &pdev->dev, "EEPROM contents:\n");
1da177e4
LT		 440 for (i = 0; i < 64; i++)
441 printk(" %4.4x%s", read_eeprom(ioaddr, i),
442 i % 16 == 15 ? "\n" : "");
443 }
444
445 ep->pci_dev = pdev;
446 ep->chip_id = chip_idx;
447 ep->chip_flags = pci_id_tbl[chip_idx].drv_flags;
f3b197ac 448 ep->irq_mask =
1da177e4
LT		 449 (ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
450 | CntFull | TxUnderrun | EpicNapiEvent;
451
452 /* Find the connected MII xcvrs.
453 Doing this in open() would allow detecting external xcvrs later, but
454 takes much time and no cards have external MII. */
455 {
456 int phy, phy_idx = 0;
457 for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) {
458 int mii_status = mdio_read(dev, phy, MII_BMSR);
459 if (mii_status != 0xffff && mii_status != 0x0000) {
460 ep->phys[phy_idx++] = phy;
9b91cf9d 461 dev_info(&pdev->dev,
2e8a538d
JG		 462 "MII transceiver #%d control "
463 "%4.4x status %4.4x.\n",
464 phy, mdio_read(dev, phy, 0), mii_status);
1da177e4
LT		 465 }
466 }
467 ep->mii_phy_cnt = phy_idx;
468 if (phy_idx != 0) {
469 phy = ep->phys[0];
470 ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE);
9b91cf9d 471 dev_info(&pdev->dev,
2e8a538d 472 "Autonegotiation advertising %4.4x link "
1da177e4 473 "partner %4.4x.\n",
2e8a538d 474 ep->mii.advertising, mdio_read(dev, phy, 5));
1da177e4 475 } else if ( ! (ep->chip_flags & NO_MII)) {
9b91cf9d 476 dev_warn(&pdev->dev,
2e8a538d 477 "***WARNING***: No MII transceiver found!\n");
1da177e4
LT		 478 /* Use the known PHY address of the EPII. */
479 ep->phys[0] = 3;
480 }
481 ep->mii.phy_id = ep->phys[0];
482 }
483
484 /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
485 if (ep->chip_flags & MII_PWRDWN)
486 outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
487 outl(0x0008, ioaddr + GENCTL);
488
489 /* The lower four bits are the media type. */
490 if (duplex) {
491 ep->mii.force_media = ep->mii.full_duplex = 1;
9b91cf9d 492 dev_info(&pdev->dev, "Forced full duplex requested.\n");
1da177e4
LT		 493 }
494 dev->if_port = ep->default_port = option;
495
496 /* The Epic-specific entries in the device structure. */
805524cb 497 dev->netdev_ops = &epic_netdev_ops;
1da177e4
LT		 498 dev->ethtool_ops = &netdev_ethtool_ops;
499 dev->watchdog_timeo = TX_TIMEOUT;
bea3348e 500 netif_napi_add(dev, &ep->napi, epic_poll, 64);
1da177e4
LT		 501
502 ret = register_netdev(dev);
503 if (ret < 0)
504 goto err_out_unmap_rx;
505
e174961c 506 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, %pM\n",
0795af57 507 dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq,
e174961c 508 dev->dev_addr);
1da177e4
LT		 509
510out:
511 return ret;
512
513err_out_unmap_rx:
514 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
515err_out_unmap_tx:
516 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
517err_out_iounmap:
518#ifndef USE_IO_OPS
519 iounmap(ioaddr);
520err_out_free_netdev:
521#endif
522 free_netdev(dev);
523err_out_free_res:
524 pci_release_regions(pdev);
525err_out_disable:
526 pci_disable_device(pdev);
527 goto out;
528}
f3b197ac 529
1da177e4
LT		 530/* Serial EEPROM section. */
531
532/* EEPROM_Ctrl bits. */
533#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
534#define EE_CS 0x02 /* EEPROM chip select. */
535#define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
536#define EE_WRITE_0 0x01
537#define EE_WRITE_1 0x09
538#define EE_DATA_READ 0x10 /* EEPROM chip data out. */
539#define EE_ENB (0x0001 | EE_CS)
540
541/* Delay between EEPROM clock transitions.
542 This serves to flush the operation to the PCI bus.
543 */
544
545#define eeprom_delay() inl(ee_addr)
546
547/* The EEPROM commands include the alway-set leading bit. */
548#define EE_WRITE_CMD (5 << 6)
549#define EE_READ64_CMD (6 << 6)
550#define EE_READ256_CMD (6 << 8)
551#define EE_ERASE_CMD (7 << 6)
552
553static void epic_disable_int(struct net_device *dev, struct epic_private *ep)
554{
555 long ioaddr = dev->base_addr;
556
557 outl(0x00000000, ioaddr + INTMASK);
558}
559
560static inline void __epic_pci_commit(long ioaddr)
561{
562#ifndef USE_IO_OPS
563 inl(ioaddr + INTMASK);
564#endif
565}
566
567static inline void epic_napi_irq_off(struct net_device *dev,
568 struct epic_private *ep)
569{
570 long ioaddr = dev->base_addr;
571
572 outl(ep->irq_mask & ~EpicNapiEvent, ioaddr + INTMASK);
573 __epic_pci_commit(ioaddr);
574}
575
576static inline void epic_napi_irq_on(struct net_device *dev,
577 struct epic_private *ep)
578{
579 long ioaddr = dev->base_addr;
580
581 /* No need to commit possible posted write */
582 outl(ep->irq_mask | EpicNapiEvent, ioaddr + INTMASK);
583}
584
585static int __devinit read_eeprom(long ioaddr, int location)
586{
587 int i;
588 int retval = 0;
589 long ee_addr = ioaddr + EECTL;
590 int read_cmd = location |
591 (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
592
593 outl(EE_ENB & ~EE_CS, ee_addr);
594 outl(EE_ENB, ee_addr);
595
596 /* Shift the read command bits out. */
597 for (i = 12; i >= 0; i--) {
598 short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
599 outl(EE_ENB | dataval, ee_addr);
600 eeprom_delay();
601 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
602 eeprom_delay();
603 }
604 outl(EE_ENB, ee_addr);
605
606 for (i = 16; i > 0; i--) {
607 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
608 eeprom_delay();
609 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
610 outl(EE_ENB, ee_addr);
611 eeprom_delay();
612 }
613
614 /* Terminate the EEPROM access. */
615 outl(EE_ENB & ~EE_CS, ee_addr);
616 return retval;
617}
618
619#define MII_READOP 1
620#define MII_WRITEOP 2
621static int mdio_read(struct net_device *dev, int phy_id, int location)
622{
623 long ioaddr = dev->base_addr;
624 int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP;
625 int i;
626
627 outl(read_cmd, ioaddr + MIICtrl);
628 /* Typical operation takes 25 loops. */
629 for (i = 400; i > 0; i--) {
630 barrier();
631 if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0) {
632 /* Work around read failure bug. */
8e95a202
JP		 633 if (phy_id == 1 && location < 6 &&
634 inw(ioaddr + MIIData) == 0xffff) {
1da177e4
LT		 635 outl(read_cmd, ioaddr + MIICtrl);
636 continue;
637 }
638 return inw(ioaddr + MIIData);
639 }
640 }
641 return 0xffff;
642}
643
644static void mdio_write(struct net_device *dev, int phy_id, int loc, int value)
645{
646 long ioaddr = dev->base_addr;
647 int i;
648
649 outw(value, ioaddr + MIIData);
650 outl((phy_id << 9) | (loc << 4) | MII_WRITEOP, ioaddr + MIICtrl);
f3b197ac 651 for (i = 10000; i > 0; i--) {
1da177e4
LT		 652 barrier();
653 if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
654 break;
655 }
656 return;
657}
658
f3b197ac 659
1da177e4
LT		 660static int epic_open(struct net_device *dev)
661{
4cf1653a 662 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 663 long ioaddr = dev->base_addr;
664 int i;
665 int retval;
666
667 /* Soft reset the chip. */
668 outl(0x4001, ioaddr + GENCTL);
669
bea3348e 670 napi_enable(&ep->napi);
a0607fd3 671 if ((retval = request_irq(dev->irq, epic_interrupt, IRQF_SHARED, dev->name, dev))) {
bea3348e 672 napi_disable(&ep->napi);
1da177e4 673 return retval;
bea3348e 674 }
1da177e4
LT		 675
676 epic_init_ring(dev);
677
678 outl(0x4000, ioaddr + GENCTL);
679 /* This magic is documented in SMSC app note 7.15 */
680 for (i = 16; i > 0; i--)
681 outl(0x0008, ioaddr + TEST1);
682
683 /* Pull the chip out of low-power mode, enable interrupts, and set for
684 PCI read multiple. The MIIcfg setting and strange write order are
685 required by the details of which bits are reset and the transceiver
686 wiring on the Ositech CardBus card.
687 */
688#if 0
689 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
690#endif
691 if (ep->chip_flags & MII_PWRDWN)
692 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
693
9ebfd492
AV		 694 /* Tell the chip to byteswap descriptors on big-endian hosts */
695#ifdef CONFIG_BIG_ENDIAN
1da177e4
LT		 696 outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
697 inl(ioaddr + GENCTL);
698 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
699#else
700 outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
701 inl(ioaddr + GENCTL);
702 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
703#endif
704
705 udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */
f3b197ac 706
1da177e4 707 for (i = 0; i < 3; i++)
9ebfd492 708 outl(le16_to_cpu(((__le16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
1da177e4
LT		 709
710 ep->tx_threshold = TX_FIFO_THRESH;
711 outl(ep->tx_threshold, ioaddr + TxThresh);
712
713 if (media2miictl[dev->if_port & 15]) {
714 if (ep->mii_phy_cnt)
715 mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]);
716 if (dev->if_port == 1) {
717 if (debug > 1)
718 printk(KERN_INFO "%s: Using the 10base2 transceiver, MII "
719 "status %4.4x.\n",
720 dev->name, mdio_read(dev, ep->phys[0], MII_BMSR));
721 }
722 } else {
723 int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA);
724 if (mii_lpa != 0xffff) {
725 if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL)
726 ep->mii.full_duplex = 1;
727 else if (! (mii_lpa & LPA_LPACK))
728 mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
729 if (debug > 1)
730 printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
731 " register read of %4.4x.\n", dev->name,
732 ep->mii.full_duplex ? "full" : "half",
733 ep->phys[0], mii_lpa);
734 }
735 }
736
737 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
738 outl(ep->rx_ring_dma, ioaddr + PRxCDAR);
739 outl(ep->tx_ring_dma, ioaddr + PTxCDAR);
740
741 /* Start the chip's Rx process. */
742 set_rx_mode(dev);
743 outl(StartRx | RxQueued, ioaddr + COMMAND);
744
745 netif_start_queue(dev);
746
747 /* Enable interrupts by setting the interrupt mask. */
748 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
f3b197ac 749 | CntFull | TxUnderrun
1da177e4
LT		 750 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
751
752 if (debug > 1)
753 printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
754 "%s-duplex.\n",
755 dev->name, ioaddr, dev->irq, (int)inl(ioaddr + GENCTL),
756 ep->mii.full_duplex ? "full" : "half");
757
758 /* Set the timer to switch to check for link beat and perhaps switch
759 to an alternate media type. */
760 init_timer(&ep->timer);
761 ep->timer.expires = jiffies + 3*HZ;
762 ep->timer.data = (unsigned long)dev;
763 ep->timer.function = &epic_timer; /* timer handler */
764 add_timer(&ep->timer);
765
766 return 0;
767}
768
769/* Reset the chip to recover from a PCI transaction error.
770 This may occur at interrupt time. */
771static void epic_pause(struct net_device *dev)
772{
773 long ioaddr = dev->base_addr;
4cf1653a 774 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 775
776 netif_stop_queue (dev);
f3b197ac 777
1da177e4
LT		 778 /* Disable interrupts by clearing the interrupt mask. */
779 outl(0x00000000, ioaddr + INTMASK);
780 /* Stop the chip's Tx and Rx DMA processes. */
781 outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND);
782
783 /* Update the error counts. */
784 if (inw(ioaddr + COMMAND) != 0xffff) {
785 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
786 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
787 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
788 }
789
790 /* Remove the packets on the Rx queue. */
791 epic_rx(dev, RX_RING_SIZE);
792}
793
794static void epic_restart(struct net_device *dev)
795{
796 long ioaddr = dev->base_addr;
4cf1653a 797 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 798 int i;
799
800 /* Soft reset the chip. */
801 outl(0x4001, ioaddr + GENCTL);
802
803 printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
804 dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
805 udelay(1);
806
807 /* This magic is documented in SMSC app note 7.15 */
808 for (i = 16; i > 0; i--)
809 outl(0x0008, ioaddr + TEST1);
810
9ebfd492 811#ifdef CONFIG_BIG_ENDIAN
1da177e4
LT		 812 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
813#else
814 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
815#endif
816 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
817 if (ep->chip_flags & MII_PWRDWN)
818 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
819
820 for (i = 0; i < 3; i++)
9ebfd492 821 outl(le16_to_cpu(((__le16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
1da177e4
LT		 822
823 ep->tx_threshold = TX_FIFO_THRESH;
824 outl(ep->tx_threshold, ioaddr + TxThresh);
825 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
826 outl(ep->rx_ring_dma + (ep->cur_rx%RX_RING_SIZE)*
827 sizeof(struct epic_rx_desc), ioaddr + PRxCDAR);
828 outl(ep->tx_ring_dma + (ep->dirty_tx%TX_RING_SIZE)*
829 sizeof(struct epic_tx_desc), ioaddr + PTxCDAR);
830
831 /* Start the chip's Rx process. */
832 set_rx_mode(dev);
833 outl(StartRx | RxQueued, ioaddr + COMMAND);
834
835 /* Enable interrupts by setting the interrupt mask. */
836 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
837 | CntFull | TxUnderrun
838 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
839
840 printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
841 " interrupt %4.4x.\n",
842 dev->name, (int)inl(ioaddr + COMMAND), (int)inl(ioaddr + GENCTL),
843 (int)inl(ioaddr + INTSTAT));
844 return;
845}
846
847static void check_media(struct net_device *dev)
848{
4cf1653a 849 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 850 long ioaddr = dev->base_addr;
851 int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0;
852 int negotiated = mii_lpa & ep->mii.advertising;
853 int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
854
855 if (ep->mii.force_media)
856 return;
857 if (mii_lpa == 0xffff) /* Bogus read */
858 return;
859 if (ep->mii.full_duplex != duplex) {
860 ep->mii.full_duplex = duplex;
861 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
862 " partner capability of %4.4x.\n", dev->name,
863 ep->mii.full_duplex ? "full" : "half", ep->phys[0], mii_lpa);
864 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
865 }
866}
867
868static void epic_timer(unsigned long data)
869{
870 struct net_device *dev = (struct net_device *)data;
4cf1653a 871 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 872 long ioaddr = dev->base_addr;
873 int next_tick = 5*HZ;
874
875 if (debug > 3) {
876 printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n",
877 dev->name, (int)inl(ioaddr + TxSTAT));
878 printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
879 "IntStatus %4.4x RxStatus %4.4x.\n",
880 dev->name, (int)inl(ioaddr + INTMASK),
881 (int)inl(ioaddr + INTSTAT), (int)inl(ioaddr + RxSTAT));
882 }
883
884 check_media(dev);
885
886 ep->timer.expires = jiffies + next_tick;
887 add_timer(&ep->timer);
888}
889
890static void epic_tx_timeout(struct net_device *dev)
891{
4cf1653a 892 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 893 long ioaddr = dev->base_addr;
894
895 if (debug > 0) {
896 printk(KERN_WARNING "%s: Transmit timeout using MII device, "
897 "Tx status %4.4x.\n",
898 dev->name, (int)inw(ioaddr + TxSTAT));
899 if (debug > 1) {
900 printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
901 dev->name, ep->dirty_tx, ep->cur_tx);
902 }
903 }
904 if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
905 ep->stats.tx_fifo_errors++;
906 outl(RestartTx, ioaddr + COMMAND);
907 } else {
908 epic_restart(dev);
909 outl(TxQueued, dev->base_addr + COMMAND);
910 }
911
912 dev->trans_start = jiffies;
913 ep->stats.tx_errors++;
914 if (!ep->tx_full)
915 netif_wake_queue(dev);
916}
917
918/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
919static void epic_init_ring(struct net_device *dev)
920{
4cf1653a 921 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 922 int i;
923
924 ep->tx_full = 0;
925 ep->dirty_tx = ep->cur_tx = 0;
926 ep->cur_rx = ep->dirty_rx = 0;
927 ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
928
929 /* Initialize all Rx descriptors. */
930 for (i = 0; i < RX_RING_SIZE; i++) {
931 ep->rx_ring[i].rxstatus = 0;
9ebfd492 932 ep->rx_ring[i].buflength = ep->rx_buf_sz;
f3b197ac 933 ep->rx_ring[i].next = ep->rx_ring_dma +
1da177e4
LT		 934 (i+1)*sizeof(struct epic_rx_desc);
935 ep->rx_skbuff[i] = NULL;
936 }
937 /* Mark the last entry as wrapping the ring. */
938 ep->rx_ring[i-1].next = ep->rx_ring_dma;
939
940 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
941 for (i = 0; i < RX_RING_SIZE; i++) {
942 struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz);
943 ep->rx_skbuff[i] = skb;
944 if (skb == NULL)
945 break;
1da177e4 946 skb_reserve(skb, 2); /* 16 byte align the IP header. */
f3b197ac 947 ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev,
689be439 948 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
9ebfd492 949 ep->rx_ring[i].rxstatus = DescOwn;
1da177e4
LT		 950 }
951 ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
952
953 /* The Tx buffer descriptor is filled in as needed, but we
954 do need to clear the ownership bit. */
955 for (i = 0; i < TX_RING_SIZE; i++) {
956 ep->tx_skbuff[i] = NULL;
957 ep->tx_ring[i].txstatus = 0x0000;
f3b197ac 958 ep->tx_ring[i].next = ep->tx_ring_dma +
1da177e4
LT		 959 (i+1)*sizeof(struct epic_tx_desc);
960 }
961 ep->tx_ring[i-1].next = ep->tx_ring_dma;
962 return;
963}
964
61357325 965static netdev_tx_t epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 966{
4cf1653a 967 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 968 int entry, free_count;
969 u32 ctrl_word;
970 unsigned long flags;
f3b197ac 971
5b057c6b 972 if (skb_padto(skb, ETH_ZLEN))
6ed10654 973 return NETDEV_TX_OK;
1da177e4
LT		 974
975 /* Caution: the write order is important here, set the field with the
976 "ownership" bit last. */
977
978 /* Calculate the next Tx descriptor entry. */
979 spin_lock_irqsave(&ep->lock, flags);
980 free_count = ep->cur_tx - ep->dirty_tx;
981 entry = ep->cur_tx % TX_RING_SIZE;
982
983 ep->tx_skbuff[entry] = skb;
f3b197ac 984 ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data,
1da177e4
LT		 985 skb->len, PCI_DMA_TODEVICE);
986 if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
9ebfd492 987 ctrl_word = 0x100000; /* No interrupt */
1da177e4 988 } else if (free_count == TX_QUEUE_LEN/2) {
9ebfd492 989 ctrl_word = 0x140000; /* Tx-done intr. */
1da177e4 990 } else if (free_count < TX_QUEUE_LEN - 1) {
9ebfd492 991 ctrl_word = 0x100000; /* No Tx-done intr. */
1da177e4
LT		 992 } else {
993 /* Leave room for an additional entry. */
9ebfd492 994 ctrl_word = 0x140000; /* Tx-done intr. */
1da177e4
LT		 995 ep->tx_full = 1;
996 }
9ebfd492 997 ep->tx_ring[entry].buflength = ctrl_word | skb->len;
1da177e4
LT		 998 ep->tx_ring[entry].txstatus =
999 ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
9ebfd492 1000 | DescOwn;
1da177e4
LT		 1001
1002 ep->cur_tx++;
1003 if (ep->tx_full)
1004 netif_stop_queue(dev);
1005
1006 spin_unlock_irqrestore(&ep->lock, flags);
1007 /* Trigger an immediate transmit demand. */
1008 outl(TxQueued, dev->base_addr + COMMAND);
1009
1010 dev->trans_start = jiffies;
1011 if (debug > 4)
1012 printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
1013 "flag %2.2x Tx status %8.8x.\n",
1014 dev->name, (int)skb->len, entry, ctrl_word,
1015 (int)inl(dev->base_addr + TxSTAT));
1016
6ed10654 1017 return NETDEV_TX_OK;
1da177e4
LT		 1018}
1019
1020static void epic_tx_error(struct net_device *dev, struct epic_private *ep,
1021 int status)
1022{
1023 struct net_device_stats *stats = &ep->stats;
1024
1025#ifndef final_version
1026 /* There was an major error, log it. */
1027 if (debug > 1)
1028 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1029 dev->name, status);
1030#endif
1031 stats->tx_errors++;
1032 if (status & 0x1050)
1033 stats->tx_aborted_errors++;
1034 if (status & 0x0008)
1035 stats->tx_carrier_errors++;
1036 if (status & 0x0040)
1037 stats->tx_window_errors++;
1038 if (status & 0x0010)
1039 stats->tx_fifo_errors++;
1040}
1041
1042static void epic_tx(struct net_device *dev, struct epic_private *ep)
1043{
1044 unsigned int dirty_tx, cur_tx;
1045
1046 /*
1047 * Note: if this lock becomes a problem we can narrow the locked
1048 * region at the cost of occasionally grabbing the lock more times.
1049 */
1050 cur_tx = ep->cur_tx;
1051 for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) {
1052 struct sk_buff *skb;
1053 int entry = dirty_tx % TX_RING_SIZE;
9ebfd492 1054 int txstatus = ep->tx_ring[entry].txstatus;
1da177e4
LT		 1055
1056 if (txstatus & DescOwn)
1057 break; /* It still hasn't been Txed */
1058
1059 if (likely(txstatus & 0x0001)) {
1060 ep->stats.collisions += (txstatus >> 8) & 15;
1061 ep->stats.tx_packets++;
1062 ep->stats.tx_bytes += ep->tx_skbuff[entry]->len;
1063 } else
1064 epic_tx_error(dev, ep, txstatus);
1065
1066 /* Free the original skb. */
1067 skb = ep->tx_skbuff[entry];
f3b197ac 1068 pci_unmap_single(ep->pci_dev, ep->tx_ring[entry].bufaddr,
1da177e4
LT		 1069 skb->len, PCI_DMA_TODEVICE);
1070 dev_kfree_skb_irq(skb);
1071 ep->tx_skbuff[entry] = NULL;
1072 }
1073
1074#ifndef final_version
1075 if (cur_tx - dirty_tx > TX_RING_SIZE) {
1076 printk(KERN_WARNING
1077 "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1078 dev->name, dirty_tx, cur_tx, ep->tx_full);
1079 dirty_tx += TX_RING_SIZE;
1080 }
1081#endif
1082 ep->dirty_tx = dirty_tx;
1083 if (ep->tx_full && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) {
1084 /* The ring is no longer full, allow new TX entries. */
1085 ep->tx_full = 0;
1086 netif_wake_queue(dev);
1087 }
1088}
1089
1090/* The interrupt handler does all of the Rx thread work and cleans up
1091 after the Tx thread. */
7d12e780 1092static irqreturn_t epic_interrupt(int irq, void *dev_instance)
1da177e4
LT		 1093{
1094 struct net_device *dev = dev_instance;
4cf1653a 1095 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 1096 long ioaddr = dev->base_addr;
1097 unsigned int handled = 0;
1098 int status;
1099
1100 status = inl(ioaddr + INTSTAT);
1101 /* Acknowledge all of the current interrupt sources ASAP. */
1102 outl(status & EpicNormalEvent, ioaddr + INTSTAT);
1103
1104 if (debug > 4) {
1105 printk(KERN_DEBUG "%s: Interrupt, status=%#8.8x new "
1106 "intstat=%#8.8x.\n", dev->name, status,
1107 (int)inl(ioaddr + INTSTAT));
1108 }
1109
1110 if ((status & IntrSummary) == 0)
1111 goto out;
1112
1113 handled = 1;
1114
1115 if ((status & EpicNapiEvent) && !ep->reschedule_in_poll) {
1116 spin_lock(&ep->napi_lock);
288379f0 1117 if (napi_schedule_prep(&ep->napi)) {
1da177e4 1118 epic_napi_irq_off(dev, ep);
288379f0 1119 __napi_schedule(&ep->napi);
1da177e4
LT		 1120 } else
1121 ep->reschedule_in_poll++;
1122 spin_unlock(&ep->napi_lock);
1123 }
1124 status &= ~EpicNapiEvent;
1125
1126 /* Check uncommon events all at once. */
1127 if (status & (CntFull | TxUnderrun | PCIBusErr170 | PCIBusErr175)) {
1128 if (status == EpicRemoved)
1129 goto out;
1130
1131 /* Always update the error counts to avoid overhead later. */
1132 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1133 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1134 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1135
1136 if (status & TxUnderrun) { /* Tx FIFO underflow. */
1137 ep->stats.tx_fifo_errors++;
1138 outl(ep->tx_threshold += 128, ioaddr + TxThresh);
1139 /* Restart the transmit process. */
1140 outl(RestartTx, ioaddr + COMMAND);
1141 }
1142 if (status & PCIBusErr170) {
1143 printk(KERN_ERR "%s: PCI Bus Error! status %4.4x.\n",
1144 dev->name, status);
1145 epic_pause(dev);
1146 epic_restart(dev);
1147 }
1148 /* Clear all error sources. */
1149 outl(status & 0x7f18, ioaddr + INTSTAT);
1150 }
1151
1152out:
1153 if (debug > 3) {
1154 printk(KERN_DEBUG "%s: exit interrupt, intr_status=%#4.4x.\n",
1155 dev->name, status);
1156 }
1157
1158 return IRQ_RETVAL(handled);
1159}
1160
1161static int epic_rx(struct net_device *dev, int budget)
1162{
4cf1653a 1163 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 1164 int entry = ep->cur_rx % RX_RING_SIZE;
1165 int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx;
1166 int work_done = 0;
1167
1168 if (debug > 4)
1169 printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1170 ep->rx_ring[entry].rxstatus);
1171
1172 if (rx_work_limit > budget)
1173 rx_work_limit = budget;
1174
1175 /* If we own the next entry, it's a new packet. Send it up. */
9ebfd492
AV		 1176 while ((ep->rx_ring[entry].rxstatus & DescOwn) == 0) {
1177 int status = ep->rx_ring[entry].rxstatus;
1da177e4
LT		 1178
1179 if (debug > 4)
1180 printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1181 if (--rx_work_limit < 0)
1182 break;
1183 if (status & 0x2006) {
1184 if (debug > 2)
1185 printk(KERN_DEBUG "%s: epic_rx() error status was %8.8x.\n",
1186 dev->name, status);
1187 if (status & 0x2000) {
1188 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1189 "multiple buffers, status %4.4x!\n", dev->name, status);
1190 ep->stats.rx_length_errors++;
1191 } else if (status & 0x0006)
1192 /* Rx Frame errors are counted in hardware. */
1193 ep->stats.rx_errors++;
1194 } else {
1195 /* Malloc up new buffer, compatible with net-2e. */
1196 /* Omit the four octet CRC from the length. */
1197 short pkt_len = (status >> 16) - 4;
1198 struct sk_buff *skb;
1199
1200 if (pkt_len > PKT_BUF_SZ - 4) {
1201 printk(KERN_ERR "%s: Oversized Ethernet frame, status %x "
1202 "%d bytes.\n",
1203 dev->name, status, pkt_len);
1204 pkt_len = 1514;
1205 }
1206 /* Check if the packet is long enough to accept without copying
1207 to a minimally-sized skbuff. */
8e95a202
JP		 1208 if (pkt_len < rx_copybreak &&
1209 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 1210 skb_reserve(skb, 2); /* 16 byte align the IP header */
1211 pci_dma_sync_single_for_cpu(ep->pci_dev,
1212 ep->rx_ring[entry].bufaddr,
1213 ep->rx_buf_sz,
1214 PCI_DMA_FROMDEVICE);
8c7b7faa 1215 skb_copy_to_linear_data(skb, ep->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT		 1216 skb_put(skb, pkt_len);
1217 pci_dma_sync_single_for_device(ep->pci_dev,
1218 ep->rx_ring[entry].bufaddr,
1219 ep->rx_buf_sz,
1220 PCI_DMA_FROMDEVICE);
1221 } else {
f3b197ac
JG		 1222 pci_unmap_single(ep->pci_dev,
1223 ep->rx_ring[entry].bufaddr,
1da177e4
LT		 1224 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1225 skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1226 ep->rx_skbuff[entry] = NULL;
1227 }
1228 skb->protocol = eth_type_trans(skb, dev);
1229 netif_receive_skb(skb);
1da177e4
LT		 1230 ep->stats.rx_packets++;
1231 ep->stats.rx_bytes += pkt_len;
1232 }
1233 work_done++;
1234 entry = (++ep->cur_rx) % RX_RING_SIZE;
1235 }
1236
1237 /* Refill the Rx ring buffers. */
1238 for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1239 entry = ep->dirty_rx % RX_RING_SIZE;
1240 if (ep->rx_skbuff[entry] == NULL) {
1241 struct sk_buff *skb;
1242 skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz);
1243 if (skb == NULL)
1244 break;
1da177e4 1245 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
f3b197ac 1246 ep->rx_ring[entry].bufaddr = pci_map_single(ep->pci_dev,
689be439 1247 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1248 work_done++;
1249 }
9ebfd492
AV		 1250 /* AV: shouldn't we add a barrier here? */
1251 ep->rx_ring[entry].rxstatus = DescOwn;
1da177e4
LT		 1252 }
1253 return work_done;
1254}
1255
1256static void epic_rx_err(struct net_device *dev, struct epic_private *ep)
1257{
1258 long ioaddr = dev->base_addr;
1259 int status;
1260
1261 status = inl(ioaddr + INTSTAT);
1262
1263 if (status == EpicRemoved)
1264 return;
1265 if (status & RxOverflow) /* Missed a Rx frame. */
1266 ep->stats.rx_errors++;
1267 if (status & (RxOverflow | RxFull))
1268 outw(RxQueued, ioaddr + COMMAND);
1269}
1270
bea3348e 1271static int epic_poll(struct napi_struct *napi, int budget)
1da177e4 1272{
bea3348e
SH		 1273 struct epic_private *ep = container_of(napi, struct epic_private, napi);
1274 struct net_device *dev = ep->mii.dev;
1275 int work_done = 0;
1da177e4
LT		 1276 long ioaddr = dev->base_addr;
1277
1da177e4
LT		 1278rx_action:
1279
1280 epic_tx(dev, ep);
1281
bea3348e 1282 work_done += epic_rx(dev, budget);
1da177e4
LT		 1283
1284 epic_rx_err(dev, ep);
1285
4ec24119 1286 if (work_done < budget) {
1da177e4
LT		 1287 unsigned long flags;
1288 int more;
1289
1290 /* A bit baroque but it avoids a (space hungry) spin_unlock */
1291
1292 spin_lock_irqsave(&ep->napi_lock, flags);
1293
1294 more = ep->reschedule_in_poll;
1295 if (!more) {
288379f0 1296 __napi_complete(napi);
1da177e4
LT		 1297 outl(EpicNapiEvent, ioaddr + INTSTAT);
1298 epic_napi_irq_on(dev, ep);
1299 } else
1300 ep->reschedule_in_poll--;
1301
1302 spin_unlock_irqrestore(&ep->napi_lock, flags);
1303
1304 if (more)
1305 goto rx_action;
1306 }
1307
bea3348e 1308 return work_done;
1da177e4
LT		 1309}
1310
1311static int epic_close(struct net_device *dev)
1312{
1313 long ioaddr = dev->base_addr;
4cf1653a 1314 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 1315 struct sk_buff *skb;
1316 int i;
1317
1318 netif_stop_queue(dev);
bea3348e 1319 napi_disable(&ep->napi);
1da177e4
LT		 1320
1321 if (debug > 1)
1322 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1323 dev->name, (int)inl(ioaddr + INTSTAT));
1324
1325 del_timer_sync(&ep->timer);
1326
1327 epic_disable_int(dev, ep);
1328
1329 free_irq(dev->irq, dev);
1330
1331 epic_pause(dev);
1332
1333 /* Free all the skbuffs in the Rx queue. */
1334 for (i = 0; i < RX_RING_SIZE; i++) {
1335 skb = ep->rx_skbuff[i];
1336 ep->rx_skbuff[i] = NULL;
1337 ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */
1338 ep->rx_ring[i].buflength = 0;
1339 if (skb) {
f3b197ac 1340 pci_unmap_single(ep->pci_dev, ep->rx_ring[i].bufaddr,
1da177e4
LT		 1341 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1342 dev_kfree_skb(skb);
1343 }
1344 ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1345 }
1346 for (i = 0; i < TX_RING_SIZE; i++) {
1347 skb = ep->tx_skbuff[i];
1348 ep->tx_skbuff[i] = NULL;
1349 if (!skb)
1350 continue;
f3b197ac 1351 pci_unmap_single(ep->pci_dev, ep->tx_ring[i].bufaddr,
1da177e4
LT		 1352 skb->len, PCI_DMA_TODEVICE);
1353 dev_kfree_skb(skb);
1354 }
1355
1356 /* Green! Leave the chip in low-power mode. */
1357 outl(0x0008, ioaddr + GENCTL);
1358
1359 return 0;
1360}
1361
1362static struct net_device_stats *epic_get_stats(struct net_device *dev)
1363{
4cf1653a 1364 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 1365 long ioaddr = dev->base_addr;
1366
1367 if (netif_running(dev)) {
1368 /* Update the error counts. */
1369 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1370 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1371 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1372 }
1373
1374 return &ep->stats;
1375}
1376
1377/* Set or clear the multicast filter for this adaptor.
1378 Note that we only use exclusion around actually queueing the
1379 new frame, not around filling ep->setup_frame. This is non-deterministic
1380 when re-entered but still correct. */
1381
1382static void set_rx_mode(struct net_device *dev)
1383{
1384 long ioaddr = dev->base_addr;
4cf1653a 1385 struct epic_private *ep = netdev_priv(dev);
1da177e4
LT		 1386 unsigned char mc_filter[8]; /* Multicast hash filter */
1387 int i;
1388
1389 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1390 outl(0x002C, ioaddr + RxCtrl);
1391 /* Unconditionally log net taps. */
1da177e4 1392 memset(mc_filter, 0xff, sizeof(mc_filter));
4cd24eaf 1393 } else if ((!netdev_mc_empty(dev)) || (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 1394 /* There is apparently a chip bug, so the multicast filter
1395 is never enabled. */
1396 /* Too many to filter perfectly -- accept all multicasts. */
1397 memset(mc_filter, 0xff, sizeof(mc_filter));
1398 outl(0x000C, ioaddr + RxCtrl);
4cd24eaf 1399 } else if (netdev_mc_empty(dev)) {
1da177e4
LT		 1400 outl(0x0004, ioaddr + RxCtrl);
1401 return;
1402 } else { /* Never executed, for now. */
22bedad3 1403 struct netdev_hw_addr *ha;
1da177e4
LT		 1404
1405 memset(mc_filter, 0, sizeof(mc_filter));
22bedad3 1406 netdev_for_each_mc_addr(ha, dev) {
1da177e4 1407 unsigned int bit_nr =
22bedad3 1408 ether_crc_le(ETH_ALEN, ha->addr) & 0x3f;
1da177e4
LT		 1409 mc_filter[bit_nr >> 3] |= (1 << bit_nr);
1410 }
1411 }
1412 /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1413 if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1414 for (i = 0; i < 4; i++)
1415 outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1416 memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1417 }
1418 return;
1419}
1420
1421static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1422{
4cf1653a 1423 struct epic_private *np = netdev_priv(dev);
1da177e4
LT		 1424
1425 strcpy (info->driver, DRV_NAME);
1426 strcpy (info->version, DRV_VERSION);
1427 strcpy (info->bus_info, pci_name(np->pci_dev));
1428}
1429
1430static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1431{
4cf1653a 1432 struct epic_private *np = netdev_priv(dev);
1da177e4
LT		 1433 int rc;
1434
1435 spin_lock_irq(&np->lock);
1436 rc = mii_ethtool_gset(&np->mii, cmd);
1437 spin_unlock_irq(&np->lock);
1438
1439 return rc;
1440}
1441
1442static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1443{
4cf1653a 1444 struct epic_private *np = netdev_priv(dev);
1da177e4
LT		 1445 int rc;
1446
1447 spin_lock_irq(&np->lock);
1448 rc = mii_ethtool_sset(&np->mii, cmd);
1449 spin_unlock_irq(&np->lock);
1450
1451 return rc;
1452}
1453
1454static int netdev_nway_reset(struct net_device *dev)
1455{
4cf1653a 1456 struct epic_private *np = netdev_priv(dev);
1da177e4
LT		 1457 return mii_nway_restart(&np->mii);
1458}
1459
1460static u32 netdev_get_link(struct net_device *dev)
1461{
4cf1653a 1462 struct epic_private *np = netdev_priv(dev);
1da177e4
LT		 1463 return mii_link_ok(&np->mii);
1464}
1465
1466static u32 netdev_get_msglevel(struct net_device *dev)
1467{
1468 return debug;
1469}
1470
1471static void netdev_set_msglevel(struct net_device *dev, u32 value)
1472{
1473 debug = value;
1474}
1475
1476static int ethtool_begin(struct net_device *dev)
1477{
1478 unsigned long ioaddr = dev->base_addr;
1479 /* power-up, if interface is down */
1480 if (! netif_running(dev)) {
1481 outl(0x0200, ioaddr + GENCTL);
1482 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1483 }
1484 return 0;
1485}
1486
1487static void ethtool_complete(struct net_device *dev)
1488{
1489 unsigned long ioaddr = dev->base_addr;
1490 /* power-down, if interface is down */
1491 if (! netif_running(dev)) {
1492 outl(0x0008, ioaddr + GENCTL);
1493 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1494 }
1495}
1496
7282d491 1497static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 1498 .get_drvinfo = netdev_get_drvinfo,
1499 .get_settings = netdev_get_settings,
1500 .set_settings = netdev_set_settings,
1501 .nway_reset = netdev_nway_reset,
1502 .get_link = netdev_get_link,
1503 .get_msglevel = netdev_get_msglevel,
1504 .set_msglevel = netdev_set_msglevel,
1da177e4
LT		 1505 .begin = ethtool_begin,
1506 .complete = ethtool_complete
1507};
1508
1509static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1510{
4cf1653a 1511 struct epic_private *np = netdev_priv(dev);
1da177e4
LT		 1512 long ioaddr = dev->base_addr;
1513 struct mii_ioctl_data *data = if_mii(rq);
1514 int rc;
1515
1516 /* power-up, if interface is down */
1517 if (! netif_running(dev)) {
1518 outl(0x0200, ioaddr + GENCTL);
1519 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1520 }
1521
1522 /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */
1523 spin_lock_irq(&np->lock);
1524 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
1525 spin_unlock_irq(&np->lock);
1526
1527 /* power-down, if interface is down */
1528 if (! netif_running(dev)) {
1529 outl(0x0008, ioaddr + GENCTL);
1530 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1531 }
1532 return rc;
1533}
1534
1535
1536static void __devexit epic_remove_one (struct pci_dev *pdev)
1537{
1538 struct net_device *dev = pci_get_drvdata(pdev);
4cf1653a 1539 struct epic_private *ep = netdev_priv(dev);
f3b197ac 1540
1da177e4
LT		 1541 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
1542 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
1543 unregister_netdev(dev);
1544#ifndef USE_IO_OPS
1545 iounmap((void*) dev->base_addr);
1546#endif
1547 pci_release_regions(pdev);
1548 free_netdev(dev);
1549 pci_disable_device(pdev);
1550 pci_set_drvdata(pdev, NULL);
1551 /* pci_power_off(pdev, -1); */
1552}
1553
1554
1555#ifdef CONFIG_PM
1556
1557static int epic_suspend (struct pci_dev *pdev, pm_message_t state)
1558{
1559 struct net_device *dev = pci_get_drvdata(pdev);
1560 long ioaddr = dev->base_addr;
1561
1562 if (!netif_running(dev))
1563 return 0;
1564 epic_pause(dev);
1565 /* Put the chip into low-power mode. */
1566 outl(0x0008, ioaddr + GENCTL);
1567 /* pci_power_off(pdev, -1); */
1568 return 0;
1569}
1570
1571
1572static int epic_resume (struct pci_dev *pdev)
1573{
1574 struct net_device *dev = pci_get_drvdata(pdev);
1575
1576 if (!netif_running(dev))
1577 return 0;
1578 epic_restart(dev);
1579 /* pci_power_on(pdev); */
1580 return 0;
1581}
1582
1583#endif /* CONFIG_PM */
1584
1585
1586static struct pci_driver epic_driver = {
1587 .name = DRV_NAME,
1588 .id_table = epic_pci_tbl,
1589 .probe = epic_init_one,
1590 .remove = __devexit_p(epic_remove_one),
1591#ifdef CONFIG_PM
1592 .suspend = epic_suspend,
1593 .resume = epic_resume,
1594#endif /* CONFIG_PM */
1595};
1596
1597
1598static int __init epic_init (void)
1599{
1600/* when a module, this is printed whether or not devices are found in probe */
1601#ifdef MODULE
ad361c98 1602 printk (KERN_INFO "%s%s",
2c2a8c53 1603 version, version2);
1da177e4
LT		 1604#endif
1605
29917620 1606 return pci_register_driver(&epic_driver);
1da177e4
LT		 1607}
1608
1609
1610static void __exit epic_cleanup (void)
1611{
1612 pci_unregister_driver (&epic_driver);
1613}
1614
1615
1616module_init(epic_init);
1617module_exit(epic_cleanup);
kernel source for telekom puls (alcatel/mediatek)