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3758bf25 AG |
1 | /* |
2 | * TI HECC (CAN) device driver | |
3 | * | |
4 | * This driver supports TI's HECC (High End CAN Controller module) and the | |
5 | * specs for the same is available at <http://www.ti.com> | |
6 | * | |
7 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation version 2. | |
12 | * | |
13 | * This program is distributed as is WITHOUT ANY WARRANTY of any | |
14 | * kind, whether express or implied; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * Your platform definitions should specify module ram offsets and interrupt | |
22 | * number to use as follows: | |
23 | * | |
24 | * static struct ti_hecc_platform_data am3517_evm_hecc_pdata = { | |
25 | * .scc_hecc_offset = 0, | |
26 | * .scc_ram_offset = 0x3000, | |
27 | * .hecc_ram_offset = 0x3000, | |
28 | * .mbx_offset = 0x2000, | |
29 | * .int_line = 0, | |
30 | * .revision = 1, | |
773c3e75 | 31 | * .transceiver_switch = hecc_phy_control, |
3758bf25 AG |
32 | * }; |
33 | * | |
773c3e75 S |
34 | * Please see include/linux/can/platform/ti_hecc.h for description of |
35 | * above fields. | |
3758bf25 AG |
36 | * |
37 | */ | |
38 | ||
39 | #include <linux/module.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/kernel.h> | |
42 | #include <linux/types.h> | |
43 | #include <linux/interrupt.h> | |
44 | #include <linux/errno.h> | |
45 | #include <linux/netdevice.h> | |
46 | #include <linux/skbuff.h> | |
47 | #include <linux/platform_device.h> | |
48 | #include <linux/clk.h> | |
34b8686d | 49 | #include <linux/io.h> |
3758bf25 | 50 | |
3758bf25 AG |
51 | #include <linux/can/dev.h> |
52 | #include <linux/can/error.h> | |
53 | #include <linux/can/platform/ti_hecc.h> | |
54 | ||
55 | #define DRV_NAME "ti_hecc" | |
56 | #define HECC_MODULE_VERSION "0.7" | |
57 | MODULE_VERSION(HECC_MODULE_VERSION); | |
58 | #define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION | |
59 | ||
60 | /* TX / RX Mailbox Configuration */ | |
61 | #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */ | |
62 | #define MAX_TX_PRIO 0x3F /* hardware value - do not change */ | |
63 | ||
64 | /* | |
65 | * Important Note: TX mailbox configuration | |
66 | * TX mailboxes should be restricted to the number of SKB buffers to avoid | |
67 | * maintaining SKB buffers separately. TX mailboxes should be a power of 2 | |
68 | * for the mailbox logic to work. Top mailbox numbers are reserved for RX | |
69 | * and lower mailboxes for TX. | |
70 | * | |
71 | * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT | |
72 | * 4 (default) 2 | |
73 | * 8 3 | |
74 | * 16 4 | |
75 | */ | |
76 | #define HECC_MB_TX_SHIFT 2 /* as per table above */ | |
77 | #define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT) | |
78 | ||
3758bf25 AG |
79 | #define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT) |
80 | #define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT) | |
81 | #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1) | |
82 | #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK) | |
83 | #define HECC_TX_MBOX_MASK (~(BIT(HECC_MAX_TX_MBOX) - 1)) | |
84 | #define HECC_DEF_NAPI_WEIGHT HECC_MAX_RX_MBOX | |
85 | ||
86 | /* | |
87 | * Important Note: RX mailbox configuration | |
88 | * RX mailboxes are further logically split into two - main and buffer | |
89 | * mailboxes. The goal is to get all packets into main mailboxes as | |
90 | * driven by mailbox number and receive priority (higher to lower) and | |
91 | * buffer mailboxes are used to receive pkts while main mailboxes are being | |
92 | * processed. This ensures in-order packet reception. | |
93 | * | |
94 | * Here are the recommended values for buffer mailbox. Note that RX mailboxes | |
95 | * start after TX mailboxes: | |
96 | * | |
97 | * HECC_MAX_RX_MBOX HECC_RX_BUFFER_MBOX No of buffer mailboxes | |
98 | * 28 12 8 | |
99 | * 16 20 4 | |
100 | */ | |
101 | ||
102 | #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX) | |
103 | #define HECC_RX_BUFFER_MBOX 12 /* as per table above */ | |
104 | #define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1) | |
105 | #define HECC_RX_HIGH_MBOX_MASK (~(BIT(HECC_RX_BUFFER_MBOX) - 1)) | |
106 | ||
107 | /* TI HECC module registers */ | |
108 | #define HECC_CANME 0x0 /* Mailbox enable */ | |
109 | #define HECC_CANMD 0x4 /* Mailbox direction */ | |
110 | #define HECC_CANTRS 0x8 /* Transmit request set */ | |
111 | #define HECC_CANTRR 0xC /* Transmit request */ | |
112 | #define HECC_CANTA 0x10 /* Transmission acknowledge */ | |
113 | #define HECC_CANAA 0x14 /* Abort acknowledge */ | |
114 | #define HECC_CANRMP 0x18 /* Receive message pending */ | |
115 | #define HECC_CANRML 0x1C /* Remote message lost */ | |
116 | #define HECC_CANRFP 0x20 /* Remote frame pending */ | |
117 | #define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */ | |
118 | #define HECC_CANMC 0x28 /* Master control */ | |
119 | #define HECC_CANBTC 0x2C /* Bit timing configuration */ | |
120 | #define HECC_CANES 0x30 /* Error and status */ | |
121 | #define HECC_CANTEC 0x34 /* Transmit error counter */ | |
122 | #define HECC_CANREC 0x38 /* Receive error counter */ | |
123 | #define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */ | |
124 | #define HECC_CANGIM 0x40 /* Global interrupt mask */ | |
125 | #define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */ | |
126 | #define HECC_CANMIM 0x48 /* Mailbox interrupt mask */ | |
127 | #define HECC_CANMIL 0x4C /* Mailbox interrupt level */ | |
128 | #define HECC_CANOPC 0x50 /* Overwrite protection control */ | |
129 | #define HECC_CANTIOC 0x54 /* Transmit I/O control */ | |
130 | #define HECC_CANRIOC 0x58 /* Receive I/O control */ | |
131 | #define HECC_CANLNT 0x5C /* HECC only: Local network time */ | |
132 | #define HECC_CANTOC 0x60 /* HECC only: Time-out control */ | |
133 | #define HECC_CANTOS 0x64 /* HECC only: Time-out status */ | |
134 | #define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */ | |
135 | #define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */ | |
136 | ||
137 | /* Mailbox registers */ | |
138 | #define HECC_CANMID 0x0 | |
139 | #define HECC_CANMCF 0x4 | |
140 | #define HECC_CANMDL 0x8 | |
141 | #define HECC_CANMDH 0xC | |
142 | ||
143 | #define HECC_SET_REG 0xFFFFFFFF | |
144 | #define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */ | |
145 | #define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */ | |
146 | ||
147 | #define HECC_CANMC_SCM BIT(13) /* SCC compat mode */ | |
148 | #define HECC_CANMC_CCR BIT(12) /* Change config request */ | |
149 | #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */ | |
150 | #define HECC_CANMC_ABO BIT(7) /* Auto Bus On */ | |
151 | #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */ | |
152 | #define HECC_CANMC_SRES BIT(5) /* Software reset */ | |
153 | ||
154 | #define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */ | |
155 | #define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */ | |
156 | ||
157 | #define HECC_CANMID_IDE BIT(31) /* Extended frame format */ | |
158 | #define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */ | |
159 | #define HECC_CANMID_AAM BIT(29) /* Auto answer mode */ | |
160 | ||
161 | #define HECC_CANES_FE BIT(24) /* form error */ | |
162 | #define HECC_CANES_BE BIT(23) /* bit error */ | |
163 | #define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */ | |
164 | #define HECC_CANES_CRCE BIT(21) /* CRC error */ | |
165 | #define HECC_CANES_SE BIT(20) /* stuff bit error */ | |
166 | #define HECC_CANES_ACKE BIT(19) /* ack error */ | |
167 | #define HECC_CANES_BO BIT(18) /* Bus off status */ | |
168 | #define HECC_CANES_EP BIT(17) /* Error passive status */ | |
169 | #define HECC_CANES_EW BIT(16) /* Error warning status */ | |
170 | #define HECC_CANES_SMA BIT(5) /* suspend mode ack */ | |
171 | #define HECC_CANES_CCE BIT(4) /* Change config enabled */ | |
172 | #define HECC_CANES_PDA BIT(3) /* Power down mode ack */ | |
173 | ||
174 | #define HECC_CANBTC_SAM BIT(7) /* sample points */ | |
175 | ||
176 | #define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\ | |
177 | HECC_CANES_CRCE | HECC_CANES_SE |\ | |
178 | HECC_CANES_ACKE) | |
179 | ||
180 | #define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */ | |
181 | ||
182 | #define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */ | |
183 | #define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */ | |
184 | #define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */ | |
185 | #define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */ | |
186 | #define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */ | |
187 | #define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */ | |
188 | #define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */ | |
189 | #define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */ | |
190 | #define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */ | |
191 | #define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */ | |
192 | #define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */ | |
193 | #define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */ | |
194 | #define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */ | |
195 | #define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */ | |
196 | #define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */ | |
197 | ||
198 | /* CAN Bittiming constants as per HECC specs */ | |
194b9a4c | 199 | static const struct can_bittiming_const ti_hecc_bittiming_const = { |
3758bf25 AG |
200 | .name = DRV_NAME, |
201 | .tseg1_min = 1, | |
202 | .tseg1_max = 16, | |
203 | .tseg2_min = 1, | |
204 | .tseg2_max = 8, | |
205 | .sjw_max = 4, | |
206 | .brp_min = 1, | |
207 | .brp_max = 256, | |
208 | .brp_inc = 1, | |
209 | }; | |
210 | ||
211 | struct ti_hecc_priv { | |
212 | struct can_priv can; /* MUST be first member/field */ | |
213 | struct napi_struct napi; | |
214 | struct net_device *ndev; | |
215 | struct clk *clk; | |
216 | void __iomem *base; | |
217 | u32 scc_ram_offset; | |
218 | u32 hecc_ram_offset; | |
219 | u32 mbx_offset; | |
220 | u32 int_line; | |
221 | spinlock_t mbx_lock; /* CANME register needs protection */ | |
222 | u32 tx_head; | |
223 | u32 tx_tail; | |
224 | u32 rx_next; | |
773c3e75 | 225 | void (*transceiver_switch)(int); |
3758bf25 AG |
226 | }; |
227 | ||
228 | static inline int get_tx_head_mb(struct ti_hecc_priv *priv) | |
229 | { | |
230 | return priv->tx_head & HECC_TX_MB_MASK; | |
231 | } | |
232 | ||
233 | static inline int get_tx_tail_mb(struct ti_hecc_priv *priv) | |
234 | { | |
235 | return priv->tx_tail & HECC_TX_MB_MASK; | |
236 | } | |
237 | ||
238 | static inline int get_tx_head_prio(struct ti_hecc_priv *priv) | |
239 | { | |
240 | return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO; | |
241 | } | |
242 | ||
243 | static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val) | |
244 | { | |
245 | __raw_writel(val, priv->base + priv->hecc_ram_offset + mbxno * 4); | |
246 | } | |
247 | ||
248 | static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno, | |
249 | u32 reg, u32 val) | |
250 | { | |
251 | __raw_writel(val, priv->base + priv->mbx_offset + mbxno * 0x10 + | |
252 | reg); | |
253 | } | |
254 | ||
255 | static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg) | |
256 | { | |
257 | return __raw_readl(priv->base + priv->mbx_offset + mbxno * 0x10 + | |
258 | reg); | |
259 | } | |
260 | ||
261 | static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val) | |
262 | { | |
263 | __raw_writel(val, priv->base + reg); | |
264 | } | |
265 | ||
266 | static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg) | |
267 | { | |
268 | return __raw_readl(priv->base + reg); | |
269 | } | |
270 | ||
271 | static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg, | |
272 | u32 bit_mask) | |
273 | { | |
274 | hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask); | |
275 | } | |
276 | ||
277 | static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg, | |
278 | u32 bit_mask) | |
279 | { | |
280 | hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask); | |
281 | } | |
282 | ||
283 | static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask) | |
284 | { | |
285 | return (hecc_read(priv, reg) & bit_mask) ? 1 : 0; | |
286 | } | |
287 | ||
288 | static int ti_hecc_get_state(const struct net_device *ndev, | |
289 | enum can_state *state) | |
290 | { | |
291 | struct ti_hecc_priv *priv = netdev_priv(ndev); | |
292 | ||
293 | *state = priv->can.state; | |
294 | return 0; | |
295 | } | |
296 | ||
297 | static int ti_hecc_set_btc(struct ti_hecc_priv *priv) | |
298 | { | |
299 | struct can_bittiming *bit_timing = &priv->can.bittiming; | |
300 | u32 can_btc; | |
301 | ||
302 | can_btc = (bit_timing->phase_seg2 - 1) & 0x7; | |
303 | can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1) | |
304 | & 0xF) << 3; | |
305 | if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) { | |
306 | if (bit_timing->brp > 4) | |
307 | can_btc |= HECC_CANBTC_SAM; | |
308 | else | |
aabdfd6a | 309 | netdev_warn(priv->ndev, "WARN: Triple" |
3758bf25 AG |
310 | "sampling not set due to h/w limitations"); |
311 | } | |
312 | can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8; | |
313 | can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16; | |
314 | ||
315 | /* ERM being set to 0 by default meaning resync at falling edge */ | |
316 | ||
317 | hecc_write(priv, HECC_CANBTC, can_btc); | |
aabdfd6a | 318 | netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc); |
3758bf25 AG |
319 | |
320 | return 0; | |
321 | } | |
322 | ||
773c3e75 S |
323 | static void ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv, |
324 | int on) | |
325 | { | |
326 | if (priv->transceiver_switch) | |
327 | priv->transceiver_switch(on); | |
328 | } | |
329 | ||
3758bf25 AG |
330 | static void ti_hecc_reset(struct net_device *ndev) |
331 | { | |
332 | u32 cnt; | |
333 | struct ti_hecc_priv *priv = netdev_priv(ndev); | |
334 | ||
aabdfd6a | 335 | netdev_dbg(ndev, "resetting hecc ...\n"); |
3758bf25 AG |
336 | hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES); |
337 | ||
338 | /* Set change control request and wait till enabled */ | |
339 | hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR); | |
340 | ||
341 | /* | |
342 | * INFO: It has been observed that at times CCE bit may not be | |
343 | * set and hw seems to be ok even if this bit is not set so | |
344 | * timing out with a timing of 1ms to respect the specs | |
345 | */ | |
346 | cnt = HECC_CCE_WAIT_COUNT; | |
347 | while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { | |
348 | --cnt; | |
349 | udelay(10); | |
350 | } | |
351 | ||
352 | /* | |
353 | * Note: On HECC, BTC can be programmed only in initialization mode, so | |
354 | * it is expected that the can bittiming parameters are set via ip | |
355 | * utility before the device is opened | |
356 | */ | |
357 | ti_hecc_set_btc(priv); | |
358 | ||
359 | /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */ | |
360 | hecc_write(priv, HECC_CANMC, 0); | |
361 | ||
362 | /* | |
363 | * INFO: CAN net stack handles bus off and hence disabling auto-bus-on | |
364 | * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO); | |
365 | */ | |
366 | ||
367 | /* | |
368 | * INFO: It has been observed that at times CCE bit may not be | |
369 | * set and hw seems to be ok even if this bit is not set so | |
370 | */ | |
371 | cnt = HECC_CCE_WAIT_COUNT; | |
372 | while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { | |
373 | --cnt; | |
374 | udelay(10); | |
375 | } | |
376 | ||
377 | /* Enable TX and RX I/O Control pins */ | |
378 | hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN); | |
379 | hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN); | |
380 | ||
381 | /* Clear registers for clean operation */ | |
382 | hecc_write(priv, HECC_CANTA, HECC_SET_REG); | |
383 | hecc_write(priv, HECC_CANRMP, HECC_SET_REG); | |
384 | hecc_write(priv, HECC_CANGIF0, HECC_SET_REG); | |
385 | hecc_write(priv, HECC_CANGIF1, HECC_SET_REG); | |
386 | hecc_write(priv, HECC_CANME, 0); | |
387 | hecc_write(priv, HECC_CANMD, 0); | |
388 | ||
389 | /* SCC compat mode NOT supported (and not needed too) */ | |
390 | hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM); | |
391 | } | |
392 | ||
393 | static void ti_hecc_start(struct net_device *ndev) | |
394 | { | |
395 | struct ti_hecc_priv *priv = netdev_priv(ndev); | |
396 | u32 cnt, mbxno, mbx_mask; | |
397 | ||
398 | /* put HECC in initialization mode and set btc */ | |
399 | ti_hecc_reset(ndev); | |
400 | ||
401 | priv->tx_head = priv->tx_tail = HECC_TX_MASK; | |
402 | priv->rx_next = HECC_RX_FIRST_MBOX; | |
403 | ||
404 | /* Enable local and global acceptance mask registers */ | |
405 | hecc_write(priv, HECC_CANGAM, HECC_SET_REG); | |
406 | ||
407 | /* Prepare configured mailboxes to receive messages */ | |
408 | for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) { | |
409 | mbxno = HECC_MAX_MAILBOXES - 1 - cnt; | |
410 | mbx_mask = BIT(mbxno); | |
411 | hecc_clear_bit(priv, HECC_CANME, mbx_mask); | |
412 | hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME); | |
413 | hecc_write_lam(priv, mbxno, HECC_SET_REG); | |
414 | hecc_set_bit(priv, HECC_CANMD, mbx_mask); | |
415 | hecc_set_bit(priv, HECC_CANME, mbx_mask); | |
416 | hecc_set_bit(priv, HECC_CANMIM, mbx_mask); | |
417 | } | |
418 | ||
419 | /* Prevent message over-write & Enable interrupts */ | |
420 | hecc_write(priv, HECC_CANOPC, HECC_SET_REG); | |
421 | if (priv->int_line) { | |
422 | hecc_write(priv, HECC_CANMIL, HECC_SET_REG); | |
423 | hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK | | |
424 | HECC_CANGIM_I1EN | HECC_CANGIM_SIL); | |
425 | } else { | |
426 | hecc_write(priv, HECC_CANMIL, 0); | |
427 | hecc_write(priv, HECC_CANGIM, | |
428 | HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN); | |
429 | } | |
430 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
431 | } | |
432 | ||
433 | static void ti_hecc_stop(struct net_device *ndev) | |
434 | { | |
435 | struct ti_hecc_priv *priv = netdev_priv(ndev); | |
436 | ||
437 | /* Disable interrupts and disable mailboxes */ | |
438 | hecc_write(priv, HECC_CANGIM, 0); | |
439 | hecc_write(priv, HECC_CANMIM, 0); | |
440 | hecc_write(priv, HECC_CANME, 0); | |
441 | priv->can.state = CAN_STATE_STOPPED; | |
442 | } | |
443 | ||
444 | static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode) | |
445 | { | |
446 | int ret = 0; | |
447 | ||
448 | switch (mode) { | |
449 | case CAN_MODE_START: | |
450 | ti_hecc_start(ndev); | |
451 | netif_wake_queue(ndev); | |
452 | break; | |
453 | default: | |
454 | ret = -EOPNOTSUPP; | |
455 | break; | |
456 | } | |
457 | ||
458 | return ret; | |
459 | } | |
460 | ||
79d0d8a7 WG |
461 | static int ti_hecc_get_berr_counter(const struct net_device *ndev, |
462 | struct can_berr_counter *bec) | |
463 | { | |
464 | struct ti_hecc_priv *priv = netdev_priv(ndev); | |
465 | ||
466 | bec->txerr = hecc_read(priv, HECC_CANTEC); | |
467 | bec->rxerr = hecc_read(priv, HECC_CANREC); | |
468 | ||
469 | return 0; | |
470 | } | |
471 | ||
3758bf25 AG |
472 | /* |
473 | * ti_hecc_xmit: HECC Transmit | |
474 | * | |
475 | * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the | |
476 | * priority of the mailbox for tranmission is dependent upon priority setting | |
477 | * field in mailbox registers. The mailbox with highest value in priority field | |
478 | * is transmitted first. Only when two mailboxes have the same value in | |
479 | * priority field the highest numbered mailbox is transmitted first. | |
480 | * | |
481 | * To utilize the HECC priority feature as described above we start with the | |
482 | * highest numbered mailbox with highest priority level and move on to the next | |
483 | * mailbox with the same priority level and so on. Once we loop through all the | |
484 | * transmit mailboxes we choose the next priority level (lower) and so on | |
485 | * until we reach the lowest priority level on the lowest numbered mailbox | |
486 | * when we stop transmission until all mailboxes are transmitted and then | |
487 | * restart at highest numbered mailbox with highest priority. | |
488 | * | |
489 | * Two counters (head and tail) are used to track the next mailbox to transmit | |
490 | * and to track the echo buffer for already transmitted mailbox. The queue | |
491 | * is stopped when all the mailboxes are busy or when there is a priority | |
492 | * value roll-over happens. | |
493 | */ | |
494 | static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev) | |
495 | { | |
496 | struct ti_hecc_priv *priv = netdev_priv(ndev); | |
497 | struct can_frame *cf = (struct can_frame *)skb->data; | |
498 | u32 mbxno, mbx_mask, data; | |
499 | unsigned long flags; | |
500 | ||
3ccd4c61 OH |
501 | if (can_dropped_invalid_skb(ndev, skb)) |
502 | return NETDEV_TX_OK; | |
503 | ||
3758bf25 AG |
504 | mbxno = get_tx_head_mb(priv); |
505 | mbx_mask = BIT(mbxno); | |
506 | spin_lock_irqsave(&priv->mbx_lock, flags); | |
507 | if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) { | |
508 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | |
509 | netif_stop_queue(ndev); | |
aabdfd6a | 510 | netdev_err(priv->ndev, |
3758bf25 AG |
511 | "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n", |
512 | priv->tx_head, priv->tx_tail); | |
513 | return NETDEV_TX_BUSY; | |
514 | } | |
515 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | |
516 | ||
517 | /* Prepare mailbox for transmission */ | |
6f288cc5 | 518 | data = cf->can_dlc | (get_tx_head_prio(priv) << 8); |
3758bf25 AG |
519 | if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ |
520 | data |= HECC_CANMCF_RTR; | |
3758bf25 AG |
521 | hecc_write_mbx(priv, mbxno, HECC_CANMCF, data); |
522 | ||
523 | if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ | |
524 | data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE; | |
525 | else /* Standard frame format */ | |
526 | data = (cf->can_id & CAN_SFF_MASK) << 18; | |
527 | hecc_write_mbx(priv, mbxno, HECC_CANMID, data); | |
528 | hecc_write_mbx(priv, mbxno, HECC_CANMDL, | |
529 | be32_to_cpu(*(u32 *)(cf->data))); | |
530 | if (cf->can_dlc > 4) | |
531 | hecc_write_mbx(priv, mbxno, HECC_CANMDH, | |
532 | be32_to_cpu(*(u32 *)(cf->data + 4))); | |
533 | else | |
534 | *(u32 *)(cf->data + 4) = 0; | |
535 | can_put_echo_skb(skb, ndev, mbxno); | |
536 | ||
537 | spin_lock_irqsave(&priv->mbx_lock, flags); | |
538 | --priv->tx_head; | |
539 | if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) || | |
540 | (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) { | |
541 | netif_stop_queue(ndev); | |
542 | } | |
543 | hecc_set_bit(priv, HECC_CANME, mbx_mask); | |
544 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | |
545 | ||
546 | hecc_clear_bit(priv, HECC_CANMD, mbx_mask); | |
547 | hecc_set_bit(priv, HECC_CANMIM, mbx_mask); | |
548 | hecc_write(priv, HECC_CANTRS, mbx_mask); | |
549 | ||
550 | return NETDEV_TX_OK; | |
551 | } | |
552 | ||
553 | static int ti_hecc_rx_pkt(struct ti_hecc_priv *priv, int mbxno) | |
554 | { | |
555 | struct net_device_stats *stats = &priv->ndev->stats; | |
556 | struct can_frame *cf; | |
557 | struct sk_buff *skb; | |
558 | u32 data, mbx_mask; | |
559 | unsigned long flags; | |
560 | ||
7b6856a0 | 561 | skb = alloc_can_skb(priv->ndev, &cf); |
3758bf25 AG |
562 | if (!skb) { |
563 | if (printk_ratelimit()) | |
aabdfd6a | 564 | netdev_err(priv->ndev, |
7b6856a0 | 565 | "ti_hecc_rx_pkt: alloc_can_skb() failed\n"); |
3758bf25 AG |
566 | return -ENOMEM; |
567 | } | |
3758bf25 AG |
568 | |
569 | mbx_mask = BIT(mbxno); | |
3758bf25 AG |
570 | data = hecc_read_mbx(priv, mbxno, HECC_CANMID); |
571 | if (data & HECC_CANMID_IDE) | |
572 | cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
573 | else | |
574 | cf->can_id = (data >> 18) & CAN_SFF_MASK; | |
575 | data = hecc_read_mbx(priv, mbxno, HECC_CANMCF); | |
576 | if (data & HECC_CANMCF_RTR) | |
577 | cf->can_id |= CAN_RTR_FLAG; | |
c7cd606f | 578 | cf->can_dlc = get_can_dlc(data & 0xF); |
3758bf25 AG |
579 | data = hecc_read_mbx(priv, mbxno, HECC_CANMDL); |
580 | *(u32 *)(cf->data) = cpu_to_be32(data); | |
581 | if (cf->can_dlc > 4) { | |
582 | data = hecc_read_mbx(priv, mbxno, HECC_CANMDH); | |
583 | *(u32 *)(cf->data + 4) = cpu_to_be32(data); | |
584 | } else { | |
585 | *(u32 *)(cf->data + 4) = 0; | |
586 | } | |
587 | spin_lock_irqsave(&priv->mbx_lock, flags); | |
588 | hecc_clear_bit(priv, HECC_CANME, mbx_mask); | |
589 | hecc_write(priv, HECC_CANRMP, mbx_mask); | |
590 | /* enable mailbox only if it is part of rx buffer mailboxes */ | |
591 | if (priv->rx_next < HECC_RX_BUFFER_MBOX) | |
592 | hecc_set_bit(priv, HECC_CANME, mbx_mask); | |
593 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | |
594 | ||
595 | stats->rx_bytes += cf->can_dlc; | |
596 | netif_receive_skb(skb); | |
597 | stats->rx_packets++; | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
602 | /* | |
603 | * ti_hecc_rx_poll - HECC receive pkts | |
604 | * | |
605 | * The receive mailboxes start from highest numbered mailbox till last xmit | |
606 | * mailbox. On CAN frame reception the hardware places the data into highest | |
607 | * numbered mailbox that matches the CAN ID filter. Since all receive mailboxes | |
608 | * have same filtering (ALL CAN frames) packets will arrive in the highest | |
609 | * available RX mailbox and we need to ensure in-order packet reception. | |
610 | * | |
611 | * To ensure the packets are received in the right order we logically divide | |
612 | * the RX mailboxes into main and buffer mailboxes. Packets are received as per | |
613 | * mailbox priotity (higher to lower) in the main bank and once it is full we | |
614 | * disable further reception into main mailboxes. While the main mailboxes are | |
615 | * processed in NAPI, further packets are received in buffer mailboxes. | |
616 | * | |
617 | * We maintain a RX next mailbox counter to process packets and once all main | |
618 | * mailboxe packets are passed to the upper stack we enable all of them but | |
619 | * continue to process packets received in buffer mailboxes. With each packet | |
620 | * received from buffer mailbox we enable it immediately so as to handle the | |
621 | * overflow from higher mailboxes. | |
622 | */ | |
623 | static int ti_hecc_rx_poll(struct napi_struct *napi, int quota) | |
624 | { | |
625 | struct net_device *ndev = napi->dev; | |
626 | struct ti_hecc_priv *priv = netdev_priv(ndev); | |
627 | u32 num_pkts = 0; | |
628 | u32 mbx_mask; | |
629 | unsigned long pending_pkts, flags; | |
630 | ||
631 | if (!netif_running(ndev)) | |
632 | return 0; | |
633 | ||
634 | while ((pending_pkts = hecc_read(priv, HECC_CANRMP)) && | |
635 | num_pkts < quota) { | |
636 | mbx_mask = BIT(priv->rx_next); /* next rx mailbox to process */ | |
637 | if (mbx_mask & pending_pkts) { | |
638 | if (ti_hecc_rx_pkt(priv, priv->rx_next) < 0) | |
639 | return num_pkts; | |
640 | ++num_pkts; | |
641 | } else if (priv->rx_next > HECC_RX_BUFFER_MBOX) { | |
642 | break; /* pkt not received yet */ | |
643 | } | |
644 | --priv->rx_next; | |
645 | if (priv->rx_next == HECC_RX_BUFFER_MBOX) { | |
646 | /* enable high bank mailboxes */ | |
647 | spin_lock_irqsave(&priv->mbx_lock, flags); | |
648 | mbx_mask = hecc_read(priv, HECC_CANME); | |
649 | mbx_mask |= HECC_RX_HIGH_MBOX_MASK; | |
650 | hecc_write(priv, HECC_CANME, mbx_mask); | |
651 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | |
652 | } else if (priv->rx_next == HECC_MAX_TX_MBOX - 1) { | |
653 | priv->rx_next = HECC_RX_FIRST_MBOX; | |
654 | break; | |
655 | } | |
656 | } | |
657 | ||
658 | /* Enable packet interrupt if all pkts are handled */ | |
659 | if (hecc_read(priv, HECC_CANRMP) == 0) { | |
660 | napi_complete(napi); | |
661 | /* Re-enable RX mailbox interrupts */ | |
662 | mbx_mask = hecc_read(priv, HECC_CANMIM); | |
663 | mbx_mask |= HECC_TX_MBOX_MASK; | |
664 | hecc_write(priv, HECC_CANMIM, mbx_mask); | |
665 | } | |
666 | ||
667 | return num_pkts; | |
668 | } | |
669 | ||
670 | static int ti_hecc_error(struct net_device *ndev, int int_status, | |
671 | int err_status) | |
672 | { | |
673 | struct ti_hecc_priv *priv = netdev_priv(ndev); | |
674 | struct net_device_stats *stats = &ndev->stats; | |
675 | struct can_frame *cf; | |
676 | struct sk_buff *skb; | |
677 | ||
25985edc | 678 | /* propagate the error condition to the can stack */ |
7b6856a0 | 679 | skb = alloc_can_err_skb(ndev, &cf); |
3758bf25 AG |
680 | if (!skb) { |
681 | if (printk_ratelimit()) | |
aabdfd6a | 682 | netdev_err(priv->ndev, |
7b6856a0 | 683 | "ti_hecc_error: alloc_can_err_skb() failed\n"); |
3758bf25 AG |
684 | return -ENOMEM; |
685 | } | |
3758bf25 AG |
686 | |
687 | if (int_status & HECC_CANGIF_WLIF) { /* warning level int */ | |
688 | if ((int_status & HECC_CANGIF_BOIF) == 0) { | |
689 | priv->can.state = CAN_STATE_ERROR_WARNING; | |
690 | ++priv->can.can_stats.error_warning; | |
691 | cf->can_id |= CAN_ERR_CRTL; | |
692 | if (hecc_read(priv, HECC_CANTEC) > 96) | |
693 | cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; | |
694 | if (hecc_read(priv, HECC_CANREC) > 96) | |
695 | cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; | |
696 | } | |
697 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW); | |
aabdfd6a | 698 | netdev_dbg(priv->ndev, "Error Warning interrupt\n"); |
3758bf25 AG |
699 | hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); |
700 | } | |
701 | ||
702 | if (int_status & HECC_CANGIF_EPIF) { /* error passive int */ | |
703 | if ((int_status & HECC_CANGIF_BOIF) == 0) { | |
704 | priv->can.state = CAN_STATE_ERROR_PASSIVE; | |
705 | ++priv->can.can_stats.error_passive; | |
706 | cf->can_id |= CAN_ERR_CRTL; | |
707 | if (hecc_read(priv, HECC_CANTEC) > 127) | |
708 | cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; | |
709 | if (hecc_read(priv, HECC_CANREC) > 127) | |
710 | cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; | |
711 | } | |
712 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP); | |
aabdfd6a | 713 | netdev_dbg(priv->ndev, "Error passive interrupt\n"); |
3758bf25 AG |
714 | hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); |
715 | } | |
716 | ||
717 | /* | |
718 | * Need to check busoff condition in error status register too to | |
719 | * ensure warning interrupts don't hog the system | |
720 | */ | |
721 | if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) { | |
722 | priv->can.state = CAN_STATE_BUS_OFF; | |
723 | cf->can_id |= CAN_ERR_BUSOFF; | |
724 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO); | |
725 | hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); | |
726 | /* Disable all interrupts in bus-off to avoid int hog */ | |
727 | hecc_write(priv, HECC_CANGIM, 0); | |
728 | can_bus_off(ndev); | |
729 | } | |
730 | ||
731 | if (err_status & HECC_BUS_ERROR) { | |
732 | ++priv->can.can_stats.bus_error; | |
733 | cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; | |
734 | cf->data[2] |= CAN_ERR_PROT_UNSPEC; | |
735 | if (err_status & HECC_CANES_FE) { | |
736 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE); | |
737 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
738 | } | |
739 | if (err_status & HECC_CANES_BE) { | |
740 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE); | |
741 | cf->data[2] |= CAN_ERR_PROT_BIT; | |
742 | } | |
743 | if (err_status & HECC_CANES_SE) { | |
744 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE); | |
745 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
746 | } | |
747 | if (err_status & HECC_CANES_CRCE) { | |
748 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE); | |
749 | cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | | |
750 | CAN_ERR_PROT_LOC_CRC_DEL; | |
751 | } | |
752 | if (err_status & HECC_CANES_ACKE) { | |
753 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE); | |
754 | cf->data[2] |= CAN_ERR_PROT_LOC_ACK | | |
755 | CAN_ERR_PROT_LOC_ACK_DEL; | |
756 | } | |
757 | } | |
758 | ||
e3f240f4 | 759 | netif_rx(skb); |
3758bf25 AG |
760 | stats->rx_packets++; |
761 | stats->rx_bytes += cf->can_dlc; | |
e3f240f4 | 762 | |
3758bf25 AG |
763 | return 0; |
764 | } | |
765 | ||
766 | static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id) | |
767 | { | |
768 | struct net_device *ndev = (struct net_device *)dev_id; | |
769 | struct ti_hecc_priv *priv = netdev_priv(ndev); | |
770 | struct net_device_stats *stats = &ndev->stats; | |
771 | u32 mbxno, mbx_mask, int_status, err_status; | |
772 | unsigned long ack, flags; | |
773 | ||
774 | int_status = hecc_read(priv, | |
775 | (priv->int_line) ? HECC_CANGIF1 : HECC_CANGIF0); | |
776 | ||
777 | if (!int_status) | |
778 | return IRQ_NONE; | |
779 | ||
780 | err_status = hecc_read(priv, HECC_CANES); | |
781 | if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO | | |
782 | HECC_CANES_EP | HECC_CANES_EW)) | |
783 | ti_hecc_error(ndev, int_status, err_status); | |
784 | ||
785 | if (int_status & HECC_CANGIF_GMIF) { | |
786 | while (priv->tx_tail - priv->tx_head > 0) { | |
787 | mbxno = get_tx_tail_mb(priv); | |
788 | mbx_mask = BIT(mbxno); | |
789 | if (!(mbx_mask & hecc_read(priv, HECC_CANTA))) | |
790 | break; | |
791 | hecc_clear_bit(priv, HECC_CANMIM, mbx_mask); | |
792 | hecc_write(priv, HECC_CANTA, mbx_mask); | |
793 | spin_lock_irqsave(&priv->mbx_lock, flags); | |
794 | hecc_clear_bit(priv, HECC_CANME, mbx_mask); | |
795 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | |
796 | stats->tx_bytes += hecc_read_mbx(priv, mbxno, | |
797 | HECC_CANMCF) & 0xF; | |
798 | stats->tx_packets++; | |
799 | can_get_echo_skb(ndev, mbxno); | |
800 | --priv->tx_tail; | |
801 | } | |
802 | ||
803 | /* restart queue if wrap-up or if queue stalled on last pkt */ | |
804 | if (((priv->tx_head == priv->tx_tail) && | |
805 | ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) || | |
806 | (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) && | |
807 | ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK))) | |
808 | netif_wake_queue(ndev); | |
809 | ||
810 | /* Disable RX mailbox interrupts and let NAPI reenable them */ | |
811 | if (hecc_read(priv, HECC_CANRMP)) { | |
812 | ack = hecc_read(priv, HECC_CANMIM); | |
813 | ack &= BIT(HECC_MAX_TX_MBOX) - 1; | |
814 | hecc_write(priv, HECC_CANMIM, ack); | |
815 | napi_schedule(&priv->napi); | |
816 | } | |
817 | } | |
818 | ||
819 | /* clear all interrupt conditions - read back to avoid spurious ints */ | |
820 | if (priv->int_line) { | |
821 | hecc_write(priv, HECC_CANGIF1, HECC_SET_REG); | |
822 | int_status = hecc_read(priv, HECC_CANGIF1); | |
823 | } else { | |
824 | hecc_write(priv, HECC_CANGIF0, HECC_SET_REG); | |
825 | int_status = hecc_read(priv, HECC_CANGIF0); | |
826 | } | |
827 | ||
828 | return IRQ_HANDLED; | |
829 | } | |
830 | ||
831 | static int ti_hecc_open(struct net_device *ndev) | |
832 | { | |
833 | struct ti_hecc_priv *priv = netdev_priv(ndev); | |
834 | int err; | |
835 | ||
836 | err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED, | |
837 | ndev->name, ndev); | |
838 | if (err) { | |
aabdfd6a | 839 | netdev_err(ndev, "error requesting interrupt\n"); |
3758bf25 AG |
840 | return err; |
841 | } | |
842 | ||
773c3e75 S |
843 | ti_hecc_transceiver_switch(priv, 1); |
844 | ||
3758bf25 AG |
845 | /* Open common can device */ |
846 | err = open_candev(ndev); | |
847 | if (err) { | |
aabdfd6a | 848 | netdev_err(ndev, "open_candev() failed %d\n", err); |
773c3e75 | 849 | ti_hecc_transceiver_switch(priv, 0); |
3758bf25 AG |
850 | free_irq(ndev->irq, ndev); |
851 | return err; | |
852 | } | |
853 | ||
3758bf25 AG |
854 | ti_hecc_start(ndev); |
855 | napi_enable(&priv->napi); | |
856 | netif_start_queue(ndev); | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
861 | static int ti_hecc_close(struct net_device *ndev) | |
862 | { | |
863 | struct ti_hecc_priv *priv = netdev_priv(ndev); | |
864 | ||
865 | netif_stop_queue(ndev); | |
866 | napi_disable(&priv->napi); | |
867 | ti_hecc_stop(ndev); | |
868 | free_irq(ndev->irq, ndev); | |
3758bf25 | 869 | close_candev(ndev); |
773c3e75 | 870 | ti_hecc_transceiver_switch(priv, 0); |
3758bf25 AG |
871 | |
872 | return 0; | |
873 | } | |
874 | ||
875 | static const struct net_device_ops ti_hecc_netdev_ops = { | |
876 | .ndo_open = ti_hecc_open, | |
877 | .ndo_stop = ti_hecc_close, | |
878 | .ndo_start_xmit = ti_hecc_xmit, | |
879 | }; | |
880 | ||
881 | static int ti_hecc_probe(struct platform_device *pdev) | |
882 | { | |
883 | struct net_device *ndev = (struct net_device *)0; | |
884 | struct ti_hecc_priv *priv; | |
885 | struct ti_hecc_platform_data *pdata; | |
886 | struct resource *mem, *irq; | |
887 | void __iomem *addr; | |
888 | int err = -ENODEV; | |
889 | ||
890 | pdata = pdev->dev.platform_data; | |
891 | if (!pdata) { | |
892 | dev_err(&pdev->dev, "No platform data\n"); | |
893 | goto probe_exit; | |
894 | } | |
895 | ||
896 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
897 | if (!mem) { | |
898 | dev_err(&pdev->dev, "No mem resources\n"); | |
899 | goto probe_exit; | |
900 | } | |
901 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
902 | if (!irq) { | |
903 | dev_err(&pdev->dev, "No irq resource\n"); | |
904 | goto probe_exit; | |
905 | } | |
906 | if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) { | |
907 | dev_err(&pdev->dev, "HECC region already claimed\n"); | |
908 | err = -EBUSY; | |
909 | goto probe_exit; | |
910 | } | |
911 | addr = ioremap(mem->start, resource_size(mem)); | |
912 | if (!addr) { | |
913 | dev_err(&pdev->dev, "ioremap failed\n"); | |
914 | err = -ENOMEM; | |
915 | goto probe_exit_free_region; | |
916 | } | |
917 | ||
a6e4bc53 | 918 | ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX); |
3758bf25 AG |
919 | if (!ndev) { |
920 | dev_err(&pdev->dev, "alloc_candev failed\n"); | |
921 | err = -ENOMEM; | |
922 | goto probe_exit_iounmap; | |
923 | } | |
924 | ||
925 | priv = netdev_priv(ndev); | |
926 | priv->ndev = ndev; | |
927 | priv->base = addr; | |
928 | priv->scc_ram_offset = pdata->scc_ram_offset; | |
929 | priv->hecc_ram_offset = pdata->hecc_ram_offset; | |
930 | priv->mbx_offset = pdata->mbx_offset; | |
931 | priv->int_line = pdata->int_line; | |
773c3e75 | 932 | priv->transceiver_switch = pdata->transceiver_switch; |
3758bf25 AG |
933 | |
934 | priv->can.bittiming_const = &ti_hecc_bittiming_const; | |
935 | priv->can.do_set_mode = ti_hecc_do_set_mode; | |
936 | priv->can.do_get_state = ti_hecc_get_state; | |
79d0d8a7 | 937 | priv->can.do_get_berr_counter = ti_hecc_get_berr_counter; |
ad72c347 | 938 | priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; |
3758bf25 | 939 | |
86ad47ff | 940 | spin_lock_init(&priv->mbx_lock); |
3758bf25 AG |
941 | ndev->irq = irq->start; |
942 | ndev->flags |= IFF_ECHO; | |
943 | platform_set_drvdata(pdev, ndev); | |
944 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
945 | ndev->netdev_ops = &ti_hecc_netdev_ops; | |
946 | ||
947 | priv->clk = clk_get(&pdev->dev, "hecc_ck"); | |
948 | if (IS_ERR(priv->clk)) { | |
949 | dev_err(&pdev->dev, "No clock available\n"); | |
950 | err = PTR_ERR(priv->clk); | |
951 | priv->clk = NULL; | |
952 | goto probe_exit_candev; | |
953 | } | |
954 | priv->can.clock.freq = clk_get_rate(priv->clk); | |
955 | netif_napi_add(ndev, &priv->napi, ti_hecc_rx_poll, | |
956 | HECC_DEF_NAPI_WEIGHT); | |
957 | ||
35e2da46 | 958 | clk_enable(priv->clk); |
3758bf25 AG |
959 | err = register_candev(ndev); |
960 | if (err) { | |
961 | dev_err(&pdev->dev, "register_candev() failed\n"); | |
962 | goto probe_exit_clk; | |
963 | } | |
964 | dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", | |
965 | priv->base, (u32) ndev->irq); | |
966 | ||
967 | return 0; | |
968 | ||
969 | probe_exit_clk: | |
970 | clk_put(priv->clk); | |
971 | probe_exit_candev: | |
972 | free_candev(ndev); | |
973 | probe_exit_iounmap: | |
974 | iounmap(addr); | |
975 | probe_exit_free_region: | |
976 | release_mem_region(mem->start, resource_size(mem)); | |
977 | probe_exit: | |
978 | return err; | |
979 | } | |
980 | ||
3c8ac0f2 | 981 | static int ti_hecc_remove(struct platform_device *pdev) |
3758bf25 AG |
982 | { |
983 | struct resource *res; | |
984 | struct net_device *ndev = platform_get_drvdata(pdev); | |
985 | struct ti_hecc_priv *priv = netdev_priv(ndev); | |
986 | ||
ab04c8bd | 987 | unregister_candev(ndev); |
35e2da46 | 988 | clk_disable(priv->clk); |
3758bf25 AG |
989 | clk_put(priv->clk); |
990 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
991 | iounmap(priv->base); | |
992 | release_mem_region(res->start, resource_size(res)); | |
3758bf25 AG |
993 | free_candev(ndev); |
994 | platform_set_drvdata(pdev, NULL); | |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
35e2da46 S |
999 | |
1000 | #ifdef CONFIG_PM | |
1001 | static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state) | |
1002 | { | |
1003 | struct net_device *dev = platform_get_drvdata(pdev); | |
1004 | struct ti_hecc_priv *priv = netdev_priv(dev); | |
1005 | ||
1006 | if (netif_running(dev)) { | |
1007 | netif_stop_queue(dev); | |
1008 | netif_device_detach(dev); | |
1009 | } | |
1010 | ||
1011 | hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR); | |
1012 | priv->can.state = CAN_STATE_SLEEPING; | |
1013 | ||
1014 | clk_disable(priv->clk); | |
1015 | ||
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | static int ti_hecc_resume(struct platform_device *pdev) | |
1020 | { | |
1021 | struct net_device *dev = platform_get_drvdata(pdev); | |
1022 | struct ti_hecc_priv *priv = netdev_priv(dev); | |
1023 | ||
1024 | clk_enable(priv->clk); | |
1025 | ||
1026 | hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR); | |
1027 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1028 | ||
1029 | if (netif_running(dev)) { | |
1030 | netif_device_attach(dev); | |
1031 | netif_start_queue(dev); | |
1032 | } | |
1033 | ||
1034 | return 0; | |
1035 | } | |
1036 | #else | |
1037 | #define ti_hecc_suspend NULL | |
1038 | #define ti_hecc_resume NULL | |
1039 | #endif | |
1040 | ||
3758bf25 AG |
1041 | /* TI HECC netdevice driver: platform driver structure */ |
1042 | static struct platform_driver ti_hecc_driver = { | |
1043 | .driver = { | |
1044 | .name = DRV_NAME, | |
1045 | .owner = THIS_MODULE, | |
1046 | }, | |
1047 | .probe = ti_hecc_probe, | |
3c8ac0f2 | 1048 | .remove = ti_hecc_remove, |
35e2da46 S |
1049 | .suspend = ti_hecc_suspend, |
1050 | .resume = ti_hecc_resume, | |
3758bf25 AG |
1051 | }; |
1052 | ||
871d3372 | 1053 | module_platform_driver(ti_hecc_driver); |
3758bf25 AG |
1054 | |
1055 | MODULE_AUTHOR("Anant Gole <anantgole@ti.com>"); | |
1056 | MODULE_LICENSE("GPL v2"); | |
1057 | MODULE_DESCRIPTION(DRV_DESC); | |
64116c14 | 1058 | MODULE_ALIAS("platform:" DRV_NAME); |