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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / can / mcp251x.c
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e0000163
CP		 1/*
2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 *
34 *
35 *
36 * Your platform definition file should specify something like:
37 *
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
41 * .model = CAN_MCP251X_MCP2510,
42 * .power_enable = mcp251x_power_enable,
43 * .transceiver_enable = NULL,
44 * };
45 *
46 * static struct spi_board_info spi_board_info[] = {
47 * {
48 * .modalias = "mcp251x",
49 * .platform_data = &mcp251x_info,
50 * .irq = IRQ_EINT13,
51 * .max_speed_hz = 2*1000*1000,
52 * .chip_select = 2,
53 * },
54 * };
55 *
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
58 *
59 */
60
61#include <linux/can.h>
62#include <linux/can/core.h>
63#include <linux/can/dev.h>
64#include <linux/can/platform/mcp251x.h>
65#include <linux/completion.h>
66#include <linux/delay.h>
67#include <linux/device.h>
68#include <linux/dma-mapping.h>
69#include <linux/freezer.h>
70#include <linux/interrupt.h>
71#include <linux/io.h>
72#include <linux/kernel.h>
73#include <linux/module.h>
74#include <linux/netdevice.h>
75#include <linux/platform_device.h>
5a0e3ad6 76#include <linux/slab.h>
e0000163
CP		 77#include <linux/spi/spi.h>
78#include <linux/uaccess.h>
79
80/* SPI interface instruction set */
81#define INSTRUCTION_WRITE 0x02
82#define INSTRUCTION_READ 0x03
83#define INSTRUCTION_BIT_MODIFY 0x05
84#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
85#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
86#define INSTRUCTION_RESET 0xC0
87
88/* MPC251x registers */
89#define CANSTAT 0x0e
90#define CANCTRL 0x0f
91# define CANCTRL_REQOP_MASK 0xe0
92# define CANCTRL_REQOP_CONF 0x80
93# define CANCTRL_REQOP_LISTEN_ONLY 0x60
94# define CANCTRL_REQOP_LOOPBACK 0x40
95# define CANCTRL_REQOP_SLEEP 0x20
96# define CANCTRL_REQOP_NORMAL 0x00
97# define CANCTRL_OSM 0x08
98# define CANCTRL_ABAT 0x10
99#define TEC 0x1c
100#define REC 0x1d
101#define CNF1 0x2a
102# define CNF1_SJW_SHIFT 6
103#define CNF2 0x29
104# define CNF2_BTLMODE 0x80
105# define CNF2_SAM 0x40
106# define CNF2_PS1_SHIFT 3
107#define CNF3 0x28
108# define CNF3_SOF 0x08
109# define CNF3_WAKFIL 0x04
110# define CNF3_PHSEG2_MASK 0x07
111#define CANINTE 0x2b
112# define CANINTE_MERRE 0x80
113# define CANINTE_WAKIE 0x40
114# define CANINTE_ERRIE 0x20
115# define CANINTE_TX2IE 0x10
116# define CANINTE_TX1IE 0x08
117# define CANINTE_TX0IE 0x04
118# define CANINTE_RX1IE 0x02
119# define CANINTE_RX0IE 0x01
120#define CANINTF 0x2c
121# define CANINTF_MERRF 0x80
122# define CANINTF_WAKIF 0x40
123# define CANINTF_ERRIF 0x20
124# define CANINTF_TX2IF 0x10
125# define CANINTF_TX1IF 0x08
126# define CANINTF_TX0IF 0x04
127# define CANINTF_RX1IF 0x02
128# define CANINTF_RX0IF 0x01
129#define EFLG 0x2d
130# define EFLG_EWARN 0x01
131# define EFLG_RXWAR 0x02
132# define EFLG_TXWAR 0x04
133# define EFLG_RXEP 0x08
134# define EFLG_TXEP 0x10
135# define EFLG_TXBO 0x20
136# define EFLG_RX0OVR 0x40
137# define EFLG_RX1OVR 0x80
138#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
139# define TXBCTRL_ABTF 0x40
140# define TXBCTRL_MLOA 0x20
141# define TXBCTRL_TXERR 0x10
142# define TXBCTRL_TXREQ 0x08
143#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
144# define SIDH_SHIFT 3
145#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
146# define SIDL_SID_MASK 7
147# define SIDL_SID_SHIFT 5
148# define SIDL_EXIDE_SHIFT 3
149# define SIDL_EID_SHIFT 16
150# define SIDL_EID_MASK 3
151#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
152#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
153#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
154# define DLC_RTR_SHIFT 6
155#define TXBCTRL_OFF 0
156#define TXBSIDH_OFF 1
157#define TXBSIDL_OFF 2
158#define TXBEID8_OFF 3
159#define TXBEID0_OFF 4
160#define TXBDLC_OFF 5
161#define TXBDAT_OFF 6
162#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
163# define RXBCTRL_BUKT 0x04
164# define RXBCTRL_RXM0 0x20
165# define RXBCTRL_RXM1 0x40
166#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
167# define RXBSIDH_SHIFT 3
168#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
169# define RXBSIDL_IDE 0x08
170# define RXBSIDL_EID 3
171# define RXBSIDL_SHIFT 5
172#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
173#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
174#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
175# define RXBDLC_LEN_MASK 0x0f
176# define RXBDLC_RTR 0x40
177#define RXBCTRL_OFF 0
178#define RXBSIDH_OFF 1
179#define RXBSIDL_OFF 2
180#define RXBEID8_OFF 3
181#define RXBEID0_OFF 4
182#define RXBDLC_OFF 5
183#define RXBDAT_OFF 6
bf66f373
CP		 184#define RXFSIDH(n) ((n) * 4)
185#define RXFSIDL(n) ((n) * 4 + 1)
186#define RXFEID8(n) ((n) * 4 + 2)
187#define RXFEID0(n) ((n) * 4 + 3)
188#define RXMSIDH(n) ((n) * 4 + 0x20)
189#define RXMSIDL(n) ((n) * 4 + 0x21)
190#define RXMEID8(n) ((n) * 4 + 0x22)
191#define RXMEID0(n) ((n) * 4 + 0x23)
e0000163
CP		 192
193#define GET_BYTE(val, byte) \
194 (((val) >> ((byte) * 8)) & 0xff)
195#define SET_BYTE(val, byte) \
196 (((val) & 0xff) << ((byte) * 8))
197
198/*
199 * Buffer size required for the largest SPI transfer (i.e., reading a
200 * frame)
201 */
202#define CAN_FRAME_MAX_DATA_LEN 8
203#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
204#define CAN_FRAME_MAX_BITS 128
205
206#define TX_ECHO_SKB_MAX 1
207
208#define DEVICE_NAME "mcp251x"
209
210static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
211module_param(mcp251x_enable_dma, int, S_IRUGO);
212MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
213
214static struct can_bittiming_const mcp251x_bittiming_const = {
215 .name = DEVICE_NAME,
216 .tseg1_min = 3,
217 .tseg1_max = 16,
218 .tseg2_min = 2,
219 .tseg2_max = 8,
220 .sjw_max = 4,
221 .brp_min = 1,
222 .brp_max = 64,
223 .brp_inc = 1,
224};
225
226struct mcp251x_priv {
227 struct can_priv can;
228 struct net_device *net;
229 struct spi_device *spi;
230
bf66f373
CP		 231 struct mutex mcp_lock; /* SPI device lock */
232
e0000163
CP		 233 u8 *spi_tx_buf;
234 u8 *spi_rx_buf;
235 dma_addr_t spi_tx_dma;
236 dma_addr_t spi_rx_dma;
237
238 struct sk_buff *tx_skb;
239 int tx_len;
bf66f373 240
e0000163
CP		 241 struct workqueue_struct *wq;
242 struct work_struct tx_work;
bf66f373
CP		 243 struct work_struct restart_work;
244
e0000163
CP		 245 int force_quit;
246 int after_suspend;
247#define AFTER_SUSPEND_UP 1
248#define AFTER_SUSPEND_DOWN 2
249#define AFTER_SUSPEND_POWER 4
250#define AFTER_SUSPEND_RESTART 8
251 int restart_tx;
252};
253
254static void mcp251x_clean(struct net_device *net)
255{
256 struct mcp251x_priv *priv = netdev_priv(net);
257
bf66f373
CP		 258 if (priv->tx_skb || priv->tx_len)
259 net->stats.tx_errors++;
e0000163
CP		 260 if (priv->tx_skb)
261 dev_kfree_skb(priv->tx_skb);
262 if (priv->tx_len)
263 can_free_echo_skb(priv->net, 0);
264 priv->tx_skb = NULL;
265 priv->tx_len = 0;
266}
267
268/*
269 * Note about handling of error return of mcp251x_spi_trans: accessing
270 * registers via SPI is not really different conceptually than using
271 * normal I/O assembler instructions, although it's much more
272 * complicated from a practical POV. So it's not advisable to always
273 * check the return value of this function. Imagine that every
274 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
275 * error();", it would be a great mess (well there are some situation
276 * when exception handling C++ like could be useful after all). So we
277 * just check that transfers are OK at the beginning of our
278 * conversation with the chip and to avoid doing really nasty things
279 * (like injecting bogus packets in the network stack).
280 */
281static int mcp251x_spi_trans(struct spi_device *spi, int len)
282{
283 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
284 struct spi_transfer t = {
285 .tx_buf = priv->spi_tx_buf,
286 .rx_buf = priv->spi_rx_buf,
287 .len = len,
288 .cs_change = 0,
289 };
290 struct spi_message m;
291 int ret;
292
293 spi_message_init(&m);
294
295 if (mcp251x_enable_dma) {
296 t.tx_dma = priv->spi_tx_dma;
297 t.rx_dma = priv->spi_rx_dma;
298 m.is_dma_mapped = 1;
299 }
300
301 spi_message_add_tail(&t, &m);
302
303 ret = spi_sync(spi, &m);
304 if (ret)
305 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
306 return ret;
307}
308
309static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
310{
311 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
312 u8 val = 0;
313
e0000163
CP		 314 priv->spi_tx_buf[0] = INSTRUCTION_READ;
315 priv->spi_tx_buf[1] = reg;
316
317 mcp251x_spi_trans(spi, 3);
318 val = priv->spi_rx_buf[2];
319
e0000163
CP		 320 return val;
321}
322
323static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
324{
325 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
326
e0000163
CP		 327 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
328 priv->spi_tx_buf[1] = reg;
329 priv->spi_tx_buf[2] = val;
330
331 mcp251x_spi_trans(spi, 3);
e0000163
CP		 332}
333
334static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
335 u8 mask, uint8_t val)
336{
337 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
338
e0000163
CP		 339 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
340 priv->spi_tx_buf[1] = reg;
341 priv->spi_tx_buf[2] = mask;
342 priv->spi_tx_buf[3] = val;
343
344 mcp251x_spi_trans(spi, 4);
e0000163
CP		 345}
346
347static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
348 int len, int tx_buf_idx)
349{
350 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
351 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
352
353 if (pdata->model == CAN_MCP251X_MCP2510) {
354 int i;
355
356 for (i = 1; i < TXBDAT_OFF + len; i++)
357 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
358 buf[i]);
359 } else {
e0000163
CP		 360 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
361 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
e0000163
CP		 362 }
363}
364
365static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
366 int tx_buf_idx)
367{
368 u32 sid, eid, exide, rtr;
369 u8 buf[SPI_TRANSFER_BUF_LEN];
370
371 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
372 if (exide)
373 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
374 else
375 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
376 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
377 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
378
379 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
380 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
381 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
382 (exide << SIDL_EXIDE_SHIFT) |
383 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
384 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
385 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
386 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
387 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
388 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
389 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx), TXBCTRL_TXREQ);
390}
391
392static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
393 int buf_idx)
394{
395 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
396 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
397
398 if (pdata->model == CAN_MCP251X_MCP2510) {
399 int i, len;
400
401 for (i = 1; i < RXBDAT_OFF; i++)
402 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
c7cd606f
OH		 403
404 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
e0000163
CP		 405 for (; i < (RXBDAT_OFF + len); i++)
406 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
407 } else {
e0000163
CP		 408 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
409 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
410 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
e0000163
CP		 411 }
412}
413
414static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
415{
416 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
417 struct sk_buff *skb;
418 struct can_frame *frame;
419 u8 buf[SPI_TRANSFER_BUF_LEN];
420
421 skb = alloc_can_skb(priv->net, &frame);
422 if (!skb) {
423 dev_err(&spi->dev, "cannot allocate RX skb\n");
424 priv->net->stats.rx_dropped++;
425 return;
426 }
427
428 mcp251x_hw_rx_frame(spi, buf, buf_idx);
429 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
430 /* Extended ID format */
431 frame->can_id = CAN_EFF_FLAG;
432 frame->can_id |=
433 /* Extended ID part */
434 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
435 SET_BYTE(buf[RXBEID8_OFF], 1) |
436 SET_BYTE(buf[RXBEID0_OFF], 0) |
437 /* Standard ID part */
438 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
439 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
440 /* Remote transmission request */
441 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
442 frame->can_id |= CAN_RTR_FLAG;
443 } else {
444 /* Standard ID format */
445 frame->can_id =
446 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
447 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
448 }
449 /* Data length */
c7cd606f 450 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
e0000163
CP		 451 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
452
453 priv->net->stats.rx_packets++;
454 priv->net->stats.rx_bytes += frame->can_dlc;
455 netif_rx(skb);
456}
457
458static void mcp251x_hw_sleep(struct spi_device *spi)
459{
460 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
461}
462
e0000163
CP		 463static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
464 struct net_device *net)
465{
466 struct mcp251x_priv *priv = netdev_priv(net);
467 struct spi_device *spi = priv->spi;
468
469 if (priv->tx_skb || priv->tx_len) {
470 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
e0000163
CP		 471 return NETDEV_TX_BUSY;
472 }
473
3ccd4c61 474 if (can_dropped_invalid_skb(net, skb))
e0000163 475 return NETDEV_TX_OK;
e0000163
CP		 476
477 netif_stop_queue(net);
478 priv->tx_skb = skb;
479 net->trans_start = jiffies;
480 queue_work(priv->wq, &priv->tx_work);
481
482 return NETDEV_TX_OK;
483}
484
485static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
486{
487 struct mcp251x_priv *priv = netdev_priv(net);
488
489 switch (mode) {
490 case CAN_MODE_START:
bf66f373 491 mcp251x_clean(net);
e0000163
CP		 492 /* We have to delay work since SPI I/O may sleep */
493 priv->can.state = CAN_STATE_ERROR_ACTIVE;
494 priv->restart_tx = 1;
495 if (priv->can.restart_ms == 0)
496 priv->after_suspend = AFTER_SUSPEND_RESTART;
bf66f373 497 queue_work(priv->wq, &priv->restart_work);
e0000163
CP		 498 break;
499 default:
500 return -EOPNOTSUPP;
501 }
502
503 return 0;
504}
505
bf66f373 506static int mcp251x_set_normal_mode(struct spi_device *spi)
e0000163
CP		 507{
508 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
509 unsigned long timeout;
510
511 /* Enable interrupts */
512 mcp251x_write_reg(spi, CANINTE,
513 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
bf66f373 514 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
e0000163
CP		 515
516 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
517 /* Put device into loopback mode */
518 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
ad72c347
CP		 519 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
520 /* Put device into listen-only mode */
521 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
e0000163
CP		 522 } else {
523 /* Put device into normal mode */
bf66f373 524 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
e0000163
CP		 525
526 /* Wait for the device to enter normal mode */
527 timeout = jiffies + HZ;
528 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
529 schedule();
530 if (time_after(jiffies, timeout)) {
531 dev_err(&spi->dev, "MCP251x didn't"
532 " enter in normal mode\n");
bf66f373 533 return -EBUSY;
e0000163
CP		 534 }
535 }
536 }
537 priv->can.state = CAN_STATE_ERROR_ACTIVE;
bf66f373 538 return 0;
e0000163
CP		 539}
540
541static int mcp251x_do_set_bittiming(struct net_device *net)
542{
543 struct mcp251x_priv *priv = netdev_priv(net);
544 struct can_bittiming *bt = &priv->can.bittiming;
545 struct spi_device *spi = priv->spi;
546
547 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
548 (bt->brp - 1));
549 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
550 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
551 CNF2_SAM : 0) |
552 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
553 (bt->prop_seg - 1));
554 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
555 (bt->phase_seg2 - 1));
556 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
557 mcp251x_read_reg(spi, CNF1),
558 mcp251x_read_reg(spi, CNF2),
559 mcp251x_read_reg(spi, CNF3));
560
561 return 0;
562}
563
564static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
565 struct spi_device *spi)
566{
615534bc 567 mcp251x_do_set_bittiming(net);
e0000163 568
bf66f373
CP		 569 mcp251x_write_reg(spi, RXBCTRL(0),
570 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
571 mcp251x_write_reg(spi, RXBCTRL(1),
572 RXBCTRL_RXM0 | RXBCTRL_RXM1);
e0000163
CP		 573 return 0;
574}
575
bf66f373 576static int mcp251x_hw_reset(struct spi_device *spi)
e0000163
CP		 577{
578 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
579 int ret;
bf66f373 580 unsigned long timeout;
e0000163
CP		 581
582 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
e0000163 583 ret = spi_write(spi, priv->spi_tx_buf, 1);
bf66f373 584 if (ret) {
e0000163 585 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
bf66f373
CP		 586 return -EIO;
587 }
588
e0000163 589 /* Wait for reset to finish */
bf66f373 590 timeout = jiffies + HZ;
e0000163 591 mdelay(10);
bf66f373
CP		 592 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK)
593 != CANCTRL_REQOP_CONF) {
594 schedule();
595 if (time_after(jiffies, timeout)) {
596 dev_err(&spi->dev, "MCP251x didn't"
597 " enter in conf mode after reset\n");
598 return -EBUSY;
599 }
600 }
601 return 0;
e0000163
CP		 602}
603
604static int mcp251x_hw_probe(struct spi_device *spi)
605{
606 int st1, st2;
607
608 mcp251x_hw_reset(spi);
609
610 /*
611 * Please note that these are "magic values" based on after
612 * reset defaults taken from data sheet which allows us to see
613 * if we really have a chip on the bus (we avoid common all
614 * zeroes or all ones situations)
615 */
616 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
617 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
618
619 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
620
621 /* Check for power up default values */
622 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
623}
624
bf66f373 625static void mcp251x_open_clean(struct net_device *net)
e0000163
CP		 626{
627 struct mcp251x_priv *priv = netdev_priv(net);
628 struct spi_device *spi = priv->spi;
629 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
615534bc 630
bf66f373
CP		 631 free_irq(spi->irq, priv);
632 mcp251x_hw_sleep(spi);
e0000163 633 if (pdata->transceiver_enable)
bf66f373
CP		 634 pdata->transceiver_enable(0);
635 close_candev(net);
e0000163
CP		 636}
637
638static int mcp251x_stop(struct net_device *net)
639{
640 struct mcp251x_priv *priv = netdev_priv(net);
641 struct spi_device *spi = priv->spi;
642 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
643
644 close_candev(net);
645
bf66f373
CP		 646 priv->force_quit = 1;
647 free_irq(spi->irq, priv);
648 destroy_workqueue(priv->wq);
649 priv->wq = NULL;
650
651 mutex_lock(&priv->mcp_lock);
652
e0000163
CP		 653 /* Disable and clear pending interrupts */
654 mcp251x_write_reg(spi, CANINTE, 0x00);
655 mcp251x_write_reg(spi, CANINTF, 0x00);
656
e0000163 657 mcp251x_write_reg(spi, TXBCTRL(0), 0);
bf66f373 658 mcp251x_clean(net);
e0000163
CP		 659
660 mcp251x_hw_sleep(spi);
661
662 if (pdata->transceiver_enable)
663 pdata->transceiver_enable(0);
664
665 priv->can.state = CAN_STATE_STOPPED;
666
bf66f373
CP		 667 mutex_unlock(&priv->mcp_lock);
668
e0000163
CP		 669 return 0;
670}
671
bf66f373
CP		 672static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
673{
674 struct sk_buff *skb;
675 struct can_frame *frame;
676
677 skb = alloc_can_err_skb(net, &frame);
678 if (skb) {
679 frame->can_id = can_id;
680 frame->data[1] = data1;
681 netif_rx(skb);
682 } else {
683 dev_err(&net->dev,
684 "cannot allocate error skb\n");
685 }
686}
687
e0000163
CP		 688static void mcp251x_tx_work_handler(struct work_struct *ws)
689{
690 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
691 tx_work);
692 struct spi_device *spi = priv->spi;
693 struct net_device *net = priv->net;
694 struct can_frame *frame;
695
bf66f373 696 mutex_lock(&priv->mcp_lock);
e0000163 697 if (priv->tx_skb) {
e0000163
CP		 698 if (priv->can.state == CAN_STATE_BUS_OFF) {
699 mcp251x_clean(net);
bf66f373
CP		 700 } else {
701 frame = (struct can_frame *)priv->tx_skb->data;
702
703 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
704 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
705 mcp251x_hw_tx(spi, frame, 0);
706 priv->tx_len = 1 + frame->can_dlc;
707 can_put_echo_skb(priv->tx_skb, net, 0);
708 priv->tx_skb = NULL;
e0000163 709 }
e0000163 710 }
bf66f373 711 mutex_unlock(&priv->mcp_lock);
e0000163
CP		 712}
713
bf66f373 714static void mcp251x_restart_work_handler(struct work_struct *ws)
e0000163
CP		 715{
716 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
bf66f373 717 restart_work);
e0000163
CP		 718 struct spi_device *spi = priv->spi;
719 struct net_device *net = priv->net;
e0000163 720
bf66f373 721 mutex_lock(&priv->mcp_lock);
e0000163
CP		 722 if (priv->after_suspend) {
723 mdelay(10);
724 mcp251x_hw_reset(spi);
725 mcp251x_setup(net, priv, spi);
726 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
727 mcp251x_set_normal_mode(spi);
728 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
729 netif_device_attach(net);
bf66f373 730 mcp251x_clean(net);
e0000163 731 mcp251x_set_normal_mode(spi);
bf66f373 732 netif_wake_queue(net);
e0000163
CP		 733 } else {
734 mcp251x_hw_sleep(spi);
735 }
736 priv->after_suspend = 0;
bf66f373 737 priv->force_quit = 0;
e0000163
CP		 738 }
739
bf66f373
CP		 740 if (priv->restart_tx) {
741 priv->restart_tx = 0;
742 mcp251x_write_reg(spi, TXBCTRL(0), 0);
743 mcp251x_clean(net);
744 netif_wake_queue(net);
745 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
746 }
747 mutex_unlock(&priv->mcp_lock);
748}
e0000163 749
bf66f373
CP		 750static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
751{
752 struct mcp251x_priv *priv = dev_id;
753 struct spi_device *spi = priv->spi;
754 struct net_device *net = priv->net;
e0000163 755
bf66f373
CP		 756 mutex_lock(&priv->mcp_lock);
757 while (!priv->force_quit) {
758 enum can_state new_state;
759 u8 intf = mcp251x_read_reg(spi, CANINTF);
760 u8 eflag;
761 int can_id = 0, data1 = 0;
e0000163 762
bf66f373
CP		 763 if (intf & CANINTF_RX0IF) {
764 mcp251x_hw_rx(spi, 0);
765 /* Free one buffer ASAP */
766 mcp251x_write_bits(spi, CANINTF, intf & CANINTF_RX0IF,
767 0x00);
e0000163
CP		 768 }
769
bf66f373
CP		 770 if (intf & CANINTF_RX1IF)
771 mcp251x_hw_rx(spi, 1);
e0000163 772
e0000163
CP		 773 mcp251x_write_bits(spi, CANINTF, intf, 0x00);
774
bf66f373
CP		 775 eflag = mcp251x_read_reg(spi, EFLG);
776 mcp251x_write_reg(spi, EFLG, 0x00);
777
e0000163
CP		 778 /* Update can state */
779 if (eflag & EFLG_TXBO) {
780 new_state = CAN_STATE_BUS_OFF;
781 can_id |= CAN_ERR_BUSOFF;
782 } else if (eflag & EFLG_TXEP) {
783 new_state = CAN_STATE_ERROR_PASSIVE;
784 can_id |= CAN_ERR_CRTL;
785 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
786 } else if (eflag & EFLG_RXEP) {
787 new_state = CAN_STATE_ERROR_PASSIVE;
788 can_id |= CAN_ERR_CRTL;
789 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
790 } else if (eflag & EFLG_TXWAR) {
791 new_state = CAN_STATE_ERROR_WARNING;
792 can_id |= CAN_ERR_CRTL;
793 data1 |= CAN_ERR_CRTL_TX_WARNING;
794 } else if (eflag & EFLG_RXWAR) {
795 new_state = CAN_STATE_ERROR_WARNING;
796 can_id |= CAN_ERR_CRTL;
797 data1 |= CAN_ERR_CRTL_RX_WARNING;
798 } else {
799 new_state = CAN_STATE_ERROR_ACTIVE;
800 }
801
802 /* Update can state statistics */
803 switch (priv->can.state) {
804 case CAN_STATE_ERROR_ACTIVE:
805 if (new_state >= CAN_STATE_ERROR_WARNING &&
806 new_state <= CAN_STATE_BUS_OFF)
807 priv->can.can_stats.error_warning++;
808 case CAN_STATE_ERROR_WARNING: /* fallthrough */
809 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
810 new_state <= CAN_STATE_BUS_OFF)
811 priv->can.can_stats.error_passive++;
812 break;
813 default:
814 break;
815 }
816 priv->can.state = new_state;
817
bf66f373
CP		 818 if (intf & CANINTF_ERRIF) {
819 /* Handle overflow counters */
820 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
821 if (eflag & EFLG_RX0OVR)
822 net->stats.rx_over_errors++;
823 if (eflag & EFLG_RX1OVR)
824 net->stats.rx_over_errors++;
825 can_id |= CAN_ERR_CRTL;
826 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
e0000163 827 }
bf66f373 828 mcp251x_error_skb(net, can_id, data1);
e0000163
CP		 829 }
830
831 if (priv->can.state == CAN_STATE_BUS_OFF) {
832 if (priv->can.restart_ms == 0) {
bf66f373 833 priv->force_quit = 1;
e0000163
CP		 834 can_bus_off(net);
835 mcp251x_hw_sleep(spi);
bf66f373 836 break;
e0000163
CP		 837 }
838 }
839
840 if (intf == 0)
841 break;
842
e0000163
CP		 843 if (intf & (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)) {
844 net->stats.tx_packets++;
845 net->stats.tx_bytes += priv->tx_len - 1;
846 if (priv->tx_len) {
847 can_get_echo_skb(net, 0);
848 priv->tx_len = 0;
849 }
850 netif_wake_queue(net);
851 }
852
bf66f373
CP		 853 }
854 mutex_unlock(&priv->mcp_lock);
855 return IRQ_HANDLED;
856}
e0000163 857
bf66f373
CP		 858static int mcp251x_open(struct net_device *net)
859{
860 struct mcp251x_priv *priv = netdev_priv(net);
861 struct spi_device *spi = priv->spi;
862 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
863 int ret;
864
865 ret = open_candev(net);
866 if (ret) {
867 dev_err(&spi->dev, "unable to set initial baudrate!\n");
868 return ret;
869 }
870
871 mutex_lock(&priv->mcp_lock);
872 if (pdata->transceiver_enable)
873 pdata->transceiver_enable(1);
874
875 priv->force_quit = 0;
876 priv->tx_skb = NULL;
877 priv->tx_len = 0;
878
879 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
880 IRQF_TRIGGER_FALLING, DEVICE_NAME, priv);
881 if (ret) {
882 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
883 if (pdata->transceiver_enable)
884 pdata->transceiver_enable(0);
885 close_candev(net);
886 goto open_unlock;
887 }
888
889 priv->wq = create_freezeable_workqueue("mcp251x_wq");
890 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
891 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
892
893 ret = mcp251x_hw_reset(spi);
894 if (ret) {
895 mcp251x_open_clean(net);
896 goto open_unlock;
897 }
898 ret = mcp251x_setup(net, priv, spi);
899 if (ret) {
900 mcp251x_open_clean(net);
901 goto open_unlock;
e0000163 902 }
bf66f373
CP		 903 ret = mcp251x_set_normal_mode(spi);
904 if (ret) {
905 mcp251x_open_clean(net);
906 goto open_unlock;
907 }
908 netif_wake_queue(net);
909
910open_unlock:
911 mutex_unlock(&priv->mcp_lock);
912 return ret;
e0000163
CP		 913}
914
915static const struct net_device_ops mcp251x_netdev_ops = {
916 .ndo_open = mcp251x_open,
917 .ndo_stop = mcp251x_stop,
918 .ndo_start_xmit = mcp251x_hard_start_xmit,
919};
920
921static int __devinit mcp251x_can_probe(struct spi_device *spi)
922{
923 struct net_device *net;
924 struct mcp251x_priv *priv;
925 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
926 int ret = -ENODEV;
927
928 if (!pdata)
929 /* Platform data is required for osc freq */
930 goto error_out;
931
932 /* Allocate can/net device */
933 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
934 if (!net) {
935 ret = -ENOMEM;
936 goto error_alloc;
937 }
938
939 net->netdev_ops = &mcp251x_netdev_ops;
940 net->flags |= IFF_ECHO;
941
942 priv = netdev_priv(net);
943 priv->can.bittiming_const = &mcp251x_bittiming_const;
944 priv->can.do_set_mode = mcp251x_do_set_mode;
945 priv->can.clock.freq = pdata->oscillator_frequency / 2;
ad72c347
CP		 946 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
947 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
e0000163
CP		 948 priv->net = net;
949 dev_set_drvdata(&spi->dev, priv);
950
951 priv->spi = spi;
bf66f373 952 mutex_init(&priv->mcp_lock);
e0000163
CP		 953
954 /* If requested, allocate DMA buffers */
955 if (mcp251x_enable_dma) {
956 spi->dev.coherent_dma_mask = ~0;
957
958 /*
959 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
960 * that much and share it between Tx and Rx DMA buffers.
961 */
962 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
963 PAGE_SIZE,
964 &priv->spi_tx_dma,
965 GFP_DMA);
966
967 if (priv->spi_tx_buf) {
968 priv->spi_rx_buf = (u8 *)(priv->spi_tx_buf +
969 (PAGE_SIZE / 2));
970 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
971 (PAGE_SIZE / 2));
972 } else {
973 /* Fall back to non-DMA */
974 mcp251x_enable_dma = 0;
975 }
976 }
977
978 /* Allocate non-DMA buffers */
979 if (!mcp251x_enable_dma) {
980 priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
981 if (!priv->spi_tx_buf) {
982 ret = -ENOMEM;
983 goto error_tx_buf;
984 }
985 priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
ce739b47 986 if (!priv->spi_rx_buf) {
e0000163
CP		 987 ret = -ENOMEM;
988 goto error_rx_buf;
989 }
990 }
991
992 if (pdata->power_enable)
993 pdata->power_enable(1);
994
995 /* Call out to platform specific setup */
996 if (pdata->board_specific_setup)
997 pdata->board_specific_setup(spi);
998
999 SET_NETDEV_DEV(net, &spi->dev);
1000
e0000163
CP		 1001 /* Configure the SPI bus */
1002 spi->mode = SPI_MODE_0;
1003 spi->bits_per_word = 8;
1004 spi_setup(spi);
1005
bf66f373 1006 /* Here is OK to not lock the MCP, no one knows about it yet */
e0000163
CP		 1007 if (!mcp251x_hw_probe(spi)) {
1008 dev_info(&spi->dev, "Probe failed\n");
1009 goto error_probe;
1010 }
1011 mcp251x_hw_sleep(spi);
1012
1013 if (pdata->transceiver_enable)
1014 pdata->transceiver_enable(0);
1015
1016 ret = register_candev(net);
1017 if (!ret) {
1018 dev_info(&spi->dev, "probed\n");
1019 return ret;
1020 }
1021error_probe:
1022 if (!mcp251x_enable_dma)
1023 kfree(priv->spi_rx_buf);
1024error_rx_buf:
1025 if (!mcp251x_enable_dma)
1026 kfree(priv->spi_tx_buf);
1027error_tx_buf:
1028 free_candev(net);
1029 if (mcp251x_enable_dma)
1030 dma_free_coherent(&spi->dev, PAGE_SIZE,
1031 priv->spi_tx_buf, priv->spi_tx_dma);
1032error_alloc:
1033 if (pdata->power_enable)
1034 pdata->power_enable(0);
1035 dev_err(&spi->dev, "probe failed\n");
1036error_out:
1037 return ret;
1038}
1039
1040static int __devexit mcp251x_can_remove(struct spi_device *spi)
1041{
1042 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1043 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1044 struct net_device *net = priv->net;
1045
1046 unregister_candev(net);
1047 free_candev(net);
1048
e0000163
CP		 1049 if (mcp251x_enable_dma) {
1050 dma_free_coherent(&spi->dev, PAGE_SIZE,
1051 priv->spi_tx_buf, priv->spi_tx_dma);
1052 } else {
1053 kfree(priv->spi_tx_buf);
1054 kfree(priv->spi_rx_buf);
1055 }
1056
1057 if (pdata->power_enable)
1058 pdata->power_enable(0);
1059
1060 return 0;
1061}
1062
1063#ifdef CONFIG_PM
1064static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state)
1065{
1066 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1067 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1068 struct net_device *net = priv->net;
1069
bf66f373
CP		 1070 priv->force_quit = 1;
1071 disable_irq(spi->irq);
1072 /*
1073 * Note: at this point neither IST nor workqueues are running.
1074 * open/stop cannot be called anyway so locking is not needed
1075 */
e0000163
CP		 1076 if (netif_running(net)) {
1077 netif_device_detach(net);
1078
1079 mcp251x_hw_sleep(spi);
1080 if (pdata->transceiver_enable)
1081 pdata->transceiver_enable(0);
1082 priv->after_suspend = AFTER_SUSPEND_UP;
1083 } else {
1084 priv->after_suspend = AFTER_SUSPEND_DOWN;
1085 }
1086
1087 if (pdata->power_enable) {
1088 pdata->power_enable(0);
1089 priv->after_suspend |= AFTER_SUSPEND_POWER;
1090 }
1091
1092 return 0;
1093}
1094
1095static int mcp251x_can_resume(struct spi_device *spi)
1096{
1097 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1098 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1099
1100 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1101 pdata->power_enable(1);
bf66f373 1102 queue_work(priv->wq, &priv->restart_work);
e0000163
CP		 1103 } else {
1104 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1105 if (pdata->transceiver_enable)
1106 pdata->transceiver_enable(1);
bf66f373 1107 queue_work(priv->wq, &priv->restart_work);
e0000163
CP		 1108 } else {
1109 priv->after_suspend = 0;
1110 }
1111 }
bf66f373
CP		 1112 priv->force_quit = 0;
1113 enable_irq(spi->irq);
e0000163
CP		 1114 return 0;
1115}
1116#else
1117#define mcp251x_can_suspend NULL
1118#define mcp251x_can_resume NULL
1119#endif
1120
1121static struct spi_driver mcp251x_can_driver = {
1122 .driver = {
1123 .name = DEVICE_NAME,
1124 .bus = &spi_bus_type,
1125 .owner = THIS_MODULE,
1126 },
1127
1128 .probe = mcp251x_can_probe,
1129 .remove = __devexit_p(mcp251x_can_remove),
1130 .suspend = mcp251x_can_suspend,
1131 .resume = mcp251x_can_resume,
1132};
1133
1134static int __init mcp251x_can_init(void)
1135{
1136 return spi_register_driver(&mcp251x_can_driver);
1137}
1138
1139static void __exit mcp251x_can_exit(void)
1140{
1141 spi_unregister_driver(&mcp251x_can_driver);
1142}
1143
1144module_init(mcp251x_can_init);
1145module_exit(mcp251x_can_exit);
1146
1147MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1148 "Christian Pellegrin <chripell@evolware.org>");
1149MODULE_DESCRIPTION("Microchip 251x CAN driver");
1150MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)