[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x / bnx2x_link.h

/* Copyright 2008-2011 Broadcom Corporation
 *
 * Unless you and Broadcom execute a separate written software license
 * agreement governing use of this software, this software is licensed to you
 * under the terms of the GNU General Public License version 2, available
 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
 *
 * Notwithstanding the above, under no circumstances may you combine this
 * software in any way with any other Broadcom software provided under a
 * license other than the GPL, without Broadcom's express prior written
 * consent.
 *
 * Written by Yaniv Rosner
 *
 */

#ifndef BNX2X_LINK_H
#define BNX2X_LINK_H


/***********************************************************/
/*                         Defines                         */
/***********************************************************/
#define DEFAULT_PHY_DEV_ADDR	3
#define E2_DEFAULT_PHY_DEV_ADDR	5


#define BNX2X_FLOW_CTRL_AUTO		PORT_FEATURE_FLOW_CONTROL_AUTO
#define BNX2X_FLOW_CTRL_TX		PORT_FEATURE_FLOW_CONTROL_TX
#define BNX2X_FLOW_CTRL_RX		PORT_FEATURE_FLOW_CONTROL_RX
#define BNX2X_FLOW_CTRL_BOTH		PORT_FEATURE_FLOW_CONTROL_BOTH
#define BNX2X_FLOW_CTRL_NONE		PORT_FEATURE_FLOW_CONTROL_NONE

#define NET_SERDES_IF_XFI		1
#define NET_SERDES_IF_SFI		2
#define NET_SERDES_IF_KR		3
#define NET_SERDES_IF_DXGXS	4

#define SPEED_AUTO_NEG		0
#define SPEED_20000		20000

#define SFP_EEPROM_VENDOR_NAME_ADDR		0x14
#define SFP_EEPROM_VENDOR_NAME_SIZE		16
#define SFP_EEPROM_VENDOR_OUI_ADDR		0x25
#define SFP_EEPROM_VENDOR_OUI_SIZE		3
#define SFP_EEPROM_PART_NO_ADDR			0x28
#define SFP_EEPROM_PART_NO_SIZE			16
#define SFP_EEPROM_REVISION_ADDR		0x38
#define SFP_EEPROM_REVISION_SIZE		4
#define SFP_EEPROM_SERIAL_ADDR			0x44
#define SFP_EEPROM_SERIAL_SIZE			16
#define SFP_EEPROM_DATE_ADDR			0x54 /* ASCII YYMMDD */
#define SFP_EEPROM_DATE_SIZE			6
#define PWR_FLT_ERR_MSG_LEN			250

#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
		((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
		(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
		 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
		((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)

/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
#define SINGLE_MEDIA_DIRECT(params)	(params->num_phys == 1)
/* Single Media board contains single external phy */
#define SINGLE_MEDIA(params)		(params->num_phys == 2)
/* Dual Media board contains two external phy with different media */
#define DUAL_MEDIA(params)		(params->num_phys == 3)

#define FW_PARAM_PHY_ADDR_MASK		0x000000FF
#define FW_PARAM_PHY_TYPE_MASK		0x0000FF00
#define FW_PARAM_MDIO_CTRL_MASK		0xFFFF0000
#define FW_PARAM_MDIO_CTRL_OFFSET		16
#define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
					   FW_PARAM_PHY_ADDR_MASK)
#define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
					   FW_PARAM_PHY_TYPE_MASK)
#define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
					    FW_PARAM_MDIO_CTRL_MASK) >> \
					    FW_PARAM_MDIO_CTRL_OFFSET)
#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
	(phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)


#define PFC_BRB_FULL_LB_XOFF_THRESHOLD				170
#define PFC_BRB_FULL_LB_XON_THRESHOLD				250

#define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
/***********************************************************/
/*                         Structs                         */
/***********************************************************/
#define INT_PHY		0
#define EXT_PHY1	1
#define EXT_PHY2	2
#define MAX_PHYS	3

/* Same configuration is shared between the XGXS and the first external phy */
#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
					 0 : (_phy_idx - 1))
/***********************************************************/
/*                      bnx2x_phy struct                     */
/*  Defines the required arguments and function per phy    */
/***********************************************************/
struct link_vars;
struct link_params;
struct bnx2x_phy;

typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
			    struct link_vars *vars);
typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
			    struct link_vars *vars);
typedef void (*link_reset_t)(struct bnx2x_phy *phy,
			     struct link_params *params);
typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
				  struct link_params *params);
typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
			       struct link_params *params, u8 mode);
typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
				    struct link_params *params, u32 action);

struct bnx2x_phy {
	u32 type;

	/* Loaded during init */
	u8 addr;
	u8 def_md_devad;
	u16 flags;
	/* Require HW lock */
#define FLAGS_HW_LOCK_REQUIRED		(1<<0)
	/* No Over-Current detection */
#define FLAGS_NOC			(1<<1)
	/* Fan failure detection required */
#define FLAGS_FAN_FAILURE_DET_REQ	(1<<2)
	/* Initialize first the XGXS and only then the phy itself */
#define FLAGS_INIT_XGXS_FIRST		(1<<3)
#define FLAGS_WC_DUAL_MODE		(1<<4)
#define FLAGS_4_PORT_MODE		(1<<5)
#define FLAGS_REARM_LATCH_SIGNAL	(1<<6)
#define FLAGS_SFP_NOT_APPROVED		(1<<7)
#define FLAGS_MDC_MDIO_WA		(1<<8)
#define FLAGS_DUMMY_READ		(1<<9)
#define FLAGS_MDC_MDIO_WA_B0		(1<<10)
#define FLAGS_TX_ERROR_CHECK		(1<<12)

	/* preemphasis values for the rx side */
	u16 rx_preemphasis[4];

	/* preemphasis values for the tx side */
	u16 tx_preemphasis[4];

	/* EMAC address for access MDIO */
	u32 mdio_ctrl;

	u32 supported;

	u32 media_type;
#define	ETH_PHY_UNSPECIFIED 0x0
#define	ETH_PHY_SFP_FIBER   0x1
#define	ETH_PHY_XFP_FIBER   0x2
#define	ETH_PHY_DA_TWINAX   0x3
#define	ETH_PHY_BASE_T      0x4
#define	ETH_PHY_KR          0xf0
#define	ETH_PHY_CX4         0xf1
#define	ETH_PHY_NOT_PRESENT 0xff

	/* The address in which version is located*/
	u32 ver_addr;

	u16 req_flow_ctrl;

	u16 req_line_speed;

	u32 speed_cap_mask;

	u16 req_duplex;
	u16 rsrv;
	/* Called per phy/port init, and it configures LASI, speed, autoneg,
	 duplex, flow control negotiation, etc. */
	config_init_t config_init;

	/* Called due to interrupt. It determines the link, speed */
	read_status_t read_status;

	/* Called when driver is unloading. Should reset the phy */
	link_reset_t link_reset;

	/* Set the loopback configuration for the phy */
	config_loopback_t config_loopback;

	/* Format the given raw number into str up to len */
	format_fw_ver_t format_fw_ver;

	/* Reset the phy (both ports) */
	hw_reset_t hw_reset;

	/* Set link led mode (on/off/oper)*/
	set_link_led_t set_link_led;

	/* PHY Specific tasks */
	phy_specific_func_t phy_specific_func;
#define DISABLE_TX	1
#define ENABLE_TX	2
};

/* Inputs parameters to the CLC */
struct link_params {

	u8 port;

	/* Default / User Configuration */
	u8 loopback_mode;
#define LOOPBACK_NONE		0
#define LOOPBACK_EMAC		1
#define LOOPBACK_BMAC		2
#define LOOPBACK_XGXS		3
#define LOOPBACK_EXT_PHY	4
#define LOOPBACK_EXT		5
#define LOOPBACK_UMAC		6
#define LOOPBACK_XMAC		7

	/* Device parameters */
	u8 mac_addr[6];

	u16 req_duplex[LINK_CONFIG_SIZE];
	u16 req_flow_ctrl[LINK_CONFIG_SIZE];

	u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */

	/* shmem parameters */
	u32 shmem_base;
	u32 shmem2_base;
	u32 speed_cap_mask[LINK_CONFIG_SIZE];
	u32 switch_cfg;
#define SWITCH_CFG_1G		PORT_FEATURE_CON_SWITCH_1G_SWITCH
#define SWITCH_CFG_10G		PORT_FEATURE_CON_SWITCH_10G_SWITCH
#define SWITCH_CFG_AUTO_DETECT	PORT_FEATURE_CON_SWITCH_AUTO_DETECT

	u32 lane_config;

	/* Phy register parameter */
	u32 chip_id;

	/* features */
	u32 feature_config_flags;
#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED	(1<<0)
#define FEATURE_CONFIG_PFC_ENABLED			(1<<1)
#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY		(1<<2)
#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY	(1<<3)
#define FEATURE_CONFIG_AUTOGREEEN_ENABLED			(1<<9)
#define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED		(1<<10)
	/* Will be populated during common init */
	struct bnx2x_phy phy[MAX_PHYS];

	/* Will be populated during common init */
	u8 num_phys;

	u8 rsrv;
	u16 hw_led_mode; /* part of the hw_config read from the shmem */
	u32 multi_phy_config;

	/* Device pointer passed to all callback functions */
	struct bnx2x *bp;
	u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
				req_flow_ctrl is set to AUTO */
};

/* Output parameters */
struct link_vars {
	u8 phy_flags;
#define PHY_XGXS_FLAG			(1<<0)
#define PHY_SGMII_FLAG			(1<<1)
#define PHY_PHYSICAL_LINK_FLAG		(1<<2)
#define PHY_HALF_OPEN_CONN_FLAG		(1<<3)
#define PHY_OVER_CURRENT_FLAG		(1<<4)

	u8 mac_type;
#define MAC_TYPE_NONE		0
#define MAC_TYPE_EMAC		1
#define MAC_TYPE_BMAC		2
#define MAC_TYPE_UMAC		3
#define MAC_TYPE_XMAC		4

	u8 phy_link_up; /* internal phy link indication */
	u8 link_up;

	u16 line_speed;
	u16 duplex;

	u16 flow_ctrl;
	u16 ieee_fc;

	/* The same definitions as the shmem parameter */
	u32 link_status;
	u8 fault_detected;
	u8 rsrv1;
	u16 periodic_flags;
#define PERIODIC_FLAGS_LINK_EVENT	0x0001

	u32 aeu_int_mask;
};

/***********************************************************/
/*                         Functions                       */
/***********************************************************/
int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);

/* Reset the link. Should be called when driver or interface goes down
   Before calling phy firmware upgrade, the reset_ext_phy should be set
   to 0 */
int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
		     u8 reset_ext_phy);

/* bnx2x_link_update should be called upon link interrupt */
int bnx2x_link_update(struct link_params *params, struct link_vars *vars);

/* use the following phy functions to read/write from external_phy
  In order to use it to read/write internal phy registers, use
  DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
  the register */
int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
		   u8 devad, u16 reg, u16 *ret_val);

int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
		    u8 devad, u16 reg, u16 val);

/* Reads the link_status from the shmem,
   and update the link vars accordingly */
void bnx2x_link_status_update(struct link_params *input,
			    struct link_vars *output);
/* returns string representing the fw_version of the external phy */
int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
				 u8 *version, u16 len);

/* Set/Unset the led
   Basically, the CLC takes care of the led for the link, but in case one needs
   to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
   blink the led, and LED_MODE_OFF to set the led off.*/
int bnx2x_set_led(struct link_params *params,
		  struct link_vars *vars, u8 mode, u32 speed);
#define LED_MODE_OFF			0
#define LED_MODE_ON			1
#define LED_MODE_OPER			2
#define LED_MODE_FRONT_PANEL_OFF	3

/* bnx2x_handle_module_detect_int should be called upon module detection
   interrupt */
void bnx2x_handle_module_detect_int(struct link_params *params);

/* Get the actual link status. In case it returns 0, link is up,
	otherwise link is down*/
int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
		    u8 is_serdes);

/* One-time initialization for external phy after power up */
int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
			  u32 shmem2_base_path[], u32 chip_id);

/* Reset the external PHY using GPIO */
void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);

/* Reset the external of SFX7101 */
void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);

/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
				 struct link_params *params, u16 addr,
				 u8 byte_cnt, u8 *o_buf);

void bnx2x_hw_reset_phy(struct link_params *params);

/* Checks if HW lock is required for this phy/board type */
u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
			  u32 shmem2_base);

/* Check swap bit and adjust PHY order */
u32 bnx2x_phy_selection(struct link_params *params);

/* Probe the phys on board, and populate them in "params" */
int bnx2x_phy_probe(struct link_params *params);

/* Checks if fan failure detection is required on one of the phys on board */
u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
			     u32 shmem2_base, u8 port);


/* DCBX structs */

/* Number of maximum COS per chip */
#define DCBX_E2E3_MAX_NUM_COS		(2)
#define DCBX_E3B0_MAX_NUM_COS_PORT0	(6)
#define DCBX_E3B0_MAX_NUM_COS_PORT1	(3)
#define DCBX_E3B0_MAX_NUM_COS		( \
			MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
			    DCBX_E3B0_MAX_NUM_COS_PORT1))

#define DCBX_MAX_NUM_COS			( \
			MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
			    DCBX_E2E3_MAX_NUM_COS))

/* PFC port configuration params */
struct bnx2x_nig_brb_pfc_port_params {
	/* NIG */
	u32 pause_enable;
	u32 llfc_out_en;
	u32 llfc_enable;
	u32 pkt_priority_to_cos;
	u8 num_of_rx_cos_priority_mask;
	u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
	u32 llfc_high_priority_classes;
	u32 llfc_low_priority_classes;
	/* BRB */
	u32 cos0_pauseable;
	u32 cos1_pauseable;
};


/* ETS port configuration params */
struct bnx2x_ets_bw_params {
	u8 bw;
};

struct bnx2x_ets_sp_params {
	/**
	 * valid values are 0 - 5. 0 is highest strict priority.
	 * There can't be two COS's with the same pri.
	 */
	u8 pri;
};

enum bnx2x_cos_state {
	bnx2x_cos_state_strict = 0,
	bnx2x_cos_state_bw = 1,
};

struct bnx2x_ets_cos_params {
	enum bnx2x_cos_state state ;
	union {
		struct bnx2x_ets_bw_params bw_params;
		struct bnx2x_ets_sp_params sp_params;
	} params;
};

struct bnx2x_ets_params {
	u8 num_of_cos; /* Number of valid COS entries*/
	struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS];
};

/**
 * Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
 * when link is already up
 */
int bnx2x_update_pfc(struct link_params *params,
		      struct link_vars *vars,
		      struct bnx2x_nig_brb_pfc_port_params *pfc_params);


/* Used to configure the ETS to disable */
int bnx2x_ets_disabled(struct link_params *params,
		       struct link_vars *vars);

/* Used to configure the ETS to BW limited */
void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
			const u32 cos1_bw);

/* Used to configure the ETS to strict */
int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);


/*  Configure the COS to ETS according to BW and SP settings.*/
int bnx2x_ets_e3b0_config(const struct link_params *params,
			 const struct link_vars *vars,
			 const struct bnx2x_ets_params *ets_params);
/* Read pfc statistic*/
void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
						 u32 pfc_frames_sent[2],
						 u32 pfc_frames_received[2]);
void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
			    u32 chip_id, u32 shmem_base, u32 shmem2_base,
			    u8 port);

int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
			       struct link_params *params);

void bnx2x_period_func(struct link_params *params, struct link_vars *vars);

#endif /* BNX2X_LINK_H */
Commit	Line	Data
cd88ccee	1	/* Copyright 2008-2011 Broadcom Corporation
ea4e040a YR	2	*
	3	* Unless you and Broadcom execute a separate written software license
	4	* agreement governing use of this software, this software is licensed to you
	5	* under the terms of the GNU General Public License version 2, available
	6	* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
	7	*
	8	* Notwithstanding the above, under no circumstances may you combine this
	9	* software in any way with any other Broadcom software provided under a
	10	* license other than the GPL, without Broadcom's express prior written
	11	* consent.
	12	*
	13	* Written by Yaniv Rosner
	14	*
	15	*/
	16
	17	#ifndef BNX2X_LINK_H
	18	#define BNX2X_LINK_H
	19
	20
	21
	22	/***********************************************************/
	23	/* Defines */
	24	/***********************************************************/
f2e0899f DK	25	#define DEFAULT_PHY_DEV_ADDR 3
f2e0899f DK	26	#define E2_DEFAULT_PHY_DEV_ADDR 5
ea4e040a YR	27
	28
	29
c0700f90 DM	30	#define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
	31	#define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
	32	#define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
	33	#define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
	34	#define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
ea4e040a	35
3c9ada22 YR	36	#define NET_SERDES_IF_XFI 1
	37	#define NET_SERDES_IF_SFI 2
	38	#define NET_SERDES_IF_KR 3
	39	#define NET_SERDES_IF_DXGXS 4
	40
cd88ccee	41	#define SPEED_AUTO_NEG 0
3c9ada22	42	#define SPEED_20000 20000
ea4e040a	43
4d295db0 EG	44	#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
	45	#define SFP_EEPROM_VENDOR_NAME_SIZE 16
	46	#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
	47	#define SFP_EEPROM_VENDOR_OUI_SIZE 3
cd88ccee YR	48	#define SFP_EEPROM_PART_NO_ADDR 0x28
cd88ccee YR	49	#define SFP_EEPROM_PART_NO_SIZE 16
3c9ada22 YR	50	#define SFP_EEPROM_REVISION_ADDR 0x38
	51	#define SFP_EEPROM_REVISION_SIZE 4
	52	#define SFP_EEPROM_SERIAL_ADDR 0x44
	53	#define SFP_EEPROM_SERIAL_SIZE 16
	54	#define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
	55	#define SFP_EEPROM_DATE_SIZE 6
4d295db0	56	#define PWR_FLT_ERR_MSG_LEN 250
b7737c9b YR	57
	58	#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
	59	((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
	60	#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
	61	(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
	62	PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
	63	#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
	64	((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
	65
e10bc84d YR	66	/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
	67	#define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
	68	/* Single Media board contains single external phy */
	69	#define SINGLE_MEDIA(params) (params->num_phys == 2)
a22f0788 YR	70	/* Dual Media board contains two external phy with different media */
a22f0788 YR	71	#define DUAL_MEDIA(params) (params->num_phys == 3)
3c9ada22 YR	72
	73	#define FW_PARAM_PHY_ADDR_MASK 0x000000FF
	74	#define FW_PARAM_PHY_TYPE_MASK 0x0000FF00
	75	#define FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
cd88ccee	76	#define FW_PARAM_MDIO_CTRL_OFFSET 16
3c9ada22 YR	77	#define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
	78	FW_PARAM_PHY_ADDR_MASK)
	79	#define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
	80	FW_PARAM_PHY_TYPE_MASK)
	81	#define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
	82	FW_PARAM_MDIO_CTRL_MASK) >> \
	83	FW_PARAM_MDIO_CTRL_OFFSET)
a22f0788 YR	84	#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
a22f0788 YR	85	(phy_addr \| phy_type \| mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
bcab15c5	86
bcab15c5 VZ	87
	88	#define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
	89	#define PFC_BRB_FULL_LB_XON_THRESHOLD 250
	90
619c5cb6	91	#define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
ea4e040a YR	92	/***********************************************************/
	93	/* Structs */
	94	/***********************************************************/
e10bc84d YR	95	#define INT_PHY 0
e10bc84d YR	96	#define EXT_PHY1 1
a22f0788 YR	97	#define EXT_PHY2 2
a22f0788 YR	98	#define MAX_PHYS 3
e10bc84d	99
b7737c9b YR	100	/* Same configuration is shared between the XGXS and the first external phy */
	101	#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
	102	#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
	103	0 : (_phy_idx - 1))
e10bc84d YR	104	/***********************************************************/
	105	/* bnx2x_phy struct */
	106	/* Defines the required arguments and function per phy */
	107	/***********************************************************/
	108	struct link_vars;
	109	struct link_params;
	110	struct bnx2x_phy;
	111
b7737c9b YR	112	typedef u8 (config_init_t)(struct bnx2x_phy phy, struct link_params *params,
	113	struct link_vars *vars);
	114	typedef u8 (read_status_t)(struct bnx2x_phy phy, struct link_params *params,
	115	struct link_vars *vars);
	116	typedef void (link_reset_t)(struct bnx2x_phy phy,
	117	struct link_params *params);
	118	typedef void (config_loopback_t)(struct bnx2x_phy phy,
	119	struct link_params *params);
	120	typedef u8 (format_fw_ver_t)(u32 raw, u8 str, u16 *len);
	121	typedef void (hw_reset_t)(struct bnx2x_phy phy, struct link_params *params);
	122	typedef void (set_link_led_t)(struct bnx2x_phy phy,
	123	struct link_params *params, u8 mode);
a22f0788 YR	124	typedef void (phy_specific_func_t)(struct bnx2x_phy phy,
a22f0788 YR	125	struct link_params *params, u32 action);
b7737c9b	126
e10bc84d YR	127	struct bnx2x_phy {
	128	u32 type;
	129
	130	/* Loaded during init */
	131	u8 addr;
9045f6b4 YR	132	u8 def_md_devad;
9045f6b4 YR	133	u16 flags;
b7737c9b YR	134	/* Require HW lock */
	135	#define FLAGS_HW_LOCK_REQUIRED (1<<0)
	136	/* No Over-Current detection */
	137	#define FLAGS_NOC (1<<1)
	138	/* Fan failure detection required */
	139	#define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
	140	/* Initialize first the XGXS and only then the phy itself */
a22f0788	141	#define FLAGS_INIT_XGXS_FIRST (1<<3)
3c9ada22	142	#define FLAGS_WC_DUAL_MODE (1<<4)
9380bb9e	143	#define FLAGS_4_PORT_MODE (1<<5)
a22f0788 YR	144	#define FLAGS_REARM_LATCH_SIGNAL (1<<6)
a22f0788 YR	145	#define FLAGS_SFP_NOT_APPROVED (1<<7)
3c9ada22 YR	146	#define FLAGS_MDC_MDIO_WA (1<<8)
3c9ada22 YR	147	#define FLAGS_DUMMY_READ (1<<9)
157fa283	148	#define FLAGS_MDC_MDIO_WA_B0 (1<<10)
de6f3377	149	#define FLAGS_TX_ERROR_CHECK (1<<12)
b7737c9b	150
b7737c9b YR	151	/* preemphasis values for the rx side */
	152	u16 rx_preemphasis[4];
	153
	154	/* preemphasis values for the tx side */
	155	u16 tx_preemphasis[4];
	156
	157	/* EMAC address for access MDIO */
e10bc84d	158	u32 mdio_ctrl;
b7737c9b YR	159
	160	u32 supported;
	161
	162	u32 media_type;
	163	#define ETH_PHY_UNSPECIFIED 0x0
	164	#define ETH_PHY_SFP_FIBER 0x1
	165	#define ETH_PHY_XFP_FIBER 0x2
	166	#define ETH_PHY_DA_TWINAX 0x3
	167	#define ETH_PHY_BASE_T 0x4
3c9ada22 YR	168	#define ETH_PHY_KR 0xf0
3c9ada22 YR	169	#define ETH_PHY_CX4 0xf1
b7737c9b YR	170	#define ETH_PHY_NOT_PRESENT 0xff
	171
	172	/* The address in which version is located*/
	173	u32 ver_addr;
	174
	175	u16 req_flow_ctrl;
	176
	177	u16 req_line_speed;
	178
	179	u32 speed_cap_mask;
	180
	181	u16 req_duplex;
	182	u16 rsrv;
	183	/* Called per phy/port init, and it configures LASI, speed, autoneg,
	184	duplex, flow control negotiation, etc. */
	185	config_init_t config_init;
	186
	187	/* Called due to interrupt. It determines the link, speed */
	188	read_status_t read_status;
	189
	190	/* Called when driver is unloading. Should reset the phy */
	191	link_reset_t link_reset;
	192
	193	/* Set the loopback configuration for the phy */
	194	config_loopback_t config_loopback;
	195
	196	/* Format the given raw number into str up to len */
	197	format_fw_ver_t format_fw_ver;
	198
	199	/* Reset the phy (both ports) */
	200	hw_reset_t hw_reset;
	201
	202	/* Set link led mode (on/off/oper)*/
	203	set_link_led_t set_link_led;
a22f0788 YR	204
	205	/* PHY Specific tasks */
	206	phy_specific_func_t phy_specific_func;
	207	#define DISABLE_TX 1
	208	#define ENABLE_TX 2
e10bc84d YR	209	};
e10bc84d YR	210
ea4e040a YR	211	/* Inputs parameters to the CLC */
	212	struct link_params {
	213
	214	u8 port;
	215
	216	/* Default / User Configuration */
	217	u8 loopback_mode;
cd88ccee YR	218	#define LOOPBACK_NONE 0
	219	#define LOOPBACK_EMAC 1
	220	#define LOOPBACK_BMAC 2
de6eae1f	221	#define LOOPBACK_XGXS 3
ea4e040a	222	#define LOOPBACK_EXT_PHY 4
cd88ccee YR	223	#define LOOPBACK_EXT 5
	224	#define LOOPBACK_UMAC 6
	225	#define LOOPBACK_XMAC 7
ea4e040a	226
ea4e040a YR	227	/* Device parameters */
ea4e040a YR	228	u8 mac_addr[6];
8c99e7b0	229
a22f0788 YR	230	u16 req_duplex[LINK_CONFIG_SIZE];
	231	u16 req_flow_ctrl[LINK_CONFIG_SIZE];
	232
	233	u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
	234
ea4e040a YR	235	/* shmem parameters */
ea4e040a YR	236	u32 shmem_base;
a22f0788 YR	237	u32 shmem2_base;
a22f0788 YR	238	u32 speed_cap_mask[LINK_CONFIG_SIZE];
ea4e040a YR	239	u32 switch_cfg;
	240	#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
	241	#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
	242	#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
	243
ea4e040a	244	u32 lane_config;
659bc5c4	245
ea4e040a YR	246	/* Phy register parameter */
	247	u32 chip_id;
	248
cd88ccee	249	/* features */
589abe3a	250	u32 feature_config_flags;
cd88ccee YR	251	#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
	252	#define FEATURE_CONFIG_PFC_ENABLED (1<<1)
	253	#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
a22f0788	254	#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
a89a1d4a	255	#define FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
85242eea	256	#define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
e10bc84d YR	257	/* Will be populated during common init */
	258	struct bnx2x_phy phy[MAX_PHYS];
	259
	260	/* Will be populated during common init */
	261	u8 num_phys;
1ef70b9c	262
b7737c9b YR	263	u8 rsrv;
b7737c9b YR	264	u16 hw_led_mode; /* part of the hw_config read from the shmem */
a22f0788	265	u32 multi_phy_config;
b7737c9b	266
ea4e040a YR	267	/* Device pointer passed to all callback functions */
ea4e040a YR	268	struct bnx2x *bp;
a22f0788 YR	269	u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
a22f0788 YR	270	req_flow_ctrl is set to AUTO */
ea4e040a YR	271	};
	272
	273	/* Output parameters */
	274	struct link_vars {
1ef70b9c	275	u8 phy_flags;
3c9ada22 YR	276	#define PHY_XGXS_FLAG (1<<0)
3c9ada22 YR	277	#define PHY_SGMII_FLAG (1<<1)
3deb8167 YR	278	#define PHY_PHYSICAL_LINK_FLAG (1<<2)
	279	#define PHY_HALF_OPEN_CONN_FLAG (1<<3)
	280	#define PHY_OVER_CURRENT_FLAG (1<<4)
1ef70b9c EG	281
	282	u8 mac_type;
	283	#define MAC_TYPE_NONE 0
	284	#define MAC_TYPE_EMAC 1
	285	#define MAC_TYPE_BMAC 2
619c5cb6 VZ	286	#define MAC_TYPE_UMAC 3
619c5cb6 VZ	287	#define MAC_TYPE_XMAC 4
1ef70b9c	288
ea4e040a YR	289	u8 phy_link_up; /* internal phy link indication */
ea4e040a YR	290	u8 link_up;
1ef70b9c EG	291
1ef70b9c EG	292	u16 line_speed;
ea4e040a	293	u16 duplex;
1ef70b9c	294
ea4e040a	295	u16 flow_ctrl;
1ef70b9c	296	u16 ieee_fc;
ea4e040a	297
ea4e040a YR	298	/* The same definitions as the shmem parameter */
ea4e040a YR	299	u32 link_status;
c688fe2f YR	300	u8 fault_detected;
c688fe2f YR	301	u8 rsrv1;
3deb8167 YR	302	u16 periodic_flags;
	303	#define PERIODIC_FLAGS_LINK_EVENT 0x0001
	304
020c7e3f	305	u32 aeu_int_mask;
ea4e040a YR	306	};
	307
	308	/***********************************************************/
	309	/* Functions */
	310	/***********************************************************/
fcf5b650	311	int bnx2x_phy_init(struct link_params params, struct link_vars vars);
ea4e040a	312
589abe3a EG	313	/* Reset the link. Should be called when driver or interface goes down
	314	Before calling phy firmware upgrade, the reset_ext_phy should be set
	315	to 0 */
fcf5b650 YR	316	int bnx2x_link_reset(struct link_params params, struct link_vars vars,
fcf5b650 YR	317	u8 reset_ext_phy);
ea4e040a YR	318
ea4e040a YR	319	/* bnx2x_link_update should be called upon link interrupt */
fcf5b650	320	int bnx2x_link_update(struct link_params params, struct link_vars vars);
ea4e040a	321
e10bc84d	322	/* use the following phy functions to read/write from external_phy
ea4e040a YR	323	In order to use it to read/write internal phy registers, use
ea4e040a YR	324	DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
ea4e040a	325	the register */
fcf5b650 YR	326	int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
	327	u8 devad, u16 reg, u16 *ret_val);
	328
	329	int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
	330	u8 devad, u16 reg, u16 val);
ea4e040a	331
ea4e040a	332	/* Reads the link_status from the shmem,
33471629	333	and update the link vars accordingly */
ea4e040a YR	334	void bnx2x_link_status_update(struct link_params *input,
	335	struct link_vars *output);
	336	/* returns string representing the fw_version of the external phy */
fcf5b650 YR	337	int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
fcf5b650 YR	338	u8 *version, u16 len);
ea4e040a YR	339
	340	/* Set/Unset the led
	341	Basically, the CLC takes care of the led for the link, but in case one needs
33471629	342	to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
ea4e040a	343	blink the led, and LED_MODE_OFF to set the led off.*/
fcf5b650 YR	344	int bnx2x_set_led(struct link_params *params,
fcf5b650 YR	345	struct link_vars *vars, u8 mode, u32 speed);
7f02c4ad YR	346	#define LED_MODE_OFF 0
	347	#define LED_MODE_ON 1
	348	#define LED_MODE_OPER 2
	349	#define LED_MODE_FRONT_PANEL_OFF 3
ea4e040a	350
589abe3a EG	351	/* bnx2x_handle_module_detect_int should be called upon module detection
	352	interrupt */
	353	void bnx2x_handle_module_detect_int(struct link_params *params);
	354
ea4e040a YR	355	/* Get the actual link status. In case it returns 0, link is up,
ea4e040a YR	356	otherwise link is down*/
fcf5b650 YR	357	int bnx2x_test_link(struct link_params params, struct link_vars vars,
fcf5b650 YR	358	u8 is_serdes);
ea4e040a	359
6bbca910	360	/* One-time initialization for external phy after power up */
fcf5b650 YR	361	int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
fcf5b650 YR	362	u32 shmem2_base_path[], u32 chip_id);
ea4e040a	363
f57a6025 EG	364	/* Reset the external PHY using GPIO */
	365	void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
	366
e10bc84d YR	367	/* Reset the external of SFX7101 */
e10bc84d YR	368	void bnx2x_sfx7101_sp_sw_reset(struct bnx2x bp, struct bnx2x_phy phy);
356e2385	369
65a001ba	370	/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
fcf5b650 YR	371	int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
	372	struct link_params *params, u16 addr,
	373	u8 byte_cnt, u8 *o_buf);
65a001ba	374
d90d96ba YR	375	void bnx2x_hw_reset_phy(struct link_params *params);
	376
	377	/* Checks if HW lock is required for this phy/board type */
a22f0788 YR	378	u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
	379	u32 shmem2_base);
	380
a22f0788 YR	381	/* Check swap bit and adjust PHY order */
	382	u32 bnx2x_phy_selection(struct link_params *params);
	383
e10bc84d	384	/* Probe the phys on board, and populate them in "params" */
fcf5b650 YR	385	int bnx2x_phy_probe(struct link_params *params);
fcf5b650 YR	386
d90d96ba	387	/* Checks if fan failure detection is required on one of the phys on board */
a22f0788 YR	388	u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
a22f0788 YR	389	u32 shmem2_base, u8 port);
d90d96ba	390
9380bb9e YR	391
9380bb9e YR	392
619c5cb6 VZ	393	/* DCBX structs */
	394
	395	/* Number of maximum COS per chip */
	396	#define DCBX_E2E3_MAX_NUM_COS (2)
	397	#define DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
	398	#define DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
	399	#define DCBX_E3B0_MAX_NUM_COS ( \
	400	MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
	401	DCBX_E3B0_MAX_NUM_COS_PORT1))
	402
	403	#define DCBX_MAX_NUM_COS ( \
	404	MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
	405	DCBX_E2E3_MAX_NUM_COS))
	406
e4901dde VZ	407	/* PFC port configuration params */
	408	struct bnx2x_nig_brb_pfc_port_params {
	409	/* NIG */
	410	u32 pause_enable;
	411	u32 llfc_out_en;
	412	u32 llfc_enable;
	413	u32 pkt_priority_to_cos;
619c5cb6 VZ	414	u8 num_of_rx_cos_priority_mask;
619c5cb6 VZ	415	u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
e4901dde VZ	416	u32 llfc_high_priority_classes;
	417	u32 llfc_low_priority_classes;
	418	/* BRB */
	419	u32 cos0_pauseable;
	420	u32 cos1_pauseable;
	421	};
	422
6c3218c6 YR	423
	424	/* ETS port configuration params */
	425	struct bnx2x_ets_bw_params {
	426	u8 bw;
	427	};
	428
	429	struct bnx2x_ets_sp_params {
	430	/**
	431	* valid values are 0 - 5. 0 is highest strict priority.
	432	* There can't be two COS's with the same pri.
	433	*/
	434	u8 pri;
	435	};
	436
	437	enum bnx2x_cos_state {
	438	bnx2x_cos_state_strict = 0,
	439	bnx2x_cos_state_bw = 1,
	440	};
	441
	442	struct bnx2x_ets_cos_params {
	443	enum bnx2x_cos_state state ;
	444	union {
	445	struct bnx2x_ets_bw_params bw_params;
	446	struct bnx2x_ets_sp_params sp_params;
	447	} params;
	448	};
	449
	450	struct bnx2x_ets_params {
	451	u8 num_of_cos; /* Number of valid COS entries*/
	452	struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS];
	453	};
	454
e4901dde VZ	455	/**
	456	* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
	457	* when link is already up
	458	*/
9380bb9e	459	int bnx2x_update_pfc(struct link_params *params,
e4901dde VZ	460	struct link_vars *vars,
	461	struct bnx2x_nig_brb_pfc_port_params *pfc_params);
	462
	463
	464	/* Used to configure the ETS to disable */
6c3218c6 YR	465	int bnx2x_ets_disabled(struct link_params *params,
6c3218c6 YR	466	struct link_vars *vars);
e4901dde VZ	467
	468	/* Used to configure the ETS to BW limited */
	469	void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
cd88ccee	470	const u32 cos1_bw);
e4901dde VZ	471
e4901dde VZ	472	/* Used to configure the ETS to strict */
fcf5b650	473	int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
e4901dde	474
6c3218c6 YR	475
	476	/* Configure the COS to ETS according to BW and SP settings.*/
	477	int bnx2x_ets_e3b0_config(const struct link_params *params,
	478	const struct link_vars *vars,
	479	const struct bnx2x_ets_params *ets_params);
e4901dde VZ	480	/* Read pfc statistic*/
	481	void bnx2x_pfc_statistic(struct link_params params, struct link_vars vars,
	482	u32 pfc_frames_sent[2],
	483	u32 pfc_frames_received[2]);
020c7e3f YR	484	void bnx2x_init_mod_abs_int(struct bnx2x bp, struct link_vars vars,
	485	u32 chip_id, u32 shmem_base, u32 shmem2_base,
	486	u8 port);
3c9ada22 YR	487
	488	int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
	489	struct link_params *params);
3deb8167 YR	490
	491	void bnx2x_period_func(struct link_params params, struct link_vars vars);
	492
ea4e040a	493	#endif /* BNX2X_LINK_H */