Commit | Line | Data |
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e190d6b1 | 1 | /* |
2fb9d6f5 | 2 | * Blackfin On-Chip MAC Driver |
e190d6b1 | 3 | * |
2fb9d6f5 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
e190d6b1 | 5 | * |
2fb9d6f5 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
e190d6b1 | 7 | * |
2fb9d6f5 | 8 | * Licensed under the GPL-2 or later. |
e190d6b1 BW |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/crc32.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/spinlock.h> | |
e190d6b1 | 25 | #include <linux/mii.h> |
4ae5a3ad | 26 | #include <linux/phy.h> |
e190d6b1 BW |
27 | #include <linux/netdevice.h> |
28 | #include <linux/etherdevice.h> | |
679dce39 | 29 | #include <linux/ethtool.h> |
e190d6b1 | 30 | #include <linux/skbuff.h> |
e190d6b1 | 31 | #include <linux/platform_device.h> |
e190d6b1 BW |
32 | |
33 | #include <asm/dma.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | ||
36 | #include <asm/blackfin.h> | |
37 | #include <asm/cacheflush.h> | |
38 | #include <asm/portmux.h> | |
39 | ||
40 | #include "bfin_mac.h" | |
41 | ||
42 | #define DRV_NAME "bfin_mac" | |
43 | #define DRV_VERSION "1.1" | |
44 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
7ef0a7ee | 45 | #define DRV_DESC "Blackfin on-chip Ethernet MAC driver" |
e190d6b1 BW |
46 | |
47 | MODULE_AUTHOR(DRV_AUTHOR); | |
48 | MODULE_LICENSE("GPL"); | |
49 | MODULE_DESCRIPTION(DRV_DESC); | |
72abb461 | 50 | MODULE_ALIAS("platform:bfin_mac"); |
e190d6b1 BW |
51 | |
52 | #if defined(CONFIG_BFIN_MAC_USE_L1) | |
53 | # define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size) | |
54 | # define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr) | |
55 | #else | |
56 | # define bfin_mac_alloc(dma_handle, size) \ | |
57 | dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL) | |
58 | # define bfin_mac_free(dma_handle, ptr) \ | |
59 | dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle) | |
60 | #endif | |
61 | ||
62 | #define PKT_BUF_SZ 1580 | |
63 | ||
64 | #define MAX_TIMEOUT_CNT 500 | |
65 | ||
66 | /* pointers to maintain transmit list */ | |
67 | static struct net_dma_desc_tx *tx_list_head; | |
68 | static struct net_dma_desc_tx *tx_list_tail; | |
69 | static struct net_dma_desc_rx *rx_list_head; | |
70 | static struct net_dma_desc_rx *rx_list_tail; | |
71 | static struct net_dma_desc_rx *current_rx_ptr; | |
72 | static struct net_dma_desc_tx *current_tx_ptr; | |
73 | static struct net_dma_desc_tx *tx_desc; | |
74 | static struct net_dma_desc_rx *rx_desc; | |
75 | ||
7ef0a7ee BW |
76 | #if defined(CONFIG_BFIN_MAC_RMII) |
77 | static u16 pin_req[] = P_RMII0; | |
78 | #else | |
79 | static u16 pin_req[] = P_MII0; | |
80 | #endif | |
81 | ||
82 | static void bfin_mac_disable(void); | |
83 | static void bfin_mac_enable(void); | |
4ae5a3ad | 84 | |
e190d6b1 BW |
85 | static void desc_list_free(void) |
86 | { | |
87 | struct net_dma_desc_rx *r; | |
88 | struct net_dma_desc_tx *t; | |
89 | int i; | |
90 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
91 | dma_addr_t dma_handle = 0; | |
92 | #endif | |
93 | ||
94 | if (tx_desc) { | |
95 | t = tx_list_head; | |
96 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
97 | if (t) { | |
98 | if (t->skb) { | |
99 | dev_kfree_skb(t->skb); | |
100 | t->skb = NULL; | |
101 | } | |
102 | t = t->next; | |
103 | } | |
104 | } | |
105 | bfin_mac_free(dma_handle, tx_desc); | |
106 | } | |
107 | ||
108 | if (rx_desc) { | |
109 | r = rx_list_head; | |
110 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
111 | if (r) { | |
112 | if (r->skb) { | |
113 | dev_kfree_skb(r->skb); | |
114 | r->skb = NULL; | |
115 | } | |
116 | r = r->next; | |
117 | } | |
118 | } | |
119 | bfin_mac_free(dma_handle, rx_desc); | |
120 | } | |
121 | } | |
122 | ||
123 | static int desc_list_init(void) | |
124 | { | |
125 | int i; | |
126 | struct sk_buff *new_skb; | |
127 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
128 | /* | |
129 | * This dma_handle is useless in Blackfin dma_alloc_coherent(). | |
130 | * The real dma handler is the return value of dma_alloc_coherent(). | |
131 | */ | |
132 | dma_addr_t dma_handle; | |
133 | #endif | |
134 | ||
135 | tx_desc = bfin_mac_alloc(&dma_handle, | |
136 | sizeof(struct net_dma_desc_tx) * | |
137 | CONFIG_BFIN_TX_DESC_NUM); | |
138 | if (tx_desc == NULL) | |
139 | goto init_error; | |
140 | ||
141 | rx_desc = bfin_mac_alloc(&dma_handle, | |
142 | sizeof(struct net_dma_desc_rx) * | |
143 | CONFIG_BFIN_RX_DESC_NUM); | |
144 | if (rx_desc == NULL) | |
145 | goto init_error; | |
146 | ||
147 | /* init tx_list */ | |
148 | tx_list_head = tx_list_tail = tx_desc; | |
149 | ||
150 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
151 | struct net_dma_desc_tx *t = tx_desc + i; | |
152 | struct dma_descriptor *a = &(t->desc_a); | |
153 | struct dma_descriptor *b = &(t->desc_b); | |
154 | ||
155 | /* | |
156 | * disable DMA | |
157 | * read from memory WNR = 0 | |
158 | * wordsize is 32 bits | |
159 | * 6 half words is desc size | |
160 | * large desc flow | |
161 | */ | |
162 | a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
163 | a->start_addr = (unsigned long)t->packet; | |
164 | a->x_count = 0; | |
165 | a->next_dma_desc = b; | |
166 | ||
167 | /* | |
168 | * enabled DMA | |
169 | * write to memory WNR = 1 | |
170 | * wordsize is 32 bits | |
171 | * disable interrupt | |
172 | * 6 half words is desc size | |
173 | * large desc flow | |
174 | */ | |
175 | b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
176 | b->start_addr = (unsigned long)(&(t->status)); | |
177 | b->x_count = 0; | |
178 | ||
179 | t->skb = NULL; | |
180 | tx_list_tail->desc_b.next_dma_desc = a; | |
181 | tx_list_tail->next = t; | |
182 | tx_list_tail = t; | |
183 | } | |
184 | tx_list_tail->next = tx_list_head; /* tx_list is a circle */ | |
185 | tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a); | |
186 | current_tx_ptr = tx_list_head; | |
187 | ||
188 | /* init rx_list */ | |
189 | rx_list_head = rx_list_tail = rx_desc; | |
190 | ||
191 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
192 | struct net_dma_desc_rx *r = rx_desc + i; | |
193 | struct dma_descriptor *a = &(r->desc_a); | |
194 | struct dma_descriptor *b = &(r->desc_b); | |
195 | ||
196 | /* allocate a new skb for next time receive */ | |
197 | new_skb = dev_alloc_skb(PKT_BUF_SZ + 2); | |
198 | if (!new_skb) { | |
199 | printk(KERN_NOTICE DRV_NAME | |
200 | ": init: low on mem - packet dropped\n"); | |
201 | goto init_error; | |
202 | } | |
203 | skb_reserve(new_skb, 2); | |
204 | r->skb = new_skb; | |
205 | ||
206 | /* | |
207 | * enabled DMA | |
208 | * write to memory WNR = 1 | |
209 | * wordsize is 32 bits | |
210 | * disable interrupt | |
211 | * 6 half words is desc size | |
212 | * large desc flow | |
213 | */ | |
214 | a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
215 | /* since RXDWA is enabled */ | |
216 | a->start_addr = (unsigned long)new_skb->data - 2; | |
217 | a->x_count = 0; | |
218 | a->next_dma_desc = b; | |
219 | ||
220 | /* | |
221 | * enabled DMA | |
222 | * write to memory WNR = 1 | |
223 | * wordsize is 32 bits | |
224 | * enable interrupt | |
225 | * 6 half words is desc size | |
226 | * large desc flow | |
227 | */ | |
228 | b->config = DMAEN | WNR | WDSIZE_32 | DI_EN | | |
229 | NDSIZE_6 | DMAFLOW_LARGE; | |
230 | b->start_addr = (unsigned long)(&(r->status)); | |
231 | b->x_count = 0; | |
232 | ||
233 | rx_list_tail->desc_b.next_dma_desc = a; | |
234 | rx_list_tail->next = r; | |
235 | rx_list_tail = r; | |
236 | } | |
237 | rx_list_tail->next = rx_list_head; /* rx_list is a circle */ | |
238 | rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a); | |
239 | current_rx_ptr = rx_list_head; | |
240 | ||
241 | return 0; | |
242 | ||
243 | init_error: | |
244 | desc_list_free(); | |
245 | printk(KERN_ERR DRV_NAME ": kmalloc failed\n"); | |
246 | return -ENOMEM; | |
247 | } | |
248 | ||
249 | ||
250 | /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ | |
251 | ||
4ae5a3ad BW |
252 | /* |
253 | * MII operations | |
254 | */ | |
e190d6b1 | 255 | /* Wait until the previous MDC/MDIO transaction has completed */ |
4ae5a3ad | 256 | static void mdio_poll(void) |
e190d6b1 BW |
257 | { |
258 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
259 | ||
260 | /* poll the STABUSY bit */ | |
261 | while ((bfin_read_EMAC_STAADD()) & STABUSY) { | |
6db9e461 | 262 | udelay(1); |
e190d6b1 BW |
263 | if (timeout_cnt-- < 0) { |
264 | printk(KERN_ERR DRV_NAME | |
265 | ": wait MDC/MDIO transaction to complete timeout\n"); | |
266 | break; | |
267 | } | |
268 | } | |
269 | } | |
270 | ||
271 | /* Read an off-chip register in a PHY through the MDC/MDIO port */ | |
4ae5a3ad | 272 | static int mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
e190d6b1 | 273 | { |
4ae5a3ad BW |
274 | mdio_poll(); |
275 | ||
e190d6b1 | 276 | /* read mode */ |
4ae5a3ad BW |
277 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
278 | SET_REGAD((u16) regnum) | | |
e190d6b1 | 279 | STABUSY); |
e190d6b1 | 280 | |
4ae5a3ad BW |
281 | mdio_poll(); |
282 | ||
283 | return (int) bfin_read_EMAC_STADAT(); | |
e190d6b1 BW |
284 | } |
285 | ||
286 | /* Write an off-chip register in a PHY through the MDC/MDIO port */ | |
4ae5a3ad BW |
287 | static int mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
288 | u16 value) | |
e190d6b1 | 289 | { |
4ae5a3ad BW |
290 | mdio_poll(); |
291 | ||
292 | bfin_write_EMAC_STADAT((u32) value); | |
e190d6b1 BW |
293 | |
294 | /* write mode */ | |
4ae5a3ad BW |
295 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
296 | SET_REGAD((u16) regnum) | | |
e190d6b1 BW |
297 | STAOP | |
298 | STABUSY); | |
299 | ||
4ae5a3ad BW |
300 | mdio_poll(); |
301 | ||
302 | return 0; | |
e190d6b1 BW |
303 | } |
304 | ||
4ae5a3ad | 305 | static int mdiobus_reset(struct mii_bus *bus) |
e190d6b1 | 306 | { |
4ae5a3ad | 307 | return 0; |
e190d6b1 BW |
308 | } |
309 | ||
7ef0a7ee | 310 | static void bfin_mac_adjust_link(struct net_device *dev) |
e190d6b1 | 311 | { |
7ef0a7ee | 312 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
313 | struct phy_device *phydev = lp->phydev; |
314 | unsigned long flags; | |
315 | int new_state = 0; | |
316 | ||
317 | spin_lock_irqsave(&lp->lock, flags); | |
318 | if (phydev->link) { | |
319 | /* Now we make sure that we can be in full duplex mode. | |
320 | * If not, we operate in half-duplex mode. */ | |
321 | if (phydev->duplex != lp->old_duplex) { | |
322 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
323 | new_state = 1; | |
324 | ||
325 | if (phydev->duplex) | |
326 | opmode |= FDMODE; | |
327 | else | |
328 | opmode &= ~(FDMODE); | |
329 | ||
330 | bfin_write_EMAC_OPMODE(opmode); | |
331 | lp->old_duplex = phydev->duplex; | |
332 | } | |
e190d6b1 | 333 | |
4ae5a3ad BW |
334 | if (phydev->speed != lp->old_speed) { |
335 | #if defined(CONFIG_BFIN_MAC_RMII) | |
336 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
4ae5a3ad BW |
337 | switch (phydev->speed) { |
338 | case 10: | |
339 | opmode |= RMII_10; | |
340 | break; | |
341 | case 100: | |
342 | opmode &= ~(RMII_10); | |
343 | break; | |
344 | default: | |
345 | printk(KERN_WARNING | |
346 | "%s: Ack! Speed (%d) is not 10/100!\n", | |
347 | DRV_NAME, phydev->speed); | |
348 | break; | |
349 | } | |
350 | bfin_write_EMAC_OPMODE(opmode); | |
4ae5a3ad | 351 | #endif |
e190d6b1 | 352 | |
4ae5a3ad BW |
353 | new_state = 1; |
354 | lp->old_speed = phydev->speed; | |
355 | } | |
e190d6b1 | 356 | |
4ae5a3ad BW |
357 | if (!lp->old_link) { |
358 | new_state = 1; | |
359 | lp->old_link = 1; | |
360 | netif_schedule(dev); | |
361 | } | |
362 | } else if (lp->old_link) { | |
363 | new_state = 1; | |
364 | lp->old_link = 0; | |
365 | lp->old_speed = 0; | |
366 | lp->old_duplex = -1; | |
e190d6b1 BW |
367 | } |
368 | ||
4ae5a3ad BW |
369 | if (new_state) { |
370 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
371 | phy_print_status(phydev); | |
372 | pr_debug("EMAC_OPMODE = 0x%08x\n", opmode); | |
e190d6b1 | 373 | } |
4ae5a3ad BW |
374 | |
375 | spin_unlock_irqrestore(&lp->lock, flags); | |
e190d6b1 BW |
376 | } |
377 | ||
7cc8f381 BW |
378 | /* MDC = 2.5 MHz */ |
379 | #define MDC_CLK 2500000 | |
380 | ||
4ae5a3ad | 381 | static int mii_probe(struct net_device *dev) |
e190d6b1 | 382 | { |
7ef0a7ee | 383 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
384 | struct phy_device *phydev = NULL; |
385 | unsigned short sysctl; | |
386 | int i; | |
7cc8f381 | 387 | u32 sclk, mdc_div; |
e190d6b1 | 388 | |
4ae5a3ad | 389 | /* Enable PHY output early */ |
e190d6b1 BW |
390 | if (!(bfin_read_VR_CTL() & PHYCLKOE)) |
391 | bfin_write_VR_CTL(bfin_read_VR_CTL() | PHYCLKOE); | |
392 | ||
7cc8f381 BW |
393 | sclk = get_sclk(); |
394 | mdc_div = ((sclk / MDC_CLK) / 2) - 1; | |
395 | ||
4ae5a3ad | 396 | sysctl = bfin_read_EMAC_SYSCTL(); |
9dc7f30e | 397 | sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); |
e190d6b1 | 398 | bfin_write_EMAC_SYSCTL(sysctl); |
e190d6b1 | 399 | |
4ae5a3ad BW |
400 | /* search for connect PHY device */ |
401 | for (i = 0; i < PHY_MAX_ADDR; i++) { | |
402 | struct phy_device *const tmp_phydev = lp->mii_bus.phy_map[i]; | |
e190d6b1 | 403 | |
4ae5a3ad BW |
404 | if (!tmp_phydev) |
405 | continue; /* no PHY here... */ | |
e190d6b1 | 406 | |
4ae5a3ad BW |
407 | phydev = tmp_phydev; |
408 | break; /* found it */ | |
409 | } | |
410 | ||
411 | /* now we are supposed to have a proper phydev, to attach to... */ | |
412 | if (!phydev) { | |
413 | printk(KERN_INFO "%s: Don't found any phy device at all\n", | |
414 | dev->name); | |
415 | return -ENODEV; | |
e190d6b1 BW |
416 | } |
417 | ||
418 | #if defined(CONFIG_BFIN_MAC_RMII) | |
7ef0a7ee | 419 | phydev = phy_connect(dev, phydev->dev.bus_id, &bfin_mac_adjust_link, 0, |
4ae5a3ad BW |
420 | PHY_INTERFACE_MODE_RMII); |
421 | #else | |
7ef0a7ee | 422 | phydev = phy_connect(dev, phydev->dev.bus_id, &bfin_mac_adjust_link, 0, |
4ae5a3ad | 423 | PHY_INTERFACE_MODE_MII); |
e190d6b1 BW |
424 | #endif |
425 | ||
4ae5a3ad BW |
426 | if (IS_ERR(phydev)) { |
427 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
428 | return PTR_ERR(phydev); | |
429 | } | |
430 | ||
431 | /* mask with MAC supported features */ | |
432 | phydev->supported &= (SUPPORTED_10baseT_Half | |
433 | | SUPPORTED_10baseT_Full | |
434 | | SUPPORTED_100baseT_Half | |
435 | | SUPPORTED_100baseT_Full | |
436 | | SUPPORTED_Autoneg | |
437 | | SUPPORTED_Pause | SUPPORTED_Asym_Pause | |
438 | | SUPPORTED_MII | |
439 | | SUPPORTED_TP); | |
440 | ||
441 | phydev->advertising = phydev->supported; | |
442 | ||
443 | lp->old_link = 0; | |
444 | lp->old_speed = 0; | |
445 | lp->old_duplex = -1; | |
446 | lp->phydev = phydev; | |
447 | ||
448 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
7cc8f381 BW |
449 | "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)" |
450 | "@sclk=%dMHz)\n", | |
451 | DRV_NAME, phydev->drv->name, phydev->dev.bus_id, phydev->irq, | |
452 | MDC_CLK, mdc_div, sclk/1000000); | |
4ae5a3ad BW |
453 | |
454 | return 0; | |
455 | } | |
456 | ||
679dce39 BW |
457 | /* |
458 | * Ethtool support | |
459 | */ | |
460 | ||
461 | static int | |
462 | bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
463 | { | |
464 | struct bfin_mac_local *lp = netdev_priv(dev); | |
465 | ||
466 | if (lp->phydev) | |
467 | return phy_ethtool_gset(lp->phydev, cmd); | |
468 | ||
469 | return -EINVAL; | |
470 | } | |
471 | ||
472 | static int | |
473 | bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
474 | { | |
475 | struct bfin_mac_local *lp = netdev_priv(dev); | |
476 | ||
477 | if (!capable(CAP_NET_ADMIN)) | |
478 | return -EPERM; | |
479 | ||
480 | if (lp->phydev) | |
481 | return phy_ethtool_sset(lp->phydev, cmd); | |
482 | ||
483 | return -EINVAL; | |
484 | } | |
485 | ||
486 | static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev, | |
487 | struct ethtool_drvinfo *info) | |
488 | { | |
489 | strcpy(info->driver, DRV_NAME); | |
490 | strcpy(info->version, DRV_VERSION); | |
491 | strcpy(info->fw_version, "N/A"); | |
492 | strcpy(info->bus_info, dev->dev.bus_id); | |
493 | } | |
494 | ||
495 | static struct ethtool_ops bfin_mac_ethtool_ops = { | |
496 | .get_settings = bfin_mac_ethtool_getsettings, | |
497 | .set_settings = bfin_mac_ethtool_setsettings, | |
498 | .get_link = ethtool_op_get_link, | |
499 | .get_drvinfo = bfin_mac_ethtool_getdrvinfo, | |
500 | }; | |
501 | ||
4ae5a3ad BW |
502 | /**************************************************************************/ |
503 | void setup_system_regs(struct net_device *dev) | |
504 | { | |
505 | unsigned short sysctl; | |
506 | ||
507 | /* | |
508 | * Odd word alignment for Receive Frame DMA word | |
509 | * Configure checksum support and rcve frame word alignment | |
510 | */ | |
511 | sysctl = bfin_read_EMAC_SYSCTL(); | |
512 | #if defined(BFIN_MAC_CSUM_OFFLOAD) | |
513 | sysctl |= RXDWA | RXCKS; | |
514 | #else | |
515 | sysctl |= RXDWA; | |
516 | #endif | |
517 | bfin_write_EMAC_SYSCTL(sysctl); | |
e190d6b1 BW |
518 | |
519 | bfin_write_EMAC_MMC_CTL(RSTC | CROLL); | |
520 | ||
521 | /* Initialize the TX DMA channel registers */ | |
522 | bfin_write_DMA2_X_COUNT(0); | |
523 | bfin_write_DMA2_X_MODIFY(4); | |
524 | bfin_write_DMA2_Y_COUNT(0); | |
525 | bfin_write_DMA2_Y_MODIFY(0); | |
526 | ||
527 | /* Initialize the RX DMA channel registers */ | |
528 | bfin_write_DMA1_X_COUNT(0); | |
529 | bfin_write_DMA1_X_MODIFY(4); | |
530 | bfin_write_DMA1_Y_COUNT(0); | |
531 | bfin_write_DMA1_Y_MODIFY(0); | |
532 | } | |
533 | ||
73f83182 | 534 | static void setup_mac_addr(u8 *mac_addr) |
e190d6b1 BW |
535 | { |
536 | u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]); | |
537 | u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]); | |
538 | ||
539 | /* this depends on a little-endian machine */ | |
540 | bfin_write_EMAC_ADDRLO(addr_low); | |
541 | bfin_write_EMAC_ADDRHI(addr_hi); | |
542 | } | |
543 | ||
7ef0a7ee | 544 | static int bfin_mac_set_mac_address(struct net_device *dev, void *p) |
73f83182 AL |
545 | { |
546 | struct sockaddr *addr = p; | |
547 | if (netif_running(dev)) | |
548 | return -EBUSY; | |
549 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
550 | setup_mac_addr(dev->dev_addr); | |
551 | return 0; | |
552 | } | |
553 | ||
e190d6b1 BW |
554 | static void adjust_tx_list(void) |
555 | { | |
556 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
557 | ||
558 | if (tx_list_head->status.status_word != 0 | |
559 | && current_tx_ptr != tx_list_head) { | |
560 | goto adjust_head; /* released something, just return; */ | |
561 | } | |
562 | ||
563 | /* | |
564 | * if nothing released, check wait condition | |
565 | * current's next can not be the head, | |
566 | * otherwise the dma will not stop as we want | |
567 | */ | |
568 | if (current_tx_ptr->next->next == tx_list_head) { | |
569 | while (tx_list_head->status.status_word == 0) { | |
6db9e461 | 570 | mdelay(1); |
e190d6b1 BW |
571 | if (tx_list_head->status.status_word != 0 |
572 | || !(bfin_read_DMA2_IRQ_STATUS() & 0x08)) { | |
573 | goto adjust_head; | |
574 | } | |
575 | if (timeout_cnt-- < 0) { | |
576 | printk(KERN_ERR DRV_NAME | |
577 | ": wait for adjust tx list head timeout\n"); | |
578 | break; | |
579 | } | |
580 | } | |
581 | if (tx_list_head->status.status_word != 0) { | |
582 | goto adjust_head; | |
583 | } | |
584 | } | |
585 | ||
586 | return; | |
587 | ||
588 | adjust_head: | |
589 | do { | |
590 | tx_list_head->desc_a.config &= ~DMAEN; | |
591 | tx_list_head->status.status_word = 0; | |
592 | if (tx_list_head->skb) { | |
593 | dev_kfree_skb(tx_list_head->skb); | |
594 | tx_list_head->skb = NULL; | |
595 | } else { | |
596 | printk(KERN_ERR DRV_NAME | |
597 | ": no sk_buff in a transmitted frame!\n"); | |
598 | } | |
599 | tx_list_head = tx_list_head->next; | |
600 | } while (tx_list_head->status.status_word != 0 | |
601 | && current_tx_ptr != tx_list_head); | |
602 | return; | |
603 | ||
604 | } | |
605 | ||
7ef0a7ee | 606 | static int bfin_mac_hard_start_xmit(struct sk_buff *skb, |
e190d6b1 BW |
607 | struct net_device *dev) |
608 | { | |
e190d6b1 BW |
609 | unsigned int data; |
610 | ||
611 | current_tx_ptr->skb = skb; | |
612 | ||
613 | /* | |
614 | * Is skb->data always 16-bit aligned? | |
615 | * Do we need to memcpy((char *)(tail->packet + 2), skb->data, len)? | |
616 | */ | |
617 | if ((((unsigned int)(skb->data)) & 0x02) == 2) { | |
618 | /* move skb->data to current_tx_ptr payload */ | |
619 | data = (unsigned int)(skb->data) - 2; | |
620 | *((unsigned short *)data) = (unsigned short)(skb->len); | |
621 | current_tx_ptr->desc_a.start_addr = (unsigned long)data; | |
622 | /* this is important! */ | |
623 | blackfin_dcache_flush_range(data, (data + (skb->len)) + 2); | |
624 | ||
625 | } else { | |
626 | *((unsigned short *)(current_tx_ptr->packet)) = | |
627 | (unsigned short)(skb->len); | |
628 | memcpy((char *)(current_tx_ptr->packet + 2), skb->data, | |
629 | (skb->len)); | |
630 | current_tx_ptr->desc_a.start_addr = | |
631 | (unsigned long)current_tx_ptr->packet; | |
632 | if (current_tx_ptr->status.status_word != 0) | |
633 | current_tx_ptr->status.status_word = 0; | |
634 | blackfin_dcache_flush_range((unsigned int)current_tx_ptr-> | |
635 | packet, | |
636 | (unsigned int)(current_tx_ptr-> | |
637 | packet + skb->len) + | |
638 | 2); | |
639 | } | |
640 | ||
641 | /* enable this packet's dma */ | |
642 | current_tx_ptr->desc_a.config |= DMAEN; | |
643 | ||
644 | /* tx dma is running, just return */ | |
645 | if (bfin_read_DMA2_IRQ_STATUS() & 0x08) | |
646 | goto out; | |
647 | ||
648 | /* tx dma is not running */ | |
649 | bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a)); | |
650 | /* dma enabled, read from memory, size is 6 */ | |
651 | bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config); | |
652 | /* Turn on the EMAC tx */ | |
653 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); | |
654 | ||
655 | out: | |
656 | adjust_tx_list(); | |
657 | current_tx_ptr = current_tx_ptr->next; | |
658 | dev->trans_start = jiffies; | |
09f75cd7 JG |
659 | dev->stats.tx_packets++; |
660 | dev->stats.tx_bytes += (skb->len); | |
e190d6b1 BW |
661 | return 0; |
662 | } | |
663 | ||
7ef0a7ee | 664 | static void bfin_mac_rx(struct net_device *dev) |
e190d6b1 BW |
665 | { |
666 | struct sk_buff *skb, *new_skb; | |
e190d6b1 BW |
667 | unsigned short len; |
668 | ||
669 | /* allocate a new skb for next time receive */ | |
670 | skb = current_rx_ptr->skb; | |
671 | new_skb = dev_alloc_skb(PKT_BUF_SZ + 2); | |
672 | if (!new_skb) { | |
673 | printk(KERN_NOTICE DRV_NAME | |
674 | ": rx: low on mem - packet dropped\n"); | |
09f75cd7 | 675 | dev->stats.rx_dropped++; |
e190d6b1 BW |
676 | goto out; |
677 | } | |
678 | /* reserve 2 bytes for RXDWA padding */ | |
679 | skb_reserve(new_skb, 2); | |
680 | current_rx_ptr->skb = new_skb; | |
681 | current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2; | |
682 | ||
6e01d1a4 AD |
683 | /* Invidate the data cache of skb->data range when it is write back |
684 | * cache. It will prevent overwritting the new data from DMA | |
685 | */ | |
686 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, | |
687 | (unsigned long)new_skb->end); | |
688 | ||
e190d6b1 BW |
689 | len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN); |
690 | skb_put(skb, len); | |
691 | blackfin_dcache_invalidate_range((unsigned long)skb->head, | |
692 | (unsigned long)skb->tail); | |
693 | ||
694 | dev->last_rx = jiffies; | |
695 | skb->dev = dev; | |
696 | skb->protocol = eth_type_trans(skb, dev); | |
697 | #if defined(BFIN_MAC_CSUM_OFFLOAD) | |
698 | skb->csum = current_rx_ptr->status.ip_payload_csum; | |
00ff49a9 | 699 | skb->ip_summed = CHECKSUM_COMPLETE; |
e190d6b1 BW |
700 | #endif |
701 | ||
702 | netif_rx(skb); | |
09f75cd7 JG |
703 | dev->stats.rx_packets++; |
704 | dev->stats.rx_bytes += len; | |
e190d6b1 BW |
705 | current_rx_ptr->status.status_word = 0x00000000; |
706 | current_rx_ptr = current_rx_ptr->next; | |
707 | ||
708 | out: | |
709 | return; | |
710 | } | |
711 | ||
712 | /* interrupt routine to handle rx and error signal */ | |
7ef0a7ee | 713 | static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id) |
e190d6b1 BW |
714 | { |
715 | struct net_device *dev = dev_id; | |
716 | int number = 0; | |
717 | ||
718 | get_one_packet: | |
719 | if (current_rx_ptr->status.status_word == 0) { | |
720 | /* no more new packet received */ | |
721 | if (number == 0) { | |
722 | if (current_rx_ptr->next->status.status_word != 0) { | |
723 | current_rx_ptr = current_rx_ptr->next; | |
724 | goto real_rx; | |
725 | } | |
726 | } | |
727 | bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() | | |
728 | DMA_DONE | DMA_ERR); | |
729 | return IRQ_HANDLED; | |
730 | } | |
731 | ||
732 | real_rx: | |
7ef0a7ee | 733 | bfin_mac_rx(dev); |
e190d6b1 BW |
734 | number++; |
735 | goto get_one_packet; | |
736 | } | |
737 | ||
738 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7ef0a7ee | 739 | static void bfin_mac_poll(struct net_device *dev) |
e190d6b1 BW |
740 | { |
741 | disable_irq(IRQ_MAC_RX); | |
7ef0a7ee | 742 | bfin_mac_interrupt(IRQ_MAC_RX, dev); |
e190d6b1 BW |
743 | enable_irq(IRQ_MAC_RX); |
744 | } | |
745 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
746 | ||
7ef0a7ee | 747 | static void bfin_mac_disable(void) |
e190d6b1 BW |
748 | { |
749 | unsigned int opmode; | |
750 | ||
751 | opmode = bfin_read_EMAC_OPMODE(); | |
752 | opmode &= (~RE); | |
753 | opmode &= (~TE); | |
754 | /* Turn off the EMAC */ | |
755 | bfin_write_EMAC_OPMODE(opmode); | |
756 | } | |
757 | ||
758 | /* | |
759 | * Enable Interrupts, Receive, and Transmit | |
760 | */ | |
7ef0a7ee | 761 | static void bfin_mac_enable(void) |
e190d6b1 BW |
762 | { |
763 | u32 opmode; | |
764 | ||
4ae5a3ad | 765 | pr_debug("%s: %s\n", DRV_NAME, __FUNCTION__); |
e190d6b1 BW |
766 | |
767 | /* Set RX DMA */ | |
768 | bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a)); | |
769 | bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config); | |
770 | ||
771 | /* Wait MII done */ | |
4ae5a3ad | 772 | mdio_poll(); |
e190d6b1 BW |
773 | |
774 | /* We enable only RX here */ | |
775 | /* ASTP : Enable Automatic Pad Stripping | |
776 | PR : Promiscuous Mode for test | |
777 | PSF : Receive frames with total length less than 64 bytes. | |
778 | FDMODE : Full Duplex Mode | |
779 | LB : Internal Loopback for test | |
780 | RE : Receiver Enable */ | |
781 | opmode = bfin_read_EMAC_OPMODE(); | |
782 | if (opmode & FDMODE) | |
783 | opmode |= PSF; | |
784 | else | |
785 | opmode |= DRO | DC | PSF; | |
786 | opmode |= RE; | |
787 | ||
788 | #if defined(CONFIG_BFIN_MAC_RMII) | |
789 | opmode |= RMII; /* For Now only 100MBit are supported */ | |
6893ff1c | 790 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2 |
e190d6b1 BW |
791 | opmode |= TE; |
792 | #endif | |
793 | #endif | |
794 | /* Turn on the EMAC rx */ | |
795 | bfin_write_EMAC_OPMODE(opmode); | |
e190d6b1 BW |
796 | } |
797 | ||
798 | /* Our watchdog timed out. Called by the networking layer */ | |
7ef0a7ee | 799 | static void bfin_mac_timeout(struct net_device *dev) |
e190d6b1 BW |
800 | { |
801 | pr_debug("%s: %s\n", dev->name, __FUNCTION__); | |
802 | ||
7ef0a7ee | 803 | bfin_mac_disable(); |
e190d6b1 BW |
804 | |
805 | /* reset tx queue */ | |
806 | tx_list_tail = tx_list_head->next; | |
807 | ||
7ef0a7ee | 808 | bfin_mac_enable(); |
e190d6b1 BW |
809 | |
810 | /* We can accept TX packets again */ | |
811 | dev->trans_start = jiffies; | |
812 | netif_wake_queue(dev); | |
813 | } | |
814 | ||
7ef0a7ee | 815 | static void bfin_mac_multicast_hash(struct net_device *dev) |
775919bc AW |
816 | { |
817 | u32 emac_hashhi, emac_hashlo; | |
818 | struct dev_mc_list *dmi = dev->mc_list; | |
819 | char *addrs; | |
820 | int i; | |
821 | u32 crc; | |
822 | ||
823 | emac_hashhi = emac_hashlo = 0; | |
824 | ||
825 | for (i = 0; i < dev->mc_count; i++) { | |
826 | addrs = dmi->dmi_addr; | |
827 | dmi = dmi->next; | |
828 | ||
829 | /* skip non-multicast addresses */ | |
830 | if (!(*addrs & 1)) | |
831 | continue; | |
832 | ||
833 | crc = ether_crc(ETH_ALEN, addrs); | |
834 | crc >>= 26; | |
835 | ||
836 | if (crc & 0x20) | |
837 | emac_hashhi |= 1 << (crc & 0x1f); | |
838 | else | |
839 | emac_hashlo |= 1 << (crc & 0x1f); | |
840 | } | |
841 | ||
842 | bfin_write_EMAC_HASHHI(emac_hashhi); | |
843 | bfin_write_EMAC_HASHLO(emac_hashlo); | |
844 | ||
845 | return; | |
846 | } | |
847 | ||
e190d6b1 BW |
848 | /* |
849 | * This routine will, depending on the values passed to it, | |
850 | * either make it accept multicast packets, go into | |
851 | * promiscuous mode (for TCPDUMP and cousins) or accept | |
852 | * a select set of multicast packets | |
853 | */ | |
7ef0a7ee | 854 | static void bfin_mac_set_multicast_list(struct net_device *dev) |
e190d6b1 BW |
855 | { |
856 | u32 sysctl; | |
857 | ||
858 | if (dev->flags & IFF_PROMISC) { | |
859 | printk(KERN_INFO "%s: set to promisc mode\n", dev->name); | |
860 | sysctl = bfin_read_EMAC_OPMODE(); | |
861 | sysctl |= RAF; | |
862 | bfin_write_EMAC_OPMODE(sysctl); | |
775919bc | 863 | } else if (dev->flags & IFF_ALLMULTI) { |
e190d6b1 BW |
864 | /* accept all multicast */ |
865 | sysctl = bfin_read_EMAC_OPMODE(); | |
866 | sysctl |= PAM; | |
867 | bfin_write_EMAC_OPMODE(sysctl); | |
775919bc AW |
868 | } else if (dev->mc_count) { |
869 | /* set up multicast hash table */ | |
870 | sysctl = bfin_read_EMAC_OPMODE(); | |
871 | sysctl |= HM; | |
872 | bfin_write_EMAC_OPMODE(sysctl); | |
7ef0a7ee | 873 | bfin_mac_multicast_hash(dev); |
e190d6b1 BW |
874 | } else { |
875 | /* clear promisc or multicast mode */ | |
876 | sysctl = bfin_read_EMAC_OPMODE(); | |
877 | sysctl &= ~(RAF | PAM); | |
878 | bfin_write_EMAC_OPMODE(sysctl); | |
879 | } | |
880 | } | |
881 | ||
882 | /* | |
883 | * this puts the device in an inactive state | |
884 | */ | |
7ef0a7ee | 885 | static void bfin_mac_shutdown(struct net_device *dev) |
e190d6b1 BW |
886 | { |
887 | /* Turn off the EMAC */ | |
888 | bfin_write_EMAC_OPMODE(0x00000000); | |
889 | /* Turn off the EMAC RX DMA */ | |
890 | bfin_write_DMA1_CONFIG(0x0000); | |
891 | bfin_write_DMA2_CONFIG(0x0000); | |
892 | } | |
893 | ||
894 | /* | |
895 | * Open and Initialize the interface | |
896 | * | |
897 | * Set up everything, reset the card, etc.. | |
898 | */ | |
7ef0a7ee | 899 | static int bfin_mac_open(struct net_device *dev) |
e190d6b1 | 900 | { |
7ef0a7ee | 901 | struct bfin_mac_local *lp = netdev_priv(dev); |
4af4b840 | 902 | int retval; |
e190d6b1 BW |
903 | pr_debug("%s: %s\n", dev->name, __FUNCTION__); |
904 | ||
905 | /* | |
906 | * Check that the address is valid. If its not, refuse | |
907 | * to bring the device up. The user must specify an | |
908 | * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx | |
909 | */ | |
910 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
911 | printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n"); | |
912 | return -EINVAL; | |
913 | } | |
914 | ||
915 | /* initial rx and tx list */ | |
4af4b840 MH |
916 | retval = desc_list_init(); |
917 | ||
918 | if (retval) | |
919 | return retval; | |
e190d6b1 | 920 | |
4ae5a3ad | 921 | phy_start(lp->phydev); |
136492b2 | 922 | phy_write(lp->phydev, MII_BMCR, BMCR_RESET); |
e190d6b1 | 923 | setup_system_regs(dev); |
7ef0a7ee BW |
924 | bfin_mac_disable(); |
925 | bfin_mac_enable(); | |
e190d6b1 BW |
926 | pr_debug("hardware init finished\n"); |
927 | netif_start_queue(dev); | |
928 | netif_carrier_on(dev); | |
929 | ||
930 | return 0; | |
931 | } | |
932 | ||
933 | /* | |
934 | * | |
935 | * this makes the board clean up everything that it can | |
936 | * and not talk to the outside world. Caused by | |
937 | * an 'ifconfig ethX down' | |
938 | */ | |
7ef0a7ee | 939 | static int bfin_mac_close(struct net_device *dev) |
e190d6b1 | 940 | { |
7ef0a7ee | 941 | struct bfin_mac_local *lp = netdev_priv(dev); |
e190d6b1 BW |
942 | pr_debug("%s: %s\n", dev->name, __FUNCTION__); |
943 | ||
944 | netif_stop_queue(dev); | |
945 | netif_carrier_off(dev); | |
946 | ||
4ae5a3ad | 947 | phy_stop(lp->phydev); |
136492b2 | 948 | phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN); |
4ae5a3ad | 949 | |
e190d6b1 | 950 | /* clear everything */ |
7ef0a7ee | 951 | bfin_mac_shutdown(dev); |
e190d6b1 BW |
952 | |
953 | /* free the rx/tx buffers */ | |
954 | desc_list_free(); | |
955 | ||
956 | return 0; | |
957 | } | |
958 | ||
7ef0a7ee | 959 | static int __init bfin_mac_probe(struct platform_device *pdev) |
e190d6b1 | 960 | { |
7ef0a7ee BW |
961 | struct net_device *ndev; |
962 | struct bfin_mac_local *lp; | |
963 | int rc, i; | |
964 | ||
965 | ndev = alloc_etherdev(sizeof(struct bfin_mac_local)); | |
966 | if (!ndev) { | |
967 | dev_err(&pdev->dev, "Cannot allocate net device!\n"); | |
968 | return -ENOMEM; | |
969 | } | |
970 | ||
971 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
972 | platform_set_drvdata(pdev, ndev); | |
973 | lp = netdev_priv(ndev); | |
e190d6b1 BW |
974 | |
975 | /* Grab the MAC address in the MAC */ | |
7ef0a7ee BW |
976 | *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO()); |
977 | *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI()); | |
e190d6b1 BW |
978 | |
979 | /* probe mac */ | |
980 | /*todo: how to proble? which is revision_register */ | |
981 | bfin_write_EMAC_ADDRLO(0x12345678); | |
982 | if (bfin_read_EMAC_ADDRLO() != 0x12345678) { | |
7ef0a7ee BW |
983 | dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n"); |
984 | rc = -ENODEV; | |
985 | goto out_err_probe_mac; | |
e190d6b1 BW |
986 | } |
987 | ||
988 | /* set the GPIO pins to Ethernet mode */ | |
7ef0a7ee BW |
989 | rc = peripheral_request_list(pin_req, DRV_NAME); |
990 | if (rc) { | |
991 | dev_err(&pdev->dev, "Requesting peripherals failed!\n"); | |
992 | rc = -EFAULT; | |
993 | goto out_err_setup_pin_mux; | |
e190d6b1 BW |
994 | } |
995 | ||
7ef0a7ee BW |
996 | /* |
997 | * Is it valid? (Did bootloader initialize it?) | |
998 | * Grab the MAC from the board somehow | |
999 | * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c | |
1000 | */ | |
1001 | if (!is_valid_ether_addr(ndev->dev_addr)) | |
1002 | bfin_get_ether_addr(ndev->dev_addr); | |
1003 | ||
e190d6b1 | 1004 | /* If still not valid, get a random one */ |
7ef0a7ee BW |
1005 | if (!is_valid_ether_addr(ndev->dev_addr)) |
1006 | random_ether_addr(ndev->dev_addr); | |
e190d6b1 | 1007 | |
7ef0a7ee | 1008 | setup_mac_addr(ndev->dev_addr); |
e190d6b1 | 1009 | |
4ae5a3ad | 1010 | /* MDIO bus initial */ |
7ef0a7ee | 1011 | lp->mii_bus.priv = ndev; |
4ae5a3ad BW |
1012 | lp->mii_bus.read = mdiobus_read; |
1013 | lp->mii_bus.write = mdiobus_write; | |
1014 | lp->mii_bus.reset = mdiobus_reset; | |
1015 | lp->mii_bus.name = "bfin_mac_mdio"; | |
9d9326d3 | 1016 | snprintf(lp->mii_bus.id, MII_BUS_ID_SIZE, "0"); |
4ae5a3ad BW |
1017 | lp->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
1018 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
1019 | lp->mii_bus.irq[i] = PHY_POLL; | |
1020 | ||
7ef0a7ee BW |
1021 | rc = mdiobus_register(&lp->mii_bus); |
1022 | if (rc) { | |
1023 | dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); | |
1024 | goto out_err_mdiobus_register; | |
1025 | } | |
4ae5a3ad | 1026 | |
7ef0a7ee BW |
1027 | rc = mii_probe(ndev); |
1028 | if (rc) { | |
1029 | dev_err(&pdev->dev, "MII Probe failed!\n"); | |
1030 | goto out_err_mii_probe; | |
1031 | } | |
4ae5a3ad | 1032 | |
e190d6b1 | 1033 | /* Fill in the fields of the device structure with ethernet values. */ |
7ef0a7ee BW |
1034 | ether_setup(ndev); |
1035 | ||
1036 | ndev->open = bfin_mac_open; | |
1037 | ndev->stop = bfin_mac_close; | |
1038 | ndev->hard_start_xmit = bfin_mac_hard_start_xmit; | |
1039 | ndev->set_mac_address = bfin_mac_set_mac_address; | |
1040 | ndev->tx_timeout = bfin_mac_timeout; | |
1041 | ndev->set_multicast_list = bfin_mac_set_multicast_list; | |
e190d6b1 | 1042 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7ef0a7ee | 1043 | ndev->poll_controller = bfin_mac_poll; |
e190d6b1 | 1044 | #endif |
679dce39 | 1045 | ndev->ethtool_ops = &bfin_mac_ethtool_ops; |
e190d6b1 | 1046 | |
e190d6b1 BW |
1047 | spin_lock_init(&lp->lock); |
1048 | ||
1049 | /* now, enable interrupts */ | |
1050 | /* register irq handler */ | |
7ef0a7ee BW |
1051 | rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt, |
1052 | IRQF_DISABLED | IRQF_SHARED, "EMAC_RX", ndev); | |
1053 | if (rc) { | |
1054 | dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n"); | |
1055 | rc = -EBUSY; | |
1056 | goto out_err_request_irq; | |
e190d6b1 BW |
1057 | } |
1058 | ||
7ef0a7ee BW |
1059 | rc = register_netdev(ndev); |
1060 | if (rc) { | |
1061 | dev_err(&pdev->dev, "Cannot register net device!\n"); | |
1062 | goto out_err_reg_ndev; | |
e190d6b1 BW |
1063 | } |
1064 | ||
7ef0a7ee BW |
1065 | /* now, print out the card info, in a short format.. */ |
1066 | dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION); | |
e190d6b1 | 1067 | |
7ef0a7ee | 1068 | return 0; |
e190d6b1 | 1069 | |
7ef0a7ee BW |
1070 | out_err_reg_ndev: |
1071 | free_irq(IRQ_MAC_RX, ndev); | |
1072 | out_err_request_irq: | |
1073 | out_err_mii_probe: | |
1074 | mdiobus_unregister(&lp->mii_bus); | |
1075 | out_err_mdiobus_register: | |
1076 | peripheral_free_list(pin_req); | |
1077 | out_err_setup_pin_mux: | |
1078 | out_err_probe_mac: | |
1079 | platform_set_drvdata(pdev, NULL); | |
1080 | free_netdev(ndev); | |
e190d6b1 | 1081 | |
7ef0a7ee | 1082 | return rc; |
e190d6b1 BW |
1083 | } |
1084 | ||
1085 | static int bfin_mac_remove(struct platform_device *pdev) | |
1086 | { | |
1087 | struct net_device *ndev = platform_get_drvdata(pdev); | |
7ef0a7ee | 1088 | struct bfin_mac_local *lp = netdev_priv(ndev); |
e190d6b1 BW |
1089 | |
1090 | platform_set_drvdata(pdev, NULL); | |
1091 | ||
7ef0a7ee BW |
1092 | mdiobus_unregister(&lp->mii_bus); |
1093 | ||
e190d6b1 BW |
1094 | unregister_netdev(ndev); |
1095 | ||
1096 | free_irq(IRQ_MAC_RX, ndev); | |
1097 | ||
1098 | free_netdev(ndev); | |
1099 | ||
7ef0a7ee | 1100 | peripheral_free_list(pin_req); |
e190d6b1 BW |
1101 | |
1102 | return 0; | |
1103 | } | |
1104 | ||
496a34c2 BW |
1105 | #ifdef CONFIG_PM |
1106 | static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg) | |
e190d6b1 | 1107 | { |
496a34c2 BW |
1108 | struct net_device *net_dev = platform_get_drvdata(pdev); |
1109 | ||
1110 | if (netif_running(net_dev)) | |
7ef0a7ee | 1111 | bfin_mac_close(net_dev); |
496a34c2 | 1112 | |
e190d6b1 BW |
1113 | return 0; |
1114 | } | |
1115 | ||
1116 | static int bfin_mac_resume(struct platform_device *pdev) | |
1117 | { | |
496a34c2 BW |
1118 | struct net_device *net_dev = platform_get_drvdata(pdev); |
1119 | ||
1120 | if (netif_running(net_dev)) | |
7ef0a7ee | 1121 | bfin_mac_open(net_dev); |
496a34c2 | 1122 | |
e190d6b1 BW |
1123 | return 0; |
1124 | } | |
496a34c2 BW |
1125 | #else |
1126 | #define bfin_mac_suspend NULL | |
1127 | #define bfin_mac_resume NULL | |
1128 | #endif /* CONFIG_PM */ | |
e190d6b1 BW |
1129 | |
1130 | static struct platform_driver bfin_mac_driver = { | |
1131 | .probe = bfin_mac_probe, | |
1132 | .remove = bfin_mac_remove, | |
1133 | .resume = bfin_mac_resume, | |
1134 | .suspend = bfin_mac_suspend, | |
1135 | .driver = { | |
72abb461 KS |
1136 | .name = DRV_NAME, |
1137 | .owner = THIS_MODULE, | |
1138 | }, | |
e190d6b1 BW |
1139 | }; |
1140 | ||
1141 | static int __init bfin_mac_init(void) | |
1142 | { | |
1143 | return platform_driver_register(&bfin_mac_driver); | |
1144 | } | |
1145 | ||
1146 | module_init(bfin_mac_init); | |
1147 | ||
1148 | static void __exit bfin_mac_cleanup(void) | |
1149 | { | |
1150 | platform_driver_unregister(&bfin_mac_driver); | |
1151 | } | |
1152 | ||
1153 | module_exit(bfin_mac_cleanup); | |
72abb461 | 1154 |